WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_sprite.c


/*
 * Copyright © 2011 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *   Jesse Barnes 
 *
 * New plane/sprite handling.
 *
 * The older chips had a separate interface for programming plane related
 * registers; newer ones are much simpler and we can use the new DRM plane
 * support.
 */
#include 
#include 
#include 
#include "intel_drv.h"
#include 
#include "i915_drv.h"
 
static void
ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
		 unsigned int crtc_w, unsigned int crtc_h,
		 uint32_t x, uint32_t y,
		 uint32_t src_w, uint32_t src_h)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane = to_intel_plane(plane);
	int pipe = intel_plane->pipe;
	u32 sprctl, sprscale = 0;
	unsigned long sprsurf_offset, linear_offset;
	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 
	sprctl = I915_READ(SPRCTL(pipe));
 
	/* Mask out pixel format bits in case we change it */
	sprctl &= ~SPRITE_PIXFORMAT_MASK;
	sprctl &= ~SPRITE_RGB_ORDER_RGBX;
	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
	sprctl &= ~SPRITE_TILED;
 
	switch (fb->pixel_format) {
	case DRM_FORMAT_XBGR8888:
		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 
		break;
	case DRM_FORMAT_XRGB8888:
		sprctl |= SPRITE_FORMAT_RGBX888;
 
		break;
	case DRM_FORMAT_YUYV:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 
		break;
	case DRM_FORMAT_YVYU:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 
		break;
	case DRM_FORMAT_UYVY:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 
		break;
	case DRM_FORMAT_VYUY:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 
		break;
	default:
 
 
 
		BUG();
	}
 
	if (obj->tiling_mode != I915_TILING_NONE)
		sprctl |= SPRITE_TILED;
 
	/* must disable */
	sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
	sprctl |= SPRITE_ENABLE;
 
	/* Sizes are 0 based */
	src_w--;
	src_h--;
	crtc_w--;
	crtc_h--;
 
	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
 
	/*
	 * IVB workaround: must disable low power watermarks for at least
	 * one frame before enabling scaling.  LP watermarks can be re-enabled
	 * when scaling is disabled.
	 */
	if (crtc_w != src_w || crtc_h != src_h) {
		if (!dev_priv->sprite_scaling_enabled) {
		dev_priv->sprite_scaling_enabled = true;
			intel_update_watermarks(dev);
		intel_wait_for_vblank(dev, pipe);
		}
		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
	} else {
		if (dev_priv->sprite_scaling_enabled) {
		dev_priv->sprite_scaling_enabled = false;
		/* potentially re-enable LP watermarks */
			intel_update_watermarks(dev);
		}
	}
 
	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 
	linear_offset = y * fb->pitches[0] + x * pixel_size;
	sprsurf_offset =
		intel_gen4_compute_offset_xtiled(&x, &y,
						 pixel_size, fb->pitches[0]);
	linear_offset -= sprsurf_offset;
 
	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
	 * register */
	if (IS_HASWELL(dev))
		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
	else if (obj->tiling_mode != I915_TILING_NONE)
		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
	else
		I915_WRITE(SPRLINOFF(pipe), linear_offset);
 
 
 
 
	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
	if (intel_plane->can_scale)
	I915_WRITE(SPRSCALE(pipe), sprscale);
	I915_WRITE(SPRCTL(pipe), sprctl);
	I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset);
	POSTING_READ(SPRSURF(pipe));
}
 
static void
ivb_disable_plane(struct drm_plane *plane)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane = to_intel_plane(plane);
	int pipe = intel_plane->pipe;
 
	I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
	/* Can't leave the scaler enabled... */
	if (intel_plane->can_scale)
	I915_WRITE(SPRSCALE(pipe), 0);
	/* Activate double buffered register update */
	I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
	POSTING_READ(SPRSURF(pipe));
 
	dev_priv->sprite_scaling_enabled = false;
	intel_update_watermarks(dev);
}
 
static int
ivb_update_colorkey(struct drm_plane *plane,
		    struct drm_intel_sprite_colorkey *key)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane;
	u32 sprctl;
	int ret = 0;
 
	intel_plane = to_intel_plane(plane);
 
	I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
	I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
	I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 
	sprctl = I915_READ(SPRCTL(intel_plane->pipe));
	sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
	if (key->flags & I915_SET_COLORKEY_DESTINATION)
		sprctl |= SPRITE_DEST_KEY;
	else if (key->flags & I915_SET_COLORKEY_SOURCE)
		sprctl |= SPRITE_SOURCE_KEY;
	I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 
	POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 
	return ret;
}
 
static void
ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane;
	u32 sprctl;
 
	intel_plane = to_intel_plane(plane);
 
	key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
	key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
	key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
	key->flags = 0;
 
	sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 
	if (sprctl & SPRITE_DEST_KEY)
		key->flags = I915_SET_COLORKEY_DESTINATION;
	else if (sprctl & SPRITE_SOURCE_KEY)
		key->flags = I915_SET_COLORKEY_SOURCE;
	else
		key->flags = I915_SET_COLORKEY_NONE;
}
 
static void
ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
		 unsigned int crtc_w, unsigned int crtc_h,
		 uint32_t x, uint32_t y,
		 uint32_t src_w, uint32_t src_h)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane = to_intel_plane(plane);
	int pipe = intel_plane->pipe;
	unsigned long dvssurf_offset, linear_offset;
	u32 dvscntr, dvsscale;
	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 
	dvscntr = I915_READ(DVSCNTR(pipe));
 
	/* Mask out pixel format bits in case we change it */
	dvscntr &= ~DVS_PIXFORMAT_MASK;
	dvscntr &= ~DVS_RGB_ORDER_XBGR;
	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
	dvscntr &= ~DVS_TILED;
 
	switch (fb->pixel_format) {
	case DRM_FORMAT_XBGR8888:
		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 
		break;
	case DRM_FORMAT_XRGB8888:
		dvscntr |= DVS_FORMAT_RGBX888;
 
		break;
	case DRM_FORMAT_YUYV:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 
		break;
	case DRM_FORMAT_YVYU:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 
		break;
	case DRM_FORMAT_UYVY:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 
		break;
	case DRM_FORMAT_VYUY:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 
		break;
	default:
 
 
 
		BUG();
	}
 
	if (obj->tiling_mode != I915_TILING_NONE)
		dvscntr |= DVS_TILED;
 
	if (IS_GEN6(dev))
		dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
	dvscntr |= DVS_ENABLE;
 
	/* Sizes are 0 based */
	src_w--;
	src_h--;
	crtc_w--;
	crtc_h--;
 
	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
 
	dvsscale = 0;
	if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 
	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
	linear_offset = y * fb->pitches[0] + x * pixel_size;
	dvssurf_offset =
		intel_gen4_compute_offset_xtiled(&x, &y,
						 pixel_size, fb->pitches[0]);
	linear_offset -= dvssurf_offset;
 
	if (obj->tiling_mode != I915_TILING_NONE)
		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
	else
		I915_WRITE(DVSLINOFF(pipe), linear_offset);
 
 
 
 
	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
	I915_WRITE(DVSSCALE(pipe), dvsscale);
	I915_WRITE(DVSCNTR(pipe), dvscntr);
	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset);
	POSTING_READ(DVSSURF(pipe));
}
 
static void
ilk_disable_plane(struct drm_plane *plane)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane = to_intel_plane(plane);
	int pipe = intel_plane->pipe;
 
	I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
	/* Disable the scaler */
	I915_WRITE(DVSSCALE(pipe), 0);
	/* Flush double buffered register updates */
	I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
	POSTING_READ(DVSSURF(pipe));
}
 
static void
intel_enable_primary(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int reg = DSPCNTR(intel_crtc->plane);
 
	if (!intel_crtc->primary_disabled)
		return;
 
	intel_crtc->primary_disabled = false;
	intel_update_fbc(dev);
 
	I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
}
 
static void
intel_disable_primary(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int reg = DSPCNTR(intel_crtc->plane);
 
	if (intel_crtc->primary_disabled)
		return;
 
	I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 
	intel_crtc->primary_disabled = true;
	intel_update_fbc(dev);
}
 
static int
ilk_update_colorkey(struct drm_plane *plane,
		    struct drm_intel_sprite_colorkey *key)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane;
	u32 dvscntr;
	int ret = 0;
 
	intel_plane = to_intel_plane(plane);
 
	I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
	I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
	I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
 
	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
	dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
	if (key->flags & I915_SET_COLORKEY_DESTINATION)
		dvscntr |= DVS_DEST_KEY;
	else if (key->flags & I915_SET_COLORKEY_SOURCE)
		dvscntr |= DVS_SOURCE_KEY;
	I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
 
	POSTING_READ(DVSKEYMSK(intel_plane->pipe));
 
	return ret;
}
 
static void
ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_plane *intel_plane;
	u32 dvscntr;
 
	intel_plane = to_intel_plane(plane);
 
	key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
	key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
	key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
	key->flags = 0;
 
	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 
	if (dvscntr & DVS_DEST_KEY)
		key->flags = I915_SET_COLORKEY_DESTINATION;
	else if (dvscntr & DVS_SOURCE_KEY)
		key->flags = I915_SET_COLORKEY_SOURCE;
	else
		key->flags = I915_SET_COLORKEY_NONE;
}
 
static int
intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
		   struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		   unsigned int crtc_w, unsigned int crtc_h,
		   uint32_t src_x, uint32_t src_y,
		   uint32_t src_w, uint32_t src_h)
{
	struct drm_device *dev = plane->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_plane *intel_plane = to_intel_plane(plane);
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj, *old_obj;
	int pipe = intel_plane->pipe;
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
	int ret = 0;
	int x = src_x >> 16, y = src_y >> 16;
	int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
	bool disable_primary = false;
 
	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;
 
	old_obj = intel_plane->obj;
 
	src_w = src_w >> 16;
	src_h = src_h >> 16;
 
	/* Pipe must be running... */
	if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
		return -EINVAL;
 
	if (crtc_x >= primary_w || crtc_y >= primary_h)
		return -EINVAL;
 
	/* Don't modify another pipe's plane */
	if (intel_plane->pipe != intel_crtc->pipe)
		return -EINVAL;
 
	/* Sprite planes can be linear or x-tiled surfaces */
	switch (obj->tiling_mode) {
		case I915_TILING_NONE:
		case I915_TILING_X:
			break;
		default:
			return -EINVAL;
	}
 
	/*
	 * Clamp the width & height into the visible area.  Note we don't
	 * try to scale the source if part of the visible region is offscreen.
	 * The caller must handle that by adjusting source offset and size.
	 */
	if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
		crtc_w += crtc_x;
		crtc_x = 0;
	}
	if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
		goto out;
	if ((crtc_x + crtc_w) > primary_w)
		crtc_w = primary_w - crtc_x;
 
	if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
		crtc_h += crtc_y;
		crtc_y = 0;
	}
	if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
		goto out;
	if (crtc_y + crtc_h > primary_h)
		crtc_h = primary_h - crtc_y;
 
	if (!crtc_w || !crtc_h) /* Again, nothing to display */
		goto out;
 
	/*
	 * We may not have a scaler, eg. HSW does not have it any more
	 */
	if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h))
		return -EINVAL;
 
	/*
	 * We can take a larger source and scale it down, but
	 * only so much...  16x is the max on SNB.
	 */
	if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
		return -EINVAL;
 
	/*
	 * If the sprite is completely covering the primary plane,
	 * we can disable the primary and save power.
	 */
	if ((crtc_x == 0) && (crtc_y == 0) &&
	    (crtc_w == primary_w) && (crtc_h == primary_h))
		disable_primary = true;
 
	mutex_lock(&dev->struct_mutex);
 
	ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
	if (ret)
		goto out_unlock;
 
	intel_plane->obj = obj;
 
	/*
	 * Be sure to re-enable the primary before the sprite is no longer
	 * covering it fully.
	 */
	if (!disable_primary)
		intel_enable_primary(crtc);
 
	intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
				  crtc_w, crtc_h, x, y, src_w, src_h);
 
	if (disable_primary)
		intel_disable_primary(crtc);
 
	/* Unpin old obj after new one is active to avoid ugliness */
	if (old_obj) {
		/*
		 * It's fairly common to simply update the position of
		 * an existing object.  In that case, we don't need to
		 * wait for vblank to avoid ugliness, we only need to
		 * do the pin & ref bookkeeping.
		 */
		if (old_obj != obj) {
			mutex_unlock(&dev->struct_mutex);
			intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
			mutex_lock(&dev->struct_mutex);
		}
		intel_unpin_fb_obj(old_obj);
	}
 
out_unlock:
	mutex_unlock(&dev->struct_mutex);
out:
	return ret;
}
 
static int
intel_disable_plane(struct drm_plane *plane)
{
	struct drm_device *dev = plane->dev;
	struct intel_plane *intel_plane = to_intel_plane(plane);
	int ret = 0;
 
	if (plane->crtc)
		intel_enable_primary(plane->crtc);
	intel_plane->disable_plane(plane);
 
	if (!intel_plane->obj)
		goto out;
 
	mutex_lock(&dev->struct_mutex);
	intel_unpin_fb_obj(intel_plane->obj);
	intel_plane->obj = NULL;
	mutex_unlock(&dev->struct_mutex);
out:
 
	return ret;
}
 
static void intel_destroy_plane(struct drm_plane *plane)
{
	struct intel_plane *intel_plane = to_intel_plane(plane);
	intel_disable_plane(plane);
	drm_plane_cleanup(plane);
	kfree(intel_plane);
}
 
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
			      struct drm_file *file_priv)
{
	struct drm_intel_sprite_colorkey *set = data;
	struct drm_mode_object *obj;
	struct drm_plane *plane;
	struct intel_plane *intel_plane;
	int ret = 0;
 
 
 
 
	/* Make sure we don't try to enable both src & dest simultaneously */
	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
		return -EINVAL;
 
	mutex_lock(&dev->mode_config.mutex);
 
	obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
	if (!obj) {
		ret = -EINVAL;
		goto out_unlock;
	}
 
	plane = obj_to_plane(obj);
	intel_plane = to_intel_plane(plane);
	ret = intel_plane->update_colorkey(plane, set);
 
out_unlock:
	mutex_unlock(&dev->mode_config.mutex);
	return ret;
}
 
int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
			      struct drm_file *file_priv)
{
	struct drm_intel_sprite_colorkey *get = data;
	struct drm_mode_object *obj;
	struct drm_plane *plane;
	struct intel_plane *intel_plane;
	int ret = 0;
 
 
 
 
	mutex_lock(&dev->mode_config.mutex);
 
	obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
	if (!obj) {
		ret = -EINVAL;
		goto out_unlock;
	}
 
	plane = obj_to_plane(obj);
	intel_plane = to_intel_plane(plane);
	intel_plane->get_colorkey(plane, get);
 
out_unlock:
	mutex_unlock(&dev->mode_config.mutex);
	return ret;
}
 
static const struct drm_plane_funcs intel_plane_funcs = {
	.update_plane = intel_update_plane,
	.disable_plane = intel_disable_plane,
	.destroy = intel_destroy_plane,
};
 
static uint32_t ilk_plane_formats[] = {
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
};
 
static uint32_t snb_plane_formats[] = {
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
};
 
int
intel_plane_init(struct drm_device *dev, enum pipe pipe)
{
	struct intel_plane *intel_plane;
	unsigned long possible_crtcs;
	const uint32_t *plane_formats;
	int num_plane_formats;
	int ret;
 
	if (INTEL_INFO(dev)->gen < 5)
		return -ENODEV;
 
	intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
	if (!intel_plane)
		return -ENOMEM;
 
	switch (INTEL_INFO(dev)->gen) {
	case 5:
	case 6:
		intel_plane->can_scale = true;
		intel_plane->max_downscale = 16;
		intel_plane->update_plane = ilk_update_plane;
		intel_plane->disable_plane = ilk_disable_plane;
		intel_plane->update_colorkey = ilk_update_colorkey;
		intel_plane->get_colorkey = ilk_get_colorkey;
 
	if (IS_GEN6(dev)) {
			plane_formats = snb_plane_formats;
			num_plane_formats = ARRAY_SIZE(snb_plane_formats);
		} else {
			plane_formats = ilk_plane_formats;
			num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
		}
		break;
 
	case 7:
		if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev))
			intel_plane->can_scale = false;
		else
			intel_plane->can_scale = true;
		intel_plane->max_downscale = 2;
		intel_plane->update_plane = ivb_update_plane;
		intel_plane->disable_plane = ivb_disable_plane;
		intel_plane->update_colorkey = ivb_update_colorkey;
		intel_plane->get_colorkey = ivb_get_colorkey;
 
		plane_formats = snb_plane_formats;
		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
		break;
 
	default:
		kfree(intel_plane);
		return -ENODEV;
	}
 
	intel_plane->pipe = pipe;
	possible_crtcs = (1 << pipe);
	ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
			     &intel_plane_funcs,
			     plane_formats, num_plane_formats,
			     false);
	if (ret)
		kfree(intel_plane);
 
	return ret;
}

Rev 3031	Rev 3243
1	/*	1	/*
2	* Copyright © 2011 Intel Corporation	2	* Copyright © 2011 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21	* SOFTWARE.	21	* SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Jesse Barnes	24	* Jesse Barnes
25	*	25	*
26	* New plane/sprite handling.	26	* New plane/sprite handling.
27	*	27	*
28	* The older chips had a separate interface for programming plane related	28	* The older chips had a separate interface for programming plane related
29	* registers; newer ones are much simpler and we can use the new DRM plane	29	* registers; newer ones are much simpler and we can use the new DRM plane
30	* support.	30	* support.
31	*/	31	*/
32	#include	32	#include
33	#include	33	#include
34	#include	34	#include
35	#include "intel_drv.h"	35	#include "intel_drv.h"
36	#include	36	#include
37	#include "i915_drv.h"	37	#include "i915_drv.h"
38		38
39	static void	39	static void
40	ivb_update_plane(struct drm_plane plane, struct drm_framebuffer fb,	40	ivb_update_plane(struct drm_plane plane, struct drm_framebuffer fb,
41	struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,	41	struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
42	unsigned int crtc_w, unsigned int crtc_h,	42	unsigned int crtc_w, unsigned int crtc_h,
43	uint32_t x, uint32_t y,	43	uint32_t x, uint32_t y,
44	uint32_t src_w, uint32_t src_h)	44	uint32_t src_w, uint32_t src_h)
45	{	45	{
46	struct drm_device *dev = plane->dev;	46	struct drm_device *dev = plane->dev;
47	struct drm_i915_private *dev_priv = dev->dev_private;	47	struct drm_i915_private *dev_priv = dev->dev_private;
48	struct intel_plane *intel_plane = to_intel_plane(plane);	48	struct intel_plane *intel_plane = to_intel_plane(plane);
49	int pipe = intel_plane->pipe;	49	int pipe = intel_plane->pipe;
50	u32 sprctl, sprscale = 0;	50	u32 sprctl, sprscale = 0;
51	int pixel_size;	51	unsigned long sprsurf_offset, linear_offset;
-		52	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
52		53
53	sprctl = I915_READ(SPRCTL(pipe));	54	sprctl = I915_READ(SPRCTL(pipe));
54		55
55	/* Mask out pixel format bits in case we change it */	56	/* Mask out pixel format bits in case we change it */
56	sprctl &= ~SPRITE_PIXFORMAT_MASK;	57	sprctl &= ~SPRITE_PIXFORMAT_MASK;
57	sprctl &= ~SPRITE_RGB_ORDER_RGBX;	58	sprctl &= ~SPRITE_RGB_ORDER_RGBX;
58	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;	59	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
59	sprctl &= ~SPRITE_TILED;	60	sprctl &= ~SPRITE_TILED;
60		61
61	switch (fb->pixel_format) {	62	switch (fb->pixel_format) {
62	case DRM_FORMAT_XBGR8888:	63	case DRM_FORMAT_XBGR8888:
63	sprctl \|= SPRITE_FORMAT_RGBX888 \| SPRITE_RGB_ORDER_RGBX;	64	sprctl \|= SPRITE_FORMAT_RGBX888 \| SPRITE_RGB_ORDER_RGBX;
64	pixel_size = 4;	-
65	break;	65	break;
66	case DRM_FORMAT_XRGB8888:	66	case DRM_FORMAT_XRGB8888:
67	sprctl \|= SPRITE_FORMAT_RGBX888;	67	sprctl \|= SPRITE_FORMAT_RGBX888;
68	pixel_size = 4;	-
69	break;	68	break;
70	case DRM_FORMAT_YUYV:	69	case DRM_FORMAT_YUYV:
71	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_YUYV;	70	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_YUYV;
72	pixel_size = 2;	-
73	break;	71	break;
74	case DRM_FORMAT_YVYU:	72	case DRM_FORMAT_YVYU:
75	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_YVYU;	73	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_YVYU;
76	pixel_size = 2;	-
77	break;	74	break;
78	case DRM_FORMAT_UYVY:	75	case DRM_FORMAT_UYVY:
79	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_UYVY;	76	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_UYVY;
80	pixel_size = 2;	-
81	break;	77	break;
82	case DRM_FORMAT_VYUY:	78	case DRM_FORMAT_VYUY:
83	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_VYUY;	79	sprctl \|= SPRITE_FORMAT_YUV422 \| SPRITE_YUV_ORDER_VYUY;
84	pixel_size = 2;	-
85	break;	80	break;
86	default:	81	default:
87	DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");	-
88	sprctl \|= SPRITE_FORMAT_RGBX888;	-
89	pixel_size = 4;	-
90	break;	82	BUG();
91	}	83	}
92		84
93	if (obj->tiling_mode != I915_TILING_NONE)	85	if (obj->tiling_mode != I915_TILING_NONE)
94	sprctl \|= SPRITE_TILED;	86	sprctl \|= SPRITE_TILED;
95		87
96	/* must disable */	88	/* must disable */
97	sprctl \|= SPRITE_TRICKLE_FEED_DISABLE;	89	sprctl \|= SPRITE_TRICKLE_FEED_DISABLE;
98	sprctl \|= SPRITE_ENABLE;	90	sprctl \|= SPRITE_ENABLE;
99		91
100	/* Sizes are 0 based */	92	/* Sizes are 0 based */
101	src_w--;	93	src_w--;
102	src_h--;	94	src_h--;
103	crtc_w--;	95	crtc_w--;
104	crtc_h--;	96	crtc_h--;
105		97
106	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	98	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
107		99
108	/*	100	/*
109	* IVB workaround: must disable low power watermarks for at least	101	* IVB workaround: must disable low power watermarks for at least
110	* one frame before enabling scaling. LP watermarks can be re-enabled	102	* one frame before enabling scaling. LP watermarks can be re-enabled
111	* when scaling is disabled.	103	* when scaling is disabled.
112	*/	104	*/
113	if (crtc_w != src_w \|\| crtc_h != src_h) {	105	if (crtc_w != src_w \|\| crtc_h != src_h) {
114	if (!dev_priv->sprite_scaling_enabled) {	106	if (!dev_priv->sprite_scaling_enabled) {
115	dev_priv->sprite_scaling_enabled = true;	107	dev_priv->sprite_scaling_enabled = true;
116	intel_update_watermarks(dev);	108	intel_update_watermarks(dev);
117	intel_wait_for_vblank(dev, pipe);	109	intel_wait_for_vblank(dev, pipe);
118	}	110	}
119	sprscale = SPRITE_SCALE_ENABLE \| (src_w << 16) \| src_h;	111	sprscale = SPRITE_SCALE_ENABLE \| (src_w << 16) \| src_h;
120	} else {	112	} else {
121	if (dev_priv->sprite_scaling_enabled) {	113	if (dev_priv->sprite_scaling_enabled) {
122	dev_priv->sprite_scaling_enabled = false;	114	dev_priv->sprite_scaling_enabled = false;
123	/* potentially re-enable LP watermarks */	115	/* potentially re-enable LP watermarks */
124	intel_update_watermarks(dev);	116	intel_update_watermarks(dev);
125	}	117	}
126	}	118	}
127		119
128	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);	120	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
129	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) \| crtc_x);	121	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) \| crtc_x);
-		122
-		123	linear_offset = y * fb->pitches[0] + x * pixel_size;
-		124	sprsurf_offset =
-		125	intel_gen4_compute_offset_xtiled(&x, &y,
-		126	pixel_size, fb->pitches[0]);
-		127	linear_offset -= sprsurf_offset;
-		128
-		129	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
-		130	* register */
-		131	if (IS_HASWELL(dev))
-		132	I915_WRITE(SPROFFSET(pipe), (y << 16) \| x);
130	if (obj->tiling_mode != I915_TILING_NONE) {	133	else if (obj->tiling_mode != I915_TILING_NONE)
131	I915_WRITE(SPRTILEOFF(pipe), (y << 16) \| x);	134	I915_WRITE(SPRTILEOFF(pipe), (y << 16) \| x);
132	} else {	135	else
133	unsigned long offset;	136	I915_WRITE(SPRLINOFF(pipe), linear_offset);
134		-
135	offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);	-
136	I915_WRITE(SPRLINOFF(pipe), offset);	-
137	}	137
-		138	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) \| crtc_w);
138	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) \| crtc_w);	139	if (intel_plane->can_scale)
139	I915_WRITE(SPRSCALE(pipe), sprscale);	140	I915_WRITE(SPRSCALE(pipe), sprscale);
140	I915_WRITE(SPRCTL(pipe), sprctl);	141	I915_WRITE(SPRCTL(pipe), sprctl);
141	I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);	142	I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset);
142	POSTING_READ(SPRSURF(pipe));	143	POSTING_READ(SPRSURF(pipe));
143	}	144	}
144		145
145	static void	146	static void
146	ivb_disable_plane(struct drm_plane *plane)	147	ivb_disable_plane(struct drm_plane *plane)
147	{	148	{
148	struct drm_device *dev = plane->dev;	149	struct drm_device *dev = plane->dev;
149	struct drm_i915_private *dev_priv = dev->dev_private;	150	struct drm_i915_private *dev_priv = dev->dev_private;
150	struct intel_plane *intel_plane = to_intel_plane(plane);	151	struct intel_plane *intel_plane = to_intel_plane(plane);
151	int pipe = intel_plane->pipe;	152	int pipe = intel_plane->pipe;
152		153
153	I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);	154	I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
154	/* Can't leave the scaler enabled... */	155	/* Can't leave the scaler enabled... */
-		156	if (intel_plane->can_scale)
155	I915_WRITE(SPRSCALE(pipe), 0);	157	I915_WRITE(SPRSCALE(pipe), 0);
156	/* Activate double buffered register update */	158	/* Activate double buffered register update */
157	I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);	159	I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
158	POSTING_READ(SPRSURF(pipe));	160	POSTING_READ(SPRSURF(pipe));
159		161
160	dev_priv->sprite_scaling_enabled = false;	162	dev_priv->sprite_scaling_enabled = false;
161	intel_update_watermarks(dev);	163	intel_update_watermarks(dev);
162	}	164	}
163		165
164	static int	166	static int
165	ivb_update_colorkey(struct drm_plane *plane,	167	ivb_update_colorkey(struct drm_plane *plane,
166	struct drm_intel_sprite_colorkey *key)	168	struct drm_intel_sprite_colorkey *key)
167	{	169	{
168	struct drm_device *dev = plane->dev;	170	struct drm_device *dev = plane->dev;
169	struct drm_i915_private *dev_priv = dev->dev_private;	171	struct drm_i915_private *dev_priv = dev->dev_private;
170	struct intel_plane *intel_plane;	172	struct intel_plane *intel_plane;
171	u32 sprctl;	173	u32 sprctl;
172	int ret = 0;	174	int ret = 0;
173		175
174	intel_plane = to_intel_plane(plane);	176	intel_plane = to_intel_plane(plane);
175		177
176	I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);	178	I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
177	I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);	179	I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
178	I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);	180	I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
179		181
180	sprctl = I915_READ(SPRCTL(intel_plane->pipe));	182	sprctl = I915_READ(SPRCTL(intel_plane->pipe));
181	sprctl &= ~(SPRITE_SOURCE_KEY \| SPRITE_DEST_KEY);	183	sprctl &= ~(SPRITE_SOURCE_KEY \| SPRITE_DEST_KEY);
182	if (key->flags & I915_SET_COLORKEY_DESTINATION)	184	if (key->flags & I915_SET_COLORKEY_DESTINATION)
183	sprctl \|= SPRITE_DEST_KEY;	185	sprctl \|= SPRITE_DEST_KEY;
184	else if (key->flags & I915_SET_COLORKEY_SOURCE)	186	else if (key->flags & I915_SET_COLORKEY_SOURCE)
185	sprctl \|= SPRITE_SOURCE_KEY;	187	sprctl \|= SPRITE_SOURCE_KEY;
186	I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);	188	I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
187		189
188	POSTING_READ(SPRKEYMSK(intel_plane->pipe));	190	POSTING_READ(SPRKEYMSK(intel_plane->pipe));
189		191
190	return ret;	192	return ret;
191	}	193	}
192		194
193	static void	195	static void
194	ivb_get_colorkey(struct drm_plane plane, struct drm_intel_sprite_colorkey key)	196	ivb_get_colorkey(struct drm_plane plane, struct drm_intel_sprite_colorkey key)
195	{	197	{
196	struct drm_device *dev = plane->dev;	198	struct drm_device *dev = plane->dev;
197	struct drm_i915_private *dev_priv = dev->dev_private;	199	struct drm_i915_private *dev_priv = dev->dev_private;
198	struct intel_plane *intel_plane;	200	struct intel_plane *intel_plane;
199	u32 sprctl;	201	u32 sprctl;
200		202
201	intel_plane = to_intel_plane(plane);	203	intel_plane = to_intel_plane(plane);
202		204
203	key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));	205	key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
204	key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));	206	key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
205	key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));	207	key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
206	key->flags = 0;	208	key->flags = 0;
207		209
208	sprctl = I915_READ(SPRCTL(intel_plane->pipe));	210	sprctl = I915_READ(SPRCTL(intel_plane->pipe));
209		211
210	if (sprctl & SPRITE_DEST_KEY)	212	if (sprctl & SPRITE_DEST_KEY)
211	key->flags = I915_SET_COLORKEY_DESTINATION;	213	key->flags = I915_SET_COLORKEY_DESTINATION;
212	else if (sprctl & SPRITE_SOURCE_KEY)	214	else if (sprctl & SPRITE_SOURCE_KEY)
213	key->flags = I915_SET_COLORKEY_SOURCE;	215	key->flags = I915_SET_COLORKEY_SOURCE;
214	else	216	else
215	key->flags = I915_SET_COLORKEY_NONE;	217	key->flags = I915_SET_COLORKEY_NONE;
216	}	218	}
217		219
218	static void	220	static void
219	ilk_update_plane(struct drm_plane plane, struct drm_framebuffer fb,	221	ilk_update_plane(struct drm_plane plane, struct drm_framebuffer fb,
220	struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,	222	struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
221	unsigned int crtc_w, unsigned int crtc_h,	223	unsigned int crtc_w, unsigned int crtc_h,
222	uint32_t x, uint32_t y,	224	uint32_t x, uint32_t y,
223	uint32_t src_w, uint32_t src_h)	225	uint32_t src_w, uint32_t src_h)
224	{	226	{
225	struct drm_device *dev = plane->dev;	227	struct drm_device *dev = plane->dev;
226	struct drm_i915_private *dev_priv = dev->dev_private;	228	struct drm_i915_private *dev_priv = dev->dev_private;
227	struct intel_plane *intel_plane = to_intel_plane(plane);	229	struct intel_plane *intel_plane = to_intel_plane(plane);
228	int pipe = intel_plane->pipe, pixel_size;	230	int pipe = intel_plane->pipe;
-		231	unsigned long dvssurf_offset, linear_offset;
229	u32 dvscntr, dvsscale;	232	u32 dvscntr, dvsscale;
-		233	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
230		234
231	dvscntr = I915_READ(DVSCNTR(pipe));	235	dvscntr = I915_READ(DVSCNTR(pipe));
232		236
233	/* Mask out pixel format bits in case we change it */	237	/* Mask out pixel format bits in case we change it */
234	dvscntr &= ~DVS_PIXFORMAT_MASK;	238	dvscntr &= ~DVS_PIXFORMAT_MASK;
235	dvscntr &= ~DVS_RGB_ORDER_XBGR;	239	dvscntr &= ~DVS_RGB_ORDER_XBGR;
236	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;	240	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
237	dvscntr &= ~DVS_TILED;	241	dvscntr &= ~DVS_TILED;
238		242
239	switch (fb->pixel_format) {	243	switch (fb->pixel_format) {
240	case DRM_FORMAT_XBGR8888:	244	case DRM_FORMAT_XBGR8888:
241	dvscntr \|= DVS_FORMAT_RGBX888 \| DVS_RGB_ORDER_XBGR;	245	dvscntr \|= DVS_FORMAT_RGBX888 \| DVS_RGB_ORDER_XBGR;
242	pixel_size = 4;	-
243	break;	246	break;
244	case DRM_FORMAT_XRGB8888:	247	case DRM_FORMAT_XRGB8888:
245	dvscntr \|= DVS_FORMAT_RGBX888;	248	dvscntr \|= DVS_FORMAT_RGBX888;
246	pixel_size = 4;	-
247	break;	249	break;
248	case DRM_FORMAT_YUYV:	250	case DRM_FORMAT_YUYV:
249	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_YUYV;	251	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_YUYV;
250	pixel_size = 2;	-
251	break;	252	break;
252	case DRM_FORMAT_YVYU:	253	case DRM_FORMAT_YVYU:
253	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_YVYU;	254	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_YVYU;
254	pixel_size = 2;	-
255	break;	255	break;
256	case DRM_FORMAT_UYVY:	256	case DRM_FORMAT_UYVY:
257	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_UYVY;	257	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_UYVY;
258	pixel_size = 2;	-
259	break;	258	break;
260	case DRM_FORMAT_VYUY:	259	case DRM_FORMAT_VYUY:
261	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_VYUY;	260	dvscntr \|= DVS_FORMAT_YUV422 \| DVS_YUV_ORDER_VYUY;
262	pixel_size = 2;	-
263	break;	261	break;
264	default:	262	default:
265	DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");	-
266	dvscntr \|= DVS_FORMAT_RGBX888;	-
267	pixel_size = 4;	-
268	break;	263	BUG();
269	}	264	}
270		265
271	if (obj->tiling_mode != I915_TILING_NONE)	266	if (obj->tiling_mode != I915_TILING_NONE)
272	dvscntr \|= DVS_TILED;	267	dvscntr \|= DVS_TILED;
273		268
274	if (IS_GEN6(dev))	269	if (IS_GEN6(dev))
275	dvscntr \|= DVS_TRICKLE_FEED_DISABLE; /* must disable */	270	dvscntr \|= DVS_TRICKLE_FEED_DISABLE; /* must disable */
276	dvscntr \|= DVS_ENABLE;	271	dvscntr \|= DVS_ENABLE;
277		272
278	/* Sizes are 0 based */	273	/* Sizes are 0 based */
279	src_w--;	274	src_w--;
280	src_h--;	275	src_h--;
281	crtc_w--;	276	crtc_w--;
282	crtc_h--;	277	crtc_h--;
283		278
284	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	279	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
285		280
286	dvsscale = 0;	281	dvsscale = 0;
287	if (IS_GEN5(dev) \|\| crtc_w != src_w \|\| crtc_h != src_h)	282	if (IS_GEN5(dev) \|\| crtc_w != src_w \|\| crtc_h != src_h)
288	dvsscale = DVS_SCALE_ENABLE \| (src_w << 16) \| src_h;	283	dvsscale = DVS_SCALE_ENABLE \| (src_w << 16) \| src_h;
289		284
290	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);	285	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
291	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) \| crtc_x);	286	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) \| crtc_x);
-		287
-		288	linear_offset = y * fb->pitches[0] + x * pixel_size;
-		289	dvssurf_offset =
-		290	intel_gen4_compute_offset_xtiled(&x, &y,
-		291	pixel_size, fb->pitches[0]);
-		292	linear_offset -= dvssurf_offset;
-		293
292	if (obj->tiling_mode != I915_TILING_NONE) {	294	if (obj->tiling_mode != I915_TILING_NONE)
293	I915_WRITE(DVSTILEOFF(pipe), (y << 16) \| x);	295	I915_WRITE(DVSTILEOFF(pipe), (y << 16) \| x);
294	} else {	296	else
295	unsigned long offset;	297	I915_WRITE(DVSLINOFF(pipe), linear_offset);
296		-
297	offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);	-
298	I915_WRITE(DVSLINOFF(pipe), offset);	-
299	}	298
300	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) \| crtc_w);	299	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) \| crtc_w);
301	I915_WRITE(DVSSCALE(pipe), dvsscale);	300	I915_WRITE(DVSSCALE(pipe), dvsscale);
302	I915_WRITE(DVSCNTR(pipe), dvscntr);	301	I915_WRITE(DVSCNTR(pipe), dvscntr);
303	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);	302	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset);
304	POSTING_READ(DVSSURF(pipe));	303	POSTING_READ(DVSSURF(pipe));
305	}	304	}
306		305
307	static void	306	static void
308	ilk_disable_plane(struct drm_plane *plane)	307	ilk_disable_plane(struct drm_plane *plane)
309	{	308	{
310	struct drm_device *dev = plane->dev;	309	struct drm_device *dev = plane->dev;
311	struct drm_i915_private *dev_priv = dev->dev_private;	310	struct drm_i915_private *dev_priv = dev->dev_private;
312	struct intel_plane *intel_plane = to_intel_plane(plane);	311	struct intel_plane *intel_plane = to_intel_plane(plane);
313	int pipe = intel_plane->pipe;	312	int pipe = intel_plane->pipe;
314		313
315	I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);	314	I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
316	/* Disable the scaler */	315	/* Disable the scaler */
317	I915_WRITE(DVSSCALE(pipe), 0);	316	I915_WRITE(DVSSCALE(pipe), 0);
318	/* Flush double buffered register updates */	317	/* Flush double buffered register updates */
319	I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);	318	I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
320	POSTING_READ(DVSSURF(pipe));	319	POSTING_READ(DVSSURF(pipe));
321	}	320	}
322		321
323	static void	322	static void
324	intel_enable_primary(struct drm_crtc *crtc)	323	intel_enable_primary(struct drm_crtc *crtc)
325	{	324	{
326	struct drm_device *dev = crtc->dev;	325	struct drm_device *dev = crtc->dev;
327	struct drm_i915_private *dev_priv = dev->dev_private;	326	struct drm_i915_private *dev_priv = dev->dev_private;
328	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	327	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
329	int reg = DSPCNTR(intel_crtc->plane);	328	int reg = DSPCNTR(intel_crtc->plane);
330		329
331	if (!intel_crtc->primary_disabled)	330	if (!intel_crtc->primary_disabled)
332	return;	331	return;
333		332
334	intel_crtc->primary_disabled = false;	333	intel_crtc->primary_disabled = false;
335	intel_update_fbc(dev);	334	intel_update_fbc(dev);
336		335
337	I915_WRITE(reg, I915_READ(reg) \| DISPLAY_PLANE_ENABLE);	336	I915_WRITE(reg, I915_READ(reg) \| DISPLAY_PLANE_ENABLE);
338	}	337	}
339		338
340	static void	339	static void
341	intel_disable_primary(struct drm_crtc *crtc)	340	intel_disable_primary(struct drm_crtc *crtc)
342	{	341	{
343	struct drm_device *dev = crtc->dev;	342	struct drm_device *dev = crtc->dev;
344	struct drm_i915_private *dev_priv = dev->dev_private;	343	struct drm_i915_private *dev_priv = dev->dev_private;
345	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	344	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
346	int reg = DSPCNTR(intel_crtc->plane);	345	int reg = DSPCNTR(intel_crtc->plane);
347		346
348	if (intel_crtc->primary_disabled)	347	if (intel_crtc->primary_disabled)
349	return;	348	return;
350		349
351	I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);	350	I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
352		351
353	intel_crtc->primary_disabled = true;	352	intel_crtc->primary_disabled = true;
354	intel_update_fbc(dev);	353	intel_update_fbc(dev);
355	}	354	}
356		355
357	static int	356	static int
358	ilk_update_colorkey(struct drm_plane *plane,	357	ilk_update_colorkey(struct drm_plane *plane,
359	struct drm_intel_sprite_colorkey *key)	358	struct drm_intel_sprite_colorkey *key)
360	{	359	{
361	struct drm_device *dev = plane->dev;	360	struct drm_device *dev = plane->dev;
362	struct drm_i915_private *dev_priv = dev->dev_private;	361	struct drm_i915_private *dev_priv = dev->dev_private;
363	struct intel_plane *intel_plane;	362	struct intel_plane *intel_plane;
364	u32 dvscntr;	363	u32 dvscntr;
365	int ret = 0;	364	int ret = 0;
366		365
367	intel_plane = to_intel_plane(plane);	366	intel_plane = to_intel_plane(plane);
368		367
369	I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);	368	I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
370	I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);	369	I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
371	I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);	370	I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
372		371
373	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));	372	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
374	dvscntr &= ~(DVS_SOURCE_KEY \| DVS_DEST_KEY);	373	dvscntr &= ~(DVS_SOURCE_KEY \| DVS_DEST_KEY);
375	if (key->flags & I915_SET_COLORKEY_DESTINATION)	374	if (key->flags & I915_SET_COLORKEY_DESTINATION)
376	dvscntr \|= DVS_DEST_KEY;	375	dvscntr \|= DVS_DEST_KEY;
377	else if (key->flags & I915_SET_COLORKEY_SOURCE)	376	else if (key->flags & I915_SET_COLORKEY_SOURCE)
378	dvscntr \|= DVS_SOURCE_KEY;	377	dvscntr \|= DVS_SOURCE_KEY;
379	I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);	378	I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
380		379
381	POSTING_READ(DVSKEYMSK(intel_plane->pipe));	380	POSTING_READ(DVSKEYMSK(intel_plane->pipe));
382		381
383	return ret;	382	return ret;
384	}	383	}
385		384
386	static void	385	static void
387	ilk_get_colorkey(struct drm_plane plane, struct drm_intel_sprite_colorkey key)	386	ilk_get_colorkey(struct drm_plane plane, struct drm_intel_sprite_colorkey key)
388	{	387	{
389	struct drm_device *dev = plane->dev;	388	struct drm_device *dev = plane->dev;
390	struct drm_i915_private *dev_priv = dev->dev_private;	389	struct drm_i915_private *dev_priv = dev->dev_private;
391	struct intel_plane *intel_plane;	390	struct intel_plane *intel_plane;
392	u32 dvscntr;	391	u32 dvscntr;
393		392
394	intel_plane = to_intel_plane(plane);	393	intel_plane = to_intel_plane(plane);
395		394
396	key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));	395	key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
397	key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));	396	key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
398	key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));	397	key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
399	key->flags = 0;	398	key->flags = 0;
400		399
401	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));	400	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
402		401
403	if (dvscntr & DVS_DEST_KEY)	402	if (dvscntr & DVS_DEST_KEY)
404	key->flags = I915_SET_COLORKEY_DESTINATION;	403	key->flags = I915_SET_COLORKEY_DESTINATION;
405	else if (dvscntr & DVS_SOURCE_KEY)	404	else if (dvscntr & DVS_SOURCE_KEY)
406	key->flags = I915_SET_COLORKEY_SOURCE;	405	key->flags = I915_SET_COLORKEY_SOURCE;
407	else	406	else
408	key->flags = I915_SET_COLORKEY_NONE;	407	key->flags = I915_SET_COLORKEY_NONE;
409	}	408	}
410		409
411	static int	410	static int
412	intel_update_plane(struct drm_plane plane, struct drm_crtc crtc,	411	intel_update_plane(struct drm_plane plane, struct drm_crtc crtc,
413	struct drm_framebuffer *fb, int crtc_x, int crtc_y,	412	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
414	unsigned int crtc_w, unsigned int crtc_h,	413	unsigned int crtc_w, unsigned int crtc_h,
415	uint32_t src_x, uint32_t src_y,	414	uint32_t src_x, uint32_t src_y,
416	uint32_t src_w, uint32_t src_h)	415	uint32_t src_w, uint32_t src_h)
417	{	416	{
418	struct drm_device *dev = plane->dev;	417	struct drm_device *dev = plane->dev;
419	struct drm_i915_private *dev_priv = dev->dev_private;	418	struct drm_i915_private *dev_priv = dev->dev_private;
420	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	419	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
421	struct intel_plane *intel_plane = to_intel_plane(plane);	420	struct intel_plane *intel_plane = to_intel_plane(plane);
422	struct intel_framebuffer *intel_fb;	421	struct intel_framebuffer *intel_fb;
423	struct drm_i915_gem_object obj, old_obj;	422	struct drm_i915_gem_object obj, old_obj;
424	int pipe = intel_plane->pipe;	423	int pipe = intel_plane->pipe;
-		424	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
-		425	pipe);
425	int ret = 0;	426	int ret = 0;
426	int x = src_x >> 16, y = src_y >> 16;	427	int x = src_x >> 16, y = src_y >> 16;
427	int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;	428	int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
428	bool disable_primary = false;	429	bool disable_primary = false;
429		430
430	intel_fb = to_intel_framebuffer(fb);	431	intel_fb = to_intel_framebuffer(fb);
431	obj = intel_fb->obj;	432	obj = intel_fb->obj;
432		433
433	old_obj = intel_plane->obj;	434	old_obj = intel_plane->obj;
434		435
435	src_w = src_w >> 16;	436	src_w = src_w >> 16;
436	src_h = src_h >> 16;	437	src_h = src_h >> 16;
437		438
438	/* Pipe must be running... */	439	/* Pipe must be running... */
439	if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))	440	if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
440	return -EINVAL;	441	return -EINVAL;
441		442
442	if (crtc_x >= primary_w \|\| crtc_y >= primary_h)	443	if (crtc_x >= primary_w \|\| crtc_y >= primary_h)
443	return -EINVAL;	444	return -EINVAL;
444		445
445	/* Don't modify another pipe's plane */	446	/* Don't modify another pipe's plane */
446	if (intel_plane->pipe != intel_crtc->pipe)	447	if (intel_plane->pipe != intel_crtc->pipe)
447	return -EINVAL;	448	return -EINVAL;
-		449
-		450	/* Sprite planes can be linear or x-tiled surfaces */
-		451	switch (obj->tiling_mode) {
-		452	case I915_TILING_NONE:
-		453	case I915_TILING_X:
-		454	break;
-		455	default:
-		456	return -EINVAL;
-		457	}
448		458
449	/*	459	/*
450	* Clamp the width & height into the visible area. Note we don't	460	* Clamp the width & height into the visible area. Note we don't
451	* try to scale the source if part of the visible region is offscreen.	461	* try to scale the source if part of the visible region is offscreen.
452	* The caller must handle that by adjusting source offset and size.	462	* The caller must handle that by adjusting source offset and size.
453	*/	463	*/
454	if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {	464	if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
455	crtc_w += crtc_x;	465	crtc_w += crtc_x;
456	crtc_x = 0;	466	crtc_x = 0;
457	}	467	}
458	if ((crtc_x + crtc_w) <= 0) /* Nothing to display */	468	if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
459	goto out;	469	goto out;
460	if ((crtc_x + crtc_w) > primary_w)	470	if ((crtc_x + crtc_w) > primary_w)
461	crtc_w = primary_w - crtc_x;	471	crtc_w = primary_w - crtc_x;
462		472
463	if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {	473	if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
464	crtc_h += crtc_y;	474	crtc_h += crtc_y;
465	crtc_y = 0;	475	crtc_y = 0;
466	}	476	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_sprite.c – Rev 3031 → 3243