Rev 6084 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 6084 | Rev 7144 | ||
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Line 127... | Line 127... | ||
127 | mutex_unlock(&dev_priv->sb_lock); |
127 | mutex_unlock(&dev_priv->sb_lock); |
Line 128... | Line 128... | ||
128 | 128 | ||
129 | return val; |
129 | return val; |
Line 130... | Line 130... | ||
130 | } |
130 | } |
131 | 131 | ||
132 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
132 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg) |
133 | { |
133 | { |
134 | u32 val = 0; |
134 | u32 val = 0; |
135 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC, |
135 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port, |
136 | SB_CRRDDA_NP, reg, &val); |
136 | SB_CRRDDA_NP, reg, &val); |
Line 137... | Line 137... | ||
137 | return val; |
137 | return val; |
- | 138 | } |
|
138 | } |
139 | |
139 | 140 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, |
|
140 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
141 | u8 port, u32 reg, u32 val) |
141 | { |
142 | { |
Line 142... | Line 143... | ||
142 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC, |
143 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port, |
143 | SB_CRWRDA_NP, reg, &val); |
144 | SB_CRWRDA_NP, reg, &val); |
Line 169... | Line 170... | ||
169 | { |
170 | { |
170 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU, |
171 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU, |
171 | SB_CRWRDA_NP, reg, &val); |
172 | SB_CRWRDA_NP, reg, &val); |
172 | } |
173 | } |
Line 173... | Line -... | ||
173 | - | ||
174 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) |
- | |
175 | { |
- | |
176 | u32 val = 0; |
- | |
177 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE, |
- | |
178 | SB_CRRDDA_NP, reg, &val); |
- | |
179 | return val; |
- | |
180 | } |
- | |
181 | - | ||
182 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
- | |
183 | { |
- | |
184 | vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE, |
- | |
185 | SB_CRWRDA_NP, reg, &val); |
- | |
186 | } |
- | |
187 | 174 | ||
188 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) |
175 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) |
189 | { |
176 | { |
Line 190... | Line 177... | ||
190 | u32 val = 0; |
177 | u32 val = 0; |