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Rev 5060 Rev 6084
Line 47... Line 47...
47 
 
 47 
 
48 
	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
 48 
	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
49 
		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
 49 
		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
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		(bar << IOSF_BAR_SHIFT);
 50 
		(bar << IOSF_BAR_SHIFT);
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51 
 
 51 
 
52 
	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 52 
	WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
53 
 
 53 
 
54 
	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
 54 
	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
Line 73... Line 73...
73 
	I915_WRITE(VLV_IOSF_DATA, 0);
 73 
	I915_WRITE(VLV_IOSF_DATA, 0);
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74 
 
 74 
 
75 
	return 0;
 75 
	return 0;
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}
 76 
}
77 
 
 77 
 
78 
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
 78 
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
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{
 79 
{
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	u32 val = 0;
 80 
	u32 val = 0;
81 
 
 81 
 
82 
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 82 
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
83 
 
 83 
 
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	mutex_lock(&dev_priv->dpio_lock);
 84 
	mutex_lock(&dev_priv->sb_lock);
85 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
 85 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
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			SB_CRRDDA_NP, addr, &val);
 86 
			SB_CRRDDA_NP, addr, &val);
87 
	mutex_unlock(&dev_priv->dpio_lock);
 87 
	mutex_unlock(&dev_priv->sb_lock);
88 
 
 88 
 
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	return val;
 89 
	return val;
90 
}
 90 
}
91 
 
 91 
 
92 
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
 92 
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
93 
{
 93 
{
Line 94... Line 94...
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	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 94 
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
95 
 
 95 
 
96 
	mutex_lock(&dev_priv->dpio_lock);
 96 
	mutex_lock(&dev_priv->sb_lock);
Line 97... Line 97...
97 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
 97 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
98 
			SB_CRWRDA_NP, addr, &val);
 98 
			SB_CRWRDA_NP, addr, &val);
Line 99... Line 99...
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	mutex_unlock(&dev_priv->dpio_lock);
 99 
	mutex_unlock(&dev_priv->sb_lock);
100 
}
 100 
}
Line 101... Line 101...
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 101 
 
102 
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
 102 
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
103 
{
 103 
{
104 
	u32 val = 0;
 104 
	u32 val = 0;
105 
 
 105 
 
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
 106 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
107 
			SB_CRRDDA_NP, reg, &val);
 107 
			SB_CRRDDA_NP, reg, &val);
108 
 
 108 
 
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109 
	return val;
 109 
	return val;
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}
 110 
}
111 
 
 111 
 
112 
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 112 
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
113 
{
 113 
{
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
 114 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
115 
			SB_CRWRDA_NP, reg, &val);
 115 
			SB_CRWRDA_NP, reg, &val);
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116 
}
 116 
}
117 
 
 117 
 
118 
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 118 
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
119 
{
 119 
{
120 
	u32 val = 0;
 120 
	u32 val = 0;
121 
 
 121 
 
122 
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 122 
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
Line 123... Line 123...
123 
 
 123 
 
124 
	mutex_lock(&dev_priv->dpio_lock);
 124 
	mutex_lock(&dev_priv->sb_lock);
125 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
 125 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
126 
			SB_CRRDDA_NP, addr, &val);
 126 
			SB_CRRDDA_NP, addr, &val);
127 
	mutex_unlock(&dev_priv->dpio_lock);
 127 
	mutex_unlock(&dev_priv->sb_lock);
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 128 
 
129 
	return val;
 129 
	return val;
130 
}
 130 
}
131 
 
 131 
 
132 
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
 132 
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
133 
{
 133 
{
134 
	u32 val = 0;
 134 
	u32 val = 0;
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
 135 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
136 
			SB_CRRDDA_NP, reg, &val);
 136 
			SB_CRRDDA_NP, reg, &val);
137 
	return val;
 137 
	return val;
138 
}
 138 
}
139 
 
 139 
 
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void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 140 
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
141 
{
 141 
{
142 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
 142 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
143 
			SB_CRWRDA_NP, reg, &val);
 143 
			SB_CRWRDA_NP, reg, &val);
144 
}
 144 
}
145 
 
 145 
 
146 
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
 146 
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
Line 147... Line 147...
147 
{
 147 
{
148 
	u32 val = 0;
 148 
	u32 val = 0;
149 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
 149 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
150 
			SB_CRRDDA_NP, reg, &val);
 150 
			SB_CRRDDA_NP, reg, &val);
151 
	return val;
 151 
	return val;
Line 152... Line 152...
152 
}
 152 
}
153 
 
 153 
 
154 
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 154 
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
155 
{
 155 
{
156 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
 156 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
157 
			SB_CRWRDA_NP, reg, &val);
 157 
			SB_CRWRDA_NP, reg, &val);
158 
}
 158 
}
Line 159... Line 159...
159 
 
 159 
 
160 
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
 160 
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
161 
{
 161 
{
162 
	u32 val = 0;
 162 
	u32 val = 0;
163 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
 163 
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
Line 164... Line 164...
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			SB_CRRDDA_NP, reg, &val);
 164 
			SB_CRRDDA_NP, reg, &val);
165 
	return val;
 165 
	return val;
Line 211... Line 211...
211 
/* SBI access */
 211 
/* SBI access */
212 
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
 212 
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
213 
		   enum intel_sbi_destination destination)
 213 
		   enum intel_sbi_destination destination)
214 
{
 214 
{
215 
	u32 value = 0;
 215 
	u32 value = 0;
216 
	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 216 
	WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
Line 217... Line 217...
217 
 
 217 
 
218 
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
 218 
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
219 
				100)) {
 219 
				100)) {
220 
		DRM_ERROR("timeout waiting for SBI to become ready\n");
 220 
		DRM_ERROR("timeout waiting for SBI to become ready\n");
Line 241... Line 241...
241 
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 241 
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
242 
		     enum intel_sbi_destination destination)
 242 
		     enum intel_sbi_destination destination)
243 
{
 243 
{
244 
	u32 tmp;
 244 
	u32 tmp;
Line 245... Line 245...
245 
 
 245 
 
Line 246... Line 246...
246 
	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 246 
	WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
247 
 
 247 
 
248 
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
 248 
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
249 
				100)) {
 249 
				100)) {