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Rev 4104 Rev 4560
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 */
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 */
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#include "i915_drv.h"
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include "intel_drv.h"
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/*
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 * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
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 * VLV_VLV2_PUNIT_HAS_0.8.docx
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/* IOSF sideband */
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 */
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static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
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static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
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			   u32 port, u32 opcode, u32 addr, u32 *val)
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			   u32 port, u32 opcode, u32 addr, u32 *val)
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{
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{
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
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			PUNIT_OPCODE_REG_WRITE, addr, &val);
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			PUNIT_OPCODE_REG_WRITE, addr, &val);
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	mutex_unlock(&dev_priv->dpio_lock);
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	mutex_unlock(&dev_priv->dpio_lock);
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}
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}
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u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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	u32 val = 0;
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
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			PUNIT_OPCODE_REG_READ, reg, &val);
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	return val;
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}
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void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
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			PUNIT_OPCODE_REG_WRITE, reg, &val);
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}
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u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
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u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
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{
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{
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	u32 val = 0;
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	u32 val = 0;
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	mutex_unlock(&dev_priv->dpio_lock);
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	mutex_unlock(&dev_priv->dpio_lock);
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	return val;
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	return val;
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}
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}
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u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
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u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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	u32 val = 0;
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
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			PUNIT_OPCODE_REG_READ, reg, &val);
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	return val;
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}
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{
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- 
 
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void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
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			PUNIT_OPCODE_REG_WRITE, reg, &val);
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}
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u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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	u32 val = 0;
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
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			PUNIT_OPCODE_REG_READ, reg, &val);
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	return val;
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}
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void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
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			PUNIT_OPCODE_REG_WRITE, reg, &val);
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}
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u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
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	u32 val = 0;
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{
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	u32 val = 0;
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
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			PUNIT_OPCODE_REG_READ, reg, &val);
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	return val;
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}
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void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
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			PUNIT_OPCODE_REG_WRITE, reg, &val);
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}
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u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
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	u32 val = 0;
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			DPIO_OPCODE_REG_READ, reg, &val);
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
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			PUNIT_OPCODE_REG_READ, reg, &val);
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	return val;
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	return val;
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}
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void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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{
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	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
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			PUNIT_OPCODE_REG_WRITE, reg, &val);
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}
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u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
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{
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	u32 val = 0;
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	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
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			DPIO_OPCODE_REG_READ, reg, &val);
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	return val;
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}
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}
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void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
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void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
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{
 189 
{
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				100)) {
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				100)) {
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		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
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		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
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		return;
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		return;
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	}
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	}
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}
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}
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u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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	u32 val = 0;
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	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
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					DPIO_OPCODE_REG_READ, reg, &val);
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	return val;
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 259 
}
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void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
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 262 
{
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 263 
	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
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					DPIO_OPCODE_REG_WRITE, reg, &val);
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}