Rev 6937 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6937 | Rev 7144 | ||
|---|---|---|---|
| Line 91... | Line 91... | ||
| 91 | u64 max_acthd; |
91 | u64 max_acthd; |
| 92 | u32 seqno; |
92 | u32 seqno; |
| 93 | int score; |
93 | int score; |
| 94 | enum intel_ring_hangcheck_action action; |
94 | enum intel_ring_hangcheck_action action; |
| 95 | int deadlock; |
95 | int deadlock; |
| - | 96 | u32 instdone[I915_NUM_INSTDONE_REG]; |
|
| 96 | }; |
97 | }; |
| Line 97... | Line 98... | ||
| 97 | 98 | ||
| 98 | struct intel_ringbuffer { |
99 | struct intel_ringbuffer { |
| 99 | struct drm_i915_gem_object *obj; |
100 | struct drm_i915_gem_object *obj; |
| - | 101 | void __iomem *virtual_start; |
|
| Line 100... | Line 102... | ||
| 100 | void __iomem *virtual_start; |
102 | struct i915_vma *vma; |
| 101 | 103 | ||
| Line 102... | Line 104... | ||
| 102 | struct intel_engine_cs *ring; |
104 | struct intel_engine_cs *ring; |
| Line 145... | Line 147... | ||
| 145 | }; |
147 | }; |
| Line 146... | Line 148... | ||
| 146 | 148 | ||
| 147 | struct intel_engine_cs { |
149 | struct intel_engine_cs { |
| 148 | const char *name; |
150 | const char *name; |
| 149 | enum intel_ring_id { |
151 | enum intel_ring_id { |
| 150 | RCS = 0x0, |
- | |
| 151 | VCS, |
152 | RCS = 0, |
| 152 | BCS, |
153 | BCS, |
| - | 154 | VCS, |
|
| 153 | VECS, |
155 | VCS2, /* Keep instances of the same type engine together. */ |
| 154 | VCS2 |
156 | VECS |
| 155 | } id; |
157 | } id; |
| 156 | #define I915_NUM_RINGS 5 |
158 | #define I915_NUM_RINGS 5 |
| - | 159 | #define _VCS(n) (VCS + (n)) |
|
| - | 160 | unsigned int exec_id; |
|
| 157 | #define LAST_USER_RING (VECS + 1) |
161 | unsigned int guc_id; |
| 158 | u32 mmio_base; |
162 | u32 mmio_base; |
| 159 | struct drm_device *dev; |
163 | struct drm_device *dev; |
| 160 | struct intel_ringbuffer *buffer; |
164 | struct intel_ringbuffer *buffer; |
| Line 266... | Line 270... | ||
| 266 | /* Execlists */ |
270 | /* Execlists */ |
| 267 | spinlock_t execlist_lock; |
271 | spinlock_t execlist_lock; |
| 268 | struct list_head execlist_queue; |
272 | struct list_head execlist_queue; |
| 269 | struct list_head execlist_retired_req_list; |
273 | struct list_head execlist_retired_req_list; |
| 270 | u8 next_context_status_buffer; |
274 | u8 next_context_status_buffer; |
| - | 275 | bool disable_lite_restore_wa; |
|
| - | 276 | u32 ctx_desc_template; |
|
| 271 | u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ |
277 | u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ |
| 272 | int (*emit_request)(struct drm_i915_gem_request *request); |
278 | int (*emit_request)(struct drm_i915_gem_request *request); |
| 273 | int (*emit_flush)(struct drm_i915_gem_request *request, |
279 | int (*emit_flush)(struct drm_i915_gem_request *request, |
| 274 | u32 invalidate_domains, |
280 | u32 invalidate_domains, |
| 275 | u32 flush_domains); |
281 | u32 flush_domains); |
| Line 303... | Line 309... | ||
| 303 | 309 | ||
| Line 304... | Line 310... | ||
| 304 | bool gpu_caches_dirty; |
310 | bool gpu_caches_dirty; |
| Line 305... | Line -... | ||
| 305 | - | ||
| 306 | wait_queue_head_t irq_queue; |
311 | |
| Line 307... | Line 312... | ||
| 307 | 312 | wait_queue_head_t irq_queue; |
|
| Line 308... | Line 313... | ||
| 308 | struct intel_context *default_context; |
313 | |
| Line 404... | Line 409... | ||
| 404 | int reg, u32 value) |
409 | int reg, u32 value) |
| 405 | { |
410 | { |
| 406 | ring->status_page.page_addr[reg] = value; |
411 | ring->status_page.page_addr[reg] = value; |
| 407 | } |
412 | } |
| Line 408... | Line 413... | ||
| 408 | 413 | ||
| 409 | /** |
414 | /* |
| 410 | * Reads a dword out of the status page, which is written to from the command |
415 | * Reads a dword out of the status page, which is written to from the command |
| 411 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
416 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
| 412 | * MI_STORE_DATA_IMM. |
417 | * MI_STORE_DATA_IMM. |
| 413 | * |
418 | * |
| Line 421... | Line 426... | ||
| 421 | * 0x20-0x2f: Reserved (Gen6+) |
426 | * 0x20-0x2f: Reserved (Gen6+) |
| 422 | * |
427 | * |
| 423 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
428 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
| 424 | */ |
429 | */ |
| 425 | #define I915_GEM_HWS_INDEX 0x30 |
430 | #define I915_GEM_HWS_INDEX 0x30 |
| - | 431 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
|
| 426 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
432 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
| 427 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
433 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
| Line 428... | Line 434... | ||
| 428 | 434 | ||
| 429 | struct intel_ringbuffer * |
435 | struct intel_ringbuffer * |