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Rev 3480 Rev 4104
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
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#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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enum intel_ring_hangcheck_action {
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	HANGCHECK_WAIT,
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	HANGCHECK_ACTIVE,
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	HANGCHECK_KICK,
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	HANGCHECK_HUNG,
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};
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struct intel_ring_hangcheck {
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	bool deadlock;
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	u32 seqno;
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#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
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	u32 acthd;
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	int score;
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#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
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	enum intel_ring_hangcheck_action action;
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#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
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};
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struct  intel_ring_buffer {
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struct  intel_ring_buffer {
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	const char	*name;
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	const char	*name;
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	enum intel_ring_id {
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	enum intel_ring_id {
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		RCS = 0x0,
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		RCS = 0x0,
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		VCS,
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		VCS,
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		BCS,
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		BCS,
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		VECS,
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	} id;
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	} id;
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#define I915_NUM_RINGS 3
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#define I915_NUM_RINGS 4
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	u32		mmio_base;
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	u32		mmio_base;
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	 * last_retired_head is set to -1 after the value is consumed so
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	 * last_retired_head is set to -1 after the value is consumed so
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	 * we can detect new retirements.
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	 * we can detect new retirements.
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	 */
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	 */
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	u32		last_retired_head;
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	u32		last_retired_head;
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	u32		irq_refcount;		/* protected by dev_priv->irq_lock */
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	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
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	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
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	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
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	u32		trace_irq_seqno;
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	u32		trace_irq_seqno;
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	u32		sync_seqno[I915_NUM_RINGS-1];
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	u32		sync_seqno[I915_NUM_RINGS-1];
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	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
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	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
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	void		(*cleanup)(struct intel_ring_buffer *ring);
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	void		(*cleanup)(struct intel_ring_buffer *ring);
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	int		(*sync_to)(struct intel_ring_buffer *ring,
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	int		(*sync_to)(struct intel_ring_buffer *ring,
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				   struct intel_ring_buffer *to,
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				   struct intel_ring_buffer *to,
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				   u32 seqno);
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				   u32 seqno);
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	/* our mbox written by others */
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	u32		semaphore_register[3]; /*our mbox written by others */
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	u32		semaphore_register[I915_NUM_RINGS];
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	/* mboxes this ring signals to */
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	u32		signal_mbox[I915_NUM_RINGS];
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	u32		signal_mbox[2]; /* mboxes this ring signals to */
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	/**
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	/**
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	 * List of objects currently involved in rendering from the
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	 * List of objects currently involved in rendering from the
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	 * ringbuffer.
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	 * ringbuffer.
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	 *
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	 *
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	/**
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	/**
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	 * Do we have some not yet emitted requests outstanding?
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	 * Do we have some not yet emitted requests outstanding?
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	 */
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	 */
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	u32 outstanding_lazy_request;
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	u32 outstanding_lazy_request;
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	bool gpu_caches_dirty;
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	bool gpu_caches_dirty;
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	bool fbc_dirty;
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	wait_queue_head_t irq_queue;
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	wait_queue_head_t irq_queue;
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	/**
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	/**
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	 * Do an explicit TLB flush before MI_SET_CONTEXT
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	 * Do an explicit TLB flush before MI_SET_CONTEXT
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	 */
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	 */
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	bool itlb_before_ctx_switch;
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	bool itlb_before_ctx_switch;
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	struct i915_hw_context *default_context;
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	struct i915_hw_context *last_context;
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	struct intel_ring_hangcheck hangcheck;
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	struct {
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	struct i915_hw_context *default_context;
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		struct drm_i915_gem_object *obj;
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	struct drm_i915_gem_object *last_context_obj;
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		u32 gtt_offset;
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		volatile u32 *cpu_page;
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	void *private;
 162 
	} scratch;
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};
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};
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int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
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int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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int intel_init_blt_ring_buffer(struct drm_device *dev);
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int intel_init_blt_ring_buffer(struct drm_device *dev);
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int intel_init_vebox_ring_buffer(struct drm_device *dev);
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u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
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u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);