Rev 6937 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 6937 | Rev 7144 | ||
---|---|---|---|
Line 744... | Line 744... | ||
744 | if (ret != 0) |
744 | if (ret != 0) |
745 | return ret; |
745 | return ret; |
Line 746... | Line 746... | ||
746 | 746 | ||
747 | ret = i915_gem_render_state_init(req); |
747 | ret = i915_gem_render_state_init(req); |
748 | if (ret) |
- | |
749 | DRM_ERROR("init render state: %d\n", ret); |
- | |
750 | 748 | if (ret) |
|
- | 749 | return ret; |
|
- | 750 | ||
751 | return ret; |
751 | return 0; |
Line 752... | Line 752... | ||
752 | } |
752 | } |
753 | 753 | ||
754 | static int wa_add(struct drm_i915_private *dev_priv, |
754 | static int wa_add(struct drm_i915_private *dev_priv, |
Line 787... | Line 787... | ||
787 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
787 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
788 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) |
788 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) |
Line 789... | Line 789... | ||
789 | 789 | ||
Line -... | Line 790... | ||
- | 790 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
|
- | 791 | ||
- | 792 | static int wa_ring_whitelist_reg(struct intel_engine_cs *ring, i915_reg_t reg) |
|
- | 793 | { |
|
- | 794 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
|
- | 795 | struct i915_workarounds *wa = &dev_priv->workarounds; |
|
- | 796 | const uint32_t index = wa->hw_whitelist_count[ring->id]; |
|
- | 797 | ||
- | 798 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) |
|
- | 799 | return -EINVAL; |
|
- | 800 | ||
- | 801 | WA_WRITE(RING_FORCE_TO_NONPRIV(ring->mmio_base, index), |
|
- | 802 | i915_mmio_reg_offset(reg)); |
|
- | 803 | wa->hw_whitelist_count[ring->id]++; |
|
- | 804 | ||
- | 805 | return 0; |
|
790 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
806 | } |
791 | 807 | ||
792 | static int gen8_init_workarounds(struct intel_engine_cs *ring) |
808 | static int gen8_init_workarounds(struct intel_engine_cs *ring) |
793 | { |
809 | { |
Line 892... | Line 908... | ||
892 | static int gen9_init_workarounds(struct intel_engine_cs *ring) |
908 | static int gen9_init_workarounds(struct intel_engine_cs *ring) |
893 | { |
909 | { |
894 | struct drm_device *dev = ring->dev; |
910 | struct drm_device *dev = ring->dev; |
895 | struct drm_i915_private *dev_priv = dev->dev_private; |
911 | struct drm_i915_private *dev_priv = dev->dev_private; |
896 | uint32_t tmp; |
912 | uint32_t tmp; |
- | 913 | int ret; |
|
Line 897... | Line 914... | ||
897 | 914 | ||
898 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
915 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
899 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
916 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
Line 962... | Line 979... | ||
962 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
979 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
Line 963... | Line 980... | ||
963 | 980 | ||
964 | /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
981 | /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
Line -... | Line 982... | ||
- | 982 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
|
- | 983 | ||
- | 984 | /* WaOCLCoherentLineFlush:skl,bxt */ |
|
- | 985 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
|
- | 986 | GEN8_LQSC_FLUSH_COHERENT_LINES)); |
|
- | 987 | ||
- | 988 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ |
|
- | 989 | ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1); |
|
- | 990 | if (ret) |
|
- | 991 | return ret; |
|
- | 992 | ||
- | 993 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt */ |
|
- | 994 | ret = wa_ring_whitelist_reg(ring, GEN8_HDC_CHICKEN1); |
|
- | 995 | if (ret) |
|
965 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
996 | return ret; |
966 | 997 | ||
Line 967... | Line 998... | ||
967 | return 0; |
998 | return 0; |
968 | } |
999 | } |
Line 1017... | Line 1048... | ||
1017 | 1048 | ||
1018 | ret = gen9_init_workarounds(ring); |
1049 | ret = gen9_init_workarounds(ring); |
1019 | if (ret) |
1050 | if (ret) |
Line -... | Line 1051... | ||
- | 1051 | return ret; |
|
- | 1052 | ||
- | 1053 | /* |
|
- | 1054 | * Actual WA is to disable percontext preemption granularity control |
|
- | 1055 | * until D0 which is the default case so this is equivalent to |
|
- | 1056 | * !WaDisablePerCtxtPreemptionGranularityControl:skl |
|
- | 1057 | */ |
|
- | 1058 | if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { |
|
- | 1059 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
|
- | 1060 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); |
|
1020 | return ret; |
1061 | } |
1021 | 1062 | ||
1022 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
1063 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
1023 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1064 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1024 | I915_WRITE(FF_SLICE_CS_CHICKEN2, |
1065 | I915_WRITE(FF_SLICE_CS_CHICKEN2, |
Line 1070... | Line 1111... | ||
1070 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
1111 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
1071 | WA_SET_BIT_MASKED( |
1112 | WA_SET_BIT_MASKED( |
1072 | GEN7_HALF_SLICE_CHICKEN1, |
1113 | GEN7_HALF_SLICE_CHICKEN1, |
1073 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
1114 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
Line -... | Line 1115... | ||
- | 1115 | ||
- | 1116 | /* WaDisableLSQCROPERFforOCL:skl */ |
|
- | 1117 | ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4); |
|
- | 1118 | if (ret) |
|
- | 1119 | return ret; |
|
1074 | 1120 | ||
1075 | return skl_tune_iz_hashing(ring); |
1121 | return skl_tune_iz_hashing(ring); |
Line 1076... | Line 1122... | ||
1076 | } |
1122 | } |
1077 | 1123 | ||
Line 1105... | Line 1151... | ||
1105 | WA_SET_BIT_MASKED( |
1151 | WA_SET_BIT_MASKED( |
1106 | GEN7_HALF_SLICE_CHICKEN1, |
1152 | GEN7_HALF_SLICE_CHICKEN1, |
1107 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
1153 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
1108 | } |
1154 | } |
Line -... | Line 1155... | ||
- | 1155 | ||
- | 1156 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
|
- | 1157 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ |
|
- | 1158 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ |
|
- | 1159 | /* WaDisableLSQCROPERFforOCL:bxt */ |
|
- | 1160 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
|
- | 1161 | ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1); |
|
- | 1162 | if (ret) |
|
- | 1163 | return ret; |
|
- | 1164 | ||
- | 1165 | ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4); |
|
- | 1166 | if (ret) |
|
- | 1167 | return ret; |
|
- | 1168 | } |
|
1109 | 1169 | ||
1110 | return 0; |
1170 | return 0; |
Line 1111... | Line 1171... | ||
1111 | } |
1171 | } |
1112 | 1172 | ||
Line 1116... | Line 1176... | ||
1116 | struct drm_i915_private *dev_priv = dev->dev_private; |
1176 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1117... | Line 1177... | ||
1117 | 1177 | ||
Line 1118... | Line 1178... | ||
1118 | WARN_ON(ring->id != RCS); |
1178 | WARN_ON(ring->id != RCS); |
- | 1179 | ||
Line 1119... | Line 1180... | ||
1119 | 1180 | dev_priv->workarounds.count = 0; |
|
1120 | dev_priv->workarounds.count = 0; |
1181 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
Line 1121... | Line 1182... | ||
1121 | 1182 | ||
Line 1866... | Line 1927... | ||
1866 | 1927 | ||
1867 | /* ... and execute it. */ |
1928 | /* ... and execute it. */ |
1868 | offset = cs_offset; |
1929 | offset = cs_offset; |
Line 1869... | Line 1930... | ||
1869 | } |
1930 | } |
1870 | 1931 | ||
1871 | ret = intel_ring_begin(req, 4); |
1932 | ret = intel_ring_begin(req, 2); |
Line 1872... | Line 1933... | ||
1872 | if (ret) |
1933 | if (ret) |
1873 | return ret; |
1934 | return ret; |
1874 | 1935 | ||
1875 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
- | |
1876 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
- | |
1877 | 0 : MI_BATCH_NON_SECURE)); |
1936 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Line 1878... | Line 1937... | ||
1878 | intel_ring_emit(ring, offset + len - 8); |
1937 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
1879 | intel_ring_emit(ring, MI_NOOP); |
1938 | 0 : MI_BATCH_NON_SECURE)); |
Line 1995... | Line 2054... | ||
1995 | return 0; |
2054 | return 0; |
1996 | } |
2055 | } |
Line 1997... | Line 2056... | ||
1997 | 2056 | ||
1998 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2057 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
- | 2058 | { |
|
- | 2059 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
|
- | 2060 | vunmap(ringbuf->virtual_start); |
|
1999 | { |
2061 | else |
2000 | iounmap(ringbuf->virtual_start); |
2062 | iounmap(ringbuf->virtual_start); |
- | 2063 | ringbuf->virtual_start = NULL; |
|
2001 | ringbuf->virtual_start = NULL; |
2064 | ringbuf->vma = NULL; |
2002 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
2065 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
Line -... | Line 2066... | ||
- | 2066 | } |
|
- | 2067 | ||
- | 2068 | static u32 *vmap_obj(struct drm_i915_gem_object *obj) |
|
- | 2069 | { |
|
- | 2070 | struct sg_page_iter sg_iter; |
|
- | 2071 | struct page **pages; |
|
- | 2072 | void *addr; |
|
- | 2073 | int i; |
|
- | 2074 | ||
- | 2075 | pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); |
|
- | 2076 | if (pages == NULL) |
|
- | 2077 | return NULL; |
|
- | 2078 | ||
- | 2079 | i = 0; |
|
- | 2080 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) |
|
- | 2081 | pages[i++] = sg_page_iter_page(&sg_iter); |
|
- | 2082 | ||
- | 2083 | addr = vmap(pages, i, 0, PAGE_KERNEL); |
|
- | 2084 | drm_free_large(pages); |
|
- | 2085 | ||
- | 2086 | return addr; |
|
2003 | } |
2087 | } |
2004 | 2088 | ||
2005 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
2089 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
2006 | struct intel_ringbuffer *ringbuf) |
2090 | struct intel_ringbuffer *ringbuf) |
2007 | { |
2091 | { |
2008 | struct drm_i915_private *dev_priv = to_i915(dev); |
2092 | struct drm_i915_private *dev_priv = to_i915(dev); |
2009 | struct drm_i915_gem_object *obj = ringbuf->obj; |
2093 | struct drm_i915_gem_object *obj = ringbuf->obj; |
2010 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2094 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
Line -... | Line 2095... | ||
- | 2095 | unsigned flags = PIN_OFFSET_BIAS | 4096; |
|
2011 | unsigned flags = PIN_OFFSET_BIAS | 4096; |
2096 | int ret; |
- | 2097 | ||
- | 2098 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
|
- | 2099 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
|
- | 2100 | if (ret) |
|
- | 2101 | return ret; |
|
- | 2102 | ||
- | 2103 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
|
- | 2104 | if (ret) { |
|
- | 2105 | i915_gem_object_ggtt_unpin(obj); |
|
- | 2106 | return ret; |
|
- | 2107 | } |
|
- | 2108 | ||
- | 2109 | ringbuf->virtual_start = vmap_obj(obj); |
|
- | 2110 | if (ringbuf->virtual_start == NULL) { |
|
- | 2111 | i915_gem_object_ggtt_unpin(obj); |
|
- | 2112 | return -ENOMEM; |
|
- | 2113 | } |
|
2012 | int ret; |
2114 | } else { |
2013 | 2115 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
|
Line 2014... | Line 2116... | ||
2014 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
2116 | flags | PIN_MAPPABLE); |
2015 | if (ret) |
2117 | if (ret) |
2016 | return ret; |
2118 | return ret; |
2017 | 2119 | ||
2018 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
2120 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
Line -... | Line 2121... | ||
- | 2121 | if (ret) { |
|
- | 2122 | i915_gem_object_ggtt_unpin(obj); |
|
- | 2123 | return ret; |
|
2019 | if (ret) { |
2124 | } |
2020 | i915_gem_object_ggtt_unpin(obj); |
2125 | |
2021 | return ret; |
2126 | /* Access through the GTT requires the device to be awake. */ |
2022 | } |
2127 | assert_rpm_wakelock_held(dev_priv); |
2023 | 2128 | ||
2024 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + |
2129 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + |
- | 2130 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); |
|
- | 2131 | if (ringbuf->virtual_start == NULL) { |
|
- | 2132 | i915_gem_object_ggtt_unpin(obj); |
|
Line 2025... | Line 2133... | ||
2025 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); |
2133 | return -EINVAL; |
2026 | if (ringbuf->virtual_start == NULL) { |
2134 | } |
Line 2027... | Line 2135... | ||
2027 | i915_gem_object_ggtt_unpin(obj); |
2135 | } |
Line 2641... | Line 2749... | ||
2641 | struct drm_i915_gem_object *obj; |
2749 | struct drm_i915_gem_object *obj; |
2642 | int ret; |
2750 | int ret; |
Line 2643... | Line 2751... | ||
2643 | 2751 | ||
2644 | ring->name = "render ring"; |
2752 | ring->name = "render ring"; |
- | 2753 | ring->id = RCS; |
|
2645 | ring->id = RCS; |
2754 | ring->exec_id = I915_EXEC_RENDER; |
Line 2646... | Line 2755... | ||
2646 | ring->mmio_base = RENDER_RING_BASE; |
2755 | ring->mmio_base = RENDER_RING_BASE; |
2647 | 2756 | ||
2648 | if (INTEL_INFO(dev)->gen >= 8) { |
2757 | if (INTEL_INFO(dev)->gen >= 8) { |
Line 2789... | Line 2898... | ||
2789 | struct drm_i915_private *dev_priv = dev->dev_private; |
2898 | struct drm_i915_private *dev_priv = dev->dev_private; |
2790 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
2899 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
Line 2791... | Line 2900... | ||
2791 | 2900 | ||
2792 | ring->name = "bsd ring"; |
2901 | ring->name = "bsd ring"; |
- | 2902 | ring->id = VCS; |
|
Line 2793... | Line 2903... | ||
2793 | ring->id = VCS; |
2903 | ring->exec_id = I915_EXEC_BSD; |
2794 | 2904 | ||
2795 | ring->write_tail = ring_write_tail; |
2905 | ring->write_tail = ring_write_tail; |
2796 | if (INTEL_INFO(dev)->gen >= 6) { |
2906 | if (INTEL_INFO(dev)->gen >= 6) { |
Line 2865... | Line 2975... | ||
2865 | struct drm_i915_private *dev_priv = dev->dev_private; |
2975 | struct drm_i915_private *dev_priv = dev->dev_private; |
2866 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
2976 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
Line 2867... | Line 2977... | ||
2867 | 2977 | ||
2868 | ring->name = "bsd2 ring"; |
2978 | ring->name = "bsd2 ring"; |
- | 2979 | ring->id = VCS2; |
|
Line 2869... | Line 2980... | ||
2869 | ring->id = VCS2; |
2980 | ring->exec_id = I915_EXEC_BSD; |
2870 | 2981 | ||
2871 | ring->write_tail = ring_write_tail; |
2982 | ring->write_tail = ring_write_tail; |
2872 | ring->mmio_base = GEN8_BSD2_RING_BASE; |
2983 | ring->mmio_base = GEN8_BSD2_RING_BASE; |
Line 2895... | Line 3006... | ||
2895 | struct drm_i915_private *dev_priv = dev->dev_private; |
3006 | struct drm_i915_private *dev_priv = dev->dev_private; |
2896 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
3007 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
Line 2897... | Line 3008... | ||
2897 | 3008 | ||
2898 | ring->name = "blitter ring"; |
3009 | ring->name = "blitter ring"; |
- | 3010 | ring->id = BCS; |
|
Line 2899... | Line 3011... | ||
2899 | ring->id = BCS; |
3011 | ring->exec_id = I915_EXEC_BLT; |
2900 | 3012 | ||
2901 | ring->mmio_base = BLT_RING_BASE; |
3013 | ring->mmio_base = BLT_RING_BASE; |
2902 | ring->write_tail = ring_write_tail; |
3014 | ring->write_tail = ring_write_tail; |
Line 2952... | Line 3064... | ||
2952 | struct drm_i915_private *dev_priv = dev->dev_private; |
3064 | struct drm_i915_private *dev_priv = dev->dev_private; |
2953 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
3065 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
Line 2954... | Line 3066... | ||
2954 | 3066 | ||
2955 | ring->name = "video enhancement ring"; |
3067 | ring->name = "video enhancement ring"; |
- | 3068 | ring->id = VECS; |
|
Line 2956... | Line 3069... | ||
2956 | ring->id = VECS; |
3069 | ring->exec_id = I915_EXEC_VEBOX; |
2957 | 3070 | ||
2958 | ring->mmio_base = VEBOX_RING_BASE; |
3071 | ring->mmio_base = VEBOX_RING_BASE; |
2959 | ring->write_tail = ring_write_tail; |
3072 | ring->write_tail = ring_write_tail; |