Rev 5060 | Rev 5139 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 5060 | Rev 5128 | ||
|---|---|---|---|
| Line 673... | Line 673... | ||
| 673 | } |
673 | } |
| Line 674... | Line 674... | ||
| 674 | 674 | ||
| 675 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
675 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
| 676 | { |
676 | { |
| - | 677 | struct drm_device *dev = ring->dev; |
|
| - | 678 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
| - | 679 | ||
| - | 680 | if (dev_priv->semaphore_obj) { |
|
| - | 681 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); |
|
| - | 682 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); |
|
| - | 683 | dev_priv->semaphore_obj = NULL; |
|
| Line 677... | Line 684... | ||
| 677 | struct drm_device *dev = ring->dev; |
684 | } |
| 678 | 685 | ||
| Line 679... | Line 686... | ||
| 679 | if (ring->scratch.obj == NULL) |
686 | if (ring->scratch.obj == NULL) |
| Line 1351... | Line 1358... | ||
| 1351 | return 0; |
1358 | return 0; |
| 1352 | } |
1359 | } |
| Line 1353... | Line 1360... | ||
| 1353 | 1360 | ||
| 1354 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1361 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| - | 1362 | #define I830_BATCH_LIMIT (256*1024) |
|
| - | 1363 | #define I830_TLB_ENTRIES (2) |
|
| 1355 | #define I830_BATCH_LIMIT (256*1024) |
1364 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) |
| 1356 | static int |
1365 | static int |
| 1357 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
1366 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
| 1358 | u64 offset, u32 len, |
1367 | u64 offset, u32 len, |
| 1359 | unsigned flags) |
1368 | unsigned flags) |
| - | 1369 | { |
|
| 1360 | { |
1370 | u32 cs_offset = ring->scratch.gtt_offset; |
| Line 1361... | Line -... | ||
| 1361 | int ret; |
- | |
| 1362 | 1371 | int ret; |
|
| 1363 | if (flags & I915_DISPATCH_PINNED) { |
1372 | |
| 1364 | ret = intel_ring_begin(ring, 4); |
1373 | ret = intel_ring_begin(ring, 6); |
| Line -... | Line 1374... | ||
| - | 1374 | if (ret) |
|
| 1365 | if (ret) |
1375 | return ret; |
| 1366 | return ret; |
1376 | |
| - | 1377 | /* Evict the invalid PTE TLBs */ |
|
| 1367 | 1378 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
|
| - | 1379 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); |
|
| 1368 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1380 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ |
| 1369 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
1381 | intel_ring_emit(ring, cs_offset); |
| 1370 | intel_ring_emit(ring, offset + len - 8); |
- | |
| 1371 | intel_ring_emit(ring, MI_NOOP); |
- | |
| Line -... | Line 1382... | ||
| - | 1382 | intel_ring_emit(ring, 0xdeadbeef); |
|
| 1372 | intel_ring_advance(ring); |
1383 | intel_ring_emit(ring, MI_NOOP); |
| 1373 | } else { |
1384 | intel_ring_advance(ring); |
| Line 1374... | Line 1385... | ||
| 1374 | u32 cs_offset = ring->scratch.gtt_offset; |
1385 | |
| 1375 | 1386 | if ((flags & I915_DISPATCH_PINNED) == 0) { |
|
| 1376 | if (len > I830_BATCH_LIMIT) |
1387 | if (len > I830_BATCH_LIMIT) |
| - | 1388 | return -ENOSPC; |
|
| 1377 | return -ENOSPC; |
1389 | |
| 1378 | 1390 | ret = intel_ring_begin(ring, 6 + 2); |
|
| 1379 | ret = intel_ring_begin(ring, 9+3); |
1391 | if (ret) |
| - | 1392 | return ret; |
|
| 1380 | if (ret) |
1393 | |
| 1381 | return ret; |
- | |
| 1382 | /* Blit the batch (which has now all relocs applied) to the stable batch |
- | |
| 1383 | * scratch bo area (so that the CS never stumbles over its tlb |
1394 | /* Blit the batch (which has now all relocs applied) to the |
| 1384 | * invalidation bug) ... */ |
- | |
| 1385 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
1395 | * stable batch scratch bo area (so that the CS never |
| 1386 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
1396 | * stumbles over its tlb invalidation bug) ... |
| 1387 | XY_SRC_COPY_BLT_WRITE_RGB); |
- | |
| 1388 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
1397 | */ |
| 1389 | intel_ring_emit(ring, 0); |
1398 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
| - | 1399 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
|
| 1390 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
1400 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 1024); |
| - | 1401 | intel_ring_emit(ring, cs_offset); |
|
| - | 1402 | intel_ring_emit(ring, 4096); |
|
| Line 1391... | Line 1403... | ||
| 1391 | intel_ring_emit(ring, cs_offset); |
1403 | intel_ring_emit(ring, offset); |
| - | 1404 | ||
| - | 1405 | intel_ring_emit(ring, MI_FLUSH); |
|
| - | 1406 | intel_ring_emit(ring, MI_NOOP); |
|
| - | 1407 | intel_ring_advance(ring); |
|
| - | 1408 | ||
| - | 1409 | /* ... and execute it. */ |
|
| - | 1410 | offset = cs_offset; |
|
| 1392 | intel_ring_emit(ring, 0); |
1411 | } |
| 1393 | intel_ring_emit(ring, 4096); |
1412 | |
| 1394 | intel_ring_emit(ring, offset); |
1413 | ret = intel_ring_begin(ring, 4); |
| - | 1414 | if (ret) |
|
| 1395 | intel_ring_emit(ring, MI_FLUSH); |
1415 | return ret; |
| 1396 | - | ||
| Line 1397... | Line 1416... | ||
| 1397 | /* ... and execute it. */ |
1416 | |
| 1398 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1417 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| Line 1399... | Line 1418... | ||
| 1399 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
1418 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| Line 2177... | Line 2196... | ||
| 2177 | ring->init = init_render_ring; |
2196 | ring->init = init_render_ring; |
| 2178 | ring->cleanup = render_ring_cleanup; |
2197 | ring->cleanup = render_ring_cleanup; |
| Line 2179... | Line 2198... | ||
| 2179 | 2198 | ||
| 2180 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2199 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 2181 | if (HAS_BROKEN_CS_TLB(dev)) { |
2200 | if (HAS_BROKEN_CS_TLB(dev)) { |
| 2182 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
2201 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
| 2183 | if (obj == NULL) { |
2202 | if (obj == NULL) { |
| 2184 | DRM_ERROR("Failed to allocate batch bo\n"); |
2203 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 2185 | return -ENOMEM; |
2204 | return -ENOMEM; |