WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_ringbuffer.c

 	flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
 		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 		/* Workaround: we must issue a pipe_control with CS-stall bit
 		 * set before a pipe_control command that has the state cache
 		 * invalidate bit set. */
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 	intel_ring_emit(ring, flags);
-	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
+	intel_ring_emit(ring, scratch_addr);
 	intel_ring_emit(ring, 0);
 	intel_ring_advance(ring);
 	pc->gtt_offset = obj->gtt_offset;
 	pc->cpu_page =  (void*)MapIoMem((addr_t)sg_page(obj->pages->sgl),4096, PG_SW);
 	if (pc->cpu_page == NULL)
 		goto err_unpin;
+	DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
+			 ring->name, pc->gtt_offset);
 	pc->obj = obj;
 	ring->private = pc;
 	return 0;
 	return ret;
+}
 static void render_ring_cleanup(struct intel_ring_buffer *ring)
+{
+	struct drm_device *dev = ring->dev;
 	if (!ring->private)
 		return;
 	intel_ring_advance(ring);
 	return 0;
+}
+static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
+					      u32 seqno)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	return dev_priv->last_seqno < seqno;
+}
 /**
  * intel_ring_sync - sync the waiter to the signaller on seqno
+ *
 	ret = intel_ring_begin(waiter, 4);
 	if (ret)
+		return ret;
-		return ret;
+	/* If seqno wrap happened, omit the wait with no-ops */
+	if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
+	intel_ring_emit(waiter,
-	intel_ring_emit(waiter,
+				dw1 |
-			dw1 | signaller->semaphore_register[waiter->id]);
+				signaller->semaphore_register[waiter->id]);
 	intel_ring_emit(waiter, seqno);
+	intel_ring_emit(waiter, 0);
+	intel_ring_emit(waiter, MI_NOOP);
+	} else {
+		intel_ring_emit(waiter, MI_NOOP);
+		intel_ring_emit(waiter, MI_NOOP);
+		intel_ring_emit(waiter, MI_NOOP);
-	intel_ring_emit(waiter, 0);
+		intel_ring_emit(waiter, MI_NOOP);
 	intel_ring_emit(waiter, MI_NOOP);
 	intel_ring_advance(waiter);
 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
+{
 	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
+}
+static void
+ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
+{
+	intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
+}
 static u32
 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
+{
 	struct pipe_control *pc = ring->private;
 	return pc->cpu_page[0];
+}
+static void
+pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
+{
+	struct pipe_control *pc = ring->private;
+	pc->cpu_page[0] = seqno;
+}
 static bool
 gen5_ring_get_irq(struct intel_ring_buffer *ring)
+{
 		ret = init_phys_hws_pga(ring);
 		if (ret)
 			return ret;
+	}
+	obj = NULL;
+	if (!HAS_LLC(dev))
+		obj = i915_gem_object_create_stolen(dev, ring->size);
 	if (obj == NULL)
     obj = i915_gem_alloc_object(dev, ring->size);
 	if (obj == NULL) {
 		DRM_ERROR("Failed to allocate ringbuffer\n");
 		ret = -ENOMEM;
 	ret = i915_gem_object_set_to_gtt_domain(obj, true);
 	if (ret)
 		goto err_unpin;
 	ring->virtual_start =
-        ioremap(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
+		ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
 			   ring->size);
 	if (ring->virtual_start == NULL) {
 		DRM_ERROR("Failed to map ringbuffer.\n");
 		ret = -EINVAL;
 		ring->effective_size -= 128;
 	return 0;
 err_unmap:
-    FreeKernelSpace(ring->virtual_start);
+	iounmap(ring->virtual_start);
 err_unpin:
 	i915_gem_object_unpin(obj);
 err_unref:
 		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 			  ring->name, ret);
 	I915_WRITE_CTL(ring, 0);
-//   drm_core_ioremapfree(&ring->map, ring->dev);
+	iounmap(ring->virtual_start);
 			return 0;
+		}
 		msleep(1);
 		ret = i915_gem_check_wedge(&dev_priv->gpu_error,
-		ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
+					   dev_priv->mm.interruptible);
 		if (ret)
 			return ret;
     } while (!time_after(GetTimerTicks(), end));
 		return 0;
 	return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
+}
+static int __intel_ring_begin(struct intel_ring_buffer *ring,
+			      int bytes)
+{
+	int ret;
+	if (unlikely(ring->tail + bytes > ring->effective_size)) {
+		ret = intel_wrap_ring_buffer(ring);
+		if (unlikely(ret))
+			return ret;
+	}
+	if (unlikely(ring->space < bytes)) {
+		ret = ring_wait_for_space(ring, bytes);
+		if (unlikely(ret))
+			return ret;
+	}
+	ring->space -= bytes;
+	return 0;
+}
 int intel_ring_begin(struct intel_ring_buffer *ring,
 		     int num_dwords)
-{
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
-	int n = 4*num_dwords;
+	drm_i915_private_t *dev_priv = ring->dev->dev_private;
+	int ret;
 	int ret;
 	ret = i915_gem_check_wedge(&dev_priv->gpu_error,
-	ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
+				   dev_priv->mm.interruptible);
 	if (ret)
 		return ret;
 	/* Preallocate the olr before touching the ring */
-	ret = intel_ring_alloc_seqno(ring);
-	if (ret)
-		return ret;
 	ret = intel_ring_alloc_seqno(ring);
+	if (ret)
+		return ret;
-	if (unlikely(ring->tail + n > ring->effective_size)) {
+	return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
-		ret = intel_wrap_ring_buffer(ring);
+}
-		if (unlikely(ret))
+void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
+{
-			return ret;
+	struct drm_i915_private *dev_priv = ring->dev->dev_private;
+	BUG_ON(ring->outstanding_lazy_request);
-	if (unlikely(ring->space < n)) {
 		ret = ring_wait_for_space(ring, n);
-		if (unlikely(ret))
+	if (INTEL_INFO(ring->dev)->gen >= 6) {
-			return ret;
+		I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
 		I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
+	}
-	ring->space -= n;
-	return 0;
+	ring->set_seqno(ring, seqno);
+}
 		ring->flush = gen6_render_ring_flush;
 		ring->irq_get = gen6_ring_get_irq;
 		ring->irq_put = gen6_ring_put_irq;
 		ring->irq_enable_mask = GT_USER_INTERRUPT;
 		ring->get_seqno = gen6_ring_get_seqno;
+		ring->set_seqno = ring_set_seqno;
 		ring->sync_to = gen6_ring_sync;
 		ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
 		ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
 		ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
 		ring->signal_mbox[0] = GEN6_VRSYNC;
 		ring->signal_mbox[1] = GEN6_BRSYNC;
 	} else if (IS_GEN5(dev)) {
        ring->add_request = pc_render_add_request;
 		ring->flush = gen4_render_ring_flush;
 		ring->get_seqno = pc_render_get_seqno;
+		ring->set_seqno = pc_render_set_seqno;
 		ring->irq_get = gen5_ring_get_irq;
 		ring->irq_put = gen5_ring_put_irq;
 		ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
 	} else {
 		ring->add_request = i9xx_add_request;
 		if (INTEL_INFO(dev)->gen < 4)
 			ring->flush = gen2_render_ring_flush;
 		else
 			ring->flush = gen4_render_ring_flush;
 		ring->get_seqno = ring_get_seqno;
+		ring->set_seqno = ring_set_seqno;
 		if (IS_GEN2(dev)) {
 			ring->irq_get = i8xx_ring_get_irq;
 			ring->irq_put = i8xx_ring_put_irq;
 		} else {
 			ring->irq_get = i9xx_ring_get_irq;
 	if (INTEL_INFO(dev)->gen < 4)
 		ring->flush = gen2_render_ring_flush;
 	else
 		ring->flush = gen4_render_ring_flush;
 	ring->get_seqno = ring_get_seqno;
+	ring->set_seqno = ring_set_seqno;
 	if (IS_GEN2(dev)) {
 		ring->irq_get = i8xx_ring_get_irq;
 		ring->irq_put = i8xx_ring_put_irq;
 	} else {
 		ring->irq_get = i9xx_ring_get_irq;
 		if (IS_GEN6(dev))
 			ring->write_tail = gen6_bsd_ring_write_tail;
 		ring->flush = gen6_ring_flush;
 		ring->add_request = gen6_add_request;
 		ring->get_seqno = gen6_ring_get_seqno;
+		ring->set_seqno = ring_set_seqno;
 		ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
 		ring->irq_get = gen6_ring_get_irq;
 		ring->irq_put = gen6_ring_put_irq;
 		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 		ring->sync_to = gen6_ring_sync;
 	} else {
 		ring->mmio_base = BSD_RING_BASE;
 		ring->flush = bsd_ring_flush;
 		ring->add_request = i9xx_add_request;
 		ring->get_seqno = ring_get_seqno;
+		ring->set_seqno = ring_set_seqno;
 		if (IS_GEN5(dev)) {
 			ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
 			ring->irq_get = gen5_ring_get_irq;
 			ring->irq_put = gen5_ring_put_irq;
 		} else {
 	ring->mmio_base = BLT_RING_BASE;
 	ring->write_tail = ring_write_tail;
 	ring->flush = blt_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
+	ring->set_seqno = ring_set_seqno;
 	ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
 	ring->irq_get = gen6_ring_get_irq;
 	ring->irq_put = gen6_ring_put_irq;
 	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	ring->sync_to = gen6_ring_sync;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ringbuffer.c – Rev 3243 → 3480