WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_pm.c

 		return false;
 	return dev_priv->display.fbc_enabled(dev);
-}
+}
 #if 0
 static void intel_fbc_work_fn(struct work_struct *__work)
+{
 	struct intel_fbc_work *work =
 	/* Synchronisation is provided by struct_mutex and checking of
 	 * dev_priv->fbc_work, so we can perform the cancellation
 	 * entirely asynchronously.
 	 */
-	if (cancel_delayed_work(&dev_priv->fbc_work->work))
+//	if (cancel_delayed_work(&dev_priv->fbc_work->work))
 		/* tasklet was killed before being run, clean up */
-		kfree(dev_priv->fbc_work);
+//		kfree(dev_priv->fbc_work);
 	/* Mark the work as no longer wanted so that if it does
 	 * wake-up (because the work was already running and waiting
 	 * for our mutex), it will discover that is no longer
 	 * necessary to run.
 	 */
-	dev_priv->fbc_work = NULL;
 	dev_priv->fbc_work = NULL;
 #endif
 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
+{
 	struct intel_fbc_work *work;
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-//   if (!dev_priv->display.enable_fbc)
+	if (!dev_priv->display.enable_fbc)
 		return;
 #if 0
 	 * following the termination of the page-flipping sequence
 	 * and indeed performing the enable as a co-routine and not
 	 * waiting synchronously upon the vblank.
 	 */
 	schedule_delayed_work(&work->work, msecs_to_jiffies(50));
-#endif
+}
 void intel_disable_fbc(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-//   intel_cancel_fbc_work(dev_priv);
+	intel_cancel_fbc_work(dev_priv);
-//   if (!dev_priv->display.disable_fbc)
+	if (!dev_priv->display.disable_fbc)
-//       return;
+		return;
-//   dev_priv->display.disable_fbc(dev);
+	dev_priv->display.disable_fbc(dev);
 	struct drm_framebuffer *fb;
 	struct intel_framebuffer *intel_fb;
 	struct drm_i915_gem_object *obj;
 	int enable_fbc;
+    ENTER();
 	if (!i915_powersave)
 		return;
 		DRM_DEBUG_KMS("disabling active FBC for update\n");
 		intel_disable_fbc(dev);
+	}
+	intel_enable_fbc(crtc, 500);
+    LEAVE();
 	intel_enable_fbc(crtc, 500);
 	return;
 out_disable:
 	/* Multiple disables should be harmless */
 	if (intel_fbc_enabled(dev)) {
 		DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 		intel_disable_fbc(dev);
+	}
 	i915_gem_stolen_cleanup_compression(dev);
-	i915_gem_stolen_cleanup_compression(dev);
+    LEAVE();
+}
 	dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
 		I915_READ(0x112e0);
     dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks());
 	dev_priv->ips.last_count2 = I915_READ(0x112f4);
-//   getrawmonotonic(&dev_priv->ips.last_time2);
+	getrawmonotonic(&dev_priv->ips.last_time2);
 	spin_unlock_irq(&mchdev_lock);
+	}
 	gen6_gt_force_wake_put(dev_priv);
-}
+}
 #if 0
 static void gen6_update_ring_freq(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 		sandybridge_pcode_write(dev_priv,
 					GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
 					ia_freq | gpu_freq);
+	}
+}
-#endif
 void ironlake_teardown_rc6(struct drm_device *dev)
+{
 	if (IS_IRONLAKE_M(dev)) {
 		ironlake_disable_drps(dev);
 		ironlake_disable_rc6(dev);
+	} else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
+//		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
-	} else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
+		mutex_lock(&dev_priv->rps.hw_lock);
 		gen6_disable_rps(dev);
 		mutex_unlock(&dev_priv->rps.hw_lock);
+	}
+}
+static void intel_gen6_powersave_work(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(work, struct drm_i915_private,
+			     rps.delayed_resume_work.work);
+	struct drm_device *dev = dev_priv->dev;
+    ENTER();
+	mutex_lock(&dev_priv->rps.hw_lock);
+	gen6_enable_rps(dev);
+	gen6_update_ring_freq(dev);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+    LEAVE();
+}
 void intel_enable_gt_powersave(struct drm_device *dev)
+{
 		/*
 		 * PCU communication is slow and this doesn't need to be
 		 * done at any specific time, so do this out of our fast path
 		 * to make resume and init faster.
 		 */
-//		schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
+		schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
-//				      round_jiffies_up_relative(HZ));
+				      round_jiffies_up_relative(HZ));
+	}
+}
 static void ibx_init_clock_gating(struct drm_device *dev)
 	uint32_t tmp;
 	if (!IS_HASWELL(dev))
+		return;
+	if (!i915_disable_power_well && !enable)
 		return;
 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 	is_enabled = tmp & HSW_PWR_WELL_STATE;
 		dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
 	} else if (IS_GEN6(dev)) {
 		dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
 		dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
+	}
+	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
+			  intel_gen6_powersave_work);
+}
 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
+{

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_pm.c – Rev 3480 → 3482