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Rev 6937 | Rev 7144 | ||
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Line 35... | Line 35... | ||
35 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
35 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
Line 36... | Line 36... | ||
36 | 36 | ||
Line 37... | Line 37... | ||
37 | void getrawmonotonic(struct timespec *ts); |
37 | void getrawmonotonic(struct timespec *ts); |
- | 38 | ||
- | 39 | /** |
|
38 | 40 | * DOC: RC6 |
|
39 | /** |
41 | * |
40 | * RC6 is a special power stage which allows the GPU to enter an very |
42 | * RC6 is a special power stage which allows the GPU to enter an very |
41 | * low-voltage mode when idle, using down to 0V while at this stage. This |
43 | * low-voltage mode when idle, using down to 0V while at this stage. This |
42 | * stage is entered automatically when the GPU is idle when RC6 support is |
44 | * stage is entered automatically when the GPU is idle when RC6 support is |
Line 549... | Line 551... | ||
549 | 551 | ||
550 | /** |
552 | /** |
551 | * intel_calculate_wm - calculate watermark level |
553 | * intel_calculate_wm - calculate watermark level |
552 | * @clock_in_khz: pixel clock |
554 | * @clock_in_khz: pixel clock |
553 | * @wm: chip FIFO params |
555 | * @wm: chip FIFO params |
554 | * @pixel_size: display pixel size |
556 | * @cpp: bytes per pixel |
555 | * @latency_ns: memory latency for the platform |
557 | * @latency_ns: memory latency for the platform |
556 | * |
558 | * |
557 | * Calculate the watermark level (the level at which the display plane will |
559 | * Calculate the watermark level (the level at which the display plane will |
558 | * start fetching from memory again). Each chip has a different display |
560 | * start fetching from memory again). Each chip has a different display |
Line 565... | Line 567... | ||
565 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
567 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
566 | * will occur, and a display engine hang could result. |
568 | * will occur, and a display engine hang could result. |
567 | */ |
569 | */ |
568 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
570 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
569 | const struct intel_watermark_params *wm, |
571 | const struct intel_watermark_params *wm, |
570 | int fifo_size, |
572 | int fifo_size, int cpp, |
571 | int pixel_size, |
- | |
572 | unsigned long latency_ns) |
573 | unsigned long latency_ns) |
573 | { |
574 | { |
574 | long entries_required, wm_size; |
575 | long entries_required, wm_size; |
Line 575... | Line 576... | ||
575 | 576 | ||
576 | /* |
577 | /* |
577 | * Note: we need to make sure we don't overflow for various clock & |
578 | * Note: we need to make sure we don't overflow for various clock & |
578 | * latency values. |
579 | * latency values. |
579 | * clocks go from a few thousand to several hundred thousand. |
580 | * clocks go from a few thousand to several hundred thousand. |
580 | * latency is usually a few thousand |
581 | * latency is usually a few thousand |
581 | */ |
582 | */ |
582 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
583 | entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) / |
583 | 1000; |
584 | 1000; |
Line 584... | Line 585... | ||
584 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
585 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
Line 641... | Line 642... | ||
641 | } |
642 | } |
Line 642... | Line 643... | ||
642 | 643 | ||
643 | crtc = single_enabled_crtc(dev); |
644 | crtc = single_enabled_crtc(dev); |
644 | if (crtc) { |
645 | if (crtc) { |
645 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
646 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
646 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
647 | int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); |
Line 647... | Line 648... | ||
647 | int clock = adjusted_mode->crtc_clock; |
648 | int clock = adjusted_mode->crtc_clock; |
648 | 649 | ||
649 | /* Display SR */ |
650 | /* Display SR */ |
650 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
651 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
651 | pineview_display_wm.fifo_size, |
652 | pineview_display_wm.fifo_size, |
652 | pixel_size, latency->display_sr); |
653 | cpp, latency->display_sr); |
653 | reg = I915_READ(DSPFW1); |
654 | reg = I915_READ(DSPFW1); |
654 | reg &= ~DSPFW_SR_MASK; |
655 | reg &= ~DSPFW_SR_MASK; |
655 | reg |= FW_WM(wm, SR); |
656 | reg |= FW_WM(wm, SR); |
Line 656... | Line 657... | ||
656 | I915_WRITE(DSPFW1, reg); |
657 | I915_WRITE(DSPFW1, reg); |
657 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
658 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
658 | 659 | ||
659 | /* cursor SR */ |
660 | /* cursor SR */ |
660 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
661 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
661 | pineview_display_wm.fifo_size, |
662 | pineview_display_wm.fifo_size, |
662 | pixel_size, latency->cursor_sr); |
663 | cpp, latency->cursor_sr); |
663 | reg = I915_READ(DSPFW3); |
664 | reg = I915_READ(DSPFW3); |
Line 664... | Line 665... | ||
664 | reg &= ~DSPFW_CURSOR_SR_MASK; |
665 | reg &= ~DSPFW_CURSOR_SR_MASK; |
665 | reg |= FW_WM(wm, CURSOR_SR); |
666 | reg |= FW_WM(wm, CURSOR_SR); |
666 | I915_WRITE(DSPFW3, reg); |
667 | I915_WRITE(DSPFW3, reg); |
667 | 668 | ||
668 | /* Display HPLL off SR */ |
669 | /* Display HPLL off SR */ |
669 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
670 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
670 | pineview_display_hplloff_wm.fifo_size, |
671 | pineview_display_hplloff_wm.fifo_size, |
671 | pixel_size, latency->display_hpll_disable); |
672 | cpp, latency->display_hpll_disable); |
Line 672... | Line 673... | ||
672 | reg = I915_READ(DSPFW3); |
673 | reg = I915_READ(DSPFW3); |
673 | reg &= ~DSPFW_HPLL_SR_MASK; |
674 | reg &= ~DSPFW_HPLL_SR_MASK; |
674 | reg |= FW_WM(wm, HPLL_SR); |
675 | reg |= FW_WM(wm, HPLL_SR); |
675 | I915_WRITE(DSPFW3, reg); |
676 | I915_WRITE(DSPFW3, reg); |
676 | 677 | ||
677 | /* cursor HPLL off SR */ |
678 | /* cursor HPLL off SR */ |
678 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
679 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
679 | pineview_display_hplloff_wm.fifo_size, |
680 | pineview_display_hplloff_wm.fifo_size, |
680 | pixel_size, latency->cursor_hpll_disable); |
681 | cpp, latency->cursor_hpll_disable); |
Line 699... | Line 700... | ||
699 | int *plane_wm, |
700 | int *plane_wm, |
700 | int *cursor_wm) |
701 | int *cursor_wm) |
701 | { |
702 | { |
702 | struct drm_crtc *crtc; |
703 | struct drm_crtc *crtc; |
703 | const struct drm_display_mode *adjusted_mode; |
704 | const struct drm_display_mode *adjusted_mode; |
704 | int htotal, hdisplay, clock, pixel_size; |
705 | int htotal, hdisplay, clock, cpp; |
705 | int line_time_us, line_count; |
706 | int line_time_us, line_count; |
706 | int entries, tlb_miss; |
707 | int entries, tlb_miss; |
Line 707... | Line 708... | ||
707 | 708 | ||
708 | crtc = intel_get_crtc_for_plane(dev, plane); |
709 | crtc = intel_get_crtc_for_plane(dev, plane); |
Line 714... | Line 715... | ||
714 | 715 | ||
715 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
716 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
716 | clock = adjusted_mode->crtc_clock; |
717 | clock = adjusted_mode->crtc_clock; |
717 | htotal = adjusted_mode->crtc_htotal; |
718 | htotal = adjusted_mode->crtc_htotal; |
718 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
719 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
Line 719... | Line 720... | ||
719 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
720 | cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); |
720 | 721 | ||
721 | /* Use the small buffer method to calculate plane watermark */ |
722 | /* Use the small buffer method to calculate plane watermark */ |
722 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
723 | entries = ((clock * cpp / 1000) * display_latency_ns) / 1000; |
723 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
724 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
724 | if (tlb_miss > 0) |
725 | if (tlb_miss > 0) |
725 | entries += tlb_miss; |
726 | entries += tlb_miss; |
Line 729... | Line 730... | ||
729 | *plane_wm = display->max_wm; |
730 | *plane_wm = display->max_wm; |
Line 730... | Line 731... | ||
730 | 731 | ||
731 | /* Use the large buffer method to calculate cursor watermark */ |
732 | /* Use the large buffer method to calculate cursor watermark */ |
732 | line_time_us = max(htotal * 1000 / clock, 1); |
733 | line_time_us = max(htotal * 1000 / clock, 1); |
733 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
734 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
734 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
735 | entries = line_count * crtc->cursor->state->crtc_w * cpp; |
735 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
736 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
736 | if (tlb_miss > 0) |
737 | if (tlb_miss > 0) |
737 | entries += tlb_miss; |
738 | entries += tlb_miss; |
738 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
739 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
Line 785... | Line 786... | ||
785 | const struct intel_watermark_params *cursor, |
786 | const struct intel_watermark_params *cursor, |
786 | int *display_wm, int *cursor_wm) |
787 | int *display_wm, int *cursor_wm) |
787 | { |
788 | { |
788 | struct drm_crtc *crtc; |
789 | struct drm_crtc *crtc; |
789 | const struct drm_display_mode *adjusted_mode; |
790 | const struct drm_display_mode *adjusted_mode; |
790 | int hdisplay, htotal, pixel_size, clock; |
791 | int hdisplay, htotal, cpp, clock; |
791 | unsigned long line_time_us; |
792 | unsigned long line_time_us; |
792 | int line_count, line_size; |
793 | int line_count, line_size; |
793 | int small, large; |
794 | int small, large; |
794 | int entries; |
795 | int entries; |
Line 801... | Line 802... | ||
801 | crtc = intel_get_crtc_for_plane(dev, plane); |
802 | crtc = intel_get_crtc_for_plane(dev, plane); |
802 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
803 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
803 | clock = adjusted_mode->crtc_clock; |
804 | clock = adjusted_mode->crtc_clock; |
804 | htotal = adjusted_mode->crtc_htotal; |
805 | htotal = adjusted_mode->crtc_htotal; |
805 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
806 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
806 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
807 | cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); |
Line 807... | Line 808... | ||
807 | 808 | ||
808 | line_time_us = max(htotal * 1000 / clock, 1); |
809 | line_time_us = max(htotal * 1000 / clock, 1); |
809 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
810 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
Line 810... | Line 811... | ||
810 | line_size = hdisplay * pixel_size; |
811 | line_size = hdisplay * cpp; |
811 | 812 | ||
812 | /* Use the minimum of the small and large buffer method for primary */ |
813 | /* Use the minimum of the small and large buffer method for primary */ |
Line 813... | Line 814... | ||
813 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
814 | small = ((clock * cpp / 1000) * latency_ns) / 1000; |
814 | large = line_count * line_size; |
815 | large = line_count * line_size; |
Line 815... | Line 816... | ||
815 | 816 | ||
816 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
817 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
817 | *display_wm = entries + display->guard_size; |
818 | *display_wm = entries + display->guard_size; |
818 | 819 | ||
Line 819... | Line 820... | ||
819 | /* calculate the self-refresh watermark for display cursor */ |
820 | /* calculate the self-refresh watermark for display cursor */ |
820 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
821 | entries = line_count * cpp * crtc->cursor->state->crtc_w; |
Line 907... | Line 908... | ||
907 | 908 | ||
908 | /* latency must be in 0.1us units. */ |
909 | /* latency must be in 0.1us units. */ |
909 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, |
910 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, |
910 | unsigned int pipe_htotal, |
911 | unsigned int pipe_htotal, |
911 | unsigned int horiz_pixels, |
912 | unsigned int horiz_pixels, |
912 | unsigned int bytes_per_pixel, |
913 | unsigned int cpp, |
913 | unsigned int latency) |
914 | unsigned int latency) |
914 | { |
915 | { |
Line 915... | Line 916... | ||
915 | unsigned int ret; |
916 | unsigned int ret; |
916 | 917 | ||
917 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
918 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
Line 918... | Line 919... | ||
918 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
919 | ret = (ret + 1) * horiz_pixels * cpp; |
919 | ret = DIV_ROUND_UP(ret, 64); |
920 | ret = DIV_ROUND_UP(ret, 64); |
Line 942... | Line 943... | ||
942 | struct intel_crtc *crtc, |
943 | struct intel_crtc *crtc, |
943 | const struct intel_plane_state *state, |
944 | const struct intel_plane_state *state, |
944 | int level) |
945 | int level) |
945 | { |
946 | { |
946 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
947 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
947 | int clock, htotal, pixel_size, width, wm; |
948 | int clock, htotal, cpp, width, wm; |
Line 948... | Line 949... | ||
948 | 949 | ||
949 | if (dev_priv->wm.pri_latency[level] == 0) |
950 | if (dev_priv->wm.pri_latency[level] == 0) |
Line 950... | Line 951... | ||
950 | return USHRT_MAX; |
951 | return USHRT_MAX; |
951 | 952 | ||
Line 952... | Line 953... | ||
952 | if (!state->visible) |
953 | if (!state->visible) |
953 | return 0; |
954 | return 0; |
954 | 955 | ||
955 | pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
956 | cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
956 | clock = crtc->config->base.adjusted_mode.crtc_clock; |
957 | clock = crtc->config->base.adjusted_mode.crtc_clock; |
957 | htotal = crtc->config->base.adjusted_mode.crtc_htotal; |
958 | htotal = crtc->config->base.adjusted_mode.crtc_htotal; |
Line 966... | Line 967... | ||
966 | * would never be able to use cursors. For |
967 | * would never be able to use cursors. For |
967 | * now just hardcode the watermark. |
968 | * now just hardcode the watermark. |
968 | */ |
969 | */ |
969 | wm = 63; |
970 | wm = 63; |
970 | } else { |
971 | } else { |
971 | wm = vlv_wm_method2(clock, htotal, width, pixel_size, |
972 | wm = vlv_wm_method2(clock, htotal, width, cpp, |
972 | dev_priv->wm.pri_latency[level] * 10); |
973 | dev_priv->wm.pri_latency[level] * 10); |
973 | } |
974 | } |
Line 974... | Line 975... | ||
974 | 975 | ||
975 | return min_t(int, wm, USHRT_MAX); |
976 | return min_t(int, wm, USHRT_MAX); |
Line 1440... | Line 1441... | ||
1440 | static const int sr_latency_ns = 12000; |
1441 | static const int sr_latency_ns = 12000; |
1441 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1442 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
1442 | int clock = adjusted_mode->crtc_clock; |
1443 | int clock = adjusted_mode->crtc_clock; |
1443 | int htotal = adjusted_mode->crtc_htotal; |
1444 | int htotal = adjusted_mode->crtc_htotal; |
1444 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
1445 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
1445 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
1446 | int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); |
1446 | unsigned long line_time_us; |
1447 | unsigned long line_time_us; |
1447 | int entries; |
1448 | int entries; |
Line 1448... | Line 1449... | ||
1448 | 1449 | ||
Line 1449... | Line 1450... | ||
1449 | line_time_us = max(htotal * 1000 / clock, 1); |
1450 | line_time_us = max(htotal * 1000 / clock, 1); |
1450 | 1451 | ||
1451 | /* Use ns/us then divide to preserve precision */ |
1452 | /* Use ns/us then divide to preserve precision */ |
1452 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1453 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1453 | pixel_size * hdisplay; |
1454 | cpp * hdisplay; |
1454 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1455 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1455 | srwm = I965_FIFO_SIZE - entries; |
1456 | srwm = I965_FIFO_SIZE - entries; |
1456 | if (srwm < 0) |
1457 | if (srwm < 0) |
1457 | srwm = 1; |
1458 | srwm = 1; |
1458 | srwm &= 0x1ff; |
1459 | srwm &= 0x1ff; |
Line 1459... | Line 1460... | ||
1459 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1460 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
1460 | entries, srwm); |
1461 | entries, srwm); |
1461 | 1462 | ||
1462 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1463 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1463 | pixel_size * crtc->cursor->state->crtc_w; |
1464 | cpp * crtc->cursor->state->crtc_w; |
1464 | entries = DIV_ROUND_UP(entries, |
1465 | entries = DIV_ROUND_UP(entries, |
Line 1519... | Line 1520... | ||
1519 | 1520 | ||
1520 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1521 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
1521 | crtc = intel_get_crtc_for_plane(dev, 0); |
1522 | crtc = intel_get_crtc_for_plane(dev, 0); |
1522 | if (intel_crtc_active(crtc)) { |
1523 | if (intel_crtc_active(crtc)) { |
1523 | const struct drm_display_mode *adjusted_mode; |
1524 | const struct drm_display_mode *adjusted_mode; |
1524 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
1525 | int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); |
1525 | if (IS_GEN2(dev)) |
1526 | if (IS_GEN2(dev)) |
Line 1526... | Line 1527... | ||
1526 | cpp = 4; |
1527 | cpp = 4; |
1527 | 1528 | ||
Line 1541... | Line 1542... | ||
1541 | 1542 | ||
1542 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1543 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
1543 | crtc = intel_get_crtc_for_plane(dev, 1); |
1544 | crtc = intel_get_crtc_for_plane(dev, 1); |
1544 | if (intel_crtc_active(crtc)) { |
1545 | if (intel_crtc_active(crtc)) { |
1545 | const struct drm_display_mode *adjusted_mode; |
1546 | const struct drm_display_mode *adjusted_mode; |
1546 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
1547 | int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); |
1547 | if (IS_GEN2(dev)) |
1548 | if (IS_GEN2(dev)) |
Line 1548... | Line 1549... | ||
1548 | cpp = 4; |
1549 | cpp = 4; |
1549 | 1550 | ||
Line 1587... | Line 1588... | ||
1587 | static const int sr_latency_ns = 6000; |
1588 | static const int sr_latency_ns = 6000; |
1588 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; |
1589 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; |
1589 | int clock = adjusted_mode->crtc_clock; |
1590 | int clock = adjusted_mode->crtc_clock; |
1590 | int htotal = adjusted_mode->crtc_htotal; |
1591 | int htotal = adjusted_mode->crtc_htotal; |
1591 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
1592 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
1592 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
1593 | int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0); |
1593 | unsigned long line_time_us; |
1594 | unsigned long line_time_us; |
1594 | int entries; |
1595 | int entries; |
Line 1595... | Line 1596... | ||
1595 | 1596 | ||
Line 1596... | Line 1597... | ||
1596 | line_time_us = max(htotal * 1000 / clock, 1); |
1597 | line_time_us = max(htotal * 1000 / clock, 1); |
1597 | 1598 | ||
1598 | /* Use ns/us then divide to preserve precision */ |
1599 | /* Use ns/us then divide to preserve precision */ |
1599 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1600 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
1600 | pixel_size * hdisplay; |
1601 | cpp * hdisplay; |
1601 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1602 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1602 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1603 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
1603 | srwm = wm_info->fifo_size - entries; |
1604 | srwm = wm_info->fifo_size - entries; |
Line 1675... | Line 1676... | ||
1675 | if (pipe_w < pfit_w) |
1676 | if (pipe_w < pfit_w) |
1676 | pipe_w = pfit_w; |
1677 | pipe_w = pfit_w; |
1677 | if (pipe_h < pfit_h) |
1678 | if (pipe_h < pfit_h) |
1678 | pipe_h = pfit_h; |
1679 | pipe_h = pfit_h; |
Line -... | Line 1680... | ||
- | 1680 | ||
- | 1681 | if (WARN_ON(!pfit_w || !pfit_h)) |
|
- | 1682 | return pixel_rate; |
|
1679 | 1683 | ||
1680 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
1684 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
1681 | pfit_w * pfit_h); |
1685 | pfit_w * pfit_h); |
Line 1682... | Line 1686... | ||
1682 | } |
1686 | } |
1683 | 1687 | ||
Line 1684... | Line 1688... | ||
1684 | return pixel_rate; |
1688 | return pixel_rate; |
1685 | } |
1689 | } |
1686 | - | ||
1687 | /* latency must be in 0.1us units. */ |
1690 | |
1688 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
1691 | /* latency must be in 0.1us units. */ |
Line 1689... | Line 1692... | ||
1689 | uint32_t latency) |
1692 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) |
1690 | { |
1693 | { |
Line 1691... | Line 1694... | ||
1691 | uint64_t ret; |
1694 | uint64_t ret; |
1692 | 1695 | ||
Line 1693... | Line 1696... | ||
1693 | if (WARN(latency == 0, "Latency value missing\n")) |
1696 | if (WARN(latency == 0, "Latency value missing\n")) |
1694 | return UINT_MAX; |
1697 | return UINT_MAX; |
Line 1695... | Line 1698... | ||
1695 | 1698 | ||
1696 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1699 | ret = (uint64_t) pixel_rate * cpp * latency; |
1697 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
1700 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
1698 | 1701 | ||
1699 | return ret; |
1702 | return ret; |
1700 | } |
1703 | } |
Line 1701... | Line 1704... | ||
1701 | 1704 | ||
1702 | /* latency must be in 0.1us units. */ |
1705 | /* latency must be in 0.1us units. */ |
- | 1706 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
|
- | 1707 | uint32_t horiz_pixels, uint8_t cpp, |
|
Line 1703... | Line 1708... | ||
1703 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
1708 | uint32_t latency) |
1704 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1709 | { |
1705 | uint32_t latency) |
1710 | uint32_t ret; |
1706 | { |
1711 | |
1707 | uint32_t ret; |
1712 | if (WARN(latency == 0, "Latency value missing\n")) |
Line 1708... | Line 1713... | ||
1708 | 1713 | return UINT_MAX; |
|
1709 | if (WARN(latency == 0, "Latency value missing\n")) |
1714 | if (WARN_ON(!pipe_htotal)) |
1710 | return UINT_MAX; |
1715 | return UINT_MAX; |
- | 1716 | ||
- | 1717 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
|
- | 1718 | ret = (ret + 1) * horiz_pixels * cpp; |
|
- | 1719 | ret = DIV_ROUND_UP(ret, 64) + 2; |
|
- | 1720 | return ret; |
|
- | 1721 | } |
|
- | 1722 | ||
- | 1723 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
|
- | 1724 | uint8_t cpp) |
|
- | 1725 | { |
|
- | 1726 | /* |
|
1711 | 1727 | * Neither of these should be possible since this function shouldn't be |
|
1712 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1728 | * called if the CRTC is off or the plane is invisible. But let's be |
Line 1713... | Line 1729... | ||
1713 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
1729 | * extra paranoid to avoid a potential divide-by-zero if we screw up |
1714 | ret = DIV_ROUND_UP(ret, 64) + 2; |
1730 | * elsewhere in the driver. |
1715 | return ret; |
1731 | */ |
Line 1735... | Line 1751... | ||
1735 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
1751 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
1736 | const struct intel_plane_state *pstate, |
1752 | const struct intel_plane_state *pstate, |
1737 | uint32_t mem_value, |
1753 | uint32_t mem_value, |
1738 | bool is_lp) |
1754 | bool is_lp) |
1739 | { |
1755 | { |
- | 1756 | int cpp = pstate->base.fb ? |
|
1740 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1757 | drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0; |
1741 | uint32_t method1, method2; |
1758 | uint32_t method1, method2; |
Line 1742... | Line 1759... | ||
1742 | 1759 | ||
1743 | if (!cstate->base.active || !pstate->visible) |
1760 | if (!cstate->base.active || !pstate->visible) |
Line 1744... | Line 1761... | ||
1744 | return 0; |
1761 | return 0; |
Line 1745... | Line 1762... | ||
1745 | 1762 | ||
1746 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1763 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value); |
Line 1747... | Line 1764... | ||
1747 | 1764 | ||
1748 | if (!is_lp) |
1765 | if (!is_lp) |
1749 | return method1; |
1766 | return method1; |
1750 | - | ||
1751 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1767 | |
Line 1752... | Line 1768... | ||
1752 | cstate->base.adjusted_mode.crtc_htotal, |
1768 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1753 | drm_rect_width(&pstate->dst), |
1769 | cstate->base.adjusted_mode.crtc_htotal, |
Line 1754... | Line 1770... | ||
1754 | bpp, |
1770 | drm_rect_width(&pstate->dst), |
Line 1763... | Line 1779... | ||
1763 | */ |
1779 | */ |
1764 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
1780 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
1765 | const struct intel_plane_state *pstate, |
1781 | const struct intel_plane_state *pstate, |
1766 | uint32_t mem_value) |
1782 | uint32_t mem_value) |
1767 | { |
1783 | { |
- | 1784 | int cpp = pstate->base.fb ? |
|
1768 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1785 | drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0; |
1769 | uint32_t method1, method2; |
1786 | uint32_t method1, method2; |
Line 1770... | Line 1787... | ||
1770 | 1787 | ||
1771 | if (!cstate->base.active || !pstate->visible) |
1788 | if (!cstate->base.active || !pstate->visible) |
Line 1772... | Line 1789... | ||
1772 | return 0; |
1789 | return 0; |
1773 | 1790 | ||
1774 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1791 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value); |
1775 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1792 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1776 | cstate->base.adjusted_mode.crtc_htotal, |
- | |
1777 | drm_rect_width(&pstate->dst), |
1793 | cstate->base.adjusted_mode.crtc_htotal, |
1778 | bpp, |
1794 | drm_rect_width(&pstate->dst), |
1779 | mem_value); |
1795 | cpp, mem_value); |
Line 1780... | Line 1796... | ||
1780 | return min(method1, method2); |
1796 | return min(method1, method2); |
1781 | } |
1797 | } |
Line 1807... | Line 1823... | ||
1807 | /* Only for WM_LP. */ |
1823 | /* Only for WM_LP. */ |
1808 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
1824 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
1809 | const struct intel_plane_state *pstate, |
1825 | const struct intel_plane_state *pstate, |
1810 | uint32_t pri_val) |
1826 | uint32_t pri_val) |
1811 | { |
1827 | { |
- | 1828 | int cpp = pstate->base.fb ? |
|
1812 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1829 | drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0; |
Line 1813... | Line 1830... | ||
1813 | 1830 | ||
1814 | if (!cstate->base.active || !pstate->visible) |
1831 | if (!cstate->base.active || !pstate->visible) |
Line 1815... | Line 1832... | ||
1815 | return 0; |
1832 | return 0; |
1816 | 1833 | ||
Line 1817... | Line 1834... | ||
1817 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); |
1834 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp); |
1818 | } |
1835 | } |
1819 | 1836 | ||
Line 2005... | Line 2022... | ||
2005 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); |
2022 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); |
2006 | result->enable = true; |
2023 | result->enable = true; |
2007 | } |
2024 | } |
Line 2008... | Line 2025... | ||
2008 | 2025 | ||
2009 | static uint32_t |
2026 | static uint32_t |
- | 2027 | hsw_compute_linetime_wm(struct drm_device *dev, |
|
2010 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
2028 | struct intel_crtc_state *cstate) |
2011 | { |
2029 | { |
2012 | struct drm_i915_private *dev_priv = dev->dev_private; |
2030 | struct drm_i915_private *dev_priv = dev->dev_private; |
2013 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2031 | const struct drm_display_mode *adjusted_mode = |
2014 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
2032 | &cstate->base.adjusted_mode; |
Line 2015... | Line 2033... | ||
2015 | u32 linetime, ips_linetime; |
2033 | u32 linetime, ips_linetime; |
- | 2034 | ||
- | 2035 | if (!cstate->base.active) |
|
- | 2036 | return 0; |
|
- | 2037 | if (WARN_ON(adjusted_mode->crtc_clock == 0)) |
|
2016 | 2038 | return 0; |
|
Line 2017... | Line 2039... | ||
2017 | if (!intel_crtc->active) |
2039 | if (WARN_ON(dev_priv->cdclk_freq == 0)) |
2018 | return 0; |
2040 | return 0; |
2019 | 2041 | ||
Line 2321... | Line 2343... | ||
2321 | 2343 | ||
2322 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
2344 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
Line 2323... | Line 2345... | ||
2323 | pristate, sprstate, curstate, &pipe_wm->wm[0]); |
2345 | pristate, sprstate, curstate, &pipe_wm->wm[0]); |
2324 | 2346 | ||
2325 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
- | |
Line 2326... | Line 2347... | ||
2326 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, |
2347 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2327 | &intel_crtc->base); |
2348 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate); |
Line 2328... | Line 2349... | ||
2328 | 2349 | ||
Line 2858... | Line 2879... | ||
2858 | static unsigned int |
2879 | static unsigned int |
2859 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
2880 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
2860 | const struct drm_plane_state *pstate, |
2881 | const struct drm_plane_state *pstate, |
2861 | int y) |
2882 | int y) |
2862 | { |
2883 | { |
2863 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
2884 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); |
2864 | struct drm_framebuffer *fb = pstate->fb; |
2885 | struct drm_framebuffer *fb = pstate->fb; |
- | 2886 | uint32_t width = 0, height = 0; |
|
- | 2887 | ||
- | 2888 | width = drm_rect_width(&intel_pstate->src) >> 16; |
|
- | 2889 | height = drm_rect_height(&intel_pstate->src) >> 16; |
|
- | 2890 | ||
- | 2891 | if (intel_rotation_90_or_270(pstate->rotation)) |
|
- | 2892 | swap(width, height); |
|
Line 2865... | Line 2893... | ||
2865 | 2893 | ||
2866 | /* for planar format */ |
2894 | /* for planar format */ |
2867 | if (fb->pixel_format == DRM_FORMAT_NV12) { |
2895 | if (fb->pixel_format == DRM_FORMAT_NV12) { |
2868 | if (y) /* y-plane data rate */ |
2896 | if (y) /* y-plane data rate */ |
2869 | return intel_crtc->config->pipe_src_w * |
- | |
2870 | intel_crtc->config->pipe_src_h * |
2897 | return width * height * |
2871 | drm_format_plane_cpp(fb->pixel_format, 0); |
2898 | drm_format_plane_cpp(fb->pixel_format, 0); |
2872 | else /* uv-plane data rate */ |
2899 | else /* uv-plane data rate */ |
2873 | return (intel_crtc->config->pipe_src_w/2) * |
- | |
2874 | (intel_crtc->config->pipe_src_h/2) * |
2900 | return (width / 2) * (height / 2) * |
2875 | drm_format_plane_cpp(fb->pixel_format, 1); |
2901 | drm_format_plane_cpp(fb->pixel_format, 1); |
Line 2876... | Line 2902... | ||
2876 | } |
2902 | } |
2877 | - | ||
2878 | /* for packed formats */ |
- | |
2879 | return intel_crtc->config->pipe_src_w * |
2903 | |
2880 | intel_crtc->config->pipe_src_h * |
2904 | /* for packed formats */ |
Line 2881... | Line 2905... | ||
2881 | drm_format_plane_cpp(fb->pixel_format, 0); |
2905 | return width * height * drm_format_plane_cpp(fb->pixel_format, 0); |
2882 | } |
2906 | } |
2883 | 2907 | ||
Line 2955... | Line 2979... | ||
2955 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
2979 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
2956 | struct drm_plane *plane = &intel_plane->base; |
2980 | struct drm_plane *plane = &intel_plane->base; |
2957 | struct drm_framebuffer *fb = plane->state->fb; |
2981 | struct drm_framebuffer *fb = plane->state->fb; |
2958 | int id = skl_wm_plane_id(intel_plane); |
2982 | int id = skl_wm_plane_id(intel_plane); |
Line 2959... | Line 2983... | ||
2959 | 2983 | ||
2960 | if (fb == NULL) |
2984 | if (!to_intel_plane_state(plane->state)->visible) |
- | 2985 | continue; |
|
2961 | continue; |
2986 | |
2962 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
2987 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
Line 2963... | Line 2988... | ||
2963 | continue; |
2988 | continue; |
2964 | 2989 | ||
Line 2982... | Line 3007... | ||
2982 | struct drm_plane_state *pstate = intel_plane->base.state; |
3007 | struct drm_plane_state *pstate = intel_plane->base.state; |
2983 | unsigned int data_rate, y_data_rate; |
3008 | unsigned int data_rate, y_data_rate; |
2984 | uint16_t plane_blocks, y_plane_blocks = 0; |
3009 | uint16_t plane_blocks, y_plane_blocks = 0; |
2985 | int id = skl_wm_plane_id(intel_plane); |
3010 | int id = skl_wm_plane_id(intel_plane); |
Line 2986... | Line 3011... | ||
2986 | 3011 | ||
2987 | if (pstate->fb == NULL) |
3012 | if (!to_intel_plane_state(pstate)->visible) |
2988 | continue; |
3013 | continue; |
2989 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
3014 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
Line 2990... | Line 3015... | ||
2990 | continue; |
3015 | continue; |
Line 3032... | Line 3057... | ||
3032 | return config->base.adjusted_mode.crtc_clock; |
3057 | return config->base.adjusted_mode.crtc_clock; |
3033 | } |
3058 | } |
Line 3034... | Line 3059... | ||
3034 | 3059 | ||
3035 | /* |
3060 | /* |
3036 | * The max latency should be 257 (max the punit can code is 255 and we add 2us |
3061 | * The max latency should be 257 (max the punit can code is 255 and we add 2us |
3037 | * for the read latency) and bytes_per_pixel should always be <= 8, so that |
3062 | * for the read latency) and cpp should always be <= 8, so that |
3038 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
3063 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
3039 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. |
3064 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. |
3040 | */ |
3065 | */ |
3041 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
- | |
3042 | uint32_t latency) |
3066 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) |
3043 | { |
3067 | { |
Line 3044... | Line 3068... | ||
3044 | uint32_t wm_intermediate_val, ret; |
3068 | uint32_t wm_intermediate_val, ret; |
3045 | 3069 | ||
Line 3046... | Line 3070... | ||
3046 | if (latency == 0) |
3070 | if (latency == 0) |
3047 | return UINT_MAX; |
3071 | return UINT_MAX; |
Line 3048... | Line 3072... | ||
3048 | 3072 | ||
3049 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
3073 | wm_intermediate_val = latency * pixel_rate * cpp / 512; |
Line 3050... | Line 3074... | ||
3050 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
3074 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
3051 | 3075 | ||
3052 | return ret; |
3076 | return ret; |
3053 | } |
3077 | } |
3054 | 3078 | ||
3055 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
3079 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
3056 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
3080 | uint32_t horiz_pixels, uint8_t cpp, |
Line 3057... | Line 3081... | ||
3057 | uint64_t tiling, uint32_t latency) |
3081 | uint64_t tiling, uint32_t latency) |
3058 | { |
3082 | { |
Line 3059... | Line 3083... | ||
3059 | uint32_t ret; |
3083 | uint32_t ret; |
Line 3060... | Line 3084... | ||
3060 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3084 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3061 | uint32_t wm_intermediate_val; |
3085 | uint32_t wm_intermediate_val; |
3062 | 3086 | ||
3063 | if (latency == 0) |
3087 | if (latency == 0) |
Line 3106... | Line 3130... | ||
3106 | uint16_t *out_blocks, /* out */ |
3130 | uint16_t *out_blocks, /* out */ |
3107 | uint8_t *out_lines /* out */) |
3131 | uint8_t *out_lines /* out */) |
3108 | { |
3132 | { |
3109 | struct drm_plane *plane = &intel_plane->base; |
3133 | struct drm_plane *plane = &intel_plane->base; |
3110 | struct drm_framebuffer *fb = plane->state->fb; |
3134 | struct drm_framebuffer *fb = plane->state->fb; |
- | 3135 | struct intel_plane_state *intel_pstate = |
|
- | 3136 | to_intel_plane_state(plane->state); |
|
3111 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
3137 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
3112 | uint32_t method1, method2; |
3138 | uint32_t method1, method2; |
3113 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3139 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
3114 | uint32_t res_blocks, res_lines; |
3140 | uint32_t res_blocks, res_lines; |
3115 | uint32_t selected_result; |
3141 | uint32_t selected_result; |
3116 | uint8_t bytes_per_pixel; |
3142 | uint8_t cpp; |
- | 3143 | uint32_t width = 0, height = 0; |
|
Line 3117... | Line 3144... | ||
3117 | 3144 | ||
3118 | if (latency == 0 || !cstate->base.active || !fb) |
3145 | if (latency == 0 || !cstate->base.active || !intel_pstate->visible) |
Line -... | Line 3146... | ||
- | 3146 | return false; |
|
- | 3147 | ||
- | 3148 | width = drm_rect_width(&intel_pstate->src) >> 16; |
|
- | 3149 | height = drm_rect_height(&intel_pstate->src) >> 16; |
|
- | 3150 | ||
- | 3151 | if (intel_rotation_90_or_270(plane->state->rotation)) |
|
3119 | return false; |
3152 | swap(width, height); |
3120 | 3153 | ||
3121 | bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0); |
- | |
3122 | method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate), |
3154 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3123 | bytes_per_pixel, |
3155 | method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate), |
3124 | latency); |
3156 | cpp, latency); |
3125 | method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate), |
3157 | method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate), |
3126 | cstate->base.adjusted_mode.crtc_htotal, |
3158 | cstate->base.adjusted_mode.crtc_htotal, |
3127 | cstate->pipe_src_w, |
3159 | width, |
3128 | bytes_per_pixel, |
3160 | cpp, |
Line 3129... | Line 3161... | ||
3129 | fb->modifier[0], |
3161 | fb->modifier[0], |
3130 | latency); |
3162 | latency); |
Line 3131... | Line 3163... | ||
3131 | 3163 | ||
3132 | plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel; |
3164 | plane_bytes_per_line = width * cpp; |
3133 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3165 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3134 | 3166 | ||
3135 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
3167 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
3136 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { |
3168 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { |
3137 | uint32_t min_scanlines = 4; |
3169 | uint32_t min_scanlines = 4; |
3138 | uint32_t y_tile_minimum; |
3170 | uint32_t y_tile_minimum; |
Line 3139... | Line 3171... | ||
3139 | if (intel_rotation_90_or_270(plane->state->rotation)) { |
3171 | if (intel_rotation_90_or_270(plane->state->rotation)) { |
3140 | int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ? |
3172 | int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ? |
3141 | drm_format_plane_cpp(fb->pixel_format, 1) : |
3173 | drm_format_plane_cpp(fb->pixel_format, 1) : |
3142 | drm_format_plane_cpp(fb->pixel_format, 0); |
3174 | drm_format_plane_cpp(fb->pixel_format, 0); |
3143 | 3175 | ||
3144 | switch (bpp) { |
3176 | switch (cpp) { |
Line 3628... | Line 3660... | ||
3628 | config->sprites_scaled |= wm->sprites_scaled; |
3660 | config->sprites_scaled |= wm->sprites_scaled; |
3629 | config->num_pipes_active++; |
3661 | config->num_pipes_active++; |
3630 | } |
3662 | } |
3631 | } |
3663 | } |
Line 3632... | Line 3664... | ||
3632 | 3664 | ||
3633 | static void ilk_program_watermarks(struct drm_i915_private *dev_priv) |
3665 | static void ilk_program_watermarks(struct intel_crtc_state *cstate) |
- | 3666 | { |
|
3634 | { |
3667 | struct drm_crtc *crtc = cstate->base.crtc; |
- | 3668 | struct drm_device *dev = crtc->dev; |
|
3635 | struct drm_device *dev = dev_priv->dev; |
3669 | struct drm_i915_private *dev_priv = to_i915(dev); |
3636 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
3670 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
3637 | struct ilk_wm_maximums max; |
3671 | struct ilk_wm_maximums max; |
3638 | struct intel_wm_config config = {}; |
3672 | struct intel_wm_config config = {}; |
3639 | struct ilk_wm_values results = {}; |
3673 | struct ilk_wm_values results = {}; |
Line 3663... | Line 3697... | ||
3663 | ilk_write_wm_values(dev_priv, &results); |
3697 | ilk_write_wm_values(dev_priv, &results); |
3664 | } |
3698 | } |
Line 3665... | Line 3699... | ||
3665 | 3699 | ||
3666 | static void ilk_update_wm(struct drm_crtc *crtc) |
3700 | static void ilk_update_wm(struct drm_crtc *crtc) |
3667 | { |
- | |
3668 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
3701 | { |
3669 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3702 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 3670... | Line 3703... | ||
3670 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3703 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
Line 3683... | Line 3716... | ||
3683 | intel_wait_for_vblank(crtc->dev, intel_crtc->pipe); |
3716 | intel_wait_for_vblank(crtc->dev, intel_crtc->pipe); |
3684 | } |
3717 | } |
Line 3685... | Line 3718... | ||
3685 | 3718 | ||
Line 3686... | Line 3719... | ||
3686 | intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk; |
3719 | intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk; |
3687 | 3720 | ||
Line 3688... | Line 3721... | ||
3688 | ilk_program_watermarks(dev_priv); |
3721 | ilk_program_watermarks(cstate); |
3689 | } |
3722 | } |
3690 | 3723 | ||
Line 4071... | Line 4104... | ||
4071 | 4104 | ||
4072 | if (dev_priv->display.update_wm) |
4105 | if (dev_priv->display.update_wm) |
4073 | dev_priv->display.update_wm(crtc); |
4106 | dev_priv->display.update_wm(crtc); |
Line 4074... | Line 4107... | ||
4074 | } |
4107 | } |
4075 | 4108 | ||
4076 | /** |
4109 | /* |
4077 | * Lock protecting IPS related data structures |
4110 | * Lock protecting IPS related data structures |
Line 4078... | Line 4111... | ||
4078 | */ |
4111 | */ |
Line 4107... | Line 4140... | ||
4107 | } |
4140 | } |
Line 4108... | Line 4141... | ||
4108 | 4141 | ||
4109 | static void ironlake_enable_drps(struct drm_device *dev) |
4142 | static void ironlake_enable_drps(struct drm_device *dev) |
4110 | { |
4143 | { |
4111 | struct drm_i915_private *dev_priv = dev->dev_private; |
4144 | struct drm_i915_private *dev_priv = dev->dev_private; |
4112 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
4145 | u32 rgvmodectl; |
Line 4113... | Line 4146... | ||
4113 | u8 fmax, fmin, fstart, vstart; |
4146 | u8 fmax, fmin, fstart, vstart; |
Line -... | Line 4147... | ||
- | 4147 | ||
- | 4148 | spin_lock_irq(&mchdev_lock); |
|
4114 | 4149 | ||
4115 | spin_lock_irq(&mchdev_lock); |
4150 | rgvmodectl = I915_READ(MEMMODECTL); |
4116 | 4151 | ||
Line 4117... | Line 4152... | ||
4117 | /* Enable temp reporting */ |
4152 | /* Enable temp reporting */ |
Line 4544... | Line 4579... | ||
4544 | else |
4579 | else |
4545 | mode = 0; |
4580 | mode = 0; |
4546 | } |
4581 | } |
4547 | if (HAS_RC6p(dev)) |
4582 | if (HAS_RC6p(dev)) |
4548 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", |
4583 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", |
4549 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
4584 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE), |
4550 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
4585 | onoff(mode & GEN6_RC_CTL_RC6p_ENABLE), |
4551 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
4586 | onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE)); |
Line 4552... | Line 4587... | ||
4552 | 4587 | ||
4553 | else |
4588 | else |
4554 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", |
4589 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", |
- | 4590 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE)); |
|
- | 4591 | } |
|
- | 4592 | ||
- | 4593 | static bool bxt_check_bios_rc6_setup(const struct drm_device *dev) |
|
- | 4594 | { |
|
- | 4595 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4596 | bool enable_rc6 = true; |
|
- | 4597 | unsigned long rc6_ctx_base; |
|
- | 4598 | ||
- | 4599 | if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { |
|
- | 4600 | DRM_DEBUG_KMS("RC6 Base location not set properly.\n"); |
|
- | 4601 | enable_rc6 = false; |
|
- | 4602 | } |
|
- | 4603 | ||
- | 4604 | /* |
|
- | 4605 | * The exact context size is not known for BXT, so assume a page size |
|
- | 4606 | * for this check. |
|
- | 4607 | */ |
|
- | 4608 | rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; |
|
- | 4609 | if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) && |
|
- | 4610 | (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base + |
|
- | 4611 | dev_priv->gtt.stolen_reserved_size))) { |
|
- | 4612 | DRM_DEBUG_KMS("RC6 Base address not as expected.\n"); |
|
- | 4613 | enable_rc6 = false; |
|
- | 4614 | } |
|
- | 4615 | ||
- | 4616 | if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && |
|
- | 4617 | ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && |
|
- | 4618 | ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && |
|
- | 4619 | ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { |
|
- | 4620 | DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n"); |
|
- | 4621 | enable_rc6 = false; |
|
- | 4622 | } |
|
- | 4623 | ||
- | 4624 | if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE | |
|
- | 4625 | GEN6_RC_CTL_HW_ENABLE)) && |
|
- | 4626 | ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) || |
|
- | 4627 | !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) { |
|
- | 4628 | DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n"); |
|
- | 4629 | enable_rc6 = false; |
|
- | 4630 | } |
|
- | 4631 | ||
4555 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); |
4632 | return enable_rc6; |
Line 4556... | Line 4633... | ||
4556 | } |
4633 | } |
4557 | 4634 | ||
4558 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
4635 | int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
4559 | { |
4636 | { |
4560 | /* No RC6 before Ironlake and code is gone for ilk. */ |
4637 | /* No RC6 before Ironlake and code is gone for ilk. */ |
Line -... | Line 4638... | ||
- | 4638 | if (INTEL_INFO(dev)->gen < 6) |
|
- | 4639 | return 0; |
|
- | 4640 | ||
- | 4641 | if (!enable_rc6) |
|
- | 4642 | return 0; |
|
- | 4643 | ||
- | 4644 | if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) { |
|
- | 4645 | DRM_INFO("RC6 disabled by BIOS\n"); |
|
4561 | if (INTEL_INFO(dev)->gen < 6) |
4646 | return 0; |
4562 | return 0; |
4647 | } |
4563 | 4648 | ||
Line 4564... | Line 4649... | ||
4564 | /* Respect the kernel parameter if it is set */ |
4649 | /* Respect the kernel parameter if it is set */ |
Line 4728... | Line 4813... | ||
4728 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); |
4813 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); |
Line 4729... | Line 4814... | ||
4729 | 4814 | ||
4730 | /* 3a: Enable RC6 */ |
4815 | /* 3a: Enable RC6 */ |
4731 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
4816 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
4732 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
4817 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
4733 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
- | |
4734 | "on" : "off"); |
4818 | DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); |
4735 | /* WaRsUseTimeoutMode */ |
4819 | /* WaRsUseTimeoutMode */ |
4736 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
4820 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
4737 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
4821 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
4738 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ |
4822 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ |
Line 4748... | Line 4832... | ||
4748 | 4832 | ||
4749 | /* |
4833 | /* |
4750 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. |
4834 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. |
4751 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
4835 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
4752 | */ |
4836 | */ |
4753 | if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || |
- | |
4754 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0))) |
4837 | if (NEEDS_WaRsDisableCoarsePowerGating(dev)) |
4755 | I915_WRITE(GEN9_PG_ENABLE, 0); |
4838 | I915_WRITE(GEN9_PG_ENABLE, 0); |
4756 | else |
4839 | else |
4757 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
4840 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
Line 5167... | Line 5250... | ||
5167 | unsigned long pctx_paddr, paddr; |
5250 | unsigned long pctx_paddr, paddr; |
5168 | struct i915_gtt *gtt = &dev_priv->gtt; |
5251 | struct i915_gtt *gtt = &dev_priv->gtt; |
5169 | u32 pcbr; |
5252 | u32 pcbr; |
5170 | int pctx_size = 32*1024; |
5253 | int pctx_size = 32*1024; |
Line 5171... | Line -... | ||
5171 | - | ||
5172 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
- | |
5173 | 5254 | ||
5174 | pcbr = I915_READ(VLV_PCBR); |
5255 | pcbr = I915_READ(VLV_PCBR); |
5175 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { |
5256 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { |
5176 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5257 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5177 | paddr = (dev_priv->mm.stolen_base + |
5258 | paddr = (dev_priv->mm.stolen_base + |
Line 5190... | Line 5271... | ||
5190 | struct drm_i915_gem_object *pctx; |
5271 | struct drm_i915_gem_object *pctx; |
5191 | unsigned long pctx_paddr; |
5272 | unsigned long pctx_paddr; |
5192 | u32 pcbr; |
5273 | u32 pcbr; |
5193 | int pctx_size = 24*1024; |
5274 | int pctx_size = 24*1024; |
Line 5194... | Line 5275... | ||
5194 | 5275 | ||
Line 5195... | Line 5276... | ||
5195 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5276 | mutex_lock(&dev->struct_mutex); |
5196 | 5277 | ||
5197 | pcbr = I915_READ(VLV_PCBR); |
5278 | pcbr = I915_READ(VLV_PCBR); |
5198 | if (pcbr) { |
5279 | if (pcbr) { |
Line 5218... | Line 5299... | ||
5218 | * memory, or any other relevant ranges. |
5299 | * memory, or any other relevant ranges. |
5219 | */ |
5300 | */ |
5220 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
5301 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
5221 | if (!pctx) { |
5302 | if (!pctx) { |
5222 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
5303 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
5223 | return; |
5304 | goto out; |
5224 | } |
5305 | } |
Line 5225... | Line 5306... | ||
5225 | 5306 | ||
5226 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
5307 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
Line 5227... | Line 5308... | ||
5227 | I915_WRITE(VLV_PCBR, pctx_paddr); |
5308 | I915_WRITE(VLV_PCBR, pctx_paddr); |
5228 | 5309 | ||
5229 | out: |
5310 | out: |
- | 5311 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
|
5230 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
5312 | dev_priv->vlv_pctx = pctx; |
Line 5231... | Line 5313... | ||
5231 | dev_priv->vlv_pctx = pctx; |
5313 | mutex_unlock(&dev->struct_mutex); |
5232 | } |
5314 | } |
5233 | 5315 | ||
Line 5234... | Line 5316... | ||
5234 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
5316 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
5235 | { |
5317 | { |
Line 5236... | Line 5318... | ||
5236 | struct drm_i915_private *dev_priv = dev->dev_private; |
5318 | struct drm_i915_private *dev_priv = dev->dev_private; |
5237 | 5319 | ||
5238 | if (WARN_ON(!dev_priv->vlv_pctx)) |
5320 | if (WARN_ON(!dev_priv->vlv_pctx)) |
Line 5239... | Line 5321... | ||
5239 | return; |
5321 | return; |
5240 | 5322 | ||
Line 6045... | Line 6127... | ||
6045 | 6127 | ||
6046 | void intel_init_gt_powersave(struct drm_device *dev) |
6128 | void intel_init_gt_powersave(struct drm_device *dev) |
6047 | { |
6129 | { |
Line 6048... | Line -... | ||
6048 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
6049 | 6130 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
6050 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
6131 | |
6051 | /* |
6132 | /* |
6052 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
6133 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
6053 | * requirement. |
6134 | * requirement. |
Line 6180... | Line 6261... | ||
6180 | /* Powersaving is controlled by the host when inside a VM */ |
6261 | /* Powersaving is controlled by the host when inside a VM */ |
6181 | if (intel_vgpu_active(dev)) |
6262 | if (intel_vgpu_active(dev)) |
6182 | return; |
6263 | return; |
Line 6183... | Line 6264... | ||
6183 | 6264 | ||
6184 | if (IS_IRONLAKE_M(dev)) { |
- | |
6185 | mutex_lock(&dev->struct_mutex); |
6265 | if (IS_IRONLAKE_M(dev)) { |
- | 6266 | ironlake_enable_drps(dev); |
|
6186 | ironlake_enable_drps(dev); |
6267 | mutex_lock(&dev->struct_mutex); |
6187 | intel_init_emon(dev); |
6268 | intel_init_emon(dev); |
6188 | mutex_unlock(&dev->struct_mutex); |
6269 | mutex_unlock(&dev->struct_mutex); |
6189 | } else if (INTEL_INFO(dev)->gen >= 6) { |
6270 | } else if (INTEL_INFO(dev)->gen >= 6) { |
6190 | /* |
6271 | /* |
Line 7017... | Line 7098... | ||
7017 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
7098 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
7018 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
7099 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
7019 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
7100 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
7020 | dev_priv->display.update_wm = ilk_update_wm; |
7101 | dev_priv->display.update_wm = ilk_update_wm; |
7021 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
7102 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
- | 7103 | dev_priv->display.program_watermarks = ilk_program_watermarks; |
|
7022 | } else { |
7104 | } else { |
7023 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
7105 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
7024 | "Disable CxSR\n"); |
7106 | "Disable CxSR\n"); |
7025 | } |
7107 | } |
Line 7182... | Line 7264... | ||
7182 | 7264 | ||
7183 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7265 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7184 | { |
7266 | { |
Line 7185... | Line 7267... | ||
7185 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7267 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7186 | 7268 | ||
7187 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
7269 | div = vlv_gpu_freq_div(czclk_freq); |
- | 7270 | if (div < 0) |
|
Line 7188... | Line 7271... | ||
7188 | if (div < 0) |
7271 | return div; |
7189 | return div; |
7272 | div /= 2; |
Line 7190... | Line 7273... | ||
7190 | 7273 | ||
7191 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
7274 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
7192 | } |
7275 | } |
Line 7193... | Line 7276... | ||
7193 | 7276 | ||
7194 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7277 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7195 | { |
7278 | { |
- | 7279 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
|
Line 7196... | Line 7280... | ||
7196 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
7280 | |
7197 | 7281 | mul = vlv_gpu_freq_div(czclk_freq); |
|
7198 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
7282 | if (mul < 0) |