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Rev 6084 Rev 6937
Line 141... Line 141...
141 
static bool get_mocs_settings(struct drm_device *dev,
 141 
static bool get_mocs_settings(struct drm_device *dev,
142 
			      struct drm_i915_mocs_table *table)
 142 
			      struct drm_i915_mocs_table *table)
143 
{
 143 
{
144 
	bool result = false;
 144 
	bool result = false;
Line 145... Line 145...
145 
 
 145 
 
146 
	if (IS_SKYLAKE(dev)) {
 146 
	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
147 
		table->size  = ARRAY_SIZE(skylake_mocs_table);
 147 
		table->size  = ARRAY_SIZE(skylake_mocs_table);
148 
		table->table = skylake_mocs_table;
 148 
		table->table = skylake_mocs_table;
149 
		result = true;
 149 
		result = true;
150 
	} else if (IS_BROXTON(dev)) {
 150 
	} else if (IS_BROXTON(dev)) {
Line 157... Line 157...
157 
	}
 157 
	}
Line 158... Line 158...
158 
 
 158 
 
159 
	return result;
 159 
	return result;
Line -... Line 160...
- 
 
 160 
}
- 
 
 161 
 
- 
 
 162 
static i915_reg_t mocs_register(enum intel_ring_id ring, int index)
- 
 
 163 
{
- 
 
 164 
	switch (ring) {
- 
 
 165 
	case RCS:
- 
 
 166 
		return GEN9_GFX_MOCS(index);
- 
 
 167 
	case VCS:
- 
 
 168 
		return GEN9_MFX0_MOCS(index);
- 
 
 169 
	case BCS:
- 
 
 170 
		return GEN9_BLT_MOCS(index);
- 
 
 171 
	case VECS:
- 
 
 172 
		return GEN9_VEBOX_MOCS(index);
- 
 
 173 
	case VCS2:
- 
 
 174 
		return GEN9_MFX1_MOCS(index);
- 
 
 175 
	default:
- 
 
 176 
		MISSING_CASE(ring);
- 
 
 177 
		return INVALID_MMIO_REG;
- 
 
 178 
	}
160 
}
 179 
}
161 
 
 180 
 
162 
/**
 181 
/**
163 
 * emit_mocs_control_table() - emit the mocs control table
 182 
 * emit_mocs_control_table() - emit the mocs control table
164 
 * @req:	Request to set up the MOCS table for.
 183 
 * @req:	Request to set up the MOCS table for.
165 
 * @table:	The values to program into the control regs.
 184 
 * @table:	The values to program into the control regs.
166 
 * @reg_base:	The base for the engine that needs to be programmed.
 185 
 * @ring:	The engine for whom to emit the registers.
167 
 *
 186 
 *
168 
 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
 187 
 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
169 
 * given table starting at the given address.
 188 
 * given table starting at the given address.
170 
 *
 189 
 *
171 
 * Return: 0 on success, otherwise the error status.
 190 
 * Return: 0 on success, otherwise the error status.
172 
 */
 191 
 */
173 
static int emit_mocs_control_table(struct drm_i915_gem_request *req,
 192 
static int emit_mocs_control_table(struct drm_i915_gem_request *req,
174 
				   const struct drm_i915_mocs_table *table,
 193 
				   const struct drm_i915_mocs_table *table,
175 
				   u32 reg_base)
 194 
				   enum intel_ring_id ring)
176 
{
 195 
{
177 
	struct intel_ringbuffer *ringbuf = req->ringbuf;
 196 
	struct intel_ringbuffer *ringbuf = req->ringbuf;
Line 189... Line 208...
189 
 
 208 
 
190 
	intel_logical_ring_emit(ringbuf,
 209 
	intel_logical_ring_emit(ringbuf,
Line 191... Line 210...
191 
				MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
 210 
				MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
192 
 
 211 
 
193 
	for (index = 0; index < table->size; index++) {
 212 
	for (index = 0; index < table->size; index++) {
194 
		intel_logical_ring_emit(ringbuf, reg_base + index * 4);
 213 
		intel_logical_ring_emit_reg(ringbuf, mocs_register(ring, index));
195 
		intel_logical_ring_emit(ringbuf,
 214 
		intel_logical_ring_emit(ringbuf,
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196 
					table->table[index].control_value);
 215 
					table->table[index].control_value);
Line 203... Line 222...
203 
	 *
 222 
	 *
204 
	 * Entry 0 in the table is uncached - so we are just writing
 223 
	 * Entry 0 in the table is uncached - so we are just writing
205 
	 * that value to all the used entries.
 224 
	 * that value to all the used entries.
206 
	 */
 225 
	 */
207 
	for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
 226 
	for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
208 
		intel_logical_ring_emit(ringbuf, reg_base + index * 4);
 227 
		intel_logical_ring_emit_reg(ringbuf, mocs_register(ring, index));
209 
		intel_logical_ring_emit(ringbuf, table->table[0].control_value);
 228 
		intel_logical_ring_emit(ringbuf, table->table[0].control_value);
210 
	}
 229 
	}
Line 211... Line 230...
211 
 
 230 
 
212 
	intel_logical_ring_emit(ringbuf, MI_NOOP);
 231 
	intel_logical_ring_emit(ringbuf, MI_NOOP);
Line 251... Line 270...
251 
 
 270 
 
252 
	for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
 271 
	for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
253 
		value = (table->table[count].l3cc_value & 0xffff) |
 272 
		value = (table->table[count].l3cc_value & 0xffff) |
Line 254... Line 273...
254 
			((table->table[count + 1].l3cc_value & 0xffff) << 16);
 273 
			((table->table[count + 1].l3cc_value & 0xffff) << 16);
255 
 
 274 
 
256 
		intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
 275 
		intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
Line 257... Line 276...
257 
		intel_logical_ring_emit(ringbuf, value);
 276 
		intel_logical_ring_emit(ringbuf, value);
258 
	}
 277 
	}
Line 268... Line 287...
268 
	 * Now set the rest of the table to uncached - use entry 0 as
 287 
	 * Now set the rest of the table to uncached - use entry 0 as
269 
	 * this will be uncached. Leave the last pair uninitialised as
 288 
	 * this will be uncached. Leave the last pair uninitialised as
270 
	 * they are reserved by the hardware.
 289 
	 * they are reserved by the hardware.
271 
	 */
 290 
	 */
272 
	for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
 291 
	for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
273 
		intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
 292 
		intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
274 
		intel_logical_ring_emit(ringbuf, value);
 293 
		intel_logical_ring_emit(ringbuf, value);
Line 275... Line 294...
275 
 
 294 
 
276 
		value = filler;
 295 
		value = filler;
Line 302... Line 321...
302 
{
 321 
{
303 
	struct drm_i915_mocs_table t;
 322 
	struct drm_i915_mocs_table t;
304 
	int ret;
 323 
	int ret;
Line 305... Line 324...
305 
 
 324 
 
306 
	if (get_mocs_settings(req->ring->dev, &t)) {
 - 
 
307 
		/* Program the control registers */
 325 
	if (get_mocs_settings(req->ring->dev, &t)) {
308 
		ret = emit_mocs_control_table(req, &t, GEN9_GFX_MOCS_0);
 - 
 
309 
		if (ret)
 326 
		struct drm_i915_private *dev_priv = req->i915;
310 
			return ret;
 - 
 
311 
 
 - 
 
312 
		ret = emit_mocs_control_table(req, &t, GEN9_MFX0_MOCS_0);
 - 
 
313 
		if (ret)
 327 
		struct intel_engine_cs *ring;
Line 314... Line 328...
314 
			return ret;
 328 
		enum intel_ring_id ring_id;
315 
 
 - 
 
316 
		ret = emit_mocs_control_table(req, &t, GEN9_MFX1_MOCS_0);
 - 
 
317 
		if (ret)
 - 
 
318 
			return ret;
 329 
 
319 
 
 - 
 
320 
		ret = emit_mocs_control_table(req, &t, GEN9_VEBOX_MOCS_0);
 - 
 
321 
		if (ret)
 - 
 
322 
			return ret;
 330 
		/* Program the control registers */
323 
 
 331 
		for_each_ring(ring, dev_priv, ring_id) {
324 
		ret = emit_mocs_control_table(req, &t, GEN9_BLT_MOCS_0);
 332 
			ret = emit_mocs_control_table(req, &t, ring_id);
- 
 
 333 
		if (ret)
Line 325... Line 334...
325 
		if (ret)
 334 
			return ret;
326 
			return ret;
 335 
		}
327 
 
 336 
 
328 
		/* Now program the l3cc registers */
 337 
		/* Now program the l3cc registers */