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#ifndef _INTEL_LRC_H_
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#define GEN8_LR_CONTEXT_ALIGN 4096
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x07
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#define GEN8_LR_CONTEXT_ALIGN 4096
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/* Execlists regs */
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/* Execlists regs */
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#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
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#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
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#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_PTR(ring)		_MMIO((ring)->mmio_base + 0x3a0)
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#define RING_CONTEXT_STATUS_PTR(ring)		_MMIO((ring)->mmio_base + 0x3a0)
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/* The docs specify that the write pointer wraps around after 5h, "After status
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 * is written out to the last available status QW at offset 5h, this pointer
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 * wraps to 0."
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 *
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 * Therefore, one must infer than even though there are 3 bits available, 6 and
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 * 7 appear to be * reserved.
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 */
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x7
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#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
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#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
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#define GEN8_CSB_WRITE_PTR(csb_status) \
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	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
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#define GEN8_CSB_READ_PTR(csb_status) \
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	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
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/* Logical Rings */
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/* Logical Rings */
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int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
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int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
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int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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void intel_logical_ring_stop(struct intel_engine_cs *ring);
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void intel_logical_ring_stop(struct intel_engine_cs *ring);
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#define LRC_GUCSHR_PN	(0)
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#define LRC_GUCSHR_PN	(0)
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#define LRC_PPHWSP_PN	(LRC_GUCSHR_PN + 1)
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#define LRC_PPHWSP_PN	(LRC_GUCSHR_PN + 1)
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#define LRC_STATE_PN	(LRC_PPHWSP_PN + 1)
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#define LRC_STATE_PN	(LRC_PPHWSP_PN + 1)
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void intel_lr_context_free(struct intel_context *ctx);
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void intel_lr_context_free(struct intel_context *ctx);
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uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
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int intel_lr_context_deferred_alloc(struct intel_context *ctx,
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int intel_lr_context_deferred_alloc(struct intel_context *ctx,
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				    struct intel_engine_cs *ring);
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				    struct intel_engine_cs *ring);
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void intel_lr_context_unpin(struct intel_context *ctx,
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void intel_lr_context_unpin(struct drm_i915_gem_request *req);
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			    struct intel_engine_cs *engine);
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void intel_lr_context_reset(struct drm_device *dev,
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void intel_lr_context_reset(struct drm_device *dev,
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			struct intel_context *ctx);
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			struct intel_context *ctx);
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uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
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uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
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				     struct intel_engine_cs *ring);
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u32 intel_execlists_ctx_id(struct intel_context *ctx,
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				     struct intel_engine_cs *ring);
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			   struct intel_engine_cs *ring);
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/* Execlists */
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/* Execlists */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
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struct i915_execbuffer_params;
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struct i915_execbuffer_params;
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int intel_execlists_submission(struct i915_execbuffer_params *params,
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int intel_execlists_submission(struct i915_execbuffer_params *params,
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			       struct drm_i915_gem_execbuffer2 *args,
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			       struct list_head *vmas);
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			       struct drm_i915_gem_execbuffer2 *args,
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u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
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			       struct list_head *vmas);
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