WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_i2c.c

 #include
 #include "intel_drv.h"
 #include
 #include "i915_drv.h"
-struct gmbus_port {
+struct gmbus_pin {
 	const char *name;
 	int reg;
+};
-};
+/* Map gmbus pin pairs to names and registers. */
-static const struct gmbus_port gmbus_ports[] = {
+static const struct gmbus_pin gmbus_pins[] = {
-	{ "ssc", GPIOB },
+	[GMBUS_PIN_SSC] = { "ssc", GPIOB },
-	{ "vga", GPIOA },
+	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
-	{ "panel", GPIOC },
+	[GMBUS_PIN_PANEL] = { "panel", GPIOC },
-	{ "dpc", GPIOD },
+	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
-	{ "dpb", GPIOE },
+	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
+	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
+};
+static const struct gmbus_pin gmbus_pins_bdw[] = {
+	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
+	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
+	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
+	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
+};
+static const struct gmbus_pin gmbus_pins_skl[] = {
+	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
+	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
+	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
+};
+static const struct gmbus_pin gmbus_pins_bxt[] = {
+	[GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
+	[GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
+};
+/* pin is expected to be valid */
+static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
+					     unsigned int pin)
+{
+	if (IS_BROXTON(dev_priv))
+		return &gmbus_pins_bxt[pin];
+	else if (IS_SKYLAKE(dev_priv))
+		return &gmbus_pins_skl[pin];
+	else if (IS_BROADWELL(dev_priv))
+		return &gmbus_pins_bdw[pin];
+	else
+		return &gmbus_pins[pin];
+}
+bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
+			      unsigned int pin)
+{
+	unsigned int size;
+	if (IS_BROXTON(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_bxt);
+	else if (IS_SKYLAKE(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_skl);
+	else if (IS_BROADWELL(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_bdw);
+	else
+		size = ARRAY_SIZE(gmbus_pins);
-	{ "dpd", GPIOF },
+	return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
 };
 void
 intel_i2c_reset(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
+	I915_WRITE(GMBUS0, 0);
-	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
+	I915_WRITE(GMBUS4, 0);
+}
 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
 	set_clock(bus, 1);
 	intel_i2c_quirk_set(dev_priv, false);
+}
 static void
-intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
+intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
+{
 	struct drm_i915_private *dev_priv = bus->dev_priv;
 	struct i2c_algo_bit_data *algo;
 	algo = &bus->bit_algo;
-	/* -1 to map pin pair to gmbus index */
+	bus->gpio_reg = dev_priv->gpio_mmio_base +
-	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
+		get_gmbus_pin(dev_priv, pin)->reg;
 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 		     u32 gmbus2_status,
 		     u32 gmbus4_irq_en)
+{
 	int i;
-	int reg_offset = dev_priv->gpio_mmio_base;
 	u32 gmbus2 = 0;
 	DEFINE_WAIT(wait);
 	if (!HAS_GMBUS_IRQ(dev_priv->dev))
 		gmbus4_irq_en = 0;
 	/* Important: The hw handles only the first bit, so set only one! Since
 	 * we also need to check for NAKs besides the hw ready/idle signal, we
 	 * need to wake up periodically and check that ourselves. */
-	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
+	I915_WRITE(GMBUS4, gmbus4_irq_en);
 	for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
 		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 				TASK_UNINTERRUPTIBLE);
-		gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
+		gmbus2 = I915_READ_NOTRACE(GMBUS2);
 		if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 			break;
 		schedule_timeout(1);
+	}
 	finish_wait(&dev_priv->gmbus_wait_queue, &wait);
 static int
 gmbus_wait_idle(struct drm_i915_private *dev_priv)
+{
-	int ret;
-	int reg_offset = dev_priv->gpio_mmio_base;
+	int ret;
-#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
+#define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
 	if (!HAS_GMBUS_IRQ(dev_priv->dev))
 		return wait_for(C, 10);
 	/* Important: The hw handles only the first bit, so set only one! */
-	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
+	I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
 	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 				 msecs_to_jiffies_timeout(10));
-	I915_WRITE(GMBUS4 + reg_offset, 0);
+	I915_WRITE(GMBUS4, 0);
 	if (ret)
+		return 0;
-		return 0;
+	else
-	else
+		return -ETIMEDOUT;
-		return -ETIMEDOUT;
-#undef C
-}
-static int
+#undef C
 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 		u32 gmbus1_index)
 static int
-	int reg_offset = dev_priv->gpio_mmio_base;
+gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
-	u16 len = msg->len;
+		      unsigned short addr, u8 *buf, unsigned int len,
-	u8 *buf = msg->buf;
+		      u32 gmbus1_index)
+{
-	I915_WRITE(GMBUS1 + reg_offset,
+	I915_WRITE(GMBUS1,
 		   gmbus1_index |
 		   GMBUS_CYCLE_WAIT |
 		   (len << GMBUS_BYTE_COUNT_SHIFT) |
-		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
+		   (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 		   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 	while (len) {
 		int ret;
 		u32 val, loop = 0;
 		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 					   GMBUS_HW_RDY_EN);
 		if (ret)
 			return ret;
+		val = I915_READ(GMBUS3);
-		val = I915_READ(GMBUS3 + reg_offset);
+		do {
-		do {
-			*buf++ = val & 0xff;
-			val >>= 8;
+			*buf++ = val & 0xff;
+			val >>= 8;
+		} while (--len && ++loop < 4);
+	}
+	return 0;
+}
+static int
+gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
+		u32 gmbus1_index)
+{
+	u8 *buf = msg->buf;
+	unsigned int rx_size = msg->len;
+	unsigned int len;
+	int ret;
+	do {
+		len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
+		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
+					    buf, len, gmbus1_index);
+		if (ret)
+			return ret;
-		} while (--len && ++loop < 4);
+		rx_size -= len;
 		buf += len;
 	} while (rx_size != 0);
 	return 0;
 	return 0;
+}
-static int
-gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
+static int
 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
-	int reg_offset = dev_priv->gpio_mmio_base;
+		       unsigned short addr, u8 *buf, unsigned int len)
-	u16 len = msg->len;
+{
-	u8 *buf = msg->buf;
+	unsigned int chunk_size = len;
 	u32 val, loop;
 	val = loop = 0;
 	while (len && loop < 4) {
 		val |= *buf++ << (8 * loop++);
 		len -= 1;
 	}
-	I915_WRITE(GMBUS3 + reg_offset, val);
+	I915_WRITE(GMBUS3, val);
-	I915_WRITE(GMBUS1 + reg_offset,
+	I915_WRITE(GMBUS1,
 		   GMBUS_CYCLE_WAIT |
-		   (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
+		   (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
+		   (addr << GMBUS_SLAVE_ADDR_SHIFT) |
+		   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
+	while (len) {
+		int ret;
+		val = loop = 0;
+		do {
+			val |= *buf++ << (8 * loop);
+		} while (--len && ++loop < 4);
+		I915_WRITE(GMBUS3, val);
+		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
+					   GMBUS_HW_RDY_EN);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+static int
+gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
-		   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
+	u8 *buf = msg->buf;
-	while (len) {
+	unsigned int tx_size = msg->len;
-		int ret;
+	unsigned int len;
+}
 static int
 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
-{
 	int reg_offset = dev_priv->gpio_mmio_base;
 	u32 gmbus1_index = 0;
 	u32 gmbus5 = 0;
 	int ret;
 		gmbus1_index = GMBUS_CYCLE_INDEX |
 			       (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 	/* GMBUS5 holds 16-bit index */
 	if (gmbus5)
-		I915_WRITE(GMBUS5 + reg_offset, gmbus5);
+		I915_WRITE(GMBUS5, gmbus5);
 	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 	/* Clear GMBUS5 after each index transfer */
 	if (gmbus5)
-		I915_WRITE(GMBUS5 + reg_offset, 0);
+		I915_WRITE(GMBUS5, 0);
+{
 	struct intel_gmbus *bus = container_of(adapter,
 					       struct intel_gmbus,
 					       adapter);
 	struct drm_i915_private *dev_priv = bus->dev_priv;
-	int i, reg_offset;
+	int i = 0, inc, try = 0;
 	int ret = 0;
-	intel_aux_display_runtime_get(dev_priv);
+	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 	mutex_lock(&dev_priv->gmbus_mutex);
 	if (bus->force_bit) {
 		ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
+		goto out;
-		goto out;
+	}
-	}
-	reg_offset = dev_priv->gpio_mmio_base;
+retry:
 	I915_WRITE(GMBUS0, bus->reg0);
 	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
+	for (; i < num; i += inc) {
-	for (i = 0; i < num; i++) {
+		inc = 1;
 		if (gmbus_is_index_read(msgs, i, num)) {
 			ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
-			i += 1;  /* set i to the index of the read xfer */
+			inc = 2; /* an index read is two msgs */
 		} else if (msgs[i].flags & I2C_M_RD) {
 	/* Generate a STOP condition on the bus. Note that gmbus can't generata
 	 * a STOP on the very first cycle. To simplify the code we
 	 * unconditionally generate the STOP condition with an additional gmbus
 	 * cycle. */
-	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
+	I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 	/* Mark the GMBUS interface as disabled after waiting for idle.
 	 * We will re-enable it at the start of the next xfer,
 	 * till then let it sleep.
 	 */
 	if (gmbus_wait_idle(dev_priv)) {
 		DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 			 adapter->name);
 		ret = -ETIMEDOUT;
+	}
-	I915_WRITE(GMBUS0 + reg_offset, 0);
+	I915_WRITE(GMBUS0, 0);
 	ret = ret ?: i;
 	goto out;
 	/* Toggle the Software Clear Interrupt bit. This has the effect
 	 * of resetting the GMBUS controller and so clearing the
 	 * BUS_ERROR raised by the slave's NAK.
 	 */
-	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
+	I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
-	I915_WRITE(GMBUS1 + reg_offset, 0);
+	I915_WRITE(GMBUS1, 0);
-	I915_WRITE(GMBUS0 + reg_offset, 0);
+	I915_WRITE(GMBUS0, 0);
 	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
+			 adapter->name, msgs[i].addr,
+			 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
+	/*
+	 * Passive adapters sometimes NAK the first probe. Retry the first
+	 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
+	 * has retries internally. See also the retry loop in
+	 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
+	 */
+	if (ret == -ENXIO && i == 0 && try++ == 0) {
+		DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
+			      adapter->name);
-			 adapter->name, msgs[i].addr,
+		goto retry;
 			 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 	goto out;
 timeout:
 	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 		 bus->adapter.name, bus->reg0 & 0xff);
-	I915_WRITE(GMBUS0 + reg_offset, 0);
+	I915_WRITE(GMBUS0, 0);
+	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
-	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
+	bus->force_bit = 1;
+	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 	bus->force_bit = 1;
-	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
+out:
 	mutex_unlock(&dev_priv->gmbus_mutex);
 out:
  * @dev: DRM device
  */
 int intel_setup_gmbus(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_gmbus *bus;
+	unsigned int pin;
-	int ret, i;
+	int ret;
 	if (HAS_PCH_NOP(dev))
 		return 0;
 	else if (HAS_PCH_SPLIT(dev))
 		dev_priv->gpio_mmio_base = 0;
 	mutex_init(&dev_priv->gmbus_mutex);
 	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
+	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
+		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
-	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
+			continue;
 		struct intel_gmbus *bus = &dev_priv->gmbus[i];
-		u32 port = i + 1; /* +1 to map gmbus index to pin pair */
+		bus = &dev_priv->gmbus[pin];
 		bus->adapter.owner = THIS_MODULE;
 		bus->adapter.class = I2C_CLASS_DDC;
 		snprintf(bus->adapter.name,
 			 sizeof(bus->adapter.name),
 			 "i915 gmbus %s",
-			 gmbus_ports[i].name);
+			 get_gmbus_pin(dev_priv, pin)->name);
 		bus->adapter.dev.parent = &dev->pdev->dev;
 		bus->dev_priv = dev_priv;
 		bus->adapter.algo = &gmbus_algorithm;
 		/* By default use a conservative clock rate */
-		bus->reg0 = port | GMBUS_RATE_100KHZ;
+		bus->reg0 = pin | GMBUS_RATE_100KHZ;
 		/* gmbus seems to be broken on i830 */
 	intel_i2c_reset(dev_priv->dev);
 	return 0;
+err:
+	while (--pin) {
+		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
-err:
+			continue;
 	while (--i) {
-		struct intel_gmbus *bus = &dev_priv->gmbus[i];
+		bus = &dev_priv->gmbus[pin];
 		i2c_del_adapter(&bus->adapter);
+	}
 	return ret;
 }
 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
-					    unsigned port)
-{
+					    unsigned int pin)
+{
-	WARN_ON(!intel_gmbus_is_port_valid(port));
+	if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
-	/* -1 to map pin pair to gmbus index */
+		return NULL;
 	return (intel_gmbus_is_port_valid(port)) ?
-		&dev_priv->gmbus[port - 1].adapter : NULL;
+	return &dev_priv->gmbus[pin].adapter;
+}
+}
 void intel_teardown_gmbus(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_gmbus *bus;
+	unsigned int pin;
+	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
-	struct drm_i915_private *dev_priv = dev->dev_private;
+		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
-	int i;
+			continue;
 	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
-		struct intel_gmbus *bus = &dev_priv->gmbus[i];
+		bus = &dev_priv->gmbus[pin];
 		i2c_del_adapter(&bus->adapter);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_i2c.c – Rev 5060 → 6084