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#include
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#include
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#include "intel_drv.h"
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#include "intel_drv.h"
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#include
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#include
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#include "i915_drv.h"
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#include "i915_drv.h"
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enum disp_clk {
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	CDCLK,
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	CZCLK
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};
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struct gmbus_port {
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struct gmbus_port {
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	const char *name;
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	const char *name;
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	int reg;
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	int reg;
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to_intel_gmbus(struct i2c_adapter *i2c)
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to_intel_gmbus(struct i2c_adapter *i2c)
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{
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{
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	return container_of(i2c, struct intel_gmbus, adapter);
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	return container_of(i2c, struct intel_gmbus, adapter);
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}
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}
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static int get_disp_clk_div(struct drm_i915_private *dev_priv,
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			    enum disp_clk clk)
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{
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	u32 reg_val;
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	int clk_ratio;
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	reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
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	if (clk == CDCLK)
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		clk_ratio =
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			((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1;
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	else
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		clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1;
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	return clk_ratio;
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}
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static void gmbus_set_freq(struct drm_i915_private *dev_priv)
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{
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	int vco, gmbus_freq = 0, cdclk_div;
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	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
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	vco = valleyview_get_vco(dev_priv);
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	/* Get the CDCLK divide ratio */
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	cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
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	/*
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	 * Program the gmbus_freq based on the cdclk frequency.
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	 * BSpec erroneously claims we should aim for 4MHz, but
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	 * in fact 1MHz is the correct frequency.
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	 */
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	if (cdclk_div)
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		gmbus_freq = (vco << 1) / cdclk_div;
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	if (WARN_ON(gmbus_freq == 0))
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		return;
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	I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
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}
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void
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void
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intel_i2c_reset(struct drm_device *dev)
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intel_i2c_reset(struct drm_device *dev)
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{
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	/*
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	 * In BIOS-less system, program the correct gmbus frequency
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	 * before reading edid.
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	 */
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	if (IS_VALLEYVIEW(dev))
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		gmbus_set_freq(dev_priv);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
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	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
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	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
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	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
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	algo->udelay = I2C_RISEFALL_TIME;
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	algo->udelay = I2C_RISEFALL_TIME;
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	algo->timeout = usecs_to_jiffies(2200);
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	algo->timeout = usecs_to_jiffies(2200);
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	algo->data = bus;
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	algo->data = bus;
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}
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}
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/*
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 * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
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 * mode. This results in spurious interrupt warnings if the legacy irq no. is
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 * shared with another device. The kernel then disables that interrupt source
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 * and so prevents the other device from working properly.
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 */
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#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
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static int
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static int
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gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
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gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
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		     u32 gmbus2_status,
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		     u32 gmbus2_status,
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		     u32 gmbus4_irq_en)
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		     u32 gmbus4_irq_en)