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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
2 | * Copyright (c) 2006 Dave Airlie |
3 | * Copyright © 2006-2008,2010 Intel Corporation |
3 | * Copyright © 2006-2008,2010 Intel Corporation |
4 | * Jesse Barnes |
4 | * Jesse Barnes |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice (including the next |
13 | * The above copyright notice and this permission notice (including the next |
14 | * paragraph) shall be included in all copies or substantial portions of the |
14 | * paragraph) shall be included in all copies or substantial portions of the |
15 | * Software. |
15 | * Software. |
16 | * |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
23 | * DEALINGS IN THE SOFTWARE. |
23 | * DEALINGS IN THE SOFTWARE. |
24 | * |
24 | * |
25 | * Authors: |
25 | * Authors: |
26 | * Eric Anholt |
26 | * Eric Anholt |
27 | * Chris Wilson |
27 | * Chris Wilson |
28 | */ |
28 | */ |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include "intel_drv.h" |
33 | #include "intel_drv.h" |
34 | #include |
34 | #include |
35 | #include "i915_drv.h" |
35 | #include "i915_drv.h" |
36 | 36 | ||
37 | struct gmbus_port { |
37 | struct gmbus_port { |
38 | const char *name; |
38 | const char *name; |
39 | int reg; |
39 | int reg; |
40 | }; |
40 | }; |
41 | 41 | ||
42 | static const struct gmbus_port gmbus_ports[] = { |
42 | static const struct gmbus_port gmbus_ports[] = { |
43 | { "ssc", GPIOB }, |
43 | { "ssc", GPIOB }, |
44 | { "vga", GPIOA }, |
44 | { "vga", GPIOA }, |
45 | { "panel", GPIOC }, |
45 | { "panel", GPIOC }, |
46 | { "dpc", GPIOD }, |
46 | { "dpc", GPIOD }, |
47 | { "dpb", GPIOE }, |
47 | { "dpb", GPIOE }, |
48 | { "dpd", GPIOF }, |
48 | { "dpd", GPIOF }, |
49 | }; |
49 | }; |
50 | 50 | ||
51 | /* Intel GPIO access functions */ |
51 | /* Intel GPIO access functions */ |
52 | 52 | ||
53 | #define I2C_RISEFALL_TIME 10 |
53 | #define I2C_RISEFALL_TIME 10 |
54 | 54 | ||
55 | static inline struct intel_gmbus * |
55 | static inline struct intel_gmbus * |
56 | to_intel_gmbus(struct i2c_adapter *i2c) |
56 | to_intel_gmbus(struct i2c_adapter *i2c) |
57 | { |
57 | { |
58 | return container_of(i2c, struct intel_gmbus, adapter); |
58 | return container_of(i2c, struct intel_gmbus, adapter); |
59 | } |
59 | } |
60 | 60 | ||
61 | void |
61 | void |
62 | intel_i2c_reset(struct drm_device *dev) |
62 | intel_i2c_reset(struct drm_device *dev) |
63 | { |
63 | { |
64 | struct drm_i915_private *dev_priv = dev->dev_private; |
64 | struct drm_i915_private *dev_priv = dev->dev_private; |
65 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); |
65 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); |
- | 66 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); |
|
66 | } |
67 | } |
67 | 68 | ||
68 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
69 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
69 | { |
70 | { |
70 | u32 val; |
71 | u32 val; |
71 | 72 | ||
72 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
73 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
73 | if (!IS_PINEVIEW(dev_priv->dev)) |
74 | if (!IS_PINEVIEW(dev_priv->dev)) |
74 | return; |
75 | return; |
75 | 76 | ||
76 | val = I915_READ(DSPCLK_GATE_D); |
77 | val = I915_READ(DSPCLK_GATE_D); |
77 | if (enable) |
78 | if (enable) |
78 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
79 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
79 | else |
80 | else |
80 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
81 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
81 | I915_WRITE(DSPCLK_GATE_D, val); |
82 | I915_WRITE(DSPCLK_GATE_D, val); |
82 | } |
83 | } |
83 | 84 | ||
84 | static u32 get_reserved(struct intel_gmbus *bus) |
85 | static u32 get_reserved(struct intel_gmbus *bus) |
85 | { |
86 | { |
86 | struct drm_i915_private *dev_priv = bus->dev_priv; |
87 | struct drm_i915_private *dev_priv = bus->dev_priv; |
87 | struct drm_device *dev = dev_priv->dev; |
88 | struct drm_device *dev = dev_priv->dev; |
88 | u32 reserved = 0; |
89 | u32 reserved = 0; |
89 | 90 | ||
90 | /* On most chips, these bits must be preserved in software. */ |
91 | /* On most chips, these bits must be preserved in software. */ |
91 | if (!IS_I830(dev) && !IS_845G(dev)) |
92 | if (!IS_I830(dev) && !IS_845G(dev)) |
92 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
93 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
93 | (GPIO_DATA_PULLUP_DISABLE | |
94 | (GPIO_DATA_PULLUP_DISABLE | |
94 | GPIO_CLOCK_PULLUP_DISABLE); |
95 | GPIO_CLOCK_PULLUP_DISABLE); |
95 | 96 | ||
96 | return reserved; |
97 | return reserved; |
97 | } |
98 | } |
98 | 99 | ||
99 | static int get_clock(void *data) |
100 | static int get_clock(void *data) |
100 | { |
101 | { |
101 | struct intel_gmbus *bus = data; |
102 | struct intel_gmbus *bus = data; |
102 | struct drm_i915_private *dev_priv = bus->dev_priv; |
103 | struct drm_i915_private *dev_priv = bus->dev_priv; |
103 | u32 reserved = get_reserved(bus); |
104 | u32 reserved = get_reserved(bus); |
104 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); |
105 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); |
105 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
106 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
106 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; |
107 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; |
107 | } |
108 | } |
108 | 109 | ||
109 | static int get_data(void *data) |
110 | static int get_data(void *data) |
110 | { |
111 | { |
111 | struct intel_gmbus *bus = data; |
112 | struct intel_gmbus *bus = data; |
112 | struct drm_i915_private *dev_priv = bus->dev_priv; |
113 | struct drm_i915_private *dev_priv = bus->dev_priv; |
113 | u32 reserved = get_reserved(bus); |
114 | u32 reserved = get_reserved(bus); |
114 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); |
115 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); |
115 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
116 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
116 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; |
117 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; |
117 | } |
118 | } |
118 | 119 | ||
119 | static void set_clock(void *data, int state_high) |
120 | static void set_clock(void *data, int state_high) |
120 | { |
121 | { |
121 | struct intel_gmbus *bus = data; |
122 | struct intel_gmbus *bus = data; |
122 | struct drm_i915_private *dev_priv = bus->dev_priv; |
123 | struct drm_i915_private *dev_priv = bus->dev_priv; |
123 | u32 reserved = get_reserved(bus); |
124 | u32 reserved = get_reserved(bus); |
124 | u32 clock_bits; |
125 | u32 clock_bits; |
125 | 126 | ||
126 | if (state_high) |
127 | if (state_high) |
127 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; |
128 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; |
128 | else |
129 | else |
129 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | |
130 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | |
130 | GPIO_CLOCK_VAL_MASK; |
131 | GPIO_CLOCK_VAL_MASK; |
131 | 132 | ||
132 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
133 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
133 | POSTING_READ(bus->gpio_reg); |
134 | POSTING_READ(bus->gpio_reg); |
134 | } |
135 | } |
135 | 136 | ||
136 | static void set_data(void *data, int state_high) |
137 | static void set_data(void *data, int state_high) |
137 | { |
138 | { |
138 | struct intel_gmbus *bus = data; |
139 | struct intel_gmbus *bus = data; |
139 | struct drm_i915_private *dev_priv = bus->dev_priv; |
140 | struct drm_i915_private *dev_priv = bus->dev_priv; |
140 | u32 reserved = get_reserved(bus); |
141 | u32 reserved = get_reserved(bus); |
141 | u32 data_bits; |
142 | u32 data_bits; |
142 | 143 | ||
143 | if (state_high) |
144 | if (state_high) |
144 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; |
145 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; |
145 | else |
146 | else |
146 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | |
147 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | |
147 | GPIO_DATA_VAL_MASK; |
148 | GPIO_DATA_VAL_MASK; |
148 | 149 | ||
149 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
150 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
150 | POSTING_READ(bus->gpio_reg); |
151 | POSTING_READ(bus->gpio_reg); |
151 | } |
152 | } |
152 | 153 | ||
153 | static int |
154 | static int |
154 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) |
155 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) |
155 | { |
156 | { |
156 | struct intel_gmbus *bus = container_of(adapter, |
157 | struct intel_gmbus *bus = container_of(adapter, |
157 | struct intel_gmbus, |
158 | struct intel_gmbus, |
158 | adapter); |
159 | adapter); |
159 | struct drm_i915_private *dev_priv = bus->dev_priv; |
160 | struct drm_i915_private *dev_priv = bus->dev_priv; |
160 | 161 | ||
161 | intel_i2c_reset(dev_priv->dev); |
162 | intel_i2c_reset(dev_priv->dev); |
162 | intel_i2c_quirk_set(dev_priv, true); |
163 | intel_i2c_quirk_set(dev_priv, true); |
163 | set_data(bus, 1); |
164 | set_data(bus, 1); |
164 | set_clock(bus, 1); |
165 | set_clock(bus, 1); |
165 | udelay(I2C_RISEFALL_TIME); |
166 | udelay(I2C_RISEFALL_TIME); |
166 | return 0; |
167 | return 0; |
167 | } |
168 | } |
168 | 169 | ||
169 | static void |
170 | static void |
170 | intel_gpio_post_xfer(struct i2c_adapter *adapter) |
171 | intel_gpio_post_xfer(struct i2c_adapter *adapter) |
171 | { |
172 | { |
172 | struct intel_gmbus *bus = container_of(adapter, |
173 | struct intel_gmbus *bus = container_of(adapter, |
173 | struct intel_gmbus, |
174 | struct intel_gmbus, |
174 | adapter); |
175 | adapter); |
175 | struct drm_i915_private *dev_priv = bus->dev_priv; |
176 | struct drm_i915_private *dev_priv = bus->dev_priv; |
176 | 177 | ||
177 | set_data(bus, 1); |
178 | set_data(bus, 1); |
178 | set_clock(bus, 1); |
179 | set_clock(bus, 1); |
179 | intel_i2c_quirk_set(dev_priv, false); |
180 | intel_i2c_quirk_set(dev_priv, false); |
180 | } |
181 | } |
181 | 182 | ||
182 | static void |
183 | static void |
183 | intel_gpio_setup(struct intel_gmbus *bus, u32 pin) |
184 | intel_gpio_setup(struct intel_gmbus *bus, u32 pin) |
184 | { |
185 | { |
185 | struct drm_i915_private *dev_priv = bus->dev_priv; |
186 | struct drm_i915_private *dev_priv = bus->dev_priv; |
186 | struct i2c_algo_bit_data *algo; |
187 | struct i2c_algo_bit_data *algo; |
187 | 188 | ||
188 | algo = &bus->bit_algo; |
189 | algo = &bus->bit_algo; |
189 | 190 | ||
190 | /* -1 to map pin pair to gmbus index */ |
191 | /* -1 to map pin pair to gmbus index */ |
191 | bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; |
192 | bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; |
192 | 193 | ||
193 | bus->adapter.algo_data = algo; |
194 | bus->adapter.algo_data = algo; |
194 | algo->setsda = set_data; |
195 | algo->setsda = set_data; |
195 | algo->setscl = set_clock; |
196 | algo->setscl = set_clock; |
196 | algo->getsda = get_data; |
197 | algo->getsda = get_data; |
197 | algo->getscl = get_clock; |
198 | algo->getscl = get_clock; |
198 | algo->pre_xfer = intel_gpio_pre_xfer; |
199 | algo->pre_xfer = intel_gpio_pre_xfer; |
199 | algo->post_xfer = intel_gpio_post_xfer; |
200 | algo->post_xfer = intel_gpio_post_xfer; |
200 | algo->udelay = I2C_RISEFALL_TIME; |
201 | algo->udelay = I2C_RISEFALL_TIME; |
201 | algo->timeout = usecs_to_jiffies(2200); |
202 | algo->timeout = usecs_to_jiffies(2200); |
202 | algo->data = bus; |
203 | algo->data = bus; |
203 | } |
204 | } |
- | 205 | ||
- | 206 | /* |
|
- | 207 | * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI |
|
- | 208 | * mode. This results in spurious interrupt warnings if the legacy irq no. is |
|
- | 209 | * shared with another device. The kernel then disables that interrupt source |
|
- | 210 | * and so prevents the other device from working properly. |
|
- | 211 | */ |
|
- | 212 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
|
- | 213 | static int |
|
- | 214 | gmbus_wait_hw_status(struct drm_i915_private *dev_priv, |
|
- | 215 | u32 gmbus2_status, |
|
- | 216 | u32 gmbus4_irq_en) |
|
- | 217 | { |
|
- | 218 | int i; |
|
- | 219 | int reg_offset = dev_priv->gpio_mmio_base; |
|
- | 220 | u32 gmbus2 = 0; |
|
- | 221 | DEFINE_WAIT(wait); |
|
- | 222 | ||
- | 223 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
|
- | 224 | gmbus4_irq_en = 0; |
|
- | 225 | ||
- | 226 | /* Important: The hw handles only the first bit, so set only one! Since |
|
- | 227 | * we also need to check for NAKs besides the hw ready/idle signal, we |
|
- | 228 | * need to wake up periodically and check that ourselves. */ |
|
- | 229 | I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); |
|
- | 230 | ||
- | 231 | for (i = 0; i < msecs_to_jiffies(50) + 1; i++) { |
|
- | 232 | prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
|
- | 233 | TASK_UNINTERRUPTIBLE); |
|
- | 234 | ||
- | 235 | gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); |
|
- | 236 | if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) |
|
- | 237 | break; |
|
- | 238 | ||
- | 239 | schedule_timeout(1); |
|
- | 240 | } |
|
- | 241 | finish_wait(&dev_priv->gmbus_wait_queue, &wait); |
|
- | 242 | ||
- | 243 | I915_WRITE(GMBUS4 + reg_offset, 0); |
|
- | 244 | ||
- | 245 | if (gmbus2 & GMBUS_SATOER) |
|
- | 246 | return -ENXIO; |
|
- | 247 | if (gmbus2 & gmbus2_status) |
|
- | 248 | return 0; |
|
- | 249 | return -ETIMEDOUT; |
|
- | 250 | } |
|
- | 251 | ||
- | 252 | static int |
|
- | 253 | gmbus_wait_idle(struct drm_i915_private *dev_priv) |
|
- | 254 | { |
|
- | 255 | int ret; |
|
- | 256 | int reg_offset = dev_priv->gpio_mmio_base; |
|
- | 257 | ||
- | 258 | #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) |
|
- | 259 | ||
- | 260 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
|
- | 261 | return wait_for(C, 10); |
|
- | 262 | ||
- | 263 | /* Important: The hw handles only the first bit, so set only one! */ |
|
- | 264 | I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); |
|
- | 265 | ||
- | 266 | ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10); |
|
- | 267 | ||
- | 268 | I915_WRITE(GMBUS4 + reg_offset, 0); |
|
- | 269 | ||
- | 270 | if (ret) |
|
- | 271 | return 0; |
|
- | 272 | else |
|
- | 273 | return -ETIMEDOUT; |
|
- | 274 | #undef C |
|
- | 275 | } |
|
204 | 276 | ||
205 | static int |
277 | static int |
206 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
278 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
207 | u32 gmbus1_index) |
279 | u32 gmbus1_index) |
208 | { |
280 | { |
209 | int reg_offset = dev_priv->gpio_mmio_base; |
281 | int reg_offset = dev_priv->gpio_mmio_base; |
210 | u16 len = msg->len; |
282 | u16 len = msg->len; |
211 | u8 *buf = msg->buf; |
283 | u8 *buf = msg->buf; |
212 | 284 | ||
213 | I915_WRITE(GMBUS1 + reg_offset, |
285 | I915_WRITE(GMBUS1 + reg_offset, |
214 | gmbus1_index | |
286 | gmbus1_index | |
215 | GMBUS_CYCLE_WAIT | |
287 | GMBUS_CYCLE_WAIT | |
216 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
288 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
217 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
289 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
218 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
290 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
219 | while (len) { |
291 | while (len) { |
220 | int ret; |
292 | int ret; |
221 | u32 val, loop = 0; |
293 | u32 val, loop = 0; |
222 | u32 gmbus2; |
- | |
223 | 294 | ||
224 | ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & |
295 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
225 | (GMBUS_SATOER | GMBUS_HW_RDY), |
- | |
226 | 50); |
296 | GMBUS_HW_RDY_EN); |
227 | if (ret) |
- | |
228 | return -ETIMEDOUT; |
- | |
229 | if (gmbus2 & GMBUS_SATOER) |
297 | if (ret) |
230 | return -ENXIO; |
298 | return ret; |
231 | 299 | ||
232 | val = I915_READ(GMBUS3 + reg_offset); |
300 | val = I915_READ(GMBUS3 + reg_offset); |
233 | do { |
301 | do { |
234 | *buf++ = val & 0xff; |
302 | *buf++ = val & 0xff; |
235 | val >>= 8; |
303 | val >>= 8; |
236 | } while (--len && ++loop < 4); |
304 | } while (--len && ++loop < 4); |
237 | } |
305 | } |
238 | 306 | ||
239 | return 0; |
307 | return 0; |
240 | } |
308 | } |
241 | 309 | ||
242 | static int |
310 | static int |
243 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) |
311 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) |
244 | { |
312 | { |
245 | int reg_offset = dev_priv->gpio_mmio_base; |
313 | int reg_offset = dev_priv->gpio_mmio_base; |
246 | u16 len = msg->len; |
314 | u16 len = msg->len; |
247 | u8 *buf = msg->buf; |
315 | u8 *buf = msg->buf; |
248 | u32 val, loop; |
316 | u32 val, loop; |
249 | 317 | ||
250 | val = loop = 0; |
318 | val = loop = 0; |
251 | while (len && loop < 4) { |
319 | while (len && loop < 4) { |
252 | val |= *buf++ << (8 * loop++); |
320 | val |= *buf++ << (8 * loop++); |
253 | len -= 1; |
321 | len -= 1; |
254 | } |
322 | } |
255 | 323 | ||
256 | I915_WRITE(GMBUS3 + reg_offset, val); |
324 | I915_WRITE(GMBUS3 + reg_offset, val); |
257 | I915_WRITE(GMBUS1 + reg_offset, |
325 | I915_WRITE(GMBUS1 + reg_offset, |
258 | GMBUS_CYCLE_WAIT | |
326 | GMBUS_CYCLE_WAIT | |
259 | (msg->len << GMBUS_BYTE_COUNT_SHIFT) | |
327 | (msg->len << GMBUS_BYTE_COUNT_SHIFT) | |
260 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
328 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
261 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
329 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
262 | while (len) { |
330 | while (len) { |
263 | int ret; |
331 | int ret; |
264 | u32 gmbus2; |
- | |
265 | 332 | ||
266 | val = loop = 0; |
333 | val = loop = 0; |
267 | do { |
334 | do { |
268 | val |= *buf++ << (8 * loop); |
335 | val |= *buf++ << (8 * loop); |
269 | } while (--len && ++loop < 4); |
336 | } while (--len && ++loop < 4); |
270 | 337 | ||
271 | I915_WRITE(GMBUS3 + reg_offset, val); |
338 | I915_WRITE(GMBUS3 + reg_offset, val); |
272 | 339 | ||
273 | ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & |
340 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
274 | (GMBUS_SATOER | GMBUS_HW_RDY), |
- | |
275 | 50); |
341 | GMBUS_HW_RDY_EN); |
276 | if (ret) |
- | |
277 | return -ETIMEDOUT; |
- | |
278 | if (gmbus2 & GMBUS_SATOER) |
342 | if (ret) |
279 | return -ENXIO; |
343 | return ret; |
280 | } |
344 | } |
281 | return 0; |
345 | return 0; |
282 | } |
346 | } |
283 | 347 | ||
284 | /* |
348 | /* |
285 | * The gmbus controller can combine a 1 or 2 byte write with a read that |
349 | * The gmbus controller can combine a 1 or 2 byte write with a read that |
286 | * immediately follows it by using an "INDEX" cycle. |
350 | * immediately follows it by using an "INDEX" cycle. |
287 | */ |
351 | */ |
288 | static bool |
352 | static bool |
289 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) |
353 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) |
290 | { |
354 | { |
291 | return (i + 1 < num && |
355 | return (i + 1 < num && |
292 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && |
356 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && |
293 | (msgs[i + 1].flags & I2C_M_RD)); |
357 | (msgs[i + 1].flags & I2C_M_RD)); |
294 | } |
358 | } |
295 | 359 | ||
296 | static int |
360 | static int |
297 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) |
361 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) |
298 | { |
362 | { |
299 | int reg_offset = dev_priv->gpio_mmio_base; |
363 | int reg_offset = dev_priv->gpio_mmio_base; |
300 | u32 gmbus1_index = 0; |
364 | u32 gmbus1_index = 0; |
301 | u32 gmbus5 = 0; |
365 | u32 gmbus5 = 0; |
302 | int ret; |
366 | int ret; |
303 | 367 | ||
304 | if (msgs[0].len == 2) |
368 | if (msgs[0].len == 2) |
305 | gmbus5 = GMBUS_2BYTE_INDEX_EN | |
369 | gmbus5 = GMBUS_2BYTE_INDEX_EN | |
306 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); |
370 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); |
307 | if (msgs[0].len == 1) |
371 | if (msgs[0].len == 1) |
308 | gmbus1_index = GMBUS_CYCLE_INDEX | |
372 | gmbus1_index = GMBUS_CYCLE_INDEX | |
309 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); |
373 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); |
310 | 374 | ||
311 | /* GMBUS5 holds 16-bit index */ |
375 | /* GMBUS5 holds 16-bit index */ |
312 | if (gmbus5) |
376 | if (gmbus5) |
313 | I915_WRITE(GMBUS5 + reg_offset, gmbus5); |
377 | I915_WRITE(GMBUS5 + reg_offset, gmbus5); |
314 | 378 | ||
315 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); |
379 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); |
316 | 380 | ||
317 | /* Clear GMBUS5 after each index transfer */ |
381 | /* Clear GMBUS5 after each index transfer */ |
318 | if (gmbus5) |
382 | if (gmbus5) |
319 | I915_WRITE(GMBUS5 + reg_offset, 0); |
383 | I915_WRITE(GMBUS5 + reg_offset, 0); |
320 | 384 | ||
321 | return ret; |
385 | return ret; |
322 | } |
386 | } |
323 | 387 | ||
324 | static int |
388 | static int |
325 | gmbus_xfer(struct i2c_adapter *adapter, |
389 | gmbus_xfer(struct i2c_adapter *adapter, |
326 | struct i2c_msg *msgs, |
390 | struct i2c_msg *msgs, |
327 | int num) |
391 | int num) |
328 | { |
392 | { |
329 | struct intel_gmbus *bus = container_of(adapter, |
393 | struct intel_gmbus *bus = container_of(adapter, |
330 | struct intel_gmbus, |
394 | struct intel_gmbus, |
331 | adapter); |
395 | adapter); |
332 | struct drm_i915_private *dev_priv = bus->dev_priv; |
396 | struct drm_i915_private *dev_priv = bus->dev_priv; |
333 | int i, reg_offset; |
397 | int i, reg_offset; |
334 | int ret = 0; |
398 | int ret = 0; |
335 | 399 | ||
336 | mutex_lock(&dev_priv->gmbus_mutex); |
400 | mutex_lock(&dev_priv->gmbus_mutex); |
337 | 401 | ||
338 | if (bus->force_bit) { |
402 | if (bus->force_bit) { |
339 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
403 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
340 | goto out; |
404 | goto out; |
341 | } |
405 | } |
342 | 406 | ||
343 | reg_offset = dev_priv->gpio_mmio_base; |
407 | reg_offset = dev_priv->gpio_mmio_base; |
344 | 408 | ||
345 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
409 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
346 | 410 | ||
347 | for (i = 0; i < num; i++) { |
411 | for (i = 0; i < num; i++) { |
348 | u32 gmbus2; |
- | |
349 | - | ||
350 | if (gmbus_is_index_read(msgs, i, num)) { |
412 | if (gmbus_is_index_read(msgs, i, num)) { |
351 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
413 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
352 | i += 1; /* set i to the index of the read xfer */ |
414 | i += 1; /* set i to the index of the read xfer */ |
353 | } else if (msgs[i].flags & I2C_M_RD) { |
415 | } else if (msgs[i].flags & I2C_M_RD) { |
354 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); |
416 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); |
355 | } else { |
417 | } else { |
356 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
418 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
357 | } |
419 | } |
358 | 420 | ||
359 | if (ret == -ETIMEDOUT) |
421 | if (ret == -ETIMEDOUT) |
360 | goto timeout; |
422 | goto timeout; |
361 | if (ret == -ENXIO) |
423 | if (ret == -ENXIO) |
362 | goto clear_err; |
424 | goto clear_err; |
363 | 425 | ||
364 | ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & |
426 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, |
- | 427 | GMBUS_HW_WAIT_EN); |
|
365 | (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), |
428 | if (ret == -ENXIO) |
366 | 50); |
429 | goto clear_err; |
367 | if (ret) |
430 | if (ret) |
368 | goto timeout; |
- | |
369 | if (gmbus2 & GMBUS_SATOER) |
- | |
370 | goto clear_err; |
431 | goto timeout; |
371 | } |
432 | } |
372 | 433 | ||
373 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
434 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
374 | * a STOP on the very first cycle. To simplify the code we |
435 | * a STOP on the very first cycle. To simplify the code we |
375 | * unconditionally generate the STOP condition with an additional gmbus |
436 | * unconditionally generate the STOP condition with an additional gmbus |
376 | * cycle. */ |
437 | * cycle. */ |
377 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
438 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
378 | 439 | ||
379 | /* Mark the GMBUS interface as disabled after waiting for idle. |
440 | /* Mark the GMBUS interface as disabled after waiting for idle. |
380 | * We will re-enable it at the start of the next xfer, |
441 | * We will re-enable it at the start of the next xfer, |
381 | * till then let it sleep. |
442 | * till then let it sleep. |
382 | */ |
443 | */ |
383 | if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, |
444 | if (gmbus_wait_idle(dev_priv)) { |
384 | 10)) { |
- | |
385 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
445 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
386 | adapter->name); |
446 | adapter->name); |
387 | ret = -ETIMEDOUT; |
447 | ret = -ETIMEDOUT; |
388 | } |
448 | } |
389 | I915_WRITE(GMBUS0 + reg_offset, 0); |
449 | I915_WRITE(GMBUS0 + reg_offset, 0); |
390 | ret = ret ?: i; |
450 | ret = ret ?: i; |
391 | goto out; |
451 | goto out; |
392 | 452 | ||
393 | clear_err: |
453 | clear_err: |
394 | /* |
454 | /* |
395 | * Wait for bus to IDLE before clearing NAK. |
455 | * Wait for bus to IDLE before clearing NAK. |
396 | * If we clear the NAK while bus is still active, then it will stay |
456 | * If we clear the NAK while bus is still active, then it will stay |
397 | * active and the next transaction may fail. |
457 | * active and the next transaction may fail. |
398 | * |
458 | * |
399 | * If no ACK is received during the address phase of a transaction, the |
459 | * If no ACK is received during the address phase of a transaction, the |
400 | * adapter must report -ENXIO. It is not clear what to return if no ACK |
460 | * adapter must report -ENXIO. It is not clear what to return if no ACK |
401 | * is received at other times. But we have to be careful to not return |
461 | * is received at other times. But we have to be careful to not return |
402 | * spurious -ENXIO because that will prevent i2c and drm edid functions |
462 | * spurious -ENXIO because that will prevent i2c and drm edid functions |
403 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
463 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
404 | * timing out seems to happen when there _is_ a ddc chip present, but |
464 | * timing out seems to happen when there _is_ a ddc chip present, but |
405 | * it's slow responding and only answers on the 2nd retry. |
465 | * it's slow responding and only answers on the 2nd retry. |
406 | */ |
466 | */ |
407 | ret = -ENXIO; |
467 | ret = -ENXIO; |
408 | if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, |
468 | if (gmbus_wait_idle(dev_priv)) { |
409 | 10)) { |
- | |
410 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
469 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
411 | adapter->name); |
470 | adapter->name); |
412 | ret = -ETIMEDOUT; |
471 | ret = -ETIMEDOUT; |
413 | } |
472 | } |
414 | 473 | ||
415 | /* Toggle the Software Clear Interrupt bit. This has the effect |
474 | /* Toggle the Software Clear Interrupt bit. This has the effect |
416 | * of resetting the GMBUS controller and so clearing the |
475 | * of resetting the GMBUS controller and so clearing the |
417 | * BUS_ERROR raised by the slave's NAK. |
476 | * BUS_ERROR raised by the slave's NAK. |
418 | */ |
477 | */ |
419 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); |
478 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); |
420 | I915_WRITE(GMBUS1 + reg_offset, 0); |
479 | I915_WRITE(GMBUS1 + reg_offset, 0); |
421 | I915_WRITE(GMBUS0 + reg_offset, 0); |
480 | I915_WRITE(GMBUS0 + reg_offset, 0); |
422 | 481 | ||
423 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
482 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
424 | adapter->name, msgs[i].addr, |
483 | adapter->name, msgs[i].addr, |
425 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); |
484 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); |
426 | 485 | ||
427 | goto out; |
486 | goto out; |
428 | 487 | ||
429 | timeout: |
488 | timeout: |
430 | DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
489 | DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
431 | bus->adapter.name, bus->reg0 & 0xff); |
490 | bus->adapter.name, bus->reg0 & 0xff); |
432 | I915_WRITE(GMBUS0 + reg_offset, 0); |
491 | I915_WRITE(GMBUS0 + reg_offset, 0); |
433 | 492 | ||
434 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
493 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
435 | bus->force_bit = 1; |
494 | bus->force_bit = 1; |
436 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
495 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
437 | 496 | ||
438 | out: |
497 | out: |
439 | mutex_unlock(&dev_priv->gmbus_mutex); |
498 | mutex_unlock(&dev_priv->gmbus_mutex); |
440 | return ret; |
499 | return ret; |
441 | } |
500 | } |
442 | 501 | ||
443 | static u32 gmbus_func(struct i2c_adapter *adapter) |
502 | static u32 gmbus_func(struct i2c_adapter *adapter) |
444 | { |
503 | { |
445 | return i2c_bit_algo.functionality(adapter) & |
504 | return i2c_bit_algo.functionality(adapter) & |
446 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
505 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
447 | /* I2C_FUNC_10BIT_ADDR | */ |
506 | /* I2C_FUNC_10BIT_ADDR | */ |
448 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | |
507 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | |
449 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); |
508 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); |
450 | } |
509 | } |
451 | 510 | ||
452 | static const struct i2c_algorithm gmbus_algorithm = { |
511 | static const struct i2c_algorithm gmbus_algorithm = { |
453 | .master_xfer = gmbus_xfer, |
512 | .master_xfer = gmbus_xfer, |
454 | .functionality = gmbus_func |
513 | .functionality = gmbus_func |
455 | }; |
514 | }; |
456 | 515 | ||
457 | /** |
516 | /** |
458 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
517 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
459 | * @dev: DRM device |
518 | * @dev: DRM device |
460 | */ |
519 | */ |
461 | int intel_setup_gmbus(struct drm_device *dev) |
520 | int intel_setup_gmbus(struct drm_device *dev) |
462 | { |
521 | { |
463 | struct drm_i915_private *dev_priv = dev->dev_private; |
522 | struct drm_i915_private *dev_priv = dev->dev_private; |
464 | int ret, i; |
523 | int ret, i; |
465 | 524 | ||
466 | if (HAS_PCH_SPLIT(dev)) |
525 | if (HAS_PCH_SPLIT(dev)) |
467 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
526 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
- | 527 | else if (IS_VALLEYVIEW(dev)) |
|
- | 528 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
|
468 | else |
529 | else |
469 | dev_priv->gpio_mmio_base = 0; |
530 | dev_priv->gpio_mmio_base = 0; |
470 | 531 | ||
471 | mutex_init(&dev_priv->gmbus_mutex); |
532 | mutex_init(&dev_priv->gmbus_mutex); |
- | 533 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
|
472 | 534 | ||
473 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
535 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
474 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
536 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
475 | u32 port = i + 1; /* +1 to map gmbus index to pin pair */ |
537 | u32 port = i + 1; /* +1 to map gmbus index to pin pair */ |
476 | 538 | ||
477 | bus->adapter.owner = THIS_MODULE; |
539 | bus->adapter.owner = THIS_MODULE; |
478 | bus->adapter.class = I2C_CLASS_DDC; |
540 | bus->adapter.class = I2C_CLASS_DDC; |
479 | snprintf(bus->adapter.name, |
541 | snprintf(bus->adapter.name, |
480 | sizeof(bus->adapter.name), |
542 | sizeof(bus->adapter.name), |
481 | "i915 gmbus %s", |
543 | "i915 gmbus %s", |
482 | gmbus_ports[i].name); |
544 | gmbus_ports[i].name); |
483 | 545 | ||
484 | bus->adapter.dev.parent = &dev->pdev->dev; |
546 | bus->adapter.dev.parent = &dev->pdev->dev; |
485 | bus->dev_priv = dev_priv; |
547 | bus->dev_priv = dev_priv; |
486 | 548 | ||
487 | bus->adapter.algo = &gmbus_algorithm; |
549 | bus->adapter.algo = &gmbus_algorithm; |
488 | 550 | ||
489 | /* By default use a conservative clock rate */ |
551 | /* By default use a conservative clock rate */ |
490 | bus->reg0 = port | GMBUS_RATE_100KHZ; |
552 | bus->reg0 = port | GMBUS_RATE_100KHZ; |
491 | 553 | ||
492 | /* gmbus seems to be broken on i830 */ |
554 | /* gmbus seems to be broken on i830 */ |
493 | if (IS_I830(dev)) |
555 | if (IS_I830(dev)) |
494 | bus->force_bit = 1; |
556 | bus->force_bit = 1; |
495 | 557 | ||
496 | intel_gpio_setup(bus, port); |
558 | intel_gpio_setup(bus, port); |
497 | 559 | ||
498 | ret = i2c_add_adapter(&bus->adapter); |
560 | ret = i2c_add_adapter(&bus->adapter); |
499 | if (ret) |
561 | if (ret) |
500 | goto err; |
562 | goto err; |
501 | } |
563 | } |
502 | 564 | ||
503 | intel_i2c_reset(dev_priv->dev); |
565 | intel_i2c_reset(dev_priv->dev); |
504 | 566 | ||
505 | return 0; |
567 | return 0; |
506 | 568 | ||
507 | err: |
569 | err: |
508 | while (--i) { |
570 | while (--i) { |
509 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
571 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
510 | i2c_del_adapter(&bus->adapter); |
572 | i2c_del_adapter(&bus->adapter); |
511 | } |
573 | } |
512 | return ret; |
574 | return ret; |
513 | } |
575 | } |
514 | 576 | ||
515 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
577 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
516 | unsigned port) |
578 | unsigned port) |
517 | { |
579 | { |
518 | WARN_ON(!intel_gmbus_is_port_valid(port)); |
580 | WARN_ON(!intel_gmbus_is_port_valid(port)); |
519 | /* -1 to map pin pair to gmbus index */ |
581 | /* -1 to map pin pair to gmbus index */ |
520 | return (intel_gmbus_is_port_valid(port)) ? |
582 | return (intel_gmbus_is_port_valid(port)) ? |
521 | &dev_priv->gmbus[port - 1].adapter : NULL; |
583 | &dev_priv->gmbus[port - 1].adapter : NULL; |
522 | } |
584 | } |
523 | 585 | ||
524 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
586 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
525 | { |
587 | { |
526 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
588 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
527 | 589 | ||
528 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
590 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
529 | } |
591 | } |
530 | 592 | ||
531 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) |
593 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) |
532 | { |
594 | { |
533 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
595 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
534 | 596 | ||
535 | bus->force_bit += force_bit ? 1 : -1; |
597 | bus->force_bit += force_bit ? 1 : -1; |
536 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", |
598 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", |
537 | force_bit ? "en" : "dis", adapter->name, |
599 | force_bit ? "en" : "dis", adapter->name, |
538 | bus->force_bit); |
600 | bus->force_bit); |
539 | } |
601 | } |
540 | 602 | ||
541 | void intel_teardown_gmbus(struct drm_device *dev) |
603 | void intel_teardown_gmbus(struct drm_device *dev) |
542 | { |
604 | { |
543 | struct drm_i915_private *dev_priv = dev->dev_private; |
605 | struct drm_i915_private *dev_priv = dev->dev_private; |
544 | int i; |
606 | int i; |
545 | 607 | ||
546 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
608 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
547 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
609 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
548 | i2c_del_adapter(&bus->adapter); |
610 | i2c_del_adapter(&bus->adapter); |
549 | } |
611 | } |
550 | }>><>>>><>><>=>>>><>><>><>><>>>><>><> |
612 | }>><>>>><>><>=>>>><>><>><>><>>>><>><>> |