WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_i2c.c

  *	Eric Anholt
  *	Chris Wilson
  */
 #include
 #include
-#include "drmP.h"
+#include
-#include "drm.h"
+#include
 #include "intel_drv.h"
-#include "i915_drm.h"
+#include
 #include "i915_drv.h"
-#define MSEC_PER_SEC    1000L
-#define USEC_PER_MSEC   1000L
-#define NSEC_PER_USEC   1000L
-#define NSEC_PER_MSEC   1000000L
-#define USEC_PER_SEC    1000000L
-#define NSEC_PER_SEC    1000000000L
-#define FSEC_PER_SEC    1000000000000000L
-#define HZ_TO_MSEC_MUL32 0xA0000000
-#define HZ_TO_MSEC_ADJ32 0x0
-#define HZ_TO_MSEC_SHR32 28
-#define HZ_TO_MSEC_MUL64 0xA000000000000000
-#define HZ_TO_MSEC_ADJ64 0x0
-#define HZ_TO_MSEC_SHR64 60
-#define MSEC_TO_HZ_MUL32 0xCCCCCCCD
-#define MSEC_TO_HZ_ADJ32 0x733333333
-#define MSEC_TO_HZ_SHR32 35
-#define MSEC_TO_HZ_MUL64 0xCCCCCCCCCCCCCCCD
-#define MSEC_TO_HZ_ADJ64 0x73333333333333333
-#define MSEC_TO_HZ_SHR64 67
-#define HZ_TO_MSEC_NUM 10
-#define HZ_TO_MSEC_DEN 1
-#define MSEC_TO_HZ_NUM 1
-#define MSEC_TO_HZ_DEN 10
-#define HZ_TO_USEC_MUL32 0x9C400000
-#define HZ_TO_USEC_ADJ32 0x0
-#define HZ_TO_USEC_SHR32 18
-#define HZ_TO_USEC_MUL64 0x9C40000000000000
-#define HZ_TO_USEC_ADJ64 0x0
-#define HZ_TO_USEC_SHR64 50
-#define USEC_TO_HZ_MUL32 0xD1B71759
-#define USEC_TO_HZ_ADJ32 0x1FFF2E48E8A7
-#define USEC_TO_HZ_SHR32 45
-#define USEC_TO_HZ_MUL64 0xD1B71758E219652C
-#define USEC_TO_HZ_ADJ64 0x1FFF2E48E8A71DE69AD4
-#define USEC_TO_HZ_SHR64 77
-#define HZ_TO_USEC_NUM 10000
-#define HZ_TO_USEC_DEN 1
-#define USEC_TO_HZ_NUM 1
-#define USEC_TO_HZ_DEN 10000
-unsigned int inline jiffies_to_usecs(const unsigned long j)
-{
-#if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ)
-        return (USEC_PER_SEC / HZ) * j;
-#elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
-        return (j + (HZ / USEC_PER_SEC) - 1)/(HZ / USEC_PER_SEC);
-#else
-# if BITS_PER_LONG == 32
-        return (HZ_TO_USEC_MUL32 * j) >> HZ_TO_USEC_SHR32;
-# else
-        return (j * HZ_TO_USEC_NUM) / HZ_TO_USEC_DEN;
-# endif
-#endif
-}
-/*
-* When we convert to jiffies then we interpret incoming values
-* the following way:
-*
-* - negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET)
-*
-* - 'too large' values [that would result in larger than
-*   MAX_JIFFY_OFFSET values] mean 'infinite timeout' too.
-*
-* - all other values are converted to jiffies by either multiplying
-*   the input value by a factor or dividing it with a factor
-*
-* We must also be careful about 32-bit overflows.
-*/
-unsigned long msecs_to_jiffies(const unsigned int m)
-{
-        /*
-         * Negative value, means infinite timeout:
-         */
-        if ((int)m < 0)
-                return MAX_JIFFY_OFFSET;
-#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
-        /*
-         * HZ is equal to or smaller than 1000, and 1000 is a nice
-         * round multiple of HZ, divide with the factor between them,
-         * but round upwards:
-         */
-        return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);
-#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
-        /*
-         * HZ is larger than 1000, and HZ is a nice round multiple of
-         * 1000 - simply multiply with the factor between them.
-         *
-         * But first make sure the multiplication result cannot
-         * overflow:
-         */
-        if (m > jiffies_to_msecs(MAX_JIFFY_OFFSET))
-                return MAX_JIFFY_OFFSET;
-        return m * (HZ / MSEC_PER_SEC);
-#else
-        /*
-         * Generic case - multiply, round and divide. But first
-         * check that if we are doing a net multiplication, that
-         * we wouldn't overflow:
-         */
-        if (HZ > MSEC_PER_SEC && m > jiffies_to_msecs(MAX_JIFFY_OFFSET))
-                return MAX_JIFFY_OFFSET;
-        return (MSEC_TO_HZ_MUL32 * m + MSEC_TO_HZ_ADJ32)
-                >> MSEC_TO_HZ_SHR32;
-#endif
-}
-unsigned long usecs_to_jiffies(const unsigned int u)
-{
-        if (u > jiffies_to_usecs(MAX_JIFFY_OFFSET))
-                return MAX_JIFFY_OFFSET;
-#if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ)
-        return (u + (USEC_PER_SEC / HZ) - 1) / (USEC_PER_SEC / HZ);
-#elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
-        return u * (HZ / USEC_PER_SEC);
-#else
-        return (USEC_TO_HZ_MUL32 * u + USEC_TO_HZ_ADJ32)
-                >> USEC_TO_HZ_SHR32;
-#endif
+struct gmbus_port {
+	const char *name;
+	int reg;
+};
+static const struct gmbus_port gmbus_ports[] = {
+	{ "ssc", GPIOB },
+	{ "vga", GPIOA },
+	{ "panel", GPIOC },
+	{ "dpc", GPIOD },
 	{ "dpb", GPIOE },
+	{ "dpd", GPIOF },
 };
 /* Intel GPIO access functions */
-#define I2C_RISEFALL_TIME 20
+#define I2C_RISEFALL_TIME 10
-static inline struct intel_gmbus *
-to_intel_gmbus(struct i2c_adapter *i2c)
-{
-	return container_of(i2c, struct intel_gmbus, adapter);
-}
 struct intel_gpio {
-	struct i2c_adapter adapter;
+static inline struct intel_gmbus *
-	struct i2c_algo_bit_data algo;
+to_intel_gmbus(struct i2c_adapter *i2c)
 	struct drm_i915_private *dev_priv;
-	u32 reg;
-};
+	return container_of(i2c, struct intel_gmbus, adapter);
-void
 intel_i2c_reset(struct drm_device *dev)
-	struct drm_i915_private *dev_priv = dev->dev_private;
+void
-	if (HAS_PCH_SPLIT(dev))
+intel_i2c_reset(struct drm_device *dev)
 	else
 		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(DSPCLK_GATE_D, val);
+}
-static u32 get_reserved(struct intel_gpio *gpio)
+static u32 get_reserved(struct intel_gmbus *bus)
 {
-	struct drm_i915_private *dev_priv = gpio->dev_priv;
+	struct drm_i915_private *dev_priv = bus->dev_priv;
 	struct drm_device *dev = dev_priv->dev;
 	u32 reserved = 0;
 	/* On most chips, these bits must be preserved in software. */
 	if (!IS_I830(dev) && !IS_845G(dev))
-		reserved = I915_READ_NOTRACE(gpio->reg) &
+		reserved = I915_READ_NOTRACE(bus->gpio_reg) &
 					     (GPIO_DATA_PULLUP_DISABLE |
 					      GPIO_CLOCK_PULLUP_DISABLE);
 	return reserved;
 }
 static int get_clock(void *data)
 {
-	struct intel_gpio *gpio = data;
+	struct intel_gmbus *bus = data;
-	struct drm_i915_private *dev_priv = gpio->dev_priv;
+	struct drm_i915_private *dev_priv = bus->dev_priv;
-	u32 reserved = get_reserved(gpio);
+	u32 reserved = get_reserved(bus);
-	I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
+	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
-	I915_WRITE_NOTRACE(gpio->reg, reserved);
+	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
-	return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
+	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 }
 static int get_data(void *data)
 {
-	struct intel_gpio *gpio = data;
+	struct intel_gmbus *bus = data;
-	struct drm_i915_private *dev_priv = gpio->dev_priv;
+	struct drm_i915_private *dev_priv = bus->dev_priv;
-	u32 reserved = get_reserved(gpio);
+	u32 reserved = get_reserved(bus);
-	I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
+	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
-	I915_WRITE_NOTRACE(gpio->reg, reserved);
+	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
-	return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
+	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 }
 static void set_clock(void *data, int state_high)
+{
-	struct intel_gpio *gpio = data;
+	struct intel_gmbus *bus = data;
-	struct drm_i915_private *dev_priv = gpio->dev_priv;
+	struct drm_i915_private *dev_priv = bus->dev_priv;
-	u32 reserved = get_reserved(gpio);
+	u32 reserved = get_reserved(bus);
 	u32 clock_bits;
 	if (state_high)
 		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 	else
 		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 			GPIO_CLOCK_VAL_MASK;
-	I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits);
+	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
-	POSTING_READ(gpio->reg);
+	POSTING_READ(bus->gpio_reg);
+}
 static void set_data(void *data, int state_high)
+{
-	struct intel_gpio *gpio = data;
+	struct intel_gmbus *bus = data;
-	struct drm_i915_private *dev_priv = gpio->dev_priv;
+	struct drm_i915_private *dev_priv = bus->dev_priv;
-	u32 reserved = get_reserved(gpio);
-	u32 data_bits;
-	if (state_high)
-		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
-	else
-		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
-			GPIO_DATA_VAL_MASK;
-	I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits);
-	POSTING_READ(gpio->reg);
-}
-static struct i2c_adapter *
-intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
-{
-	static const int map_pin_to_reg[] = {
-,
-		GPIOB,
-		GPIOA,
-		GPIOC,
-		GPIOD,
-		GPIOE,
-,
-		GPIOF,
-	};
-	struct intel_gpio *gpio;
-	if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
-		return NULL;
-	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
-	if (gpio == NULL)
-		return NULL;
-	gpio->reg = map_pin_to_reg[pin];
-	if (HAS_PCH_SPLIT(dev_priv->dev))
-		gpio->reg += PCH_GPIOA - GPIOA;
-	gpio->dev_priv = dev_priv;
-	snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
-		 "i915 GPIO%c", "?BACDE?F"[pin]);
-//   gpio->adapter.owner = THIS_MODULE;
-	gpio->adapter.algo_data	= &gpio->algo;
-	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
-	gpio->algo.setsda = set_data;
-	gpio->algo.setscl = set_clock;
-	gpio->algo.getsda = get_data;
-	gpio->algo.getscl = get_clock;
-	gpio->algo.udelay = I2C_RISEFALL_TIME;
-	gpio->algo.timeout = usecs_to_jiffies(2200);
+	u32 reserved = get_reserved(bus);
-	gpio->algo.data = gpio;
+	u32 data_bits;
-    if (i2c_bit_add_bus(&gpio->adapter))
-       goto out_free;
-	return &gpio->adapter;
+	if (state_high)
+		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
-out_free:
+	else
-	kfree(gpio);
+		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
-	return NULL;
+			GPIO_DATA_VAL_MASK;
-static int
+	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
-intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
+	POSTING_READ(bus->gpio_reg);
-		     struct i2c_adapter *adapter,
+}
 		     struct i2c_msg *msgs,
-		     int num)
-{
-	struct intel_gpio *gpio = container_of(adapter,
-					       struct intel_gpio,
-					       adapter);
-	int ret;
-	intel_i2c_reset(dev_priv->dev);
+static int
 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
-	intel_i2c_quirk_set(dev_priv, true);
+{
-	set_data(gpio, 1);
+	struct intel_gmbus *bus = container_of(adapter,
-	set_clock(gpio, 1);
-	udelay(I2C_RISEFALL_TIME);
 					       struct intel_gmbus,
-	ret = adapter->algo->master_xfer(adapter, msgs, num);
+					       adapter);
 	struct drm_i915_private *dev_priv = bus->dev_priv;
 	set_data(gpio, 1);
-	set_clock(gpio, 1);
+	intel_i2c_reset(dev_priv->dev);
-	intel_i2c_quirk_set(dev_priv, false);
+	intel_i2c_quirk_set(dev_priv, true);
-	return ret;
+	set_data(bus, 1);
-}
+	set_clock(bus, 1);
+	udelay(I2C_RISEFALL_TIME);
+	return 0;
+}
+static void
+intel_gpio_post_xfer(struct i2c_adapter *adapter)
-static int
+{
-gmbus_xfer(struct i2c_adapter *adapter,
+	struct intel_gmbus *bus = container_of(adapter,
+					       struct intel_gmbus,
+					       adapter);
+	struct drm_i915_private *dev_priv = bus->dev_priv;
+	set_data(bus, 1);
+	set_clock(bus, 1);
+	intel_i2c_quirk_set(dev_priv, false);
+}
+static void
+intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
+{
+	struct drm_i915_private *dev_priv = bus->dev_priv;
+	struct i2c_algo_bit_data *algo;
+	algo = &bus->bit_algo;
+	/* -1 to map pin pair to gmbus index */
+	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
-	   struct i2c_msg *msgs,
-	   int num)
+	bus->adapter.algo_data = algo;
-{
-	struct intel_gmbus *bus = container_of(adapter,
+	algo->setsda = set_data;
+	algo->setscl = set_clock;
-					       struct intel_gmbus,
+	algo->getsda = get_data;
-					       adapter);
+	algo->getscl = get_clock;
-	struct drm_i915_private *dev_priv = adapter->algo_data;
+	algo->pre_xfer = intel_gpio_pre_xfer;
-	int i, reg_offset;
+	algo->post_xfer = intel_gpio_post_xfer;
+	algo->udelay = I2C_RISEFALL_TIME;
-	if (bus->force_bit)
+	algo->timeout = usecs_to_jiffies(2200);
-		return intel_i2c_quirk_xfer(dev_priv,
+	algo->data = bus;
+}
-					    bus->force_bit, msgs, num);
+static int
+gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
+		u32 gmbus1_index)
+{
-	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
+	int reg_offset = dev_priv->gpio_mmio_base;
+	u16 len = msg->len;
-	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
+	u8 *buf = msg->buf;
-	for (i = 0; i < num; i++) {
+			I915_WRITE(GMBUS1 + reg_offset,
-		u16 len = msgs[i].len;
+		   gmbus1_index |
-		u8 *buf = msgs[i].buf;
+		   GMBUS_CYCLE_WAIT |
+				   (len << GMBUS_BYTE_COUNT_SHIFT) |
+		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
+				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
+	while (len) {
+		int ret;
+				u32 val, loop = 0;
+		u32 gmbus2;
+		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
+			       (GMBUS_SATOER | GMBUS_HW_RDY),
-		if (msgs[i].flags & I2C_M_RD) {
+);
-			I915_WRITE(GMBUS1 + reg_offset,
+		if (ret)
-				   GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
+			return -ETIMEDOUT;
-				   (len << GMBUS_BYTE_COUNT_SHIFT) |
+		if (gmbus2 & GMBUS_SATOER)
-				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
+			return -ENXIO;
-				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
+				val = I915_READ(GMBUS3 + reg_offset);
-			POSTING_READ(GMBUS2+reg_offset);
+				do {
-			do {
+					*buf++ = val & 0xff;
-				u32 val, loop = 0;
+					val >>= 8;
+				} while (--len && ++loop < 4);
-				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
+	}
 					goto timeout;
-				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-					goto clear_err;
 	return 0;
-				val = I915_READ(GMBUS3 + reg_offset);
-				do {
+}
-					*buf++ = val & 0xff;
-					val >>= 8;
-				} while (--len && ++loop < 4);
+static int
-			} while (len);
+gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 		} else {
-			u32 val, loop;
+	int reg_offset = dev_priv->gpio_mmio_base;
 	u16 len = msg->len;
+	u8 *buf = msg->buf;
+			u32 val, loop;
+			val = loop = 0;
+	while (len && loop < 4) {
+		val |= *buf++ << (8 * loop++);
+		len -= 1;
+	}
+			I915_WRITE(GMBUS3 + reg_offset, val);
+			I915_WRITE(GMBUS1 + reg_offset,
+		   GMBUS_CYCLE_WAIT |
+		   (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
+		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
+				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
+			while (len) {
+		int ret;
+		u32 gmbus2;
+				val = loop = 0;
+				do {
+					val |= *buf++ << (8 * loop);
+				} while (--len && ++loop < 4);
+				I915_WRITE(GMBUS3 + reg_offset, val);
+		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
+			       (GMBUS_SATOER | GMBUS_HW_RDY),
+);
+		if (ret)
+			return -ETIMEDOUT;
+		if (gmbus2 & GMBUS_SATOER)
+			return -ENXIO;
+	}
+	return 0;
+}
+/*
+ * The gmbus controller can combine a 1 or 2 byte write with a read that
+ * immediately follows it by using an "INDEX" cycle.
+ */
+static bool
+gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
+{
+	return (i + 1 < num &&
+		!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
+		(msgs[i + 1].flags & I2C_M_RD));
-			val = loop = 0;
+}
+static int
+gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
+{
+	int reg_offset = dev_priv->gpio_mmio_base;
+	u32 gmbus1_index = 0;
+	u32 gmbus5 = 0;
+	int ret;
+	if (msgs[0].len == 2)
+		gmbus5 = GMBUS_2BYTE_INDEX_EN |
+			 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
+	if (msgs[0].len == 1)
+		gmbus1_index = GMBUS_CYCLE_INDEX |
+			       (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
+	/* GMBUS5 holds 16-bit index */
+	if (gmbus5)
+		I915_WRITE(GMBUS5 + reg_offset, gmbus5);
+	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 			do {
+	/* Clear GMBUS5 after each index transfer */
+	if (gmbus5)
+		I915_WRITE(GMBUS5 + reg_offset, 0);
+	return ret;
+}
+static int
+gmbus_xfer(struct i2c_adapter *adapter,
+	   struct i2c_msg *msgs,
+	   int num)
+{
+	struct intel_gmbus *bus = container_of(adapter,
+					       struct intel_gmbus,
+					       adapter);
-				val |= *buf++ << (8 * loop);
+	struct drm_i915_private *dev_priv = bus->dev_priv;
-			} while (--len && ++loop < 4);
+	int i, reg_offset;
 	int ret = 0;
+	mutex_lock(&dev_priv->gmbus_mutex);
-			I915_WRITE(GMBUS3 + reg_offset, val);
+	if (bus->force_bit) {
+		ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
+		goto out;
+			}
+	reg_offset = dev_priv->gpio_mmio_base;
 			I915_WRITE(GMBUS1 + reg_offset,
-				   (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
+	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
+	for (i = 0; i < num; i++) {
+		u32 gmbus2;
+		if (gmbus_is_index_read(msgs, i, num)) {
+			ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
+			i += 1;  /* set i to the index of the read xfer */
+		} else if (msgs[i].flags & I2C_M_RD) {
+			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
+		} else {
+			ret = gmbus_xfer_write(dev_priv, &msgs[i]);
+		}
+		if (ret == -ETIMEDOUT)
+			goto timeout;
+		if (ret == -ENXIO)
+			goto clear_err;
-				   (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
+		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
-				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
+			       (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
+);
+		if (ret)
+			goto timeout;
+		if (gmbus2 & GMBUS_SATOER)
+			goto clear_err;
+	}
+	/* Generate a STOP condition on the bus. Note that gmbus can't generata
+	 * a STOP on the very first cycle. To simplify the code we
+	 * unconditionally generate the STOP condition with an additional gmbus
+	 * cycle. */
+	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
+	/* Mark the GMBUS interface as disabled after waiting for idle.
+	 * We will re-enable it at the start of the next xfer,
+	 * till then let it sleep.
+	 */
+	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
+)) {
+		DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
+			 adapter->name);
-				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
+		ret = -ETIMEDOUT;
 			POSTING_READ(GMBUS2+reg_offset);
 	I915_WRITE(GMBUS0 + reg_offset, 0);
-			while (len) {
+	ret = ret ?: i;
-				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
+	goto out;
 					goto timeout;
-				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-					goto clear_err;
-				val = loop = 0;
-				do {
-					val |= *buf++ << (8 * loop);
+clear_err:
+	/*
+	 * Wait for bus to IDLE before clearing NAK.
+	 * If we clear the NAK while bus is still active, then it will stay
+	 * active and the next transaction may fail.
+	 *
-				} while (--len && ++loop < 4);
+	 * If no ACK is received during the address phase of a transaction, the
 	 * adapter must report -ENXIO. It is not clear what to return if no ACK
-				I915_WRITE(GMBUS3 + reg_offset, val);
+	 * is received at other times. But we have to be careful to not return
-				POSTING_READ(GMBUS2+reg_offset);
+	 * spurious -ENXIO because that will prevent i2c and drm edid functions
 	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
 	 * timing out seems to happen when there _is_ a ddc chip present, but
-		if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
+	 * it's slow responding and only answers on the 2nd retry.
-			goto timeout;
+	 */
+	ret = -ENXIO;
-		if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
+	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
+)) {
-			goto clear_err;
+		DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 			      adapter->name);
 		ret = -ETIMEDOUT;
-	goto done;
-clear_err:
-	/* Toggle the Software Clear Interrupt bit. This has the effect
-	 * of resetting the GMBUS controller and so clearing the
-	 * BUS_ERROR raised by the slave's NAK.
+	}
-	 */
-	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
-	I915_WRITE(GMBUS1 + reg_offset, 0);
+	/* Toggle the Software Clear Interrupt bit. This has the effect
 	 * of resetting the GMBUS controller and so clearing the
-done:
+	 * BUS_ERROR raised by the slave's NAK.
-	/* Mark the GMBUS interface as disabled. We will re-enable it at the
+	 */
  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  * @dev: DRM device
  */
 int intel_setup_gmbus(struct drm_device *dev)
+{
-	static const char *names[GMBUS_NUM_PORTS] = {
-		"disabled",
-		"ssc",
-		"vga",
-		"panel",
-		"dpc",
-		"dpb",
-		"reserved",
-		"dpd",
-	};
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret, i;
+	if (HAS_PCH_SPLIT(dev))
-	dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
+		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
-				  GFP_KERNEL);
+	else
+		dev_priv->gpio_mmio_base = 0;
-	if (dev_priv->gmbus == NULL)
-		return -ENOMEM;
+	mutex_init(&dev_priv->gmbus_mutex);
+	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
-	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
+		struct intel_gmbus *bus = &dev_priv->gmbus[i];
-		struct intel_gmbus *bus = &dev_priv->gmbus[i];
+		u32 port = i + 1; /* +1 to map gmbus index to pin pair */
-//       bus->adapter.owner = THIS_MODULE;
+		bus->adapter.owner = THIS_MODULE;
 		bus->adapter.class = I2C_CLASS_DDC;
 		snprintf(bus->adapter.name,
 			 sizeof(bus->adapter.name),
 			 "i915 gmbus %s",
-			 names[i]);
+			 gmbus_ports[i].name);
-		bus->adapter.dev.parent = &dev->pdev->dev;
-		bus->adapter.algo_data	= dev_priv;
-		bus->adapter.algo = &gmbus_algorithm;
+		bus->adapter.dev.parent = &dev->pdev->dev;
+		bus->dev_priv = dev_priv;
+		bus->adapter.algo = &gmbus_algorithm;
+		/* By default use a conservative clock rate */
+		bus->reg0 = port | GMBUS_RATE_100KHZ;
-//       ret = i2c_add_adapter(&bus->adapter);
-//       if (ret)
 //           goto err;
 		/* gmbus seems to be broken on i830 */
-		/* By default use a conservative clock rate */
+		if (IS_I830(dev))
 err:
 //   while (--i) {
 //       struct intel_gmbus *bus = &dev_priv->gmbus[i];
 //       i2c_del_adapter(&bus->adapter);
 //   }
-	kfree(dev_priv->gmbus);
-	dev_priv->gmbus = NULL;
 	return ret;
+}
+struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
+					    unsigned port)
+{
+	WARN_ON(!intel_gmbus_is_port_valid(port));
+	/* -1 to map pin pair to gmbus index */
+	return (intel_gmbus_is_port_valid(port)) ?
+		&dev_priv->gmbus[port - 1].adapter : NULL;
+}
 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
+{
 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
+{
-	struct intel_gmbus *bus = to_intel_gmbus(adapter);
-	if (force_bit) {
-		if (bus->force_bit == NULL) {
-			struct drm_i915_private *dev_priv = adapter->algo_data;
-			bus->force_bit = intel_gpio_create(dev_priv,
-							   bus->reg0 & 0xff);
-		}
-	} else {
-		if (bus->force_bit) {
-//           i2c_del_adapter(bus->force_bit);
+	struct intel_gmbus *bus = to_intel_gmbus(adapter);
-			kfree(bus->force_bit);
-			bus->force_bit = NULL;
 	bus->force_bit = force_bit;
+}
 void intel_teardown_gmbus(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int i;
+{
-	if (dev_priv->gmbus == NULL)
+	struct drm_i915_private *dev_priv = dev->dev_private;
-		return;
-	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
-		struct intel_gmbus *bus = &dev_priv->gmbus[i];
-		if (bus->force_bit) {
+	int i;
 //           i2c_del_adapter(bus->force_bit);
-			kfree(bus->force_bit);
-		}
-//       i2c_del_adapter(&bus->adapter);
 	for (i = 0; i < GMBUS_NUM_PORTS; i++) {

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_i2c.c – Rev 2342 → 3031