WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_hdmi.c


/*
 * Copyright 2006 Dave Airlie 
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt 
 *	Jesse Barnes 
 */
 
#include 
#include 
#include 
#include 
#include 
#include 
#include "intel_drv.h"
#include 
#include "i915_drv.h"
 
static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
{
	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
}
 
static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t enabled_bits;
 
	enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
 
	WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
	     "HDMI port enabled, expecting disabled\n");
}
 
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
{
	struct intel_digital_port *intel_dig_port =
		container_of(encoder, struct intel_digital_port, base.base);
	return &intel_dig_port->hdmi;
}
 
static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
 
}
 
void intel_dip_infoframe_csum(struct dip_infoframe *frame)
{
	uint8_t *data = (uint8_t *)frame;
	uint8_t sum = 0;
	unsigned i;
 
	frame->checksum = 0;
	frame->ecc = 0;
 
	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
		sum += data[i];
 
	frame->checksum = 0x100 - sum;
}
 
static u32 g4x_infoframe_index(struct dip_infoframe *frame)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return VIDEO_DIP_SELECT_AVI;
	case DIP_TYPE_SPD:
		return VIDEO_DIP_SELECT_SPD;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}
 
static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI;
	case DIP_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}
 
static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI_HSW;
	case DIP_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD_HSW;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}
 
static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return HSW_TVIDEO_DIP_AVI_DATA(pipe);
	case DIP_TYPE_SPD:
		return HSW_TVIDEO_DIP_SPD_DATA(pipe);
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}
 
static void g4x_write_infoframe(struct drm_encoder *encoder,
				 struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val = I915_READ(VIDEO_DIP_CTL);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(frame);
 
	val &= ~g4x_infoframe_enable(frame);
 
	I915_WRITE(VIDEO_DIP_CTL, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VIDEO_DIP_DATA, 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(frame);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(VIDEO_DIP_CTL, val);
	POSTING_READ(VIDEO_DIP_CTL);
}
 
static void ibx_write_infoframe(struct drm_encoder *encoder,
				     struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(reg);
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(frame);
 
	val &= ~g4x_infoframe_enable(frame);
 
	I915_WRITE(reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(frame);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}
 
static void cpt_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(reg);
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(frame);
 
	/* The DIP control register spec says that we need to update the AVI
	 * infoframe without clearing its enable bit */
	if (frame->type != DIP_TYPE_AVI)
		val &= ~g4x_infoframe_enable(frame);
 
	I915_WRITE(reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(frame);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}
 
static void vlv_write_infoframe(struct drm_encoder *encoder,
				     struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(reg);
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(frame);
 
	val &= ~g4x_infoframe_enable(frame);
 
	I915_WRITE(reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(frame);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}
 
static void hsw_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
	unsigned int i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(ctl_reg);
 
	if (data_reg == 0)
		return;
 
	val &= ~hsw_infoframe_enable(frame);
	I915_WRITE(ctl_reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(data_reg + i, *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(data_reg + i, 0);
	mmiowb();
 
	val |= hsw_infoframe_enable(frame);
	I915_WRITE(ctl_reg, val);
	POSTING_READ(ctl_reg);
}
 
static void intel_set_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 
	intel_dip_infoframe_csum(frame);
	intel_hdmi->write_infoframe(encoder, frame);
}
 
static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
					 struct drm_display_mode *adjusted_mode)
{
	struct dip_infoframe avi_if = {
		.type = DIP_TYPE_AVI,
		.ver = DIP_VERSION_AVI,
		.len = DIP_LEN_AVI,
	};
 
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
		avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 
	avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode);
 
	intel_set_infoframe(encoder, &avi_if);
}
 
static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
{
	struct dip_infoframe spd_if;
 
	memset(&spd_if, 0, sizeof(spd_if));
	spd_if.type = DIP_TYPE_SPD;
	spd_if.ver = DIP_VERSION_SPD;
	spd_if.len = DIP_LEN_SPD;
	strcpy(spd_if.body.spd.vn, "Intel");
	strcpy(spd_if.body.spd.pd, "Integrated gfx");
	spd_if.body.spd.sdi = DIP_SPD_PC;
 
	intel_set_infoframe(encoder, &spd_if);
}
 
static void g4x_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = VIDEO_DIP_CTL;
	u32 val = I915_READ(reg);
	u32 port;
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* If the registers were not initialized yet, they might be zeroes,
	 * which means we're selecting the AVI DIP and we're setting its
	 * frequency to once. This seems to really confuse the HW and make
	 * things stop working (the register spec says the AVI always needs to
	 * be sent every VSync). So here we avoid writing to the register more
	 * than we need and also explicitly select the AVI DIP and explicitly
	 * set its frequency to every VSync. Avoiding to write it twice seems to
	 * be enough to solve the problem, but being defensive shouldn't hurt us
	 * either. */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	switch (intel_hdmi->sdvox_reg) {
	case SDVOB:
		port = VIDEO_DIP_PORT_B;
		break;
	case SDVOC:
		port = VIDEO_DIP_PORT_C;
		break;
	default:
		BUG();
		return;
	}
 
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
			POSTING_READ(reg);
		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}
 
	val |= VIDEO_DIP_ENABLE;
	val &= ~VIDEO_DIP_ENABLE_VENDOR;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}
 
static void ibx_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
	u32 port;
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	switch (intel_hdmi->sdvox_reg) {
	case HDMIB:
		port = VIDEO_DIP_PORT_B;
		break;
	case HDMIC:
		port = VIDEO_DIP_PORT_C;
		break;
	case HDMID:
		port = VIDEO_DIP_PORT_D;
		break;
	default:
		BUG();
		return;
	}
 
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
			POSTING_READ(reg);
		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}
 
	val |= VIDEO_DIP_ENABLE;
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}
 
static void cpt_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	/* Set both together, unset both together: see the spec. */
	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}
 
static void vlv_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	val |= VIDEO_DIP_ENABLE;
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}
 
static void hsw_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	if (!intel_hdmi->has_hdmi_sink) {
		I915_WRITE(reg, 0);
		POSTING_READ(reg);
		return;
	}
 
	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
		 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}
 
static void intel_hdmi_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 sdvox;
 
	sdvox = SDVO_ENCODING_HDMI;
	if (!HAS_PCH_SPLIT(dev))
		sdvox |= intel_hdmi->color_range;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 
	if (intel_crtc->bpp > 24)
		sdvox |= COLOR_FORMAT_12bpc;
	else
		sdvox |= COLOR_FORMAT_8bpc;
 
	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		sdvox |= HDMI_MODE_SELECT;
 
	if (intel_hdmi->has_audio) {
		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
		sdvox |= SDVO_AUDIO_ENABLE;
		sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
		intel_write_eld(encoder, adjusted_mode);
	}
 
		if (HAS_PCH_CPT(dev))
		sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
	else if (intel_crtc->pipe == PIPE_B)
			sdvox |= SDVO_PIPE_B_SELECT;
 
	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
	POSTING_READ(intel_hdmi->sdvox_reg);
 
	intel_hdmi->set_infoframes(encoder, adjusted_mode);
}
 
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
				    enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 tmp;
 
	tmp = I915_READ(intel_hdmi->sdvox_reg);
 
	if (!(tmp & SDVO_ENABLE))
		return false;
 
	if (HAS_PCH_CPT(dev))
		*pipe = PORT_TO_PIPE_CPT(tmp);
	else
		*pipe = PORT_TO_PIPE(tmp);
 
	return true;
}
 
static void intel_enable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;
	u32 enable_bits = SDVO_ENABLE;
 
	if (intel_hdmi->has_audio)
		enable_bits |= SDVO_AUDIO_ENABLE;
 
	temp = I915_READ(intel_hdmi->sdvox_reg);
 
	/* HW workaround for IBX, we need to move the port to transcoder A
	 * before disabling it. */
	if (HAS_PCH_IBX(dev)) {
		struct drm_crtc *crtc = encoder->base.crtc;
		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 
		/* Restore the transcoder select bit. */
		if (pipe == PIPE_B)
			enable_bits |= SDVO_PIPE_B_SELECT;
	}
 
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
 
	temp |= enable_bits;
 
	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);
 
	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
}
 
static void intel_disable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;
	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 
	temp = I915_READ(intel_hdmi->sdvox_reg);
 
	/* HW workaround for IBX, we need to move the port to transcoder A
	 * before disabling it. */
	if (HAS_PCH_IBX(dev)) {
		struct drm_crtc *crtc = encoder->base.crtc;
		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 
			if (temp & SDVO_PIPE_B_SELECT) {
				temp &= ~SDVO_PIPE_B_SELECT;
				I915_WRITE(intel_hdmi->sdvox_reg, temp);
				POSTING_READ(intel_hdmi->sdvox_reg);
 
				/* Again we need to write this twice. */
				I915_WRITE(intel_hdmi->sdvox_reg, temp);
				POSTING_READ(intel_hdmi->sdvox_reg);
 
				/* Transcoder selection bits only update
				 * effectively on vblank. */
				if (crtc)
					intel_wait_for_vblank(dev, pipe);
				else
					msleep(50);
			}
	}
 
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
 
		temp &= ~enable_bits;
 
	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);
 
	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
}
 
static int intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
		return MODE_CLOCK_LOW;
 
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;
 
	return MODE_OK;
}
 
bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}
 
static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
{
	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit;
 
	switch (intel_hdmi->sdvox_reg) {
	case SDVOB:
		bit = HDMIB_HOTPLUG_LIVE_STATUS;
		break;
	case SDVOC:
		bit = HDMIC_HOTPLUG_LIVE_STATUS;
		break;
	default:
		bit = 0;
		break;
	}
 
	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
 
static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	enum drm_connector_status status = connector_status_disconnected;
 
	if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
		return status;
 
	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	edid = drm_get_edid(connector,
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
 
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
			status = connector_status_connected;
			if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
				intel_hdmi->has_hdmi_sink =
						drm_detect_hdmi_monitor(edid);
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
		}
		kfree(edid);
	}
 
	if (status == connector_status_connected) {
		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
			intel_hdmi->has_audio =
				(intel_hdmi->force_audio == HDMI_AUDIO_ON);
		intel_encoder->type = INTEL_OUTPUT_HDMI;
	}
 
	return status;
}
 
static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
 
	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */
 
	return intel_ddc_get_modes(connector,
				   intel_gmbus_get_adapter(dev_priv,
							   intel_hdmi->ddc_bus));
}
 
static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;
 
	edid = drm_get_edid(connector,
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}
 
	return has_audio;
}
 
static int
intel_hdmi_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	int ret;
 
	ret = drm_object_property_set_value(&connector->base, property, val);
	if (ret)
		return ret;
#if 0
	if (property == dev_priv->force_audio_property) {
		enum hdmi_force_audio i = val;
		bool has_audio;
 
		if (i == intel_hdmi->force_audio)
			return 0;
 
		intel_hdmi->force_audio = i;
 
		if (i == HDMI_AUDIO_AUTO)
			has_audio = intel_hdmi_detect_audio(connector);
		else
			has_audio = (i == HDMI_AUDIO_ON);
 
		if (i == HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink = 0;
 
		intel_hdmi->has_audio = has_audio;
		goto done;
	}
#endif
 
	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_hdmi->color_range)
			return 0;
 
		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
		goto done;
	}
 
	return -EINVAL;
 
done:
	if (intel_dig_port->base.base.crtc) {
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
		intel_set_mode(crtc, &crtc->mode,
			       crtc->x, crtc->y, crtc->fb);
	}
 
	return 0;
}
 
static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}
 
 
 
 
 
 
 
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	.mode_fixup = intel_hdmi_mode_fixup,
	.mode_set = intel_hdmi_mode_set,
	.disable = intel_encoder_noop,
};
 
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.dpms = intel_connector_dpms,
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.set_property = intel_hdmi_set_property,
	.destroy = intel_hdmi_destroy,
};
 
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
	.best_encoder = intel_best_encoder,
};
 
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
	.destroy = intel_encoder_destroy,
};
 
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
	intel_attach_force_audio_property(connector);
	intel_attach_broadcast_rgb_property(connector);
}
 
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
 
 
	struct drm_i915_private *dev_priv = dev->dev_private;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
	enum port port = intel_dig_port->port;
 
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 
 
 
	connector->polled = DRM_CONNECTOR_POLL_HPD;
	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;
 
 
 
 
 
	switch (port) {
	case PORT_B:
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
		break;
	case PORT_C:
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
		break;
	case PORT_D:
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
		break;
	case PORT_A:
		/* Internal port only for eDP. */
	default:
		BUG();
	}
 
 
 
	if (!HAS_PCH_SPLIT(dev)) {
		intel_hdmi->write_infoframe = g4x_write_infoframe;
		intel_hdmi->set_infoframes = g4x_set_infoframes;
	} else if (IS_VALLEYVIEW(dev)) {
		intel_hdmi->write_infoframe = vlv_write_infoframe;
		intel_hdmi->set_infoframes = vlv_set_infoframes;
	} else if (IS_HASWELL(dev)) {
		intel_hdmi->write_infoframe = hsw_write_infoframe;
		intel_hdmi->set_infoframes = hsw_set_infoframes;
	} else if (HAS_PCH_IBX(dev)) {
		intel_hdmi->write_infoframe = ibx_write_infoframe;
		intel_hdmi->set_infoframes = ibx_set_infoframes;
	} else {
		intel_hdmi->write_infoframe = cpt_write_infoframe;
		intel_hdmi->set_infoframes = cpt_set_infoframes;
	}
 
 
 
	if (IS_HASWELL(dev))
 
 
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
 
 
 
 
 
 
	else
 
	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
	intel_hdmi_add_properties(intel_hdmi, connector);
 
	intel_connector_attach_encoder(intel_connector, intel_encoder);
	drm_sysfs_connector_add(connector);
 
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
 
void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;
 
	intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
	if (!intel_dig_port)
		return;
 
	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}
 
	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;
 
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);
	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
 
	intel_encoder->enable = intel_enable_hdmi;
	intel_encoder->disable = intel_disable_hdmi;
	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 
	intel_encoder->type = INTEL_OUTPUT_HDMI;
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	intel_encoder->cloneable = false;
 
	intel_dig_port->port = port;
	intel_dig_port->hdmi.sdvox_reg = sdvox_reg;
	intel_dig_port->dp.output_reg = 0;
 
	intel_hdmi_init_connector(intel_dig_port, intel_connector);
}

Rev 3031	Rev 3243
1	/*	1	/*
2	* Copyright 2006 Dave Airlie	2	* Copyright 2006 Dave Airlie
3	* Copyright © 2006-2009 Intel Corporation	3	* Copyright © 2006-2009 Intel Corporation
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),	6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation	7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the	9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:	10	* Software is furnished to do so, subject to the following conditions:
11	*	11	*
12	* The above copyright notice and this permission notice (including the next	12	* The above copyright notice and this permission notice (including the next
13	* paragraph) shall be included in all copies or substantial portions of the	13	* paragraph) shall be included in all copies or substantial portions of the
14	* Software.	14	* Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22	* DEALINGS IN THE SOFTWARE.	22	* DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors:	24	* Authors:
25	* Eric Anholt	25	* Eric Anholt
26	* Jesse Barnes	26	* Jesse Barnes
27	*/	27	*/
28		28
29	#include	29	#include
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	#include	33	#include
34	#include	34	#include
35	#include "intel_drv.h"	35	#include "intel_drv.h"
36	#include	36	#include
37	#include "i915_drv.h"	37	#include "i915_drv.h"
-		38
-		39	static struct drm_device intel_hdmi_to_dev(struct intel_hdmi intel_hdmi)
-		40	{
-		41	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
-		42	}
38		43
39	static void	44	static void
40	assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)	45	assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
41	{	46	{
42	struct drm_device *dev = intel_hdmi->base.base.dev;	47	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
43	struct drm_i915_private *dev_priv = dev->dev_private;	48	struct drm_i915_private *dev_priv = dev->dev_private;
44	uint32_t enabled_bits;	49	uint32_t enabled_bits;
45		50
46	enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;	51	enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
47		52
48	WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,	53	WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
49	"HDMI port enabled, expecting disabled\n");	54	"HDMI port enabled, expecting disabled\n");
50	}	55	}
51		56
52	struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)	57	struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
53	{	58	{
-		59	struct intel_digital_port *intel_dig_port =
54	return container_of(encoder, struct intel_hdmi, base.base);	60	container_of(encoder, struct intel_digital_port, base.base);
-		61	return &intel_dig_port->hdmi;
55	}	62	}
56		63
57	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)	64	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
58	{	65	{
59	return container_of(intel_attached_encoder(connector),	66	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
60	struct intel_hdmi, base);	-
61	}	67	}
62		68
63	void intel_dip_infoframe_csum(struct dip_infoframe *frame)	69	void intel_dip_infoframe_csum(struct dip_infoframe *frame)
64	{	70	{
65	uint8_t data = (uint8_t )frame;	71	uint8_t data = (uint8_t )frame;
66	uint8_t sum = 0;	72	uint8_t sum = 0;
67	unsigned i;	73	unsigned i;
68		74
69	frame->checksum = 0;	75	frame->checksum = 0;
70	frame->ecc = 0;	76	frame->ecc = 0;
71		77
72	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)	78	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
73	sum += data[i];	79	sum += data[i];
74		80
75	frame->checksum = 0x100 - sum;	81	frame->checksum = 0x100 - sum;
76	}	82	}
77		83
78	static u32 g4x_infoframe_index(struct dip_infoframe *frame)	84	static u32 g4x_infoframe_index(struct dip_infoframe *frame)
79	{	85	{
80	switch (frame->type) {	86	switch (frame->type) {
81	case DIP_TYPE_AVI:	87	case DIP_TYPE_AVI:
82	return VIDEO_DIP_SELECT_AVI;	88	return VIDEO_DIP_SELECT_AVI;
83	case DIP_TYPE_SPD:	89	case DIP_TYPE_SPD:
84	return VIDEO_DIP_SELECT_SPD;	90	return VIDEO_DIP_SELECT_SPD;
85	default:	91	default:
86	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);	92	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
87	return 0;	93	return 0;
88	}	94	}
89	}	95	}
90		96
91	static u32 g4x_infoframe_enable(struct dip_infoframe *frame)	97	static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
92	{	98	{
93	switch (frame->type) {	99	switch (frame->type) {
94	case DIP_TYPE_AVI:	100	case DIP_TYPE_AVI:
95	return VIDEO_DIP_ENABLE_AVI;	101	return VIDEO_DIP_ENABLE_AVI;
96	case DIP_TYPE_SPD:	102	case DIP_TYPE_SPD:
97	return VIDEO_DIP_ENABLE_SPD;	103	return VIDEO_DIP_ENABLE_SPD;
98	default:	104	default:
99	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);	105	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
100	return 0;	106	return 0;
101	}	107	}
102	}	108	}
103		109
104	static u32 hsw_infoframe_enable(struct dip_infoframe *frame)	110	static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
105	{	111	{
106	switch (frame->type) {	112	switch (frame->type) {
107	case DIP_TYPE_AVI:	113	case DIP_TYPE_AVI:
108	return VIDEO_DIP_ENABLE_AVI_HSW;	114	return VIDEO_DIP_ENABLE_AVI_HSW;
109	case DIP_TYPE_SPD:	115	case DIP_TYPE_SPD:
110	return VIDEO_DIP_ENABLE_SPD_HSW;	116	return VIDEO_DIP_ENABLE_SPD_HSW;
111	default:	117	default:
112	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);	118	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
113	return 0;	119	return 0;
114	}	120	}
115	}	121	}
116		122
117	static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)	123	static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
118	{	124	{
119	switch (frame->type) {	125	switch (frame->type) {
120	case DIP_TYPE_AVI:	126	case DIP_TYPE_AVI:
121	return HSW_TVIDEO_DIP_AVI_DATA(pipe);	127	return HSW_TVIDEO_DIP_AVI_DATA(pipe);
122	case DIP_TYPE_SPD:	128	case DIP_TYPE_SPD:
123	return HSW_TVIDEO_DIP_SPD_DATA(pipe);	129	return HSW_TVIDEO_DIP_SPD_DATA(pipe);
124	default:	130	default:
125	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);	131	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
126	return 0;	132	return 0;
127	}	133	}
128	}	134	}
129		135
130	static void g4x_write_infoframe(struct drm_encoder *encoder,	136	static void g4x_write_infoframe(struct drm_encoder *encoder,
131	struct dip_infoframe *frame)	137	struct dip_infoframe *frame)
132	{	138	{
133	uint32_t data = (uint32_t )frame;	139	uint32_t data = (uint32_t )frame;
134	struct drm_device *dev = encoder->dev;	140	struct drm_device *dev = encoder->dev;
135	struct drm_i915_private *dev_priv = dev->dev_private;	141	struct drm_i915_private *dev_priv = dev->dev_private;
136	u32 val = I915_READ(VIDEO_DIP_CTL);	142	u32 val = I915_READ(VIDEO_DIP_CTL);
137	unsigned i, len = DIP_HEADER_SIZE + frame->len;	143	unsigned i, len = DIP_HEADER_SIZE + frame->len;
138		144
139	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	145	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
140		146
141	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	147	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
142	val \|= g4x_infoframe_index(frame);	148	val \|= g4x_infoframe_index(frame);
143		149
144	val &= ~g4x_infoframe_enable(frame);	150	val &= ~g4x_infoframe_enable(frame);
145		151
146	I915_WRITE(VIDEO_DIP_CTL, val);	152	I915_WRITE(VIDEO_DIP_CTL, val);
147		153
148	mmiowb();	154	mmiowb();
149	for (i = 0; i < len; i += 4) {	155	for (i = 0; i < len; i += 4) {
150	I915_WRITE(VIDEO_DIP_DATA, *data);	156	I915_WRITE(VIDEO_DIP_DATA, *data);
151	data++;	157	data++;
152	}	158	}
153	/* Write every possible data byte to force correct ECC calculation. */	159	/* Write every possible data byte to force correct ECC calculation. */
154	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	160	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
155	I915_WRITE(VIDEO_DIP_DATA, 0);	161	I915_WRITE(VIDEO_DIP_DATA, 0);
156	mmiowb();	162	mmiowb();
157		163
158	val \|= g4x_infoframe_enable(frame);	164	val \|= g4x_infoframe_enable(frame);
159	val &= ~VIDEO_DIP_FREQ_MASK;	165	val &= ~VIDEO_DIP_FREQ_MASK;
160	val \|= VIDEO_DIP_FREQ_VSYNC;	166	val \|= VIDEO_DIP_FREQ_VSYNC;
161		167
162	I915_WRITE(VIDEO_DIP_CTL, val);	168	I915_WRITE(VIDEO_DIP_CTL, val);
163	POSTING_READ(VIDEO_DIP_CTL);	169	POSTING_READ(VIDEO_DIP_CTL);
164	}	170	}
165		171
166	static void ibx_write_infoframe(struct drm_encoder *encoder,	172	static void ibx_write_infoframe(struct drm_encoder *encoder,
167	struct dip_infoframe *frame)	173	struct dip_infoframe *frame)
168	{	174	{
169	uint32_t data = (uint32_t )frame;	175	uint32_t data = (uint32_t )frame;
170	struct drm_device *dev = encoder->dev;	176	struct drm_device *dev = encoder->dev;
171	struct drm_i915_private *dev_priv = dev->dev_private;	177	struct drm_i915_private *dev_priv = dev->dev_private;
172	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	178	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
173	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	179	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
174	unsigned i, len = DIP_HEADER_SIZE + frame->len;	180	unsigned i, len = DIP_HEADER_SIZE + frame->len;
175	u32 val = I915_READ(reg);	181	u32 val = I915_READ(reg);
176		182
177	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	183	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
178		184
179	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	185	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
180	val \|= g4x_infoframe_index(frame);	186	val \|= g4x_infoframe_index(frame);
181		187
182	val &= ~g4x_infoframe_enable(frame);	188	val &= ~g4x_infoframe_enable(frame);
183		189
184	I915_WRITE(reg, val);	190	I915_WRITE(reg, val);
185		191
186	mmiowb();	192	mmiowb();
187	for (i = 0; i < len; i += 4) {	193	for (i = 0; i < len; i += 4) {
188	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);	194	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
189	data++;	195	data++;
190	}	196	}
191	/* Write every possible data byte to force correct ECC calculation. */	197	/* Write every possible data byte to force correct ECC calculation. */
192	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	198	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
193	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);	199	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
194	mmiowb();	200	mmiowb();
195		201
196	val \|= g4x_infoframe_enable(frame);	202	val \|= g4x_infoframe_enable(frame);
197	val &= ~VIDEO_DIP_FREQ_MASK;	203	val &= ~VIDEO_DIP_FREQ_MASK;
198	val \|= VIDEO_DIP_FREQ_VSYNC;	204	val \|= VIDEO_DIP_FREQ_VSYNC;
199		205
200	I915_WRITE(reg, val);	206	I915_WRITE(reg, val);
201	POSTING_READ(reg);	207	POSTING_READ(reg);
202	}	208	}
203		209
204	static void cpt_write_infoframe(struct drm_encoder *encoder,	210	static void cpt_write_infoframe(struct drm_encoder *encoder,
205	struct dip_infoframe *frame)	211	struct dip_infoframe *frame)
206	{	212	{
207	uint32_t data = (uint32_t )frame;	213	uint32_t data = (uint32_t )frame;
208	struct drm_device *dev = encoder->dev;	214	struct drm_device *dev = encoder->dev;
209	struct drm_i915_private *dev_priv = dev->dev_private;	215	struct drm_i915_private *dev_priv = dev->dev_private;
210	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	216	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
211	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	217	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
212	unsigned i, len = DIP_HEADER_SIZE + frame->len;	218	unsigned i, len = DIP_HEADER_SIZE + frame->len;
213	u32 val = I915_READ(reg);	219	u32 val = I915_READ(reg);
214		220
215	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	221	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
216		222
217	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	223	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
218	val \|= g4x_infoframe_index(frame);	224	val \|= g4x_infoframe_index(frame);
219		225
220	/* The DIP control register spec says that we need to update the AVI	226	/* The DIP control register spec says that we need to update the AVI
221	* infoframe without clearing its enable bit */	227	* infoframe without clearing its enable bit */
222	if (frame->type != DIP_TYPE_AVI)	228	if (frame->type != DIP_TYPE_AVI)
223	val &= ~g4x_infoframe_enable(frame);	229	val &= ~g4x_infoframe_enable(frame);
224		230
225	I915_WRITE(reg, val);	231	I915_WRITE(reg, val);
226		232
227	mmiowb();	233	mmiowb();
228	for (i = 0; i < len; i += 4) {	234	for (i = 0; i < len; i += 4) {
229	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);	235	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
230	data++;	236	data++;
231	}	237	}
232	/* Write every possible data byte to force correct ECC calculation. */	238	/* Write every possible data byte to force correct ECC calculation. */
233	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	239	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
234	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);	240	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
235	mmiowb();	241	mmiowb();
236		242
237	val \|= g4x_infoframe_enable(frame);	243	val \|= g4x_infoframe_enable(frame);
238	val &= ~VIDEO_DIP_FREQ_MASK;	244	val &= ~VIDEO_DIP_FREQ_MASK;
239	val \|= VIDEO_DIP_FREQ_VSYNC;	245	val \|= VIDEO_DIP_FREQ_VSYNC;
240		246
241	I915_WRITE(reg, val);	247	I915_WRITE(reg, val);
242	POSTING_READ(reg);	248	POSTING_READ(reg);
243	}	249	}
244		250
245	static void vlv_write_infoframe(struct drm_encoder *encoder,	251	static void vlv_write_infoframe(struct drm_encoder *encoder,
246	struct dip_infoframe *frame)	252	struct dip_infoframe *frame)
247	{	253	{
248	uint32_t data = (uint32_t )frame;	254	uint32_t data = (uint32_t )frame;
249	struct drm_device *dev = encoder->dev;	255	struct drm_device *dev = encoder->dev;
250	struct drm_i915_private *dev_priv = dev->dev_private;	256	struct drm_i915_private *dev_priv = dev->dev_private;
251	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	257	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
252	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);	258	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
253	unsigned i, len = DIP_HEADER_SIZE + frame->len;	259	unsigned i, len = DIP_HEADER_SIZE + frame->len;
254	u32 val = I915_READ(reg);	260	u32 val = I915_READ(reg);
255		261
256	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	262	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
257		263
258	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	264	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
259	val \|= g4x_infoframe_index(frame);	265	val \|= g4x_infoframe_index(frame);
260		266
261	val &= ~g4x_infoframe_enable(frame);	267	val &= ~g4x_infoframe_enable(frame);
262		268
263	I915_WRITE(reg, val);	269	I915_WRITE(reg, val);
264		270
265	mmiowb();	271	mmiowb();
266	for (i = 0; i < len; i += 4) {	272	for (i = 0; i < len; i += 4) {
267	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);	273	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
268	data++;	274	data++;
269	}	275	}
270	/* Write every possible data byte to force correct ECC calculation. */	276	/* Write every possible data byte to force correct ECC calculation. */
271	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	277	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
272	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);	278	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
273	mmiowb();	279	mmiowb();
274		280
275	val \|= g4x_infoframe_enable(frame);	281	val \|= g4x_infoframe_enable(frame);
276	val &= ~VIDEO_DIP_FREQ_MASK;	282	val &= ~VIDEO_DIP_FREQ_MASK;
277	val \|= VIDEO_DIP_FREQ_VSYNC;	283	val \|= VIDEO_DIP_FREQ_VSYNC;
278		284
279	I915_WRITE(reg, val);	285	I915_WRITE(reg, val);
280	POSTING_READ(reg);	286	POSTING_READ(reg);
281	}	287	}
282		288
283	static void hsw_write_infoframe(struct drm_encoder *encoder,	289	static void hsw_write_infoframe(struct drm_encoder *encoder,
284	struct dip_infoframe *frame)	290	struct dip_infoframe *frame)
285	{	291	{
286	uint32_t data = (uint32_t )frame;	292	uint32_t data = (uint32_t )frame;
287	struct drm_device *dev = encoder->dev;	293	struct drm_device *dev = encoder->dev;
288	struct drm_i915_private *dev_priv = dev->dev_private;	294	struct drm_i915_private *dev_priv = dev->dev_private;
289	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	295	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
290	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);	296	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
291	u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);	297	u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
292	unsigned int i, len = DIP_HEADER_SIZE + frame->len;	298	unsigned int i, len = DIP_HEADER_SIZE + frame->len;
293	u32 val = I915_READ(ctl_reg);	299	u32 val = I915_READ(ctl_reg);
294		300
295	if (data_reg == 0)	301	if (data_reg == 0)
296	return;	302	return;
297		303
298	val &= ~hsw_infoframe_enable(frame);	304	val &= ~hsw_infoframe_enable(frame);
299	I915_WRITE(ctl_reg, val);	305	I915_WRITE(ctl_reg, val);
300		306
301	mmiowb();	307	mmiowb();
302	for (i = 0; i < len; i += 4) {	308	for (i = 0; i < len; i += 4) {
303	I915_WRITE(data_reg + i, *data);	309	I915_WRITE(data_reg + i, *data);
304	data++;	310	data++;
305	}	311	}
306	/* Write every possible data byte to force correct ECC calculation. */	312	/* Write every possible data byte to force correct ECC calculation. */
307	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	313	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
308	I915_WRITE(data_reg + i, 0);	314	I915_WRITE(data_reg + i, 0);
309	mmiowb();	315	mmiowb();
310		316
311	val \|= hsw_infoframe_enable(frame);	317	val \|= hsw_infoframe_enable(frame);
312	I915_WRITE(ctl_reg, val);	318	I915_WRITE(ctl_reg, val);
313	POSTING_READ(ctl_reg);	319	POSTING_READ(ctl_reg);
314	}	320	}
315		321
316	static void intel_set_infoframe(struct drm_encoder *encoder,	322	static void intel_set_infoframe(struct drm_encoder *encoder,
317	struct dip_infoframe *frame)	323	struct dip_infoframe *frame)
318	{	324	{
319	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);	325	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
320		326
321	intel_dip_infoframe_csum(frame);	327	intel_dip_infoframe_csum(frame);
322	intel_hdmi->write_infoframe(encoder, frame);	328	intel_hdmi->write_infoframe(encoder, frame);
323	}	329	}
324		330
325	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,	331	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
326	struct drm_display_mode *adjusted_mode)	332	struct drm_display_mode *adjusted_mode)
327	{	333	{
328	struct dip_infoframe avi_if = {	334	struct dip_infoframe avi_if = {
329	.type = DIP_TYPE_AVI,	335	.type = DIP_TYPE_AVI,
330	.ver = DIP_VERSION_AVI,	336	.ver = DIP_VERSION_AVI,
331	.len = DIP_LEN_AVI,	337	.len = DIP_LEN_AVI,
332	};	338	};
333		339
334	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)	340	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
335	avi_if.body.avi.YQ_CN_PR \|= DIP_AVI_PR_2;	341	avi_if.body.avi.YQ_CN_PR \|= DIP_AVI_PR_2;
-		342
-		343	avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode);
336		344
337	intel_set_infoframe(encoder, &avi_if);	345	intel_set_infoframe(encoder, &avi_if);
338	}	346	}
339		347
340	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)	348	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
341	{	349	{
342	struct dip_infoframe spd_if;	350	struct dip_infoframe spd_if;
343		351
344	memset(&spd_if, 0, sizeof(spd_if));	352	memset(&spd_if, 0, sizeof(spd_if));
345	spd_if.type = DIP_TYPE_SPD;	353	spd_if.type = DIP_TYPE_SPD;
346	spd_if.ver = DIP_VERSION_SPD;	354	spd_if.ver = DIP_VERSION_SPD;
347	spd_if.len = DIP_LEN_SPD;	355	spd_if.len = DIP_LEN_SPD;
348	strcpy(spd_if.body.spd.vn, "Intel");	356	strcpy(spd_if.body.spd.vn, "Intel");
349	strcpy(spd_if.body.spd.pd, "Integrated gfx");	357	strcpy(spd_if.body.spd.pd, "Integrated gfx");
350	spd_if.body.spd.sdi = DIP_SPD_PC;	358	spd_if.body.spd.sdi = DIP_SPD_PC;
351		359
352	intel_set_infoframe(encoder, &spd_if);	360	intel_set_infoframe(encoder, &spd_if);
353	}	361	}
354		362
355	static void g4x_set_infoframes(struct drm_encoder *encoder,	363	static void g4x_set_infoframes(struct drm_encoder *encoder,
356	struct drm_display_mode *adjusted_mode)	364	struct drm_display_mode *adjusted_mode)
357	{	365	{
358	struct drm_i915_private *dev_priv = encoder->dev->dev_private;	366	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
359	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);	367	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
360	u32 reg = VIDEO_DIP_CTL;	368	u32 reg = VIDEO_DIP_CTL;
361	u32 val = I915_READ(reg);	369	u32 val = I915_READ(reg);
362	u32 port;	370	u32 port;
363		371
364	assert_hdmi_port_disabled(intel_hdmi);	372	assert_hdmi_port_disabled(intel_hdmi);
365		373
366	/* If the registers were not initialized yet, they might be zeroes,	374	/* If the registers were not initialized yet, they might be zeroes,
367	* which means we're selecting the AVI DIP and we're setting its	375	* which means we're selecting the AVI DIP and we're setting its
368	* frequency to once. This seems to really confuse the HW and make	376	* frequency to once. This seems to really confuse the HW and make
369	* things stop working (the register spec says the AVI always needs to	377	* things stop working (the register spec says the AVI always needs to
370	* be sent every VSync). So here we avoid writing to the register more	378	* be sent every VSync). So here we avoid writing to the register more
371	* than we need and also explicitly select the AVI DIP and explicitly	379	* than we need and also explicitly select the AVI DIP and explicitly
372	* set its frequency to every VSync. Avoiding to write it twice seems to	380	* set its frequency to every VSync. Avoiding to write it twice seems to
373	* be enough to solve the problem, but being defensive shouldn't hurt us	381	* be enough to solve the problem, but being defensive shouldn't hurt us
374	* either. */	382	* either. */
375	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;	383	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
376		384
377	if (!intel_hdmi->has_hdmi_sink) {	385	if (!intel_hdmi->has_hdmi_sink) {
378	if (!(val & VIDEO_DIP_ENABLE))	386	if (!(val & VIDEO_DIP_ENABLE))
379	return;	387	return;
380	val &= ~VIDEO_DIP_ENABLE;	388	val &= ~VIDEO_DIP_ENABLE;
381	I915_WRITE(reg, val);	389	I915_WRITE(reg, val);
382	POSTING_READ(reg);	390	POSTING_READ(reg);
383	return;	391	return;
384	}	392	}
385		393
386	switch (intel_hdmi->sdvox_reg) {	394	switch (intel_hdmi->sdvox_reg) {
387	case SDVOB:	395	case SDVOB:
388	port = VIDEO_DIP_PORT_B;	396	port = VIDEO_DIP_PORT_B;
389	break;	397	break;
390	case SDVOC:	398	case SDVOC:
391	port = VIDEO_DIP_PORT_C;	399	port = VIDEO_DIP_PORT_C;
392	break;	400	break;
393	default:	401	default:
394	BUG();	402	BUG();
395	return;	403	return;
396	}	404	}
397		405
398	if (port != (val & VIDEO_DIP_PORT_MASK)) {	406	if (port != (val & VIDEO_DIP_PORT_MASK)) {
399	if (val & VIDEO_DIP_ENABLE) {	407	if (val & VIDEO_DIP_ENABLE) {
400	val &= ~VIDEO_DIP_ENABLE;	408	val &= ~VIDEO_DIP_ENABLE;
401	I915_WRITE(reg, val);	409	I915_WRITE(reg, val);
402	POSTING_READ(reg);	410	POSTING_READ(reg);
403	}	411	}
404	val &= ~VIDEO_DIP_PORT_MASK;	412	val &= ~VIDEO_DIP_PORT_MASK;
405	val \|= port;	413	val \|= port;
406	}	414	}
407		415
408	val \|= VIDEO_DIP_ENABLE;	416	val \|= VIDEO_DIP_ENABLE;
409	val &= ~VIDEO_DIP_ENABLE_VENDOR;	417	val &= ~VIDEO_DIP_ENABLE_VENDOR;
410		418
411	I915_WRITE(reg, val);	419	I915_WRITE(reg, val);
412	POSTING_READ(reg);	420	POSTING_READ(reg);
413		421
414	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);	422	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
415	intel_hdmi_set_spd_infoframe(encoder);	423	intel_hdmi_set_spd_infoframe(encoder);
416	}	424	}
417		425
418	static void ibx_set_infoframes(struct drm_encoder *encoder,	426	static void ibx_set_infoframes(struct drm_encoder *encoder,
419	struct drm_display_mode *adjusted_mode)	427	struct drm_display_mode *adjusted_mode)
420	{	428	{
421	struct drm_i915_private *dev_priv = encoder->dev->dev_private;	429	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
422	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	430	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
423	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);	431	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
424	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	432	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
425	u32 val = I915_READ(reg);	433	u32 val = I915_READ(reg);
426	u32 port;	434	u32 port;
427		435
428	assert_hdmi_port_disabled(intel_hdmi);	436	assert_hdmi_port_disabled(intel_hdmi);
429		437
430	/* See the big comment in g4x_set_infoframes() */	438	/* See the big comment in g4x_set_infoframes() */
431	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;	439	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
432		440
433	if (!intel_hdmi->has_hdmi_sink) {	441	if (!intel_hdmi->has_hdmi_sink) {
434	if (!(val & VIDEO_DIP_ENABLE))	442	if (!(val & VIDEO_DIP_ENABLE))
435	return;	443	return;
436	val &= ~VIDEO_DIP_ENABLE;	444	val &= ~VIDEO_DIP_ENABLE;
437	I915_WRITE(reg, val);	445	I915_WRITE(reg, val);
438	POSTING_READ(reg);	446	POSTING_READ(reg);
439	return;	447	return;
440	}	448	}
441		449
442	switch (intel_hdmi->sdvox_reg) {	450	switch (intel_hdmi->sdvox_reg) {
443	case HDMIB:	451	case HDMIB:
444	port = VIDEO_DIP_PORT_B;	452	port = VIDEO_DIP_PORT_B;
445	break;	453	break;
446	case HDMIC:	454	case HDMIC:
447	port = VIDEO_DIP_PORT_C;	455	port = VIDEO_DIP_PORT_C;
448	break;	456	break;
449	case HDMID:	457	case HDMID:
450	port = VIDEO_DIP_PORT_D;	458	port = VIDEO_DIP_PORT_D;
451	break;	459	break;
452	default:	460	default:
453	BUG();	461	BUG();
454	return;	462	return;
455	}	463	}
456		464
457	if (port != (val & VIDEO_DIP_PORT_MASK)) {	465	if (port != (val & VIDEO_DIP_PORT_MASK)) {
458	if (val & VIDEO_DIP_ENABLE) {	466	if (val & VIDEO_DIP_ENABLE) {
459	val &= ~VIDEO_DIP_ENABLE;	467	val &= ~VIDEO_DIP_ENABLE;
460	I915_WRITE(reg, val);	468	I915_WRITE(reg, val);
461	POSTING_READ(reg);	469	POSTING_READ(reg);
462	}	470	}
463	val &= ~VIDEO_DIP_PORT_MASK;	471	val &= ~VIDEO_DIP_PORT_MASK;
464	val \|= port;	472	val \|= port;
465	}	473	}
466		474
467	val \|= VIDEO_DIP_ENABLE;	475	val \|= VIDEO_DIP_ENABLE;
468	val &= ~(VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|	476	val &= ~(VIDEO_DIP_ENABLE_VENDOR \| VIDEO_DIP_ENABLE_GAMUT \|
469	VIDEO_DIP_ENABLE_GCP);	477	VIDEO_DIP_ENABLE_GCP);
470		478
471	I915_WRITE(reg, val);	479	I915_WRITE(reg, val);
472	POSTING_READ(reg);	480	POSTING_READ(reg);
473		481
474	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);	482	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
475	intel_hdmi_set_spd_infoframe(encoder);	483	intel_hdmi_set_spd_infoframe(encoder);
476	}	484	}
477		485
478	static void cpt_set_infoframes(struct drm_encoder *encoder,	486	static void cpt_set_infoframes(struct drm_encoder *encoder,
479	struct drm_display_mode *adjusted_mode)	487	struct drm_display_mode *adjusted_mode)
480	{	488	{
481	struct drm_i915_private *dev_priv = encoder->dev->dev_private;	489	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
482	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	490	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
483	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);	491	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
484	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	492	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
485	u32 val = I915_READ(reg);	493	u32 val = I915_READ(reg);
486		494
487	assert_hdmi_port_disabled(intel_hdmi);	495	assert_hdmi_port_disabled(intel_hdmi);
488		496
489	/* See the big comment in g4x_set_infoframes() */	497	/* See the big comment in g4x_set_infoframes() */
490	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;	498	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
491		499

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_hdmi.c @ 3480 – Rev 3031 → 3243