WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_hdmi.c

  *	Jesse Barnes
  */
 #include
 #include
-//#include
+#include
-#include "drmP.h"
-#include "drm.h"
+#include
-#include "drm_crtc.h"
+#include
-#include "drm_edid.h"
+#include
 #include "intel_drv.h"
-#include "i915_drm.h"
+#include
 #include "i915_drv.h"
-struct intel_hdmi {
-	struct intel_encoder base;
+static void
-	u32 sdvox_reg;
+assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
-	int ddc_bus;
-	uint32_t color_range;
-	bool has_hdmi_sink;
-	bool has_audio;
+{
-	int force_audio;
+	struct drm_device *dev = intel_hdmi->base.base.dev;
-	void (*write_infoframe)(struct drm_encoder *encoder,
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t enabled_bits;
+	enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
+	WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
-				struct dip_infoframe *frame);
+	     "HDMI port enabled, expecting disabled\n");
 };
-static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
+struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
+{
 		sum += data[i];
 	frame->checksum = 0x100 - sum;
 }
-static u32 intel_infoframe_index(struct dip_infoframe *frame)
-{
-	u32 flags = 0;
+static u32 g4x_infoframe_index(struct dip_infoframe *frame)
+{
 	switch (frame->type) {
-	case DIP_TYPE_AVI:
-		flags |= VIDEO_DIP_SELECT_AVI;
+	case DIP_TYPE_AVI:
-		break;
+		return VIDEO_DIP_SELECT_AVI;
-	case DIP_TYPE_SPD:
-		flags |= VIDEO_DIP_SELECT_SPD;
+	case DIP_TYPE_SPD:
-		break;
+		return VIDEO_DIP_SELECT_SPD;
 	default:
 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
-		break;
-	}
 		return 0;
-	return flags;
+	}
+}
+static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
+{
+	switch (frame->type) {
+	case DIP_TYPE_AVI:
+		return VIDEO_DIP_ENABLE_AVI;
+	case DIP_TYPE_SPD:
+		return VIDEO_DIP_ENABLE_SPD;
+	default:
+		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
+		return 0;
+	}
 static u32 intel_infoframe_flags(struct dip_infoframe *frame)
-	u32 flags = 0;
+static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
 	switch (frame->type) {
-	case DIP_TYPE_AVI:
+	switch (frame->type) {
-		flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
-		break;
+	case DIP_TYPE_AVI:
-	case DIP_TYPE_SPD:
+		return VIDEO_DIP_ENABLE_AVI_HSW;
-		flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC;
+	case DIP_TYPE_SPD:
+		return VIDEO_DIP_ENABLE_SPD_HSW;
-		break;
+	default:
+		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
+		return 0;
+	}
+}
+static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
+{
+	switch (frame->type) {
+	case DIP_TYPE_AVI:
-	default:
+		return HSW_TVIDEO_DIP_AVI_DATA(pipe);
+	case DIP_TYPE_SPD:
-		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
+		return HSW_TVIDEO_DIP_SPD_DATA(pipe);
-		break;
+	default:
 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 		return 0;
 	return flags;
+}
-static void i9xx_write_infoframe(struct drm_encoder *encoder,
-				 struct dip_infoframe *frame)
+static void g4x_write_infoframe(struct drm_encoder *encoder,
 				 struct dip_infoframe *frame)
+{
 	uint32_t *data = (uint32_t *)frame;
-	struct drm_device *dev = encoder->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
-	unsigned i, len = DIP_HEADER_SIZE + frame->len;
-	/* XXX first guess at handling video port, is this corrent? */
+	struct drm_device *dev = encoder->dev;
-	if (intel_hdmi->sdvox_reg == SDVOB)
+	struct drm_i915_private *dev_priv = dev->dev_private;
-		port = VIDEO_DIP_PORT_B;
+	u32 val = I915_READ(VIDEO_DIP_CTL);
+	unsigned i, len = DIP_HEADER_SIZE + frame->len;
 	else if (intel_hdmi->sdvox_reg == SDVOC)
-		port = VIDEO_DIP_PORT_C;
+	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 	else
-		return;
+	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+	val |= g4x_infoframe_index(frame);
+	val &= ~g4x_infoframe_enable(frame);
+	I915_WRITE(VIDEO_DIP_CTL, val);
+	mmiowb();
-	flags = intel_infoframe_index(frame);
+	for (i = 0; i < len; i += 4) {
+		I915_WRITE(VIDEO_DIP_DATA, *data);
 		data++;
-	val &= ~VIDEO_DIP_SELECT_MASK;
+	}
 	/* Write every possible data byte to force correct ECC calculation. */
-	I915_WRITE(VIDEO_DIP_CTL, val | port | flags);
+	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 		I915_WRITE(VIDEO_DIP_DATA, 0);
-	for (i = 0; i < len; i += 4) {
+	mmiowb();
 		I915_WRITE(VIDEO_DIP_DATA, *data);
-		data++;
-	}
+	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
-	flags |= intel_infoframe_flags(frame);
+	val |= VIDEO_DIP_FREQ_VSYNC;
+	I915_WRITE(VIDEO_DIP_CTL, val);
+	POSTING_READ(VIDEO_DIP_CTL);
+}
+static void ibx_write_infoframe(struct drm_encoder *encoder,
+				     struct dip_infoframe *frame)
+{
+	uint32_t *data = (uint32_t *)frame;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	unsigned i, len = DIP_HEADER_SIZE + frame->len;
+	u32 val = I915_READ(reg);
+	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
+	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+	val |= g4x_infoframe_index(frame);
+	val &= ~g4x_infoframe_enable(frame);
+	I915_WRITE(reg, val);
+	mmiowb();
+	for (i = 0; i < len; i += 4) {
+		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+		data++;
+	}
+	/* Write every possible data byte to force correct ECC calculation. */
+	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
+		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
+	mmiowb();
-	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
+	val |= g4x_infoframe_enable(frame);
+	val &= ~VIDEO_DIP_FREQ_MASK;
+	val |= VIDEO_DIP_FREQ_VSYNC;
-}
 	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+}
-static void ironlake_write_infoframe(struct drm_encoder *encoder,
+static void cpt_write_infoframe(struct drm_encoder *encoder,
+				struct dip_infoframe *frame)
+{
+	uint32_t *data = (uint32_t *)frame;
+	struct drm_device *dev = encoder->dev;
-				     struct dip_infoframe *frame)
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-	uint32_t *data = (uint32_t *)frame;
+	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
-	struct drm_device *dev = encoder->dev;
+	unsigned i, len = DIP_HEADER_SIZE + frame->len;
+	u32 val = I915_READ(reg);
+	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+	val |= g4x_infoframe_index(frame);
-	struct drm_crtc *crtc = encoder->crtc;
+	/* The DIP control register spec says that we need to update the AVI
+	 * infoframe without clearing its enable bit */
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	if (frame->type != DIP_TYPE_AVI)
+		val &= ~g4x_infoframe_enable(frame);
-	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
-	unsigned i, len = DIP_HEADER_SIZE + frame->len;
+	I915_WRITE(reg, val);
 	u32 flags, val = I915_READ(reg);
+	mmiowb();
+	for (i = 0; i < len; i += 4) {
+		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+		data++;
+	}
+	/* Write every possible data byte to force correct ECC calculation. */
+	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
+		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
+	mmiowb();
+	val |= g4x_infoframe_enable(frame);
+	val &= ~VIDEO_DIP_FREQ_MASK;
+	val |= VIDEO_DIP_FREQ_VSYNC;
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+}
-	intel_wait_for_vblank(dev, intel_crtc->pipe);
+static void vlv_write_infoframe(struct drm_encoder *encoder,
+				     struct dip_infoframe *frame)
+{
+	uint32_t *data = (uint32_t *)frame;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	unsigned i, len = DIP_HEADER_SIZE + frame->len;
+	u32 val = I915_READ(reg);
+	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
+	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+	val |= g4x_infoframe_index(frame);
+	val &= ~g4x_infoframe_enable(frame);
+	I915_WRITE(reg, val);
+	mmiowb();
+	for (i = 0; i < len; i += 4) {
+		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+		data++;
+	}
+	/* Write every possible data byte to force correct ECC calculation. */
+	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
+		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
+	mmiowb();
+	val |= g4x_infoframe_enable(frame);
+	val &= ~VIDEO_DIP_FREQ_MASK;
+	val |= VIDEO_DIP_FREQ_VSYNC;
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+}
+static void hsw_write_infoframe(struct drm_encoder *encoder,
+				struct dip_infoframe *frame)
+{
+	uint32_t *data = (uint32_t *)frame;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
+	unsigned int i, len = DIP_HEADER_SIZE + frame->len;
+	u32 val = I915_READ(ctl_reg);
+	if (data_reg == 0)
+		return;
-	flags = intel_infoframe_index(frame);
+	val &= ~hsw_infoframe_enable(frame);
 	I915_WRITE(ctl_reg, val);
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+	mmiowb();
+	for (i = 0; i < len; i += 4) {
-	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+		I915_WRITE(data_reg + i, *data);
 		data++;
 	for (i = 0; i < len; i += 4) {
-		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+	/* Write every possible data byte to force correct ECC calculation. */
-		data++;
+	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 		I915_WRITE(data_reg + i, 0);
+	mmiowb();
+	val |= hsw_infoframe_enable(frame);
 	I915_WRITE(ctl_reg, val);
-	flags |= intel_infoframe_flags(frame);
+	POSTING_READ(ctl_reg);
+}
 	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
 	spd_if.body.spd.sdi = DIP_SPD_PC;
 	intel_set_infoframe(encoder, &spd_if);
+}
+static void g4x_set_infoframes(struct drm_encoder *encoder,
+			       struct drm_display_mode *adjusted_mode)
+{
+	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	u32 reg = VIDEO_DIP_CTL;
+	u32 val = I915_READ(reg);
+	u32 port;
+	assert_hdmi_port_disabled(intel_hdmi);
+	/* If the registers were not initialized yet, they might be zeroes,
+	 * which means we're selecting the AVI DIP and we're setting its
+	 * frequency to once. This seems to really confuse the HW and make
+	 * things stop working (the register spec says the AVI always needs to
+	 * be sent every VSync). So here we avoid writing to the register more
+	 * than we need and also explicitly select the AVI DIP and explicitly
+	 * set its frequency to every VSync. Avoiding to write it twice seems to
+	 * be enough to solve the problem, but being defensive shouldn't hurt us
+	 * either. */
+	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
+	if (!intel_hdmi->has_hdmi_sink) {
+		if (!(val & VIDEO_DIP_ENABLE))
+			return;
+		val &= ~VIDEO_DIP_ENABLE;
+		I915_WRITE(reg, val);
+		POSTING_READ(reg);
+		return;
+	}
+	switch (intel_hdmi->sdvox_reg) {
+	case SDVOB:
+		port = VIDEO_DIP_PORT_B;
+		break;
+	case SDVOC:
+		port = VIDEO_DIP_PORT_C;
+		break;
+	default:
+		BUG();
+		return;
+	}
+	if (port != (val & VIDEO_DIP_PORT_MASK)) {
+		if (val & VIDEO_DIP_ENABLE) {
+			val &= ~VIDEO_DIP_ENABLE;
+			I915_WRITE(reg, val);
+			POSTING_READ(reg);
+		}
+		val &= ~VIDEO_DIP_PORT_MASK;
+		val |= port;
+	}
+	val |= VIDEO_DIP_ENABLE;
+	val &= ~VIDEO_DIP_ENABLE_VENDOR;
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
+	intel_hdmi_set_spd_infoframe(encoder);
+}
+static void ibx_set_infoframes(struct drm_encoder *encoder,
+			       struct drm_display_mode *adjusted_mode)
+{
+	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	u32 val = I915_READ(reg);
+	u32 port;
+	assert_hdmi_port_disabled(intel_hdmi);
+	/* See the big comment in g4x_set_infoframes() */
+	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
+	if (!intel_hdmi->has_hdmi_sink) {
+		if (!(val & VIDEO_DIP_ENABLE))
+			return;
+		val &= ~VIDEO_DIP_ENABLE;
+		I915_WRITE(reg, val);
+		POSTING_READ(reg);
+		return;
+	}
+	switch (intel_hdmi->sdvox_reg) {
+	case HDMIB:
+		port = VIDEO_DIP_PORT_B;
+		break;
+	case HDMIC:
+		port = VIDEO_DIP_PORT_C;
+		break;
+	case HDMID:
+		port = VIDEO_DIP_PORT_D;
+		break;
+	default:
+		BUG();
+		return;
+	}
+	if (port != (val & VIDEO_DIP_PORT_MASK)) {
+		if (val & VIDEO_DIP_ENABLE) {
+			val &= ~VIDEO_DIP_ENABLE;
+			I915_WRITE(reg, val);
+			POSTING_READ(reg);
+		}
+		val &= ~VIDEO_DIP_PORT_MASK;
+		val |= port;
+	}
+	val |= VIDEO_DIP_ENABLE;
+	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
+		 VIDEO_DIP_ENABLE_GCP);
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
+	intel_hdmi_set_spd_infoframe(encoder);
+}
+static void cpt_set_infoframes(struct drm_encoder *encoder,
+			       struct drm_display_mode *adjusted_mode)
+{
+	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+	u32 val = I915_READ(reg);
+	assert_hdmi_port_disabled(intel_hdmi);
+	/* See the big comment in g4x_set_infoframes() */
+	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
+	if (!intel_hdmi->has_hdmi_sink) {
+		if (!(val & VIDEO_DIP_ENABLE))
+			return;
+		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
+		I915_WRITE(reg, val);
+		POSTING_READ(reg);
+		return;
+	}
+	/* Set both together, unset both together: see the spec. */
+	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
+	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
+		 VIDEO_DIP_ENABLE_GCP);
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
+	intel_hdmi_set_spd_infoframe(encoder);
+}
+static void vlv_set_infoframes(struct drm_encoder *encoder,
+			       struct drm_display_mode *adjusted_mode)
+{
+	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	u32 val = I915_READ(reg);
+	assert_hdmi_port_disabled(intel_hdmi);
+	/* See the big comment in g4x_set_infoframes() */
+	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
+	if (!intel_hdmi->has_hdmi_sink) {
+		if (!(val & VIDEO_DIP_ENABLE))
+			return;
+		val &= ~VIDEO_DIP_ENABLE;
+		I915_WRITE(reg, val);
+		POSTING_READ(reg);
+		return;
+	}
+	val |= VIDEO_DIP_ENABLE;
+	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
+		 VIDEO_DIP_ENABLE_GCP);
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
+	intel_hdmi_set_spd_infoframe(encoder);
+}
+static void hsw_set_infoframes(struct drm_encoder *encoder,
+			       struct drm_display_mode *adjusted_mode)
+{
+	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	u32 val = I915_READ(reg);
+	assert_hdmi_port_disabled(intel_hdmi);
+	if (!intel_hdmi->has_hdmi_sink) {
+		I915_WRITE(reg, 0);
+		POSTING_READ(reg);
+		return;
+	}
+	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
+		 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
+	intel_hdmi_set_spd_infoframe(encoder);
+}
 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 				struct drm_display_mode *mode,
 				struct drm_display_mode *adjusted_mode)
+{
-	struct drm_device *dev = encoder->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_device *dev = encoder->dev;
-	struct drm_crtc *crtc = encoder->crtc;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	u32 sdvox;
-	sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
+	sdvox = SDVO_ENCODING_HDMI;
 	if (!HAS_PCH_SPLIT(dev))
 		sdvox |= intel_hdmi->color_range;
 		intel_write_eld(encoder, adjusted_mode);
+	}
 		if (HAS_PCH_CPT(dev))
 		sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
-	else if (intel_crtc->pipe == 1)
+	else if (intel_crtc->pipe == PIPE_B)
 			sdvox |= SDVO_PIPE_B_SELECT;
-	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
-	POSTING_READ(intel_hdmi->sdvox_reg);
+	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 	POSTING_READ(intel_hdmi->sdvox_reg);
-	intel_hdmi_set_avi_infoframe(encoder);
+	intel_hdmi->set_infoframes(encoder, adjusted_mode);
 	intel_hdmi_set_spd_infoframe(encoder);
-}
 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
-static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
+				    enum pipe *pipe)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+	u32 tmp;
+	tmp = I915_READ(intel_hdmi->sdvox_reg);
+	if (!(tmp & SDVO_ENABLE))
+		return false;
+	if (HAS_PCH_CPT(dev))
+		*pipe = PORT_TO_PIPE_CPT(tmp);
+	else
+		*pipe = PORT_TO_PIPE(tmp);
+	return true;
+}
+static void intel_enable_hdmi(struct intel_encoder *encoder)
+{
-	struct drm_device *dev = encoder->dev;
+	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	u32 temp;
+	u32 enable_bits = SDVO_ENABLE;
+	if (intel_hdmi->has_audio)
+		enable_bits |= SDVO_AUDIO_ENABLE;
+	temp = I915_READ(intel_hdmi->sdvox_reg);
+	/* HW workaround for IBX, we need to move the port to transcoder A
+	 * before disabling it. */
+	if (HAS_PCH_IBX(dev)) {
+		struct drm_crtc *crtc = encoder->base.crtc;
-	u32 enable_bits = SDVO_ENABLE;
+		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
-	if (intel_hdmi->has_audio)
+		/* Restore the transcoder select bit. */
-		enable_bits |= SDVO_AUDIO_ENABLE;
+		if (pipe == PIPE_B)
 			enable_bits |= SDVO_PIPE_B_SELECT;
 	temp = I915_READ(intel_hdmi->sdvox_reg);
-	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
-	 * we do this anyway which shows more stable in testing.
-	 */
-	if (HAS_PCH_SPLIT(dev)) {
+	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
+	 * we do this anyway which shows more stable in testing.
+	 */
+	if (HAS_PCH_SPLIT(dev)) {
+		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
+		POSTING_READ(intel_hdmi->sdvox_reg);
+	}
+	temp |= enable_bits;
+	I915_WRITE(intel_hdmi->sdvox_reg, temp);
-		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
+	POSTING_READ(intel_hdmi->sdvox_reg);
+	/* HW workaround, need to write this twice for issue that may result
+	 * in first write getting masked.
+	 */
+	if (HAS_PCH_SPLIT(dev)) {
+		I915_WRITE(intel_hdmi->sdvox_reg, temp);
+		POSTING_READ(intel_hdmi->sdvox_reg);
+	}
+}
+static void intel_disable_hdmi(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+	u32 temp;
+	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
+	temp = I915_READ(intel_hdmi->sdvox_reg);
+	/* HW workaround for IBX, we need to move the port to transcoder A
+	 * before disabling it. */
+	if (HAS_PCH_IBX(dev)) {
+		struct drm_crtc *crtc = encoder->base.crtc;
+		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
+			if (temp & SDVO_PIPE_B_SELECT) {
+				temp &= ~SDVO_PIPE_B_SELECT;
+				I915_WRITE(intel_hdmi->sdvox_reg, temp);
+				POSTING_READ(intel_hdmi->sdvox_reg);
+				/* Again we need to write this twice. */
+				I915_WRITE(intel_hdmi->sdvox_reg, temp);
+				POSTING_READ(intel_hdmi->sdvox_reg);
+				/* Transcoder selection bits only update
+				 * effectively on vblank. */
+				if (crtc)
+					intel_wait_for_vblank(dev, pipe);
+				else
+					msleep(50);
+			}
+	}
+	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
-		POSTING_READ(intel_hdmi->sdvox_reg);
+	 * we do this anyway which shows more stable in testing.
 	 */
 	if (HAS_PCH_SPLIT(dev)) {
 	return MODE_OK;
+}
 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
-				  struct drm_display_mode *mode,
+				  const struct drm_display_mode *mode,
 				  struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
+{
+	struct drm_device *dev = intel_hdmi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t bit;
+	switch (intel_hdmi->sdvox_reg) {
+	case SDVOB:
+		bit = HDMIB_HOTPLUG_LIVE_STATUS;
+		break;
+	case SDVOC:
+		bit = HDMIC_HOTPLUG_LIVE_STATUS;
+		break;
+	default:
+		bit = 0;
+		break;
+	}
-	return true;
+	return I915_READ(PORT_HOTPLUG_STAT) & bit;
+}
 static enum drm_connector_status
 intel_hdmi_detect(struct drm_connector *connector, bool force)
+{
 	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
+	struct drm_i915_private *dev_priv = connector->dev->dev_private;
+	struct edid *edid;
+	enum drm_connector_status status = connector_status_disconnected;
 	struct drm_i915_private *dev_priv = connector->dev->dev_private;
-	struct edid *edid;
+	if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
-	enum drm_connector_status status = connector_status_disconnected;
+		return status;
+	intel_hdmi->has_hdmi_sink = false;
-	intel_hdmi->has_hdmi_sink = false;
+	intel_hdmi->has_audio = false;
-	intel_hdmi->has_audio = false;
+	edid = drm_get_edid(connector,
-	edid = drm_get_edid(connector,
+			    intel_gmbus_get_adapter(dev_priv,
+						    intel_hdmi->ddc_bus));
-			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
+	if (edid) {
 		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
-	if (edid) {
+			status = connector_status_connected;
-		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
-			status = connector_status_connected;
+			if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
-			intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
+				intel_hdmi->has_hdmi_sink =
-			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
+						drm_detect_hdmi_monitor(edid);
+			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 		}
-		connector->display_info.raw_edid = NULL;
+		kfree(edid);
 		kfree(edid);
 	if (status == connector_status_connected) {
 	/* We should parse the EDID data and find out if it's an HDMI sink so
 	 * we can send audio to it.
 	 */
+	return intel_ddc_get_modes(connector,
-	return intel_ddc_get_modes(connector,
+				   intel_gmbus_get_adapter(dev_priv,
-				   &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
+							   intel_hdmi->ddc_bus));
+}
 static bool
 	struct drm_i915_private *dev_priv = connector->dev->dev_private;
 	struct edid *edid;
 	bool has_audio = false;
+	edid = drm_get_edid(connector,
-	edid = drm_get_edid(connector,
+			    intel_gmbus_get_adapter(dev_priv,
-			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
+						    intel_hdmi->ddc_bus));
 	if (edid) {
 		if (edid->input & DRM_EDID_INPUT_DIGITAL)
-			has_audio = drm_detect_monitor_audio(edid);
-		connector->display_info.raw_edid = NULL;
+			has_audio = drm_detect_monitor_audio(edid);
 		kfree(edid);
+	}
 	ret = drm_connector_property_set_value(connector, property, val);
 	if (ret)
 		return ret;
 #if 0
 	if (property == dev_priv->force_audio_property) {
-		int i = val;
+		enum hdmi_force_audio i = val;
 		bool has_audio;
 		if (i == intel_hdmi->force_audio)
 			return 0;
 		intel_hdmi->force_audio = i;
-		if (i == 0)
+		if (i == HDMI_AUDIO_AUTO)
 			has_audio = intel_hdmi_detect_audio(connector);
 		else
-			has_audio = i > 0;
+			has_audio = (i == HDMI_AUDIO_ON);
-		if (has_audio == intel_hdmi->has_audio)
+		if (i == HDMI_AUDIO_OFF_DVI)
+			intel_hdmi->has_hdmi_sink = 0;
 			return 0;
 		intel_hdmi->has_audio = has_audio;
-		intel_hdmi->has_audio = has_audio;
+		goto done;
 		goto done;
 #endif
 	if (property == dev_priv->broadcast_rgb_property) {
 		if (val == !!intel_hdmi->color_range)
 			return 0;
 		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 		goto done;
 	}
-#endif
 	return -EINVAL;
 	return -EINVAL;
 done:
 	drm_sysfs_connector_remove(connector);
 	drm_connector_cleanup(connector);
 	kfree(connector);
+}
+static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
+	.mode_fixup = intel_hdmi_mode_fixup,
+	.mode_set = intel_ddi_mode_set,
+	.disable = intel_encoder_noop,
+};
-static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
-	.dpms = intel_hdmi_dpms,
+static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
-	.mode_fixup = intel_hdmi_mode_fixup,
-	.prepare = intel_encoder_prepare,
+	.mode_fixup = intel_hdmi_mode_fixup,
 	.mode_set = intel_hdmi_mode_set,
-	.commit = intel_encoder_commit,
+	.disable = intel_encoder_noop,
 };
 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
-	.dpms = drm_helper_connector_dpms,
+	.dpms = intel_connector_dpms,
 	.detect = intel_hdmi_detect,
 	.fill_modes = drm_helper_probe_single_connector_modes,
 	.set_property = intel_hdmi_set_property,
+{
 	intel_attach_force_audio_property(connector);
 	intel_attach_broadcast_rgb_property(connector);
+}
-void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
+void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_connector *connector;
 	struct intel_encoder *intel_encoder;
 	struct intel_connector *intel_connector;
-	struct intel_hdmi *intel_hdmi;
-	int i;
+	struct intel_hdmi *intel_hdmi;
 	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 	intel_encoder->type = INTEL_OUTPUT_HDMI;
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
-	connector->interlace_allowed = 0;
+	connector->interlace_allowed = 1;
-	connector->doublescan_allowed = 0;
-	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	connector->doublescan_allowed = 0;
+	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
-	/* Set up the DDC bus. */
-	if (sdvox_reg == SDVOB) {
-		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
+	intel_encoder->cloneable = false;
-		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
-		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
-	} else if (sdvox_reg == SDVOC) {
-		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
-		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
-		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
+	intel_hdmi->ddi_port = port;
-	} else if (sdvox_reg == HDMIB) {
+	switch (port) {
-		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
+	case PORT_B:
 		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
-	} else if (sdvox_reg == HDMIC) {
+		break;
-		intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
+	case PORT_C:
 		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
-	} else if (sdvox_reg == HDMID) {
+		break;
+	case PORT_D:
+		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
+		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+		break;
+	case PORT_A:
-		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
+		/* Internal port only for eDP. */
-		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
+	default:
-		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+		BUG();
 	}
+	intel_hdmi->sdvox_reg = sdvox_reg;
+	if (!HAS_PCH_SPLIT(dev)) {
+		intel_hdmi->write_infoframe = g4x_write_infoframe;
+		intel_hdmi->set_infoframes = g4x_set_infoframes;
+	} else if (IS_VALLEYVIEW(dev)) {
+		intel_hdmi->write_infoframe = vlv_write_infoframe;
+		intel_hdmi->set_infoframes = vlv_set_infoframes;
+	} else if (IS_HASWELL(dev)) {
+		intel_hdmi->write_infoframe = hsw_write_infoframe;
+		intel_hdmi->set_infoframes = hsw_set_infoframes;
+	} else if (HAS_PCH_IBX(dev)) {
+		intel_hdmi->write_infoframe = ibx_write_infoframe;
+		intel_hdmi->set_infoframes = ibx_set_infoframes;
+	} else {
+		intel_hdmi->write_infoframe = cpt_write_infoframe;
+		intel_hdmi->set_infoframes = cpt_set_infoframes;
+	}
+	if (IS_HASWELL(dev)) {
-	intel_hdmi->sdvox_reg = sdvox_reg;
+		intel_encoder->enable = intel_enable_ddi;
+		intel_encoder->disable = intel_disable_ddi;
+		intel_encoder->get_hw_state = intel_ddi_get_hw_state;
+		drm_encoder_helper_add(&intel_encoder->base,
-	if (!HAS_PCH_SPLIT(dev)) {
+				       &intel_hdmi_helper_funcs_hsw);
-		intel_hdmi->write_infoframe = i9xx_write_infoframe;
+	} else {
-		I915_WRITE(VIDEO_DIP_CTL, 0);
+		intel_encoder->enable = intel_enable_hdmi;
+		intel_encoder->disable = intel_disable_hdmi;
-	} else {
-		intel_hdmi->write_infoframe = ironlake_write_infoframe;
+		intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
-		for_each_pipe(i)
+		drm_encoder_helper_add(&intel_encoder->base,
-			I915_WRITE(TVIDEO_DIP_CTL(i), 0);
+				       &intel_hdmi_helper_funcs);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_hdmi.c – Rev 2342 → 3031