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Rev 6084 | Rev 6937 | ||
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Line 41... | Line 41... | ||
41 | #include "intel_drv.h" |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" |
42 | #include "i915_drv.h" |
Line 43... | Line 43... | ||
43 | 43 | ||
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { |
45 | { |
- | 46 | return dev_priv->fbc.activate != NULL; |
|
- | 47 | } |
|
- | 48 | ||
- | 49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
|
- | 50 | { |
|
- | 51 | return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; |
|
- | 52 | } |
|
- | 53 | ||
- | 54 | static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) |
|
- | 55 | { |
|
46 | return dev_priv->fbc.enable_fbc != NULL; |
56 | return INTEL_INFO(dev_priv)->gen < 4; |
Line 47... | Line 57... | ||
47 | } |
57 | } |
48 | 58 | ||
49 | /* |
59 | /* |
Line 57... | Line 67... | ||
57 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) |
67 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) |
58 | { |
68 | { |
59 | return crtc->base.y - crtc->adjusted_y; |
69 | return crtc->base.y - crtc->adjusted_y; |
60 | } |
70 | } |
Line -... | Line 71... | ||
- | 71 | ||
- | 72 | /* |
|
- | 73 | * For SKL+, the plane source size used by the hardware is based on the value we |
|
- | 74 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value |
|
- | 75 | * we wrote to PIPESRC. |
|
- | 76 | */ |
|
- | 77 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, |
|
- | 78 | int *width, int *height) |
|
- | 79 | { |
|
- | 80 | struct intel_plane_state *plane_state = |
|
- | 81 | to_intel_plane_state(crtc->base.primary->state); |
|
- | 82 | int w, h; |
|
- | 83 | ||
- | 84 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { |
|
- | 85 | w = drm_rect_height(&plane_state->src) >> 16; |
|
- | 86 | h = drm_rect_width(&plane_state->src) >> 16; |
|
- | 87 | } else { |
|
- | 88 | w = drm_rect_width(&plane_state->src) >> 16; |
|
- | 89 | h = drm_rect_height(&plane_state->src) >> 16; |
|
- | 90 | } |
|
- | 91 | ||
- | 92 | if (width) |
|
- | 93 | *width = w; |
|
- | 94 | if (height) |
|
- | 95 | *height = h; |
|
- | 96 | } |
|
- | 97 | ||
- | 98 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc, |
|
- | 99 | struct drm_framebuffer *fb) |
|
- | 100 | { |
|
- | 101 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
- | 102 | int lines; |
|
- | 103 | ||
- | 104 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); |
|
- | 105 | if (INTEL_INFO(dev_priv)->gen >= 7) |
|
- | 106 | lines = min(lines, 2048); |
|
- | 107 | ||
- | 108 | /* Hardware needs the full buffer stride, not just the active area. */ |
|
- | 109 | return lines * fb->pitches[0]; |
|
- | 110 | } |
|
61 | 111 | ||
62 | static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) |
112 | static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
63 | { |
113 | { |
Line 64... | Line 114... | ||
64 | u32 fbc_ctl; |
114 | u32 fbc_ctl; |
Line 65... | Line 115... | ||
65 | 115 | ||
66 | dev_priv->fbc.enabled = false; |
116 | dev_priv->fbc.active = false; |
67 | 117 | ||
68 | /* Disable compression */ |
118 | /* Disable compression */ |
Line 76... | Line 126... | ||
76 | /* Wait for compressing bit to clear */ |
126 | /* Wait for compressing bit to clear */ |
77 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
127 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
78 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
128 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
79 | return; |
129 | return; |
80 | } |
130 | } |
81 | - | ||
82 | DRM_DEBUG_KMS("disabled FBC\n"); |
- | |
83 | } |
131 | } |
Line 84... | Line 132... | ||
84 | 132 | ||
85 | static void i8xx_fbc_enable(struct intel_crtc *crtc) |
133 | static void i8xx_fbc_activate(struct intel_crtc *crtc) |
86 | { |
134 | { |
87 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
135 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
88 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
136 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
89 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
137 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
90 | int cfb_pitch; |
138 | int cfb_pitch; |
91 | int i; |
139 | int i; |
Line 92... | Line 140... | ||
92 | u32 fbc_ctl; |
140 | u32 fbc_ctl; |
Line 93... | Line 141... | ||
93 | 141 | ||
94 | dev_priv->fbc.enabled = true; |
142 | dev_priv->fbc.active = true; |
95 | 143 | ||
96 | /* Note: fbc.threshold == 1 for i8xx */ |
144 | /* Note: fbc.threshold == 1 for i8xx */ |
Line 97... | Line 145... | ||
97 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; |
145 | cfb_pitch = intel_fbc_calculate_cfb_size(crtc, fb) / FBC_LL_SIZE; |
98 | if (fb->pitches[0] < cfb_pitch) |
146 | if (fb->pitches[0] < cfb_pitch) |
Line 125... | Line 173... | ||
125 | if (IS_I945GM(dev_priv)) |
173 | if (IS_I945GM(dev_priv)) |
126 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
174 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
127 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
175 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
128 | fbc_ctl |= obj->fence_reg; |
176 | fbc_ctl |= obj->fence_reg; |
129 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
177 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
130 | - | ||
131 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
- | |
132 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
- | |
133 | } |
178 | } |
Line 134... | Line 179... | ||
134 | 179 | ||
135 | static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) |
180 | static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
136 | { |
181 | { |
137 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
182 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
Line 138... | Line 183... | ||
138 | } |
183 | } |
139 | 184 | ||
140 | static void g4x_fbc_enable(struct intel_crtc *crtc) |
185 | static void g4x_fbc_activate(struct intel_crtc *crtc) |
141 | { |
186 | { |
142 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
187 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
143 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
188 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
Line 144... | Line 189... | ||
144 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
189 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Line 145... | Line 190... | ||
145 | u32 dpfc_ctl; |
190 | u32 dpfc_ctl; |
146 | 191 | ||
147 | dev_priv->fbc.enabled = true; |
192 | dev_priv->fbc.active = true; |
148 | 193 | ||
Line 155... | Line 200... | ||
155 | 200 | ||
Line 156... | Line 201... | ||
156 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
201 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
157 | 202 | ||
158 | /* enable it... */ |
- | |
159 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
- | |
160 | 203 | /* enable it... */ |
|
Line 161... | Line 204... | ||
161 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
204 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
162 | } |
205 | } |
163 | 206 | ||
Line 164... | Line 207... | ||
164 | static void g4x_fbc_disable(struct drm_i915_private *dev_priv) |
207 | static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
Line 165... | Line 208... | ||
165 | { |
208 | { |
166 | u32 dpfc_ctl; |
209 | u32 dpfc_ctl; |
167 | 210 | ||
168 | dev_priv->fbc.enabled = false; |
211 | dev_priv->fbc.active = false; |
169 | 212 | ||
170 | /* Disable compression */ |
- | |
171 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
- | |
172 | if (dpfc_ctl & DPFC_CTL_EN) { |
213 | /* Disable compression */ |
173 | dpfc_ctl &= ~DPFC_CTL_EN; |
214 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
Line 174... | Line 215... | ||
174 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
215 | if (dpfc_ctl & DPFC_CTL_EN) { |
175 | 216 | dpfc_ctl &= ~DPFC_CTL_EN; |
|
176 | DRM_DEBUG_KMS("disabled FBC\n"); |
217 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
177 | } |
218 | } |
Line -... | Line 219... | ||
- | 219 | } |
|
178 | } |
220 | |
179 | 221 | static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
|
180 | static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) |
222 | { |
181 | { |
223 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
182 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
224 | } |
Line 183... | Line 225... | ||
183 | } |
225 | |
184 | 226 | /* This function forces a CFB recompression through the nuke operation. */ |
|
185 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
227 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) |
186 | { |
228 | { |
187 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
229 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
188 | POSTING_READ(MSG_FBC_REND_STATE); |
230 | POSTING_READ(MSG_FBC_REND_STATE); |
189 | } |
231 | } |
190 | 232 | ||
Line 191... | Line 233... | ||
191 | static void ilk_fbc_enable(struct intel_crtc *crtc) |
233 | static void ilk_fbc_activate(struct intel_crtc *crtc) |
Line 192... | Line 234... | ||
192 | { |
234 | { |
193 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
235 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
194 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
236 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
Line 229... | Line 271... | ||
229 | I915_WRITE(SNB_DPFC_CTL_SA, |
271 | I915_WRITE(SNB_DPFC_CTL_SA, |
230 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
272 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
231 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
273 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
232 | } |
274 | } |
Line 233... | Line 275... | ||
233 | 275 | ||
234 | intel_fbc_nuke(dev_priv); |
- | |
235 | - | ||
236 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
276 | intel_fbc_recompress(dev_priv); |
Line 237... | Line 277... | ||
237 | } |
277 | } |
238 | 278 | ||
239 | static void ilk_fbc_disable(struct drm_i915_private *dev_priv) |
279 | static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
Line 240... | Line 280... | ||
240 | { |
280 | { |
Line 241... | Line 281... | ||
241 | u32 dpfc_ctl; |
281 | u32 dpfc_ctl; |
242 | 282 | ||
243 | dev_priv->fbc.enabled = false; |
283 | dev_priv->fbc.active = false; |
244 | 284 | ||
245 | /* Disable compression */ |
285 | /* Disable compression */ |
246 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
- | |
247 | if (dpfc_ctl & DPFC_CTL_EN) { |
- | |
248 | dpfc_ctl &= ~DPFC_CTL_EN; |
286 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
249 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
287 | if (dpfc_ctl & DPFC_CTL_EN) { |
Line 250... | Line 288... | ||
250 | 288 | dpfc_ctl &= ~DPFC_CTL_EN; |
|
251 | DRM_DEBUG_KMS("disabled FBC\n"); |
289 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
252 | } |
290 | } |
253 | } |
291 | } |
Line 254... | Line 292... | ||
254 | 292 | ||
255 | static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) |
293 | static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
256 | { |
294 | { |
257 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
295 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
258 | } |
296 | } |
259 | 297 | ||
260 | static void gen7_fbc_enable(struct intel_crtc *crtc) |
298 | static void gen7_fbc_activate(struct intel_crtc *crtc) |
Line 261... | Line 299... | ||
261 | { |
299 | { |
Line 262... | Line 300... | ||
262 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
300 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
263 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
301 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
264 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
302 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Line 308... | Line 346... | ||
308 | 346 | ||
309 | I915_WRITE(SNB_DPFC_CTL_SA, |
347 | I915_WRITE(SNB_DPFC_CTL_SA, |
310 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
348 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
Line 311... | Line 349... | ||
311 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
349 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
312 | - | ||
313 | intel_fbc_nuke(dev_priv); |
- | |
314 | 350 | ||
Line 315... | Line 351... | ||
315 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
351 | intel_fbc_recompress(dev_priv); |
316 | } |
352 | } |
317 | 353 | ||
318 | /** |
354 | /** |
319 | * intel_fbc_enabled - Is FBC enabled? |
355 | * intel_fbc_is_active - Is FBC active? |
320 | * @dev_priv: i915 device instance |
356 | * @dev_priv: i915 device instance |
321 | * |
357 | * |
322 | * This function is used to verify the current state of FBC. |
358 | * This function is used to verify the current state of FBC. |
323 | * FIXME: This should be tracked in the plane config eventually |
359 | * FIXME: This should be tracked in the plane config eventually |
324 | * instead of queried at runtime for most callers. |
360 | * instead of queried at runtime for most callers. |
325 | */ |
361 | */ |
326 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv) |
362 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
Line 327... | Line 363... | ||
327 | { |
363 | { |
328 | return dev_priv->fbc.enabled; |
- | |
329 | } |
364 | return dev_priv->fbc.active; |
330 | 365 | } |
|
- | 366 | ||
Line 331... | Line 367... | ||
331 | static void intel_fbc_enable(struct intel_crtc *crtc, |
367 | static void intel_fbc_activate(const struct drm_framebuffer *fb) |
Line 332... | Line -... | ||
332 | const struct drm_framebuffer *fb) |
- | |
333 | { |
368 | { |
334 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
369 | struct drm_i915_private *dev_priv = fb->dev->dev_private; |
335 | 370 | struct intel_crtc *crtc = dev_priv->fbc.crtc; |
|
Line 336... | Line 371... | ||
336 | dev_priv->fbc.enable_fbc(crtc); |
371 | |
337 | 372 | dev_priv->fbc.activate(crtc); |
|
338 | dev_priv->fbc.crtc = crtc; |
373 | |
339 | dev_priv->fbc.fb_id = fb->base.id; |
374 | dev_priv->fbc.fb_id = fb->base.id; |
340 | dev_priv->fbc.y = crtc->base.y; |
375 | dev_priv->fbc.y = crtc->base.y; |
341 | } |
376 | } |
342 | 377 | ||
Line -... | Line 378... | ||
- | 378 | static void intel_fbc_work_fn(struct work_struct *__work) |
|
- | 379 | { |
|
- | 380 | struct drm_i915_private *dev_priv = |
|
- | 381 | container_of(__work, struct drm_i915_private, fbc.work.work); |
|
- | 382 | struct intel_fbc_work *work = &dev_priv->fbc.work; |
|
343 | static void intel_fbc_work_fn(struct work_struct *__work) |
383 | struct intel_crtc *crtc = dev_priv->fbc.crtc; |
- | 384 | int delay_ms = 50; |
|
344 | { |
385 | |
345 | struct intel_fbc_work *work = |
386 | retry: |
- | 387 | /* Delay the actual enabling to let pageflipping cease and the |
|
346 | container_of(to_delayed_work(__work), |
388 | * display to settle before starting the compression. Note that |
- | 389 | * this delay also serves a second purpose: it allows for a |
|
- | 390 | * vblank to pass after disabling the FBC before we attempt |
|
347 | struct intel_fbc_work, work); |
391 | * to modify the control registers. |
348 | struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; |
- | |
349 | struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; |
392 | * |
Line 350... | Line 393... | ||
350 | 393 | * A more complicated solution would involve tracking vblanks |
|
351 | mutex_lock(&dev_priv->fbc.lock); |
394 | * following the termination of the page-flipping sequence |
- | 395 | * and indeed performing the enable as a co-routine and not |
|
- | 396 | * waiting synchronously upon the vblank. |
|
- | 397 | * |
|
- | 398 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
|
- | 399 | */ |
|
- | 400 | wait_remaining_ms_from_jiffies(work->enable_jiffies, delay_ms); |
|
- | 401 | ||
352 | if (work == dev_priv->fbc.fbc_work) { |
402 | mutex_lock(&dev_priv->fbc.lock); |
- | 403 | ||
- | 404 | /* Were we cancelled? */ |
|
- | 405 | if (!work->scheduled) |
|
- | 406 | goto out; |
|
- | 407 | ||
- | 408 | /* Were we delayed again while this function was sleeping? */ |
|
- | 409 | if (time_after(work->enable_jiffies + msecs_to_jiffies(delay_ms), |
|
Line -... | Line 410... | ||
- | 410 | jiffies)) { |
|
353 | /* Double check that we haven't switched fb without cancelling |
411 | mutex_unlock(&dev_priv->fbc.lock); |
354 | * the prior work. |
412 | goto retry; |
Line 355... | Line 413... | ||
355 | */ |
413 | } |
356 | if (crtc_fb == work->fb) |
414 | |
357 | intel_fbc_enable(work->crtc, work->fb); |
415 | if (crtc->base.primary->fb == work->fb) |
358 | - | ||
359 | dev_priv->fbc.fbc_work = NULL; |
- | |
360 | } |
- | |
361 | mutex_unlock(&dev_priv->fbc.lock); |
- | |
362 | - | ||
363 | kfree(work); |
- | |
364 | } |
- | |
365 | - | ||
366 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) |
- | |
367 | { |
- | |
368 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
- | |
369 | - | ||
370 | if (dev_priv->fbc.fbc_work == NULL) |
- | |
371 | return; |
- | |
372 | - | ||
373 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
- | |
374 | - | ||
375 | /* Synchronisation is provided by struct_mutex and checking of |
- | |
376 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
- | |
377 | * entirely asynchronously. |
416 | intel_fbc_activate(work->fb); |
378 | */ |
417 | |
Line 379... | Line 418... | ||
379 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
418 | work->scheduled = false; |
380 | /* tasklet was killed before being run, clean up */ |
419 | |
381 | kfree(dev_priv->fbc.fbc_work); |
- | |
382 | 420 | out: |
|
- | 421 | mutex_unlock(&dev_priv->fbc.lock); |
|
Line 383... | Line 422... | ||
383 | /* Mark the work as no longer wanted so that if it does |
422 | } |
Line 384... | Line 423... | ||
384 | * wake-up (because the work was already running and waiting |
423 | |
385 | * for our mutex), it will discover that is no longer |
- | |
386 | * necessary to run. |
- | |
387 | */ |
- | |
388 | dev_priv->fbc.fbc_work = NULL; |
424 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) |
389 | } |
425 | { |
390 | - | ||
391 | static void intel_fbc_schedule_enable(struct intel_crtc *crtc) |
- | |
392 | { |
- | |
393 | struct intel_fbc_work *work; |
426 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
394 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
427 | dev_priv->fbc.work.scheduled = false; |
- | 428 | } |
|
395 | 429 | ||
Line 396... | Line -... | ||
396 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
- | |
397 | - | ||
398 | intel_fbc_cancel_work(dev_priv); |
- | |
399 | - | ||
400 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
- | |
401 | if (work == NULL) { |
- | |
402 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
- | |
403 | intel_fbc_enable(crtc, crtc->base.primary->fb); |
- | |
404 | return; |
- | |
405 | } |
- | |
406 | - | ||
407 | work->crtc = crtc; |
- | |
408 | work->fb = crtc->base.primary->fb; |
- | |
409 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
- | |
410 | - | ||
411 | dev_priv->fbc.fbc_work = work; |
430 | static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
412 | 431 | { |
|
Line 413... | Line 432... | ||
413 | /* Delay the actual enabling to let pageflipping cease and the |
432 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
414 | * display to settle before starting the compression. Note that |
433 | struct intel_fbc_work *work = &dev_priv->fbc.work; |
415 | * this delay also serves a second purpose: it allows for a |
434 | |
Line 416... | Line 435... | ||
416 | * vblank to pass after disabling the FBC before we attempt |
435 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
Line 417... | Line -... | ||
417 | * to modify the control registers. |
- | |
418 | * |
436 | |
419 | * A more complicated solution would involve tracking vblanks |
- | |
420 | * following the termination of the page-flipping sequence |
- | |
421 | * and indeed performing the enable as a co-routine and not |
- | |
422 | * waiting synchronously upon the vblank. |
- | |
423 | * |
- | |
424 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
- | |
425 | */ |
- | |
426 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
- | |
427 | } |
- | |
428 | - | ||
429 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
- | |
430 | { |
- | |
431 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
- | |
432 | - | ||
433 | intel_fbc_cancel_work(dev_priv); |
437 | /* It is useless to call intel_fbc_cancel_work() in this function since |
434 | - | ||
435 | dev_priv->fbc.disable_fbc(dev_priv); |
438 | * we're not releasing fbc.lock, so it won't have an opportunity to grab |
Line 436... | Line 439... | ||
436 | dev_priv->fbc.crtc = NULL; |
439 | * it to discover that it was cancelled. So we just update the expected |
437 | } |
440 | * jiffy count. */ |
438 | 441 | work->fb = crtc->base.primary->fb; |
|
439 | /** |
442 | work->scheduled = true; |
440 | * intel_fbc_disable - disable FBC |
443 | work->enable_jiffies = jiffies; |
441 | * @dev_priv: i915 device instance |
444 | |
442 | * |
445 | schedule_work(&work->work); |
443 | * This function disables FBC. |
446 | } |
444 | */ |
447 | |
Line 445... | Line 448... | ||
445 | void intel_fbc_disable(struct drm_i915_private *dev_priv) |
448 | static void __intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
446 | { |
449 | { |
Line 447... | Line 450... | ||
447 | if (!fbc_supported(dev_priv)) |
450 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
448 | return; |
451 | |
449 | 452 | intel_fbc_cancel_work(dev_priv); |
|
450 | mutex_lock(&dev_priv->fbc.lock); |
453 | |
451 | __intel_fbc_disable(dev_priv); |
454 | if (dev_priv->fbc.active) |
Line 452... | Line -... | ||
452 | mutex_unlock(&dev_priv->fbc.lock); |
- | |
453 | } |
- | |
454 | - | ||
455 | /* |
- | |
456 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc |
- | |
457 | * @crtc: the CRTC |
- | |
458 | * |
- | |
459 | * This function disables FBC if it's associated with the provided CRTC. |
- | |
460 | */ |
- | |
461 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) |
- | |
462 | { |
- | |
463 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
- | |
464 | - | ||
465 | if (!fbc_supported(dev_priv)) |
- | |
466 | return; |
- | |
467 | - | ||
468 | mutex_lock(&dev_priv->fbc.lock); |
- | |
469 | if (dev_priv->fbc.crtc == crtc) |
- | |
470 | __intel_fbc_disable(dev_priv); |
- | |
471 | mutex_unlock(&dev_priv->fbc.lock); |
- | |
472 | } |
- | |
473 | - | ||
474 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) |
- | |
475 | { |
- | |
476 | switch (reason) { |
- | |
477 | case FBC_OK: |
- | |
478 | return "FBC enabled but currently disabled in hardware"; |
- | |
479 | case FBC_UNSUPPORTED: |
- | |
480 | return "unsupported by this chipset"; |
- | |
481 | case FBC_NO_OUTPUT: |
- | |
482 | return "no output"; |
- | |
483 | case FBC_STOLEN_TOO_SMALL: |
- | |
484 | return "not enough stolen memory"; |
- | |
485 | case FBC_UNSUPPORTED_MODE: |
- | |
486 | return "mode incompatible with compression"; |
- | |
487 | case FBC_MODE_TOO_LARGE: |
- | |
488 | return "mode too large for compression"; |
- | |
489 | case FBC_BAD_PLANE: |
- | |
490 | return "FBC unsupported on plane"; |
- | |
491 | case FBC_NOT_TILED: |
- | |
492 | return "framebuffer not tiled or fenced"; |
- | |
493 | case FBC_MULTIPLE_PIPES: |
455 | dev_priv->fbc.deactivate(dev_priv); |
494 | return "more than one pipe active"; |
456 | } |
495 | case FBC_MODULE_PARAM: |
457 | |
496 | return "disabled per module param"; |
458 | /* |
497 | case FBC_CHIP_DEFAULT: |
459 | * intel_fbc_deactivate - deactivate FBC if it's associated with crtc |
Line 498... | Line 460... | ||
498 | return "disabled per chip default"; |
460 | * @crtc: the CRTC |
499 | case FBC_ROTATION: |
461 | * |
500 | return "rotation unsupported"; |
462 | * This function deactivates FBC if it's associated with the provided CRTC. |
Line 501... | Line 463... | ||
501 | case FBC_IN_DBG_MASTER: |
463 | */ |
502 | return "Kernel debugger is active"; |
464 | void intel_fbc_deactivate(struct intel_crtc *crtc) |
503 | case FBC_BAD_STRIDE: |
465 | { |
504 | return "framebuffer stride not supported"; |
- | |
505 | case FBC_PIXEL_RATE: |
- | |
506 | return "pixel rate is too big"; |
- | |
507 | case FBC_PIXEL_FORMAT: |
- | |
508 | return "pixel format is invalid"; |
- | |
Line 509... | Line 466... | ||
509 | default: |
466 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
510 | MISSING_CASE(reason); |
467 | |
Line 511... | Line -... | ||
511 | return "unknown reason"; |
- | |
512 | } |
468 | if (!fbc_supported(dev_priv)) |
513 | } |
469 | return; |
Line 514... | Line -... | ||
514 | - | ||
515 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
470 | |
516 | enum no_fbc_reason reason) |
471 | mutex_lock(&dev_priv->fbc.lock); |
Line -... | Line 472... | ||
- | 472 | if (dev_priv->fbc.crtc == crtc) |
|
- | 473 | __intel_fbc_deactivate(dev_priv); |
|
517 | { |
474 | mutex_unlock(&dev_priv->fbc.lock); |
518 | if (dev_priv->fbc.no_fbc_reason == reason) |
475 | } |
Line -... | Line 476... | ||
- | 476 | ||
- | 477 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
|
- | 478 | const char *reason) |
|
519 | return; |
479 | { |
520 | 480 | if (dev_priv->fbc.no_fbc_reason == reason) |
|
Line 521... | Line 481... | ||
521 | dev_priv->fbc.no_fbc_reason = reason; |
481 | return; |
522 | DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); |
482 | |
523 | } |
483 | dev_priv->fbc.no_fbc_reason = reason; |
Line 579... | Line 539... | ||
579 | 539 | ||
580 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen |
540 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen |
581 | * reserved range size, so it always assumes the maximum (8mb) is used. |
541 | * reserved range size, so it always assumes the maximum (8mb) is used. |
582 | * If we enable FBC using a CFB on that memory range we'll get FIFO |
542 | * If we enable FBC using a CFB on that memory range we'll get FIFO |
- | 543 | * underruns, even if that range is not reserved by the BIOS. */ |
|
583 | * underruns, even if that range is not reserved by the BIOS. */ |
544 | if (IS_BROADWELL(dev_priv) || |
584 | if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) |
545 | IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
585 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
546 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
586 | else |
547 | else |
Line 587... | Line 548... | ||
587 | end = dev_priv->gtt.stolen_usable_size; |
548 | end = dev_priv->gtt.stolen_usable_size; |
Line 615... | Line 576... | ||
615 | } else { |
576 | } else { |
616 | return compression_threshold; |
577 | return compression_threshold; |
617 | } |
578 | } |
618 | } |
579 | } |
Line 619... | Line 580... | ||
619 | 580 | ||
620 | static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
- | |
621 | int fb_cpp) |
581 | static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) |
- | 582 | { |
|
- | 583 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
622 | { |
584 | struct drm_framebuffer *fb = crtc->base.primary->state->fb; |
623 | struct drm_mm_node *uninitialized_var(compressed_llb); |
585 | struct drm_mm_node *uninitialized_var(compressed_llb); |
- | 586 | int size, fb_cpp, ret; |
|
- | 587 | ||
- | 588 | WARN_ON(drm_mm_node_allocated(&dev_priv->fbc.compressed_fb)); |
|
- | 589 | ||
- | 590 | size = intel_fbc_calculate_cfb_size(crtc, fb); |
|
Line 624... | Line 591... | ||
624 | int ret; |
591 | fb_cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
625 | 592 | ||
626 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
593 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
627 | size, fb_cpp); |
594 | size, fb_cpp); |
Line 654... | Line 621... | ||
654 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); |
621 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); |
655 | I915_WRITE(FBC_LL_BASE, |
622 | I915_WRITE(FBC_LL_BASE, |
656 | dev_priv->mm.stolen_base + compressed_llb->start); |
623 | dev_priv->mm.stolen_base + compressed_llb->start); |
657 | } |
624 | } |
Line 658... | Line -... | ||
658 | - | ||
659 | dev_priv->fbc.uncompressed_size = size; |
- | |
660 | 625 | ||
661 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
626 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
662 | dev_priv->fbc.compressed_fb.size, |
627 | dev_priv->fbc.compressed_fb.size, |
Line 663... | Line 628... | ||
663 | dev_priv->fbc.threshold); |
628 | dev_priv->fbc.threshold); |
Line 672... | Line 637... | ||
672 | return -ENOSPC; |
637 | return -ENOSPC; |
673 | } |
638 | } |
Line 674... | Line 639... | ||
674 | 639 | ||
675 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
640 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
676 | { |
641 | { |
677 | if (dev_priv->fbc.uncompressed_size == 0) |
642 | if (drm_mm_node_allocated(&dev_priv->fbc.compressed_fb)) |
678 | return; |
- | |
679 | 643 | i915_gem_stolen_remove_node(dev_priv, |
|
Line 680... | Line 644... | ||
680 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); |
644 | &dev_priv->fbc.compressed_fb); |
681 | 645 | ||
682 | if (dev_priv->fbc.compressed_llb) { |
646 | if (dev_priv->fbc.compressed_llb) { |
683 | i915_gem_stolen_remove_node(dev_priv, |
647 | i915_gem_stolen_remove_node(dev_priv, |
684 | dev_priv->fbc.compressed_llb); |
648 | dev_priv->fbc.compressed_llb); |
685 | kfree(dev_priv->fbc.compressed_llb); |
- | |
686 | } |
- | |
687 | 649 | kfree(dev_priv->fbc.compressed_llb); |
|
Line 688... | Line 650... | ||
688 | dev_priv->fbc.uncompressed_size = 0; |
650 | } |
689 | } |
651 | } |
690 | 652 | ||
Line 696... | Line 658... | ||
696 | mutex_lock(&dev_priv->fbc.lock); |
658 | mutex_lock(&dev_priv->fbc.lock); |
697 | __intel_fbc_cleanup_cfb(dev_priv); |
659 | __intel_fbc_cleanup_cfb(dev_priv); |
698 | mutex_unlock(&dev_priv->fbc.lock); |
660 | mutex_unlock(&dev_priv->fbc.lock); |
699 | } |
661 | } |
Line 700... | Line -... | ||
700 | - | ||
701 | /* |
- | |
702 | * For SKL+, the plane source size used by the hardware is based on the value we |
- | |
703 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value |
- | |
704 | * we wrote to PIPESRC. |
- | |
705 | */ |
- | |
706 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, |
- | |
707 | int *width, int *height) |
- | |
708 | { |
- | |
709 | struct intel_plane_state *plane_state = |
- | |
710 | to_intel_plane_state(crtc->base.primary->state); |
- | |
711 | int w, h; |
- | |
712 | - | ||
713 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { |
- | |
714 | w = drm_rect_height(&plane_state->src) >> 16; |
- | |
715 | h = drm_rect_width(&plane_state->src) >> 16; |
- | |
716 | } else { |
- | |
717 | w = drm_rect_width(&plane_state->src) >> 16; |
- | |
718 | h = drm_rect_height(&plane_state->src) >> 16; |
- | |
719 | } |
- | |
720 | - | ||
721 | if (width) |
- | |
722 | *width = w; |
- | |
723 | if (height) |
- | |
724 | *height = h; |
- | |
725 | } |
- | |
726 | - | ||
727 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) |
- | |
728 | { |
- | |
729 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
- | |
730 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
- | |
731 | int lines; |
- | |
732 | - | ||
733 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); |
- | |
734 | if (INTEL_INFO(dev_priv)->gen >= 7) |
- | |
735 | lines = min(lines, 2048); |
- | |
736 | - | ||
737 | return lines * fb->pitches[0]; |
- | |
738 | } |
- | |
739 | - | ||
740 | static int intel_fbc_setup_cfb(struct intel_crtc *crtc) |
- | |
741 | { |
- | |
742 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
- | |
743 | struct drm_framebuffer *fb = crtc->base.primary->fb; |
- | |
744 | int size, cpp; |
- | |
745 | - | ||
746 | size = intel_fbc_calculate_cfb_size(crtc); |
- | |
747 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
- | |
748 | - | ||
749 | if (size <= dev_priv->fbc.uncompressed_size) |
- | |
750 | return 0; |
- | |
751 | - | ||
752 | /* Release any current block */ |
- | |
753 | __intel_fbc_cleanup_cfb(dev_priv); |
- | |
754 | - | ||
755 | return intel_fbc_alloc_cfb(dev_priv, size, cpp); |
- | |
756 | } |
- | |
757 | 662 | ||
758 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
663 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
759 | unsigned int stride) |
664 | unsigned int stride) |
760 | { |
665 | { |
761 | /* These should have been caught earlier. */ |
666 | /* These should have been caught earlier. */ |
Line 827... | Line 732... | ||
827 | 732 | ||
828 | return effective_w <= max_w && effective_h <= max_h; |
733 | return effective_w <= max_w && effective_h <= max_h; |
Line 829... | Line 734... | ||
829 | } |
734 | } |
830 | 735 | ||
831 | /** |
- | |
832 | * __intel_fbc_update - enable/disable FBC as needed, unlocked |
- | |
833 | * @dev_priv: i915 device instance |
- | |
834 | * |
- | |
835 | * Set up the framebuffer compression hardware at mode set time. We |
- | |
836 | * enable it if possible: |
736 | /** |
837 | * - plane A only (on pre-965) |
- | |
838 | * - no pixel mulitply/line duplication |
- | |
839 | * - no alpha buffer discard |
- | |
840 | * - no dual wide |
737 | * __intel_fbc_update - activate/deactivate FBC as needed, unlocked |
841 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
- | |
842 | * |
738 | * @crtc: the CRTC that triggered the update |
843 | * We can't assume that any compression will take place (worst case), |
- | |
844 | * so the compressed buffer has to be the same size as the uncompressed |
- | |
845 | * one. It also must reside (along with the line length buffer) in |
- | |
846 | * stolen memory. |
739 | * |
847 | * |
740 | * This function completely reevaluates the status of FBC, then activates, |
848 | * We need to enable/disable FBC on a global basis. |
741 | * deactivates or maintains it on the same state. |
849 | */ |
742 | */ |
850 | static void __intel_fbc_update(struct drm_i915_private *dev_priv) |
- | |
851 | { |
743 | static void __intel_fbc_update(struct intel_crtc *crtc) |
852 | struct drm_crtc *crtc = NULL; |
744 | { |
853 | struct intel_crtc *intel_crtc; |
745 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
854 | struct drm_framebuffer *fb; |
746 | struct drm_framebuffer *fb; |
Line 855... | Line 747... | ||
855 | struct drm_i915_gem_object *obj; |
747 | struct drm_i915_gem_object *obj; |
Line 856... | Line -... | ||
856 | const struct drm_display_mode *adjusted_mode; |
- | |
857 | 748 | const struct drm_display_mode *adjusted_mode; |
|
858 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
- | |
859 | - | ||
860 | /* disable framebuffer compression in vGPU */ |
- | |
861 | if (intel_vgpu_active(dev_priv->dev)) |
- | |
862 | i915.enable_fbc = 0; |
- | |
863 | - | ||
864 | if (i915.enable_fbc < 0) { |
- | |
865 | set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); |
- | |
866 | goto out_disable; |
749 | |
867 | } |
750 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
868 | 751 | ||
Line 869... | Line -... | ||
869 | if (!i915.enable_fbc) { |
- | |
870 | set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); |
- | |
871 | goto out_disable; |
- | |
872 | } |
- | |
873 | - | ||
874 | /* |
- | |
875 | * If FBC is already on, we just have to verify that we can |
- | |
876 | * keep it that way... |
- | |
877 | * Need to disable if: |
- | |
878 | * - more than one pipe is active |
- | |
879 | * - changing FBC params (stride, fence, mode) |
- | |
880 | * - new fb is too large to fit in compressed buffer |
752 | if (!multiple_pipes_ok(dev_priv)) { |
881 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
753 | set_no_fbc_reason(dev_priv, "more than one pipe active"); |
882 | */ |
- | |
Line 883... | Line 754... | ||
883 | crtc = intel_fbc_find_crtc(dev_priv); |
754 | goto out_disable; |
884 | if (!crtc) { |
755 | } |
885 | set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); |
756 | |
886 | goto out_disable; |
757 | if (!dev_priv->fbc.enabled || dev_priv->fbc.crtc != crtc) |
Line 887... | Line -... | ||
887 | } |
- | |
888 | 758 | return; |
|
889 | if (!multiple_pipes_ok(dev_priv)) { |
759 | |
890 | set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); |
760 | if (!crtc_is_valid(crtc)) { |
Line 891... | Line 761... | ||
891 | goto out_disable; |
761 | set_no_fbc_reason(dev_priv, "no output"); |
892 | } |
762 | goto out_disable; |
893 | 763 | } |
|
894 | intel_crtc = to_intel_crtc(crtc); |
764 | |
895 | fb = crtc->primary->fb; |
765 | fb = crtc->base.primary->fb; |
Line 896... | Line 766... | ||
896 | obj = intel_fb_obj(fb); |
766 | obj = intel_fb_obj(fb); |
897 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
767 | adjusted_mode = &crtc->config->base.adjusted_mode; |
898 | - | ||
899 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
- | |
900 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
- | |
901 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); |
- | |
902 | goto out_disable; |
- | |
903 | } |
- | |
904 | 768 | ||
905 | if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) { |
769 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
Line 906... | Line 770... | ||
906 | set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); |
770 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
907 | goto out_disable; |
771 | set_no_fbc_reason(dev_priv, "incompatible mode"); |
908 | } |
772 | goto out_disable; |
909 | 773 | } |
|
910 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
774 | |
911 | intel_crtc->plane != PLANE_A) { |
775 | if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
912 | set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); |
776 | set_no_fbc_reason(dev_priv, "mode too large for compression"); |
913 | goto out_disable; |
777 | goto out_disable; |
914 | } |
778 | } |
915 | 779 | ||
916 | /* The use of a CPU fence is mandatory in order to detect writes |
780 | /* The use of a CPU fence is mandatory in order to detect writes |
917 | * by the CPU to the scanout and trigger updates to the FBC. |
781 | * by the CPU to the scanout and trigger updates to the FBC. |
918 | */ |
782 | */ |
Line 919... | Line 783... | ||
919 | if (obj->tiling_mode != I915_TILING_X || |
783 | if (obj->tiling_mode != I915_TILING_X || |
920 | obj->fence_reg == I915_FENCE_REG_NONE) { |
784 | obj->fence_reg == I915_FENCE_REG_NONE) { |
921 | set_no_fbc_reason(dev_priv, FBC_NOT_TILED); |
785 | set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
922 | goto out_disable; |
786 | goto out_disable; |
Line 923... | Line 787... | ||
923 | } |
787 | } |
924 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
- | |
925 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
- | |
926 | set_no_fbc_reason(dev_priv, FBC_ROTATION); |
- | |
927 | goto out_disable; |
- | |
928 | } |
- | |
929 | - | ||
930 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
788 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
931 | set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); |
789 | crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) { |
932 | goto out_disable; |
790 | set_no_fbc_reason(dev_priv, "rotation unsupported"); |
Line 933... | Line 791... | ||
933 | } |
791 | goto out_disable; |
934 | 792 | } |
|
935 | if (!pixel_format_is_valid(fb)) { |
793 | |
936 | set_no_fbc_reason(dev_priv, FBC_PIXEL_FORMAT); |
794 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
937 | goto out_disable; |
795 | set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
938 | } |
796 | goto out_disable; |
939 | 797 | } |
|
Line -... | Line 798... | ||
- | 798 | ||
- | 799 | if (!pixel_format_is_valid(fb)) { |
|
- | 800 | set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
|
- | 801 | goto out_disable; |
|
- | 802 | } |
|
- | 803 | ||
- | 804 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
|
- | 805 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && |
|
- | 806 | ilk_pipe_pixel_rate(crtc->config) >= |
|
- | 807 | dev_priv->cdclk_freq * 95 / 100) { |
|
940 | /* If the kernel debugger is active, always disable compression */ |
808 | set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
- | 809 | goto out_disable; |
|
941 | if (in_dbg_master()) { |
810 | } |
942 | set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER); |
811 | |
943 | goto out_disable; |
812 | /* It is possible for the required CFB size change without a |
Line 944... | Line 813... | ||
944 | } |
813 | * crtc->disable + crtc->enable since it is possible to change the |
945 | 814 | * stride without triggering a full modeset. Since we try to |
|
946 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
815 | * over-allocate the CFB, there's a chance we may keep FBC enabled even |
947 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && |
816 | * if this happens, but if we exceed the current CFB size we'll have to |
948 | ilk_pipe_pixel_rate(intel_crtc->config) >= |
817 | * disable FBC. Notice that it would be possible to disable FBC, wait |
949 | dev_priv->cdclk_freq * 95 / 100) { |
818 | * for a frame, free the stolen node, then try to reenable FBC in case |
950 | set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); |
819 | * we didn't get any invalidate/deactivate calls, but this would require |
951 | goto out_disable; |
820 | * a lot of tracking just for a specific case. If we conclude it's an |
- | 821 | * important case, we can implement it later. */ |
|
952 | } |
822 | if (intel_fbc_calculate_cfb_size(crtc, fb) > |
Line 953... | Line 823... | ||
953 | 823 | dev_priv->fbc.compressed_fb.size * dev_priv->fbc.threshold) { |
|
954 | if (intel_fbc_setup_cfb(intel_crtc)) { |
824 | set_no_fbc_reason(dev_priv, "CFB requirements changed"); |
955 | set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); |
825 | goto out_disable; |
956 | goto out_disable; |
826 | } |
957 | } |
827 | |
958 | 828 | /* If the scanout has not changed, don't modify the FBC settings. |
|
Line 988... | Line 858... | ||
988 | * no strict enforcement that a vblank occurred since |
858 | * no strict enforcement that a vblank occurred since |
989 | * disabling the FBC. However, along all current pipe |
859 | * disabling the FBC. However, along all current pipe |
990 | * disabling paths we do need to wait for a vblank at |
860 | * disabling paths we do need to wait for a vblank at |
991 | * some point. And we wait before enabling FBC anyway. |
861 | * some point. And we wait before enabling FBC anyway. |
992 | */ |
862 | */ |
993 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
863 | DRM_DEBUG_KMS("deactivating FBC for update\n"); |
994 | __intel_fbc_disable(dev_priv); |
864 | __intel_fbc_deactivate(dev_priv); |
995 | } |
865 | } |
Line 996... | Line 866... | ||
996 | 866 | ||
997 | intel_fbc_schedule_enable(intel_crtc); |
867 | intel_fbc_schedule_activation(crtc); |
998 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
868 | dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)"; |
Line 999... | Line 869... | ||
999 | return; |
869 | return; |
1000 | 870 | ||
1001 | out_disable: |
871 | out_disable: |
1002 | /* Multiple disables should be harmless */ |
872 | /* Multiple disables should be harmless */ |
1003 | if (intel_fbc_enabled(dev_priv)) { |
873 | if (intel_fbc_is_active(dev_priv)) { |
1004 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
874 | DRM_DEBUG_KMS("unsupported config, deactivating FBC\n"); |
1005 | __intel_fbc_disable(dev_priv); |
- | |
1006 | } |
875 | __intel_fbc_deactivate(dev_priv); |
Line 1007... | Line 876... | ||
1007 | __intel_fbc_cleanup_cfb(dev_priv); |
876 | } |
1008 | } |
877 | } |
1009 | 878 | ||
1010 | /* |
879 | /* |
1011 | * intel_fbc_update - enable/disable FBC as needed |
880 | * intel_fbc_update - activate/deactivate FBC as needed |
1012 | * @dev_priv: i915 device instance |
881 | * @crtc: the CRTC that triggered the update |
1013 | * |
882 | * |
1014 | * This function reevaluates the overall state and enables or disables FBC. |
883 | * This function reevaluates the overall state and activates or deactivates FBC. |
- | 884 | */ |
|
- | 885 | void intel_fbc_update(struct intel_crtc *crtc) |
|
1015 | */ |
886 | { |
1016 | void intel_fbc_update(struct drm_i915_private *dev_priv) |
887 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
Line 1017... | Line 888... | ||
1017 | { |
888 | |
1018 | if (!fbc_supported(dev_priv)) |
889 | if (!fbc_supported(dev_priv)) |
1019 | return; |
890 | return; |
1020 | 891 | ||
Line 1021... | Line 892... | ||
1021 | mutex_lock(&dev_priv->fbc.lock); |
892 | mutex_lock(&dev_priv->fbc.lock); |
1022 | __intel_fbc_update(dev_priv); |
893 | __intel_fbc_update(crtc); |
Line 1037... | Line 908... | ||
1037 | 908 | ||
Line 1038... | Line 909... | ||
1038 | mutex_lock(&dev_priv->fbc.lock); |
909 | mutex_lock(&dev_priv->fbc.lock); |
1039 | 910 | ||
1040 | if (dev_priv->fbc.enabled) |
- | |
1041 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
- | |
1042 | else if (dev_priv->fbc.fbc_work) |
- | |
1043 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( |
911 | if (dev_priv->fbc.enabled) |
1044 | dev_priv->fbc.fbc_work->crtc->pipe); |
912 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
Line 1045... | Line 913... | ||
1045 | else |
913 | else |
Line 1046... | Line 914... | ||
1046 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; |
914 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; |
1047 | 915 | ||
Line 1048... | Line 916... | ||
1048 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); |
916 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); |
1049 | 917 | ||
Line 1050... | Line 918... | ||
1050 | if (dev_priv->fbc.busy_bits) |
918 | if (dev_priv->fbc.busy_bits) |
Line 1064... | Line 932... | ||
1064 | 932 | ||
Line 1065... | Line 933... | ||
1065 | mutex_lock(&dev_priv->fbc.lock); |
933 | mutex_lock(&dev_priv->fbc.lock); |
Line -... | Line 934... | ||
- | 934 | ||
- | 935 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; |
|
- | 936 | ||
- | 937 | if (!dev_priv->fbc.busy_bits && dev_priv->fbc.enabled) { |
|
- | 938 | if (origin != ORIGIN_FLIP && dev_priv->fbc.active) { |
|
- | 939 | intel_fbc_recompress(dev_priv); |
|
- | 940 | } else { |
|
- | 941 | __intel_fbc_deactivate(dev_priv); |
|
- | 942 | __intel_fbc_update(dev_priv->fbc.crtc); |
|
- | 943 | } |
|
- | 944 | } |
|
- | 945 | ||
- | 946 | mutex_unlock(&dev_priv->fbc.lock); |
|
- | 947 | } |
|
- | 948 | ||
- | 949 | /** |
|
- | 950 | * intel_fbc_enable: tries to enable FBC on the CRTC |
|
- | 951 | * @crtc: the CRTC |
|
- | 952 | * |
|
- | 953 | * This function checks if it's possible to enable FBC on the following CRTC, |
|
- | 954 | * then enables it. Notice that it doesn't activate FBC. |
|
- | 955 | */ |
|
- | 956 | void intel_fbc_enable(struct intel_crtc *crtc) |
|
- | 957 | { |
|
- | 958 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
- | 959 | ||
- | 960 | if (!fbc_supported(dev_priv)) |
|
- | 961 | return; |
|
1066 | 962 | ||
- | 963 | mutex_lock(&dev_priv->fbc.lock); |
|
- | 964 | ||
- | 965 | if (dev_priv->fbc.enabled) { |
|
- | 966 | WARN_ON(dev_priv->fbc.crtc == crtc); |
|
- | 967 | goto out; |
|
- | 968 | } |
|
- | 969 | ||
- | 970 | WARN_ON(dev_priv->fbc.active); |
|
- | 971 | WARN_ON(dev_priv->fbc.crtc != NULL); |
|
- | 972 | ||
- | 973 | if (intel_vgpu_active(dev_priv->dev)) { |
|
- | 974 | set_no_fbc_reason(dev_priv, "VGPU is active"); |
|
- | 975 | goto out; |
|
- | 976 | } |
|
- | 977 | ||
- | 978 | if (i915.enable_fbc < 0) { |
|
- | 979 | set_no_fbc_reason(dev_priv, "disabled per chip default"); |
|
- | 980 | goto out; |
|
- | 981 | } |
|
- | 982 | ||
- | 983 | if (!i915.enable_fbc) { |
|
- | 984 | set_no_fbc_reason(dev_priv, "disabled per module param"); |
|
- | 985 | goto out; |
|
- | 986 | } |
|
- | 987 | ||
- | 988 | if (!crtc_can_fbc(crtc)) { |
|
- | 989 | set_no_fbc_reason(dev_priv, "no enabled pipes can have FBC"); |
|
- | 990 | goto out; |
|
- | 991 | } |
|
- | 992 | ||
- | 993 | if (intel_fbc_alloc_cfb(crtc)) { |
|
- | 994 | set_no_fbc_reason(dev_priv, "not enough stolen memory"); |
|
- | 995 | goto out; |
|
- | 996 | } |
|
- | 997 | ||
- | 998 | DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
|
- | 999 | dev_priv->fbc.no_fbc_reason = "FBC enabled but not active yet\n"; |
|
- | 1000 | ||
- | 1001 | dev_priv->fbc.enabled = true; |
|
- | 1002 | dev_priv->fbc.crtc = crtc; |
|
- | 1003 | out: |
|
- | 1004 | mutex_unlock(&dev_priv->fbc.lock); |
|
- | 1005 | } |
|
- | 1006 | ||
- | 1007 | /** |
|
- | 1008 | * __intel_fbc_disable - disable FBC |
|
- | 1009 | * @dev_priv: i915 device instance |
|
- | 1010 | * |
|
- | 1011 | * This is the low level function that actually disables FBC. Callers should |
|
- | 1012 | * grab the FBC lock. |
|
- | 1013 | */ |
|
- | 1014 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
|
- | 1015 | { |
|
- | 1016 | struct intel_crtc *crtc = dev_priv->fbc.crtc; |
|
- | 1017 | ||
- | 1018 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
|
- | 1019 | WARN_ON(!dev_priv->fbc.enabled); |
|
- | 1020 | WARN_ON(dev_priv->fbc.active); |
|
- | 1021 | assert_pipe_disabled(dev_priv, crtc->pipe); |
|
- | 1022 | ||
- | 1023 | DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
|
- | 1024 | ||
- | 1025 | __intel_fbc_cleanup_cfb(dev_priv); |
|
- | 1026 | ||
- | 1027 | dev_priv->fbc.enabled = false; |
|
- | 1028 | dev_priv->fbc.crtc = NULL; |
|
- | 1029 | } |
|
- | 1030 | ||
- | 1031 | /** |
|
- | 1032 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc |
|
- | 1033 | * @crtc: the CRTC |
|
- | 1034 | * |
|
- | 1035 | * This function disables FBC if it's associated with the provided CRTC. |
|
- | 1036 | */ |
|
- | 1037 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) |
|
- | 1038 | { |
|
- | 1039 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
- | 1040 | ||
- | 1041 | if (!fbc_supported(dev_priv)) |
|
- | 1042 | return; |
|
- | 1043 | ||
- | 1044 | mutex_lock(&dev_priv->fbc.lock); |
|
1067 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; |
1045 | if (dev_priv->fbc.crtc == crtc) { |
- | 1046 | WARN_ON(!dev_priv->fbc.enabled); |
|
1068 | 1047 | WARN_ON(dev_priv->fbc.active); |
|
1069 | if (!dev_priv->fbc.busy_bits) { |
1048 | __intel_fbc_disable(dev_priv); |
Line -... | Line 1049... | ||
- | 1049 | } |
|
- | 1050 | mutex_unlock(&dev_priv->fbc.lock); |
|
- | 1051 | } |
|
- | 1052 | ||
- | 1053 | /** |
|
- | 1054 | * intel_fbc_disable - globally disable FBC |
|
- | 1055 | * @dev_priv: i915 device instance |
|
- | 1056 | * |
|
- | 1057 | * This function disables FBC regardless of which CRTC is associated with it. |
|
- | 1058 | */ |
|
- | 1059 | void intel_fbc_disable(struct drm_i915_private *dev_priv) |
|
- | 1060 | { |
|
- | 1061 | if (!fbc_supported(dev_priv)) |
|
- | 1062 | return; |
|
1070 | __intel_fbc_disable(dev_priv); |
1063 | |
1071 | __intel_fbc_update(dev_priv); |
1064 | mutex_lock(&dev_priv->fbc.lock); |
Line 1072... | Line 1065... | ||
1072 | } |
1065 | if (dev_priv->fbc.enabled) |
1073 | 1066 | __intel_fbc_disable(dev_priv); |
|
Line 1082... | Line 1075... | ||
1082 | */ |
1075 | */ |
1083 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1076 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1084 | { |
1077 | { |
1085 | enum pipe pipe; |
1078 | enum pipe pipe; |
Line -... | Line 1079... | ||
- | 1079 | ||
1086 | 1080 | INIT_WORK(&dev_priv->fbc.work.work, intel_fbc_work_fn); |
|
- | 1081 | mutex_init(&dev_priv->fbc.lock); |
|
- | 1082 | dev_priv->fbc.enabled = false; |
|
- | 1083 | dev_priv->fbc.active = false; |
|
Line 1087... | Line 1084... | ||
1087 | mutex_init(&dev_priv->fbc.lock); |
1084 | dev_priv->fbc.work.scheduled = false; |
1088 | - | ||
1089 | if (!HAS_FBC(dev_priv)) { |
1085 | |
1090 | dev_priv->fbc.enabled = false; |
1086 | if (!HAS_FBC(dev_priv)) { |
1091 | dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
1087 | dev_priv->fbc.no_fbc_reason = "unsupported by this chipset"; |
Line 1092... | Line 1088... | ||
1092 | return; |
1088 | return; |
1093 | } |
1089 | } |
1094 | 1090 | ||
Line 1095... | Line 1091... | ||
1095 | for_each_pipe(dev_priv, pipe) { |
1091 | for_each_pipe(dev_priv, pipe) { |
1096 | dev_priv->fbc.possible_framebuffer_bits |= |
1092 | dev_priv->fbc.possible_framebuffer_bits |= |
1097 | INTEL_FRONTBUFFER_PRIMARY(pipe); |
1093 | INTEL_FRONTBUFFER_PRIMARY(pipe); |
Line 1098... | Line 1094... | ||
1098 | 1094 | ||
1099 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
1095 | if (fbc_on_pipe_a_only(dev_priv)) |
1100 | break; |
1096 | break; |
1101 | } |
1097 | } |
1102 | 1098 | ||
1103 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
1099 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
1104 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1100 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1105 | dev_priv->fbc.enable_fbc = gen7_fbc_enable; |
1101 | dev_priv->fbc.activate = gen7_fbc_activate; |
1106 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; |
1102 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; |
1107 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
1103 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
1108 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1104 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1109 | dev_priv->fbc.enable_fbc = ilk_fbc_enable; |
1105 | dev_priv->fbc.activate = ilk_fbc_activate; |
1110 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; |
1106 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; |
1111 | } else if (IS_GM45(dev_priv)) { |
1107 | } else if (IS_GM45(dev_priv)) { |
1112 | dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; |
1108 | dev_priv->fbc.is_active = g4x_fbc_is_active; |
1113 | dev_priv->fbc.enable_fbc = g4x_fbc_enable; |
1109 | dev_priv->fbc.activate = g4x_fbc_activate; |
Line 1114... | Line 1110... | ||
1114 | dev_priv->fbc.disable_fbc = g4x_fbc_disable; |
1110 | dev_priv->fbc.deactivate = g4x_fbc_deactivate; |
1115 | } else { |
1111 | } else { |
1116 | dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; |
1112 | dev_priv->fbc.is_active = i8xx_fbc_is_active; |
Line -... | Line 1113... | ||
- | 1113 | dev_priv->fbc.activate = i8xx_fbc_activate; |
|
- | 1114 | dev_priv->fbc.deactivate = i8xx_fbc_deactivate; |
|
- | 1115 | ||
- | 1116 | /* This value was pulled out of someone's hat */ |
|
1117 | dev_priv->fbc.enable_fbc = i8xx_fbc_enable; |
1117 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
1118 | dev_priv->fbc.disable_fbc = i8xx_fbc_disable; |
1118 | } |