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Rev 6937 Rev 7144
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#include
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#include
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#include "intel_drv.h"
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#include "intel_drv.h"
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#include "i915_drv.h"
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#include "i915_drv.h"
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#include "intel_dsi.h"
 31 
#include "intel_dsi.h"
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#define DSI_HSS_PACKET_SIZE		4
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#define DSI_HSE_PACKET_SIZE		4
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#define DSI_HSA_PACKET_EXTRA_SIZE	6
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#define DSI_HBP_PACKET_EXTRA_SIZE	6
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#define DSI_HACTIVE_PACKET_EXTRA_SIZE	6
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#define DSI_HFP_PACKET_EXTRA_SIZE	6
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#define DSI_EOTP_PACKET_SIZE		4
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static int dsi_pixel_format_bpp(int pixel_format)
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int dsi_pixel_format_bpp(int pixel_format)
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{
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{
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	int bpp;
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	int bpp;
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	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
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	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
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	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
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	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
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	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
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	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
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};
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};
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#ifdef DSI_CLK_FROM_RR
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static u32 dsi_rr_formula(const struct drm_display_mode *mode,
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			  int pixel_format, int video_mode_format,
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			  int lane_count, bool eotp)
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{
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	u32 bpp;
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	u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp;
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	u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes;
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	u32 bytes_per_line, bytes_per_frame;
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	u32 num_frames;
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	u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes;
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	u32 dsi_bit_clock_hz;
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	u32 dsi_clk;
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88 
 
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	bpp = dsi_pixel_format_bpp(pixel_format);
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90 
 
 - 
 
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	hactive = mode->hdisplay;
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	vactive = mode->vdisplay;
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	hfp = mode->hsync_start - mode->hdisplay;
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	hsync = mode->hsync_end - mode->hsync_start;
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	hbp = mode->htotal - mode->hsync_end;
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	vfp = mode->vsync_start - mode->vdisplay;
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98 
	vsync = mode->vsync_end - mode->vsync_start;
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	vbp = mode->vtotal - mode->vsync_end;
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100 
 
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	hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8);
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	hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8);
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	hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8);
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	hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8);
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	bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes +
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		DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE +
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		hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE +
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		hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE +
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		hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE;
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111 
 
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	/*
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	 * XXX: Need to accurately calculate LP to HS transition timeout and add
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114 
	 * it to bytes_per_line/bytes_per_frame.
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115 
	 */
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116 
 
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	if (eotp && video_mode_format == VIDEO_MODE_BURST)
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		bytes_per_line += DSI_EOTP_PACKET_SIZE;
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	bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line +
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		vactive * bytes_per_line + vfp * bytes_per_line;
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 - 
 
123 
	if (eotp &&
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124 
	    (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ||
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	     video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS))
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		bytes_per_frame += DSI_EOTP_PACKET_SIZE;
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127 
 
 - 
 
128 
	num_frames = drm_mode_vrefresh(mode);
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	bytes_per_x_frames = num_frames * bytes_per_frame;
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130 
 
 - 
 
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	bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;
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	/* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */
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134 
	dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8;
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135 
	dsi_clk = dsi_bit_clock_hz / 1000;
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136 
 
 - 
 
137 
	if (eotp && video_mode_format == VIDEO_MODE_BURST)
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138 
		dsi_clk *= 2;
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139 
 
 - 
 
140 
	return dsi_clk;
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141 
}
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142 
 
 - 
 
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#else
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144 
 
 65 
 
145 
/* Get DSI clock from pixel clock */
 66 
/* Get DSI clock from pixel clock */
146 
static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
 67 
static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
147 
{
 68 
{
148 
	u32 dsi_clk_khz;
 69 
	u32 dsi_clk_khz;
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	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
 74 
	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
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 75 
 
155 
	return dsi_clk_khz;
 76 
	return dsi_clk_khz;
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156 
}
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157 
 
 - 
 
158 
#endif
 77 
}
159 
 
 78 
 
160 
static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
 79 
static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
161 
			struct dsi_mnp *dsi_mnp, int target_dsi_clk)
 80 
			struct dsi_mnp *dsi_mnp, int target_dsi_clk)
162 
{
 81 
{
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	WARN(bpp != pipe_bpp,
 239 
	WARN(bpp != pipe_bpp,
321 
	     "bpp match assertion failure (expected %d, current %d)\n",
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	     "bpp match assertion failure (expected %d, current %d)\n",
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	     bpp, pipe_bpp);
 241 
	     bpp, pipe_bpp);
323 
}
 242 
}
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 243 
 
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u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 244 
static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
326 
{
 245 
{
327 
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 246 
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
328 
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 247 
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
329 
	u32 dsi_clock, pclk;
 248 
	u32 dsi_clock, pclk;
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	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
 301 
	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
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 302 
 
384 
	return pclk;
 303 
	return pclk;
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}
 304 
}
386 
 
 305 
 
387 
u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 306 
static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
388 
{
 307 
{
389 
	u32 pclk;
 308 
	u32 pclk;
390 
	u32 dsi_clk;
 309 
	u32 dsi_clk;
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417 
 
 336 
 
418 
	DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
 337 
	DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
419 
	return pclk;
 338 
	return pclk;
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- 
 
 339 
}
- 
 
 340 
 
- 
 
 341 
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
- 
 
 342 
{
- 
 
 343 
	if (IS_BROXTON(encoder->base.dev))
- 
 
 344 
		return bxt_dsi_get_pclk(encoder, pipe_bpp);
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 345 
	else
- 
 
 346 
		return vlv_dsi_get_pclk(encoder, pipe_bpp);
420 
}
 347 
}
421 
 
 348 
 
422 
static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 349 
static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
423 
{
 350 
{
424 
	u32 temp;
 351 
	u32 temp;