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Rev 4560 | Rev 5060 | ||
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Line 296... | Line 296... | ||
296 | tmp |= DSI_PLL_LDO_GATE; |
296 | tmp |= DSI_PLL_LDO_GATE; |
297 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
297 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); |
Line 298... | Line 298... | ||
298 | 298 | ||
299 | mutex_unlock(&dev_priv->dpio_lock); |
299 | mutex_unlock(&dev_priv->dpio_lock); |
- | 300 | } |
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- | 301 | ||
- | 302 | static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) |
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- | 303 | { |
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- | 304 | int bpp; |
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- | 305 | ||
- | 306 | switch (pixel_format) { |
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- | 307 | default: |
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- | 308 | case VID_MODE_FORMAT_RGB888: |
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- | 309 | case VID_MODE_FORMAT_RGB666_LOOSE: |
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- | 310 | bpp = 24; |
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- | 311 | break; |
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- | 312 | case VID_MODE_FORMAT_RGB666: |
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- | 313 | bpp = 18; |
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- | 314 | break; |
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- | 315 | case VID_MODE_FORMAT_RGB565: |
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- | 316 | bpp = 16; |
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- | 317 | break; |
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- | 318 | } |
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- | 319 | ||
- | 320 | WARN(bpp != pipe_bpp, |
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- | 321 | "bpp match assertion failure (expected %d, current %d)\n", |
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- | 322 | bpp, pipe_bpp); |
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- | 323 | } |
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- | 324 | ||
- | 325 | u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) |
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- | 326 | { |
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- | 327 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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- | 328 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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- | 329 | u32 dsi_clock, pclk; |
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- | 330 | u32 pll_ctl, pll_div; |
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- | 331 | u32 m = 0, p = 0; |
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- | 332 | int refclk = 25000; |
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- | 333 | int i; |
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- | 334 | ||
- | 335 | DRM_DEBUG_KMS("\n"); |
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- | 336 | ||
- | 337 | mutex_lock(&dev_priv->dpio_lock); |
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- | 338 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
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- | 339 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); |
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- | 340 | mutex_unlock(&dev_priv->dpio_lock); |
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- | 341 | ||
- | 342 | /* mask out other bits and extract the P1 divisor */ |
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- | 343 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; |
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- | 344 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); |
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- | 345 | ||
- | 346 | /* mask out the other bits and extract the M1 divisor */ |
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- | 347 | pll_div &= DSI_PLL_M1_DIV_MASK; |
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- | 348 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; |
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- | 349 | ||
- | 350 | while (pll_ctl) { |
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- | 351 | pll_ctl = pll_ctl >> 1; |
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- | 352 | p++; |
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- | 353 | } |
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- | 354 | p--; |
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- | 355 | ||
- | 356 | if (!p) { |
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- | 357 | DRM_ERROR("wrong P1 divisor\n"); |
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- | 358 | return 0; |
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- | 359 | } |
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- | 360 | ||
- | 361 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { |
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- | 362 | if (lfsr_converts[i] == pll_div) |
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- | 363 | break; |
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- | 364 | } |
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- | 365 | ||
- | 366 | if (i == ARRAY_SIZE(lfsr_converts)) { |
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- | 367 | DRM_ERROR("wrong m_seed programmed\n"); |
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- | 368 | return 0; |
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- | 369 | } |
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- | 370 | ||
- | 371 | m = i + 62; |
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- | 372 | ||
- | 373 | dsi_clock = (m * refclk) / p; |
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- | 374 | ||
- | 375 | /* pixel_format and pipe_bpp should agree */ |
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- | 376 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); |
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- | 377 | ||
- | 378 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); |
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- | 379 | ||
- | 380 | return pclk; |