WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_dsi_cmd.c


/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Author: Jani Nikula 
 */
 
#include 
#include 
#include 
#include 
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"
#include "intel_dsi_cmd.h"
 
/*
 * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
 * MIPI_COMMAND_ADDRESS registers.
 *
 * Apparently these registers provide a MIPI adapter level way to send (lots of)
 * commands and data to the receiver, without having to write the commands and
 * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
 *
 * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
 * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
 * framebuffer in command mode displays) these are just an optimization that can
 * come later.
 *
 * For memory writes, these should probably be used for performance.
 */
 
static void print_stat(struct intel_dsi *intel_dsi)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;
 
	val = I915_READ(MIPI_INTR_STAT(pipe));
 
#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
	DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x"
		      "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
		      "\n", pipe, val,
		      STAT_BIT(val, TEARING_EFFECT),
		      STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
		      STAT_BIT(val, GEN_READ_DATA_AVAIL),
		      STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
		      STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
		      STAT_BIT(val, RX_PROT_VIOLATION),
		      STAT_BIT(val, RX_INVALID_TX_LENGTH),
		      STAT_BIT(val, ACK_WITH_NO_ERROR),
		      STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
		      STAT_BIT(val, LP_RX_TIMEOUT),
		      STAT_BIT(val, HS_TX_TIMEOUT),
		      STAT_BIT(val, DPI_FIFO_UNDERRUN),
		      STAT_BIT(val, LOW_CONTENTION),
		      STAT_BIT(val, HIGH_CONTENTION),
		      STAT_BIT(val, TXDSI_VC_ID_INVALID),
		      STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
		      STAT_BIT(val, TXCHECKSUM_ERROR),
		      STAT_BIT(val, TXECC_MULTIBIT_ERROR),
		      STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
		      STAT_BIT(val, TXFALSE_CONTROL_ERROR),
		      STAT_BIT(val, RXDSI_VC_ID_INVALID),
		      STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
		      STAT_BIT(val, RXCHECKSUM_ERROR),
		      STAT_BIT(val, RXECC_MULTIBIT_ERROR),
		      STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
		      STAT_BIT(val, RXFALSE_CONTROL_ERROR),
		      STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
		      STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
		      STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
		      STAT_BIT(val, RXEOT_SYNC_ERROR),
		      STAT_BIT(val, RXSOT_SYNC_ERROR),
		      STAT_BIT(val, RXSOT_ERROR));
#undef STAT_BIT
}
 
enum dsi_type {
	DSI_DCS,
	DSI_GENERIC,
};
 
/* enable or disable command mode hs transmissions */
void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 temp;
	u32 mask = DBI_FIFO_EMPTY;
 
	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
		DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
 
	temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));
	temp &= DBI_HS_LP_MODE_MASK;
	I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);
 
	intel_dsi->hs = enable;
}
 
static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
			     u8 data_type, u16 data)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 ctrl_reg;
	u32 ctrl;
	u32 mask;
 
	DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
		      channel, data_type, data);
 
	if (intel_dsi->hs) {
		ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
		mask = HS_CTRL_FIFO_FULL;
	} else {
		ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
		mask = LP_CTRL_FIFO_FULL;
	}
 
	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {
		DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
		print_stat(intel_dsi);
	}
 
	/*
	 * Note: This function is also used for long packets, with length passed
	 * as data, since SHORT_PACKET_PARAM_SHIFT ==
	 * LONG_PACKET_WORD_COUNT_SHIFT.
	 */
	ctrl = data << SHORT_PACKET_PARAM_SHIFT |
		channel << VIRTUAL_CHANNEL_SHIFT |
		data_type << DATA_TYPE_SHIFT;
 
	I915_WRITE(ctrl_reg, ctrl);
 
	return 0;
}
 
static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
			    u8 data_type, const u8 *data, int len)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 data_reg;
	int i, j, n;
	u32 mask;
 
	DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
		      channel, data_type, len);
 
	if (intel_dsi->hs) {
		data_reg = MIPI_HS_GEN_DATA(pipe);
		mask = HS_DATA_FIFO_FULL;
	} else {
		data_reg = MIPI_LP_GEN_DATA(pipe);
		mask = LP_DATA_FIFO_FULL;
	}
 
	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
		DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 
	for (i = 0; i < len; i += n) {
		u32 val = 0;
		n = min_t(int, len - i, 4);
 
		for (j = 0; j < n; j++)
			val |= *data++ << 8 * j;
 
		I915_WRITE(data_reg, val);
		/* XXX: check for data fifo full, once that is set, write 4
		 * dwords, then wait for not set, then continue. */
	}
 
	return dsi_vc_send_short(intel_dsi, channel, data_type, len);
}
 
static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
			       int channel, const u8 *data, int len,
			       enum dsi_type type)
{
	int ret;
 
	if (len == 0) {
		BUG_ON(type == DSI_GENERIC);
		ret = dsi_vc_send_short(intel_dsi, channel,
					MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
					0);
	} else if (len == 1) {
		ret = dsi_vc_send_short(intel_dsi, channel,
					type == DSI_GENERIC ?
					MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
					MIPI_DSI_DCS_SHORT_WRITE, data[0]);
	} else if (len == 2) {
		ret = dsi_vc_send_short(intel_dsi, channel,
					type == DSI_GENERIC ?
					MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
					MIPI_DSI_DCS_SHORT_WRITE_PARAM,
					(data[1] << 8) | data[0]);
	} else {
		ret = dsi_vc_send_long(intel_dsi, channel,
				       type == DSI_GENERIC ?
				       MIPI_DSI_GENERIC_LONG_WRITE :
				       MIPI_DSI_DCS_LONG_WRITE, data, len);
	}
 
	return ret;
}
 
int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
		     const u8 *data, int len)
{
	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
}
 
int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
			 const u8 *data, int len)
{
	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
}
 
static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
					int channel, u8 dcs_cmd)
{
	return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
				 dcs_cmd);
}
 
static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
					    int channel, u8 *reqdata,
					    int reqlen)
{
	u16 data;
	u8 data_type;
 
	switch (reqlen) {
	case 0:
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
		data = 0;
		break;
	case 1:
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
		data = reqdata[0];
		break;
	case 2:
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
		data = (reqdata[1] << 8) | reqdata[0];
		break;
	default:
		BUG();
	}
 
	return dsi_vc_send_short(intel_dsi, channel, data_type, data);
}
 
static int dsi_read_data_return(struct intel_dsi *intel_dsi,
				u8 *buf, int buflen)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	int i, len = 0;
	u32 data_reg, val;
 
	if (intel_dsi->hs) {
		data_reg = MIPI_HS_GEN_DATA(pipe);
	} else {
		data_reg = MIPI_LP_GEN_DATA(pipe);
	}
 
	while (len < buflen) {
		val = I915_READ(data_reg);
		for (i = 0; i < 4 && len < buflen; i++, len++)
			buf[len] = val >> 8 * i;
	}
 
	return len;
}
 
int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
		    u8 *buf, int buflen)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 mask;
	int ret;
 
	/*
	 * XXX: should issue multiple read requests and reads if request is
	 * longer than MIPI_MAX_RETURN_PKT_SIZE
	 */
 
	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
 
	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
	if (ret)
		return ret;
 
	mask = GEN_READ_DATA_AVAIL;
	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
		DRM_ERROR("Timeout waiting for read data.\n");
 
	ret = dsi_read_data_return(intel_dsi, buf, buflen);
	if (ret < 0)
		return ret;
 
	if (ret != buflen)
		return -EIO;
 
	return 0;
}
 
int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
			u8 *reqdata, int reqlen, u8 *buf, int buflen)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 mask;
	int ret;
 
	/*
	 * XXX: should issue multiple read requests and reads if request is
	 * longer than MIPI_MAX_RETURN_PKT_SIZE
	 */
 
	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
 
	ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
					       reqlen);
	if (ret)
		return ret;
 
	mask = GEN_READ_DATA_AVAIL;
	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
		DRM_ERROR("Timeout waiting for read data.\n");
 
	ret = dsi_read_data_return(intel_dsi, buf, buflen);
	if (ret < 0)
		return ret;
 
	if (ret != buflen)
		return -EIO;
 
	return 0;
}
 
/*
 * send a video mode command
 *
 * XXX: commands with data in MIPI_DPI_DATA?
 */
int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 mask;
 
	/* XXX: pipe, hs */
	if (hs)
		cmd &= ~DPI_LP_MODE;
	else
		cmd |= DPI_LP_MODE;
 
 
 
 
 
 
 
	/* clear bit */
	I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
 
	/* XXX: old code skips write if control unchanged */
	if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))
		DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 
	I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);
 
	mask = SPL_PKT_SENT_INTERRUPT;
	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100))
		DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 
	return 0;
}
 
void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
{
	struct drm_encoder *encoder = &intel_dsi->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	enum pipe pipe = intel_crtc->pipe;
	u32 mask;
 
	mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
					LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
 
	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100))
		DRM_ERROR("DPI FIFOs are not empty\n");
}

Rev 4560	Rev 5060
1	/*	1	/*
2	* Copyright © 2013 Intel Corporation	2	* Copyright © 2013 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.	21	* DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Author: Jani Nikula	23	* Author: Jani Nikula
24	*/	24	*/
25		25
26	#include	26	#include
27	#include	27	#include
28	#include	28	#include
29	#include	29	#include
30	#include "i915_drv.h"	30	#include "i915_drv.h"
31	#include "intel_drv.h"	31	#include "intel_drv.h"
32	#include "intel_dsi.h"	32	#include "intel_dsi.h"
33	#include "intel_dsi_cmd.h"	33	#include "intel_dsi_cmd.h"
34		34
35	/*	35	/*
36	* XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and	36	* XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
37	* MIPI_COMMAND_ADDRESS registers.	37	* MIPI_COMMAND_ADDRESS registers.
38	*	38	*
39	* Apparently these registers provide a MIPI adapter level way to send (lots of)	39	* Apparently these registers provide a MIPI adapter level way to send (lots of)
40	* commands and data to the receiver, without having to write the commands and	40	* commands and data to the receiver, without having to write the commands and
41	* data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.	41	* data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
42	*	42	*
43	* Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and	43	* Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
44	* MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external	44	* MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
45	* framebuffer in command mode displays) these are just an optimization that can	45	* framebuffer in command mode displays) these are just an optimization that can
46	* come later.	46	* come later.
47	*	47	*
48	* For memory writes, these should probably be used for performance.	48	* For memory writes, these should probably be used for performance.
49	*/	49	*/
50		50
51	static void print_stat(struct intel_dsi *intel_dsi)	51	static void print_stat(struct intel_dsi *intel_dsi)
52	{	52	{
53	struct drm_encoder *encoder = &intel_dsi->base.base;	53	struct drm_encoder *encoder = &intel_dsi->base.base;
54	struct drm_device *dev = encoder->dev;	54	struct drm_device *dev = encoder->dev;
55	struct drm_i915_private *dev_priv = dev->dev_private;	55	struct drm_i915_private *dev_priv = dev->dev_private;
56	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	56	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
57	enum pipe pipe = intel_crtc->pipe;	57	enum pipe pipe = intel_crtc->pipe;
58	u32 val;	58	u32 val;
59		59
60	val = I915_READ(MIPI_INTR_STAT(pipe));	60	val = I915_READ(MIPI_INTR_STAT(pipe));
61		61
62	#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""	62	#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
63	DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x"	63	DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x"
64	"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"	64	"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
65	"\n", pipe, val,	65	"\n", pipe, val,
66	STAT_BIT(val, TEARING_EFFECT),	66	STAT_BIT(val, TEARING_EFFECT),
67	STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),	67	STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
68	STAT_BIT(val, GEN_READ_DATA_AVAIL),	68	STAT_BIT(val, GEN_READ_DATA_AVAIL),
69	STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),	69	STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
70	STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),	70	STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
71	STAT_BIT(val, RX_PROT_VIOLATION),	71	STAT_BIT(val, RX_PROT_VIOLATION),
72	STAT_BIT(val, RX_INVALID_TX_LENGTH),	72	STAT_BIT(val, RX_INVALID_TX_LENGTH),
73	STAT_BIT(val, ACK_WITH_NO_ERROR),	73	STAT_BIT(val, ACK_WITH_NO_ERROR),
74	STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),	74	STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
75	STAT_BIT(val, LP_RX_TIMEOUT),	75	STAT_BIT(val, LP_RX_TIMEOUT),
76	STAT_BIT(val, HS_TX_TIMEOUT),	76	STAT_BIT(val, HS_TX_TIMEOUT),
77	STAT_BIT(val, DPI_FIFO_UNDERRUN),	77	STAT_BIT(val, DPI_FIFO_UNDERRUN),
78	STAT_BIT(val, LOW_CONTENTION),	78	STAT_BIT(val, LOW_CONTENTION),
79	STAT_BIT(val, HIGH_CONTENTION),	79	STAT_BIT(val, HIGH_CONTENTION),
80	STAT_BIT(val, TXDSI_VC_ID_INVALID),	80	STAT_BIT(val, TXDSI_VC_ID_INVALID),
81	STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),	81	STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
82	STAT_BIT(val, TXCHECKSUM_ERROR),	82	STAT_BIT(val, TXCHECKSUM_ERROR),
83	STAT_BIT(val, TXECC_MULTIBIT_ERROR),	83	STAT_BIT(val, TXECC_MULTIBIT_ERROR),
84	STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),	84	STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
85	STAT_BIT(val, TXFALSE_CONTROL_ERROR),	85	STAT_BIT(val, TXFALSE_CONTROL_ERROR),
86	STAT_BIT(val, RXDSI_VC_ID_INVALID),	86	STAT_BIT(val, RXDSI_VC_ID_INVALID),
87	STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),	87	STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
88	STAT_BIT(val, RXCHECKSUM_ERROR),	88	STAT_BIT(val, RXCHECKSUM_ERROR),
89	STAT_BIT(val, RXECC_MULTIBIT_ERROR),	89	STAT_BIT(val, RXECC_MULTIBIT_ERROR),
90	STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),	90	STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
91	STAT_BIT(val, RXFALSE_CONTROL_ERROR),	91	STAT_BIT(val, RXFALSE_CONTROL_ERROR),
92	STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),	92	STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
93	STAT_BIT(val, RX_LP_TX_SYNC_ERROR),	93	STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
94	STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),	94	STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
95	STAT_BIT(val, RXEOT_SYNC_ERROR),	95	STAT_BIT(val, RXEOT_SYNC_ERROR),
96	STAT_BIT(val, RXSOT_SYNC_ERROR),	96	STAT_BIT(val, RXSOT_SYNC_ERROR),
97	STAT_BIT(val, RXSOT_ERROR));	97	STAT_BIT(val, RXSOT_ERROR));
98	#undef STAT_BIT	98	#undef STAT_BIT
99	}	99	}
100		100
101	enum dsi_type {	101	enum dsi_type {
102	DSI_DCS,	102	DSI_DCS,
103	DSI_GENERIC,	103	DSI_GENERIC,
104	};	104	};
105		105
106	/* enable or disable command mode hs transmissions */	106	/* enable or disable command mode hs transmissions */
107	void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)	107	void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
108	{	108	{
109	struct drm_encoder *encoder = &intel_dsi->base.base;	109	struct drm_encoder *encoder = &intel_dsi->base.base;
110	struct drm_device *dev = encoder->dev;	110	struct drm_device *dev = encoder->dev;
111	struct drm_i915_private *dev_priv = dev->dev_private;	111	struct drm_i915_private *dev_priv = dev->dev_private;
112	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	112	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
113	enum pipe pipe = intel_crtc->pipe;	113	enum pipe pipe = intel_crtc->pipe;
114	u32 temp;	114	u32 temp;
115	u32 mask = DBI_FIFO_EMPTY;	115	u32 mask = DBI_FIFO_EMPTY;
116		116
117	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))	117	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
118	DRM_ERROR("Timeout waiting for DBI FIFO empty\n");	118	DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
119		119
120	temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));	120	temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));
121	temp &= DBI_HS_LP_MODE_MASK;	121	temp &= DBI_HS_LP_MODE_MASK;
122	I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);	122	I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);
123		123
124	intel_dsi->hs = enable;	124	intel_dsi->hs = enable;
125	}	125	}
126		126
127	static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,	127	static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
128	u8 data_type, u16 data)	128	u8 data_type, u16 data)
129	{	129	{
130	struct drm_encoder *encoder = &intel_dsi->base.base;	130	struct drm_encoder *encoder = &intel_dsi->base.base;
131	struct drm_device *dev = encoder->dev;	131	struct drm_device *dev = encoder->dev;
132	struct drm_i915_private *dev_priv = dev->dev_private;	132	struct drm_i915_private *dev_priv = dev->dev_private;
133	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	133	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
134	enum pipe pipe = intel_crtc->pipe;	134	enum pipe pipe = intel_crtc->pipe;
135	u32 ctrl_reg;	135	u32 ctrl_reg;
136	u32 ctrl;	136	u32 ctrl;
137	u32 mask;	137	u32 mask;
138		138
139	DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",	139	DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
140	channel, data_type, data);	140	channel, data_type, data);
141		141
142	if (intel_dsi->hs) {	142	if (intel_dsi->hs) {
143	ctrl_reg = MIPI_HS_GEN_CTRL(pipe);	143	ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
144	mask = HS_CTRL_FIFO_FULL;	144	mask = HS_CTRL_FIFO_FULL;
145	} else {	145	} else {
146	ctrl_reg = MIPI_LP_GEN_CTRL(pipe);	146	ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
147	mask = LP_CTRL_FIFO_FULL;	147	mask = LP_CTRL_FIFO_FULL;
148	}	148	}
149		149
150	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {	150	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {
151	DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");	151	DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
152	print_stat(intel_dsi);	152	print_stat(intel_dsi);
153	}	153	}
154		154
155	/*	155	/*
156	* Note: This function is also used for long packets, with length passed	156	* Note: This function is also used for long packets, with length passed
157	* as data, since SHORT_PACKET_PARAM_SHIFT ==	157	* as data, since SHORT_PACKET_PARAM_SHIFT ==
158	* LONG_PACKET_WORD_COUNT_SHIFT.	158	* LONG_PACKET_WORD_COUNT_SHIFT.
159	*/	159	*/
160	ctrl = data << SHORT_PACKET_PARAM_SHIFT \|	160	ctrl = data << SHORT_PACKET_PARAM_SHIFT \|
161	channel << VIRTUAL_CHANNEL_SHIFT \|	161	channel << VIRTUAL_CHANNEL_SHIFT \|
162	data_type << DATA_TYPE_SHIFT;	162	data_type << DATA_TYPE_SHIFT;
163		163
164	I915_WRITE(ctrl_reg, ctrl);	164	I915_WRITE(ctrl_reg, ctrl);
165		165
166	return 0;	166	return 0;
167	}	167	}
168		168
169	static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,	169	static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
170	u8 data_type, const u8 *data, int len)	170	u8 data_type, const u8 *data, int len)
171	{	171	{
172	struct drm_encoder *encoder = &intel_dsi->base.base;	172	struct drm_encoder *encoder = &intel_dsi->base.base;
173	struct drm_device *dev = encoder->dev;	173	struct drm_device *dev = encoder->dev;
174	struct drm_i915_private *dev_priv = dev->dev_private;	174	struct drm_i915_private *dev_priv = dev->dev_private;
175	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	175	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
176	enum pipe pipe = intel_crtc->pipe;	176	enum pipe pipe = intel_crtc->pipe;
177	u32 data_reg;	177	u32 data_reg;
178	int i, j, n;	178	int i, j, n;
179	u32 mask;	179	u32 mask;
180		180
181	DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",	181	DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
182	channel, data_type, len);	182	channel, data_type, len);
183		183
184	if (intel_dsi->hs) {	184	if (intel_dsi->hs) {
185	data_reg = MIPI_HS_GEN_DATA(pipe);	185	data_reg = MIPI_HS_GEN_DATA(pipe);
186	mask = HS_DATA_FIFO_FULL;	186	mask = HS_DATA_FIFO_FULL;
187	} else {	187	} else {
188	data_reg = MIPI_LP_GEN_DATA(pipe);	188	data_reg = MIPI_LP_GEN_DATA(pipe);
189	mask = LP_DATA_FIFO_FULL;	189	mask = LP_DATA_FIFO_FULL;
190	}	190	}
191		191
192	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))	192	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
193	DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");	193	DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
194		194
195	for (i = 0; i < len; i += n) {	195	for (i = 0; i < len; i += n) {
196	u32 val = 0;	196	u32 val = 0;
197	n = min_t(int, len - i, 4);	197	n = min_t(int, len - i, 4);
198		198
199	for (j = 0; j < n; j++)	199	for (j = 0; j < n; j++)
200	val \|= data++ << 8 j;	200	val \|= data++ << 8 j;
201		201
202	I915_WRITE(data_reg, val);	202	I915_WRITE(data_reg, val);
203	/* XXX: check for data fifo full, once that is set, write 4	203	/* XXX: check for data fifo full, once that is set, write 4
204	* dwords, then wait for not set, then continue. */	204	* dwords, then wait for not set, then continue. */
205	}	205	}
206		206
207	return dsi_vc_send_short(intel_dsi, channel, data_type, len);	207	return dsi_vc_send_short(intel_dsi, channel, data_type, len);
208	}	208	}
209		209
210	static int dsi_vc_write_common(struct intel_dsi *intel_dsi,	210	static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
211	int channel, const u8 *data, int len,	211	int channel, const u8 *data, int len,
212	enum dsi_type type)	212	enum dsi_type type)
213	{	213	{
214	int ret;	214	int ret;
215		215
216	if (len == 0) {	216	if (len == 0) {
217	BUG_ON(type == DSI_GENERIC);	217	BUG_ON(type == DSI_GENERIC);
218	ret = dsi_vc_send_short(intel_dsi, channel,	218	ret = dsi_vc_send_short(intel_dsi, channel,
219	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,	219	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
220	0);	220	0);
221	} else if (len == 1) {	221	} else if (len == 1) {
222	ret = dsi_vc_send_short(intel_dsi, channel,	222	ret = dsi_vc_send_short(intel_dsi, channel,
223	type == DSI_GENERIC ?	223	type == DSI_GENERIC ?
224	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :	224	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
225	MIPI_DSI_DCS_SHORT_WRITE, data[0]);	225	MIPI_DSI_DCS_SHORT_WRITE, data[0]);
226	} else if (len == 2) {	226	} else if (len == 2) {
227	ret = dsi_vc_send_short(intel_dsi, channel,	227	ret = dsi_vc_send_short(intel_dsi, channel,
228	type == DSI_GENERIC ?	228	type == DSI_GENERIC ?
229	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :	229	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
230	MIPI_DSI_DCS_SHORT_WRITE_PARAM,	230	MIPI_DSI_DCS_SHORT_WRITE_PARAM,
231	(data[1] << 8) \| data[0]);	231	(data[1] << 8) \| data[0]);
232	} else {	232	} else {
233	ret = dsi_vc_send_long(intel_dsi, channel,	233	ret = dsi_vc_send_long(intel_dsi, channel,
234	type == DSI_GENERIC ?	234	type == DSI_GENERIC ?
235	MIPI_DSI_GENERIC_LONG_WRITE :	235	MIPI_DSI_GENERIC_LONG_WRITE :
236	MIPI_DSI_DCS_LONG_WRITE, data, len);	236	MIPI_DSI_DCS_LONG_WRITE, data, len);
237	}	237	}
238		238
239	return ret;	239	return ret;
240	}	240	}
241		241
242	int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,	242	int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
243	const u8 *data, int len)	243	const u8 *data, int len)
244	{	244	{
245	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);	245	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
246	}	246	}
247		247
248	int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,	248	int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
249	const u8 *data, int len)	249	const u8 *data, int len)
250	{	250	{
251	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);	251	return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
252	}	252	}
253		253
254	static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,	254	static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
255	int channel, u8 dcs_cmd)	255	int channel, u8 dcs_cmd)
256	{	256	{
257	return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,	257	return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
258	dcs_cmd);	258	dcs_cmd);
259	}	259	}
260		260
261	static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,	261	static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
262	int channel, u8 *reqdata,	262	int channel, u8 *reqdata,
263	int reqlen)	263	int reqlen)
264	{	264	{
265	u16 data;	265	u16 data;
266	u8 data_type;	266	u8 data_type;
267		267
268	switch (reqlen) {	268	switch (reqlen) {
269	case 0:	269	case 0:
270	data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;	270	data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
271	data = 0;	271	data = 0;
272	break;	272	break;
273	case 1:	273	case 1:
274	data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;	274	data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
275	data = reqdata[0];	275	data = reqdata[0];
276	break;	276	break;
277	case 2:	277	case 2:
278	data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;	278	data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
279	data = (reqdata[1] << 8) \| reqdata[0];	279	data = (reqdata[1] << 8) \| reqdata[0];
280	break;	280	break;
281	default:	281	default:
282	BUG();	282	BUG();
283	}	283	}
284		284
285	return dsi_vc_send_short(intel_dsi, channel, data_type, data);	285	return dsi_vc_send_short(intel_dsi, channel, data_type, data);
286	}	286	}
287		287
288	static int dsi_read_data_return(struct intel_dsi *intel_dsi,	288	static int dsi_read_data_return(struct intel_dsi *intel_dsi,
289	u8 *buf, int buflen)	289	u8 *buf, int buflen)
290	{	290	{
291	struct drm_encoder *encoder = &intel_dsi->base.base;	291	struct drm_encoder *encoder = &intel_dsi->base.base;
292	struct drm_device *dev = encoder->dev;	292	struct drm_device *dev = encoder->dev;
293	struct drm_i915_private *dev_priv = dev->dev_private;	293	struct drm_i915_private *dev_priv = dev->dev_private;
294	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	294	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
295	enum pipe pipe = intel_crtc->pipe;	295	enum pipe pipe = intel_crtc->pipe;
296	int i, len = 0;	296	int i, len = 0;
297	u32 data_reg, val;	297	u32 data_reg, val;
298		298
299	if (intel_dsi->hs) {	299	if (intel_dsi->hs) {
300	data_reg = MIPI_HS_GEN_DATA(pipe);	300	data_reg = MIPI_HS_GEN_DATA(pipe);
301	} else {	301	} else {
302	data_reg = MIPI_LP_GEN_DATA(pipe);	302	data_reg = MIPI_LP_GEN_DATA(pipe);
303	}	303	}
304		304
305	while (len < buflen) {	305	while (len < buflen) {
306	val = I915_READ(data_reg);	306	val = I915_READ(data_reg);
307	for (i = 0; i < 4 && len < buflen; i++, len++)	307	for (i = 0; i < 4 && len < buflen; i++, len++)
308	buf[len] = val >> 8 * i;	308	buf[len] = val >> 8 * i;
309	}	309	}
310		310
311	return len;	311	return len;
312	}	312	}
313		313
314	int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,	314	int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
315	u8 *buf, int buflen)	315	u8 *buf, int buflen)
316	{	316	{
317	struct drm_encoder *encoder = &intel_dsi->base.base;	317	struct drm_encoder *encoder = &intel_dsi->base.base;
318	struct drm_device *dev = encoder->dev;	318	struct drm_device *dev = encoder->dev;
319	struct drm_i915_private *dev_priv = dev->dev_private;	319	struct drm_i915_private *dev_priv = dev->dev_private;
320	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	320	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
321	enum pipe pipe = intel_crtc->pipe;	321	enum pipe pipe = intel_crtc->pipe;
322	u32 mask;	322	u32 mask;
323	int ret;	323	int ret;
324		324
325	/*	325	/*
326	* XXX: should issue multiple read requests and reads if request is	326	* XXX: should issue multiple read requests and reads if request is
327	* longer than MIPI_MAX_RETURN_PKT_SIZE	327	* longer than MIPI_MAX_RETURN_PKT_SIZE
328	*/	328	*/
329		329
330	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);	330	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
331		331
332	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);	332	ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
333	if (ret)	333	if (ret)
334	return ret;	334	return ret;
335		335
336	mask = GEN_READ_DATA_AVAIL;	336	mask = GEN_READ_DATA_AVAIL;
337	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))	337	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
338	DRM_ERROR("Timeout waiting for read data.\n");	338	DRM_ERROR("Timeout waiting for read data.\n");
339		339
340	ret = dsi_read_data_return(intel_dsi, buf, buflen);	340	ret = dsi_read_data_return(intel_dsi, buf, buflen);
341	if (ret < 0)	341	if (ret < 0)
342	return ret;	342	return ret;
343		343
344	if (ret != buflen)	344	if (ret != buflen)
345	return -EIO;	345	return -EIO;
346		346
347	return 0;	347	return 0;
348	}	348	}
349		349
350	int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,	350	int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
351	u8 reqdata, int reqlen, u8 buf, int buflen)	351	u8 reqdata, int reqlen, u8 buf, int buflen)
352	{	352	{
353	struct drm_encoder *encoder = &intel_dsi->base.base;	353	struct drm_encoder *encoder = &intel_dsi->base.base;
354	struct drm_device *dev = encoder->dev;	354	struct drm_device *dev = encoder->dev;
355	struct drm_i915_private *dev_priv = dev->dev_private;	355	struct drm_i915_private *dev_priv = dev->dev_private;
356	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	356	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
357	enum pipe pipe = intel_crtc->pipe;	357	enum pipe pipe = intel_crtc->pipe;
358	u32 mask;	358	u32 mask;
359	int ret;	359	int ret;
360		360
361	/*	361	/*
362	* XXX: should issue multiple read requests and reads if request is	362	* XXX: should issue multiple read requests and reads if request is
363	* longer than MIPI_MAX_RETURN_PKT_SIZE	363	* longer than MIPI_MAX_RETURN_PKT_SIZE
364	*/	364	*/
365		365
366	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);	366	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
367		367
368	ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,	368	ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
369	reqlen);	369	reqlen);
370	if (ret)	370	if (ret)
371	return ret;	371	return ret;
372		372
373	mask = GEN_READ_DATA_AVAIL;	373	mask = GEN_READ_DATA_AVAIL;
374	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))	374	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
375	DRM_ERROR("Timeout waiting for read data.\n");	375	DRM_ERROR("Timeout waiting for read data.\n");
376		376
377	ret = dsi_read_data_return(intel_dsi, buf, buflen);	377	ret = dsi_read_data_return(intel_dsi, buf, buflen);
378	if (ret < 0)	378	if (ret < 0)
379	return ret;	379	return ret;
380		380
381	if (ret != buflen)	381	if (ret != buflen)
382	return -EIO;	382	return -EIO;
383		383
384	return 0;	384	return 0;
385	}	385	}
386		386
387	/*	387	/*
388	* send a video mode command	388	* send a video mode command
389	*	389	*
390	* XXX: commands with data in MIPI_DPI_DATA?	390	* XXX: commands with data in MIPI_DPI_DATA?
391	*/	391	*/
392	int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd)	392	int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
393	{	393	{
394	struct drm_encoder *encoder = &intel_dsi->base.base;	394	struct drm_encoder *encoder = &intel_dsi->base.base;
395	struct drm_device *dev = encoder->dev;	395	struct drm_device *dev = encoder->dev;
396	struct drm_i915_private *dev_priv = dev->dev_private;	396	struct drm_i915_private *dev_priv = dev->dev_private;
397	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	397	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
398	enum pipe pipe = intel_crtc->pipe;	398	enum pipe pipe = intel_crtc->pipe;
399	u32 mask;	399	u32 mask;
400		400
401	/* XXX: pipe, hs */	401	/* XXX: pipe, hs */
402	if (intel_dsi->hs)	402	if (hs)
403	cmd &= ~DPI_LP_MODE;	403	cmd &= ~DPI_LP_MODE;
404	else	404	else
405	cmd \|= DPI_LP_MODE;	405	cmd \|= DPI_LP_MODE;
406		-
407	/* DPI virtual channel?! */	-
408		-
409	mask = DPI_FIFO_EMPTY;	-
410	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))	-
411	DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");	-
412		406
413	/* clear bit */	407	/* clear bit */
414	I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);	408	I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
415		409
416	/* XXX: old code skips write if control unchanged */	410	/* XXX: old code skips write if control unchanged */
417	if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))	411	if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))
418	DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);	412	DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
419		413
420	I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);	414	I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);
421		415
422	mask = SPL_PKT_SENT_INTERRUPT;	416	mask = SPL_PKT_SENT_INTERRUPT;
423	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100))	417	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100))
424	DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);	418	DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
425		419
426	return 0;	420	return 0;
427	}	421	}
-		422
-		423	void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
-		424	{
-		425	struct drm_encoder *encoder = &intel_dsi->base.base;
-		426	struct drm_device *dev = encoder->dev;
-		427	struct drm_i915_private *dev_priv = dev->dev_private;
-		428	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-		429	enum pipe pipe = intel_crtc->pipe;
-		430	u32 mask;
-		431
-		432	mask = LP_CTRL_FIFO_EMPTY \| HS_CTRL_FIFO_EMPTY \|
-		433	LP_DATA_FIFO_EMPTY \| HS_DATA_FIFO_EMPTY;
-		434
-		435	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100))
-		436	DRM_ERROR("DPI FIFOs are not empty\n");
-		437	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_dsi_cmd.c @ 6132 – Rev 4560 → 5060