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	enum port port;

	enum port port;

	u32 tmp;

	u32 tmp;

	DRM_DEBUG_KMS("\n");

	intel_dsi_prepare(encoder);

	intel_enable_dsi_pll(encoder);

	intel_enable_dsi_pll(encoder);

	intel_dsi_prepare(encoder);

static void intel_dsi_post_disable(struct intel_encoder *encoder)

static void intel_dsi_post_disable(struct intel_encoder *encoder)

{

{

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;

	u32 val;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	DRM_DEBUG_KMS("\n");

	DRM_DEBUG_KMS("\n");

	intel_dsi_clear_device_ready(encoder);

	intel_dsi_disable(encoder);

	if (!IS_BROXTON(dev_priv)) {

	intel_dsi_clear_device_ready(encoder);

		val = I915_READ(DSPCLK_GATE_D);

	val = I915_READ(DSPCLK_GATE_D);

		val &= ~DPOUNIT_CLOCK_GATE_DISABLE;

}

}

static void intel_dsi_get_config(struct intel_encoder *encoder,

static void intel_dsi_get_config(struct intel_encoder *encoder,

				 struct intel_crtc_state *pipe_config)

				 struct intel_crtc_state *pipe_config)

	u32 pclk = 0;

	u32 pclk;

	DRM_DEBUG_KMS("\n");

	DRM_DEBUG_KMS("\n");

	pipe_config->has_dsi_encoder = true;

	pipe_config->has_dsi_encoder = true;

	/*

	/*

	 * DPLL_MD is not used in case of DSI, reading will get some default value

	 * DPLL_MD is not used in case of DSI, reading will get some default value

	else if (IS_VALLEYVIEW(encoder->base.dev) ||

	 */

		 IS_CHERRYVIEW(encoder->base.dev))

	pipe_config->dpll_hw_state.dpll_md = 0;

		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);

	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);

static void set_dsi_timings(struct drm_encoder *encoder,

static void set_dsi_timings(struct drm_encoder *encoder,

			    const struct drm_display_mode *adjusted_mode)

			    const struct drm_display_mode *adjusted_mode)

{

{

	struct drm_device *dev = encoder->dev;

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	enum port port;

	enum port port;

	unsigned int lane_count = intel_dsi->lane_count;

	unsigned int lane_count = intel_dsi->lane_count;

	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;

	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;

	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;

	enum port port;

	enum port port;

	u32 val, tmp;

	u32 val, tmp;

	u16 mode_hdisplay;

	u16 mode_hdisplay;