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Line 22... | Line 22... | ||
22 | * |
22 | * |
23 | * Author: Jani Nikula |
23 | * Author: Jani Nikula |
24 | */ |
24 | */ |
Line 25... | Line 25... | ||
25 | 25 | ||
- | 26 | #include |
|
26 | #include |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include |
- | 30 | #include |
|
- | 31 | #include |
|
29 | #include |
32 | #include |
- | 33 | #include |
|
30 | #include |
34 | #include |
31 | #include "i915_drv.h" |
35 | #include "i915_drv.h" |
32 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
33 | #include "intel_dsi.h" |
- | |
Line 34... | Line 37... | ||
34 | #include "intel_dsi_cmd.h" |
37 | #include "intel_dsi.h" |
- | 38 | ||
35 | 39 | static const struct { |
|
- | 40 | u16 panel_id; |
|
36 | /* the sub-encoders aka panel drivers */ |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { |
42 | } intel_dsi_drivers[] = { |
38 | { |
- | |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
43 | { |
40 | .name = "vbt-generic-dsi-vid-mode-display", |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
41 | .dev_ops = &vbt_generic_dsi_display_ops, |
45 | .init = vbt_panel_init, |
Line -... | Line 46... | ||
- | 46 | }, |
|
- | 47 | }; |
|
- | 48 | ||
- | 49 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
|
- | 50 | { |
|
- | 51 | struct drm_encoder *encoder = &intel_dsi->base.base; |
|
- | 52 | struct drm_device *dev = encoder->dev; |
|
- | 53 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 54 | u32 mask; |
|
- | 55 | ||
- | 56 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | |
|
- | 57 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; |
|
- | 58 | ||
- | 59 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) |
|
- | 60 | DRM_ERROR("DPI FIFOs are not empty\n"); |
|
- | 61 | } |
|
- | 62 | ||
- | 63 | static void write_data(struct drm_i915_private *dev_priv, u32 reg, |
|
- | 64 | const u8 *data, u32 len) |
|
- | 65 | { |
|
- | 66 | u32 i, j; |
|
- | 67 | ||
- | 68 | for (i = 0; i < len; i += 4) { |
|
- | 69 | u32 val = 0; |
|
- | 70 | ||
- | 71 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
|
- | 72 | val |= *data++ << 8 * j; |
|
- | 73 | ||
- | 74 | I915_WRITE(reg, val); |
|
- | 75 | } |
|
- | 76 | } |
|
- | 77 | ||
- | 78 | static void read_data(struct drm_i915_private *dev_priv, u32 reg, |
|
- | 79 | u8 *data, u32 len) |
|
- | 80 | { |
|
- | 81 | u32 i, j; |
|
- | 82 | ||
- | 83 | for (i = 0; i < len; i += 4) { |
|
- | 84 | u32 val = I915_READ(reg); |
|
- | 85 | ||
- | 86 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
|
- | 87 | *data++ = val >> 8 * j; |
|
- | 88 | } |
|
- | 89 | } |
|
- | 90 | ||
- | 91 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, |
|
- | 92 | const struct mipi_dsi_msg *msg) |
|
- | 93 | { |
|
- | 94 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); |
|
- | 95 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; |
|
- | 96 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 97 | enum port port = intel_dsi_host->port; |
|
- | 98 | struct mipi_dsi_packet packet; |
|
- | 99 | ssize_t ret; |
|
- | 100 | const u8 *header, *data; |
|
- | 101 | u32 data_reg, data_mask, ctrl_reg, ctrl_mask; |
|
- | 102 | ||
- | 103 | ret = mipi_dsi_create_packet(&packet, msg); |
|
- | 104 | if (ret < 0) |
|
- | 105 | return ret; |
|
- | 106 | ||
- | 107 | header = packet.header; |
|
- | 108 | data = packet.payload; |
|
- | 109 | ||
- | 110 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { |
|
- | 111 | data_reg = MIPI_LP_GEN_DATA(port); |
|
- | 112 | data_mask = LP_DATA_FIFO_FULL; |
|
- | 113 | ctrl_reg = MIPI_LP_GEN_CTRL(port); |
|
- | 114 | ctrl_mask = LP_CTRL_FIFO_FULL; |
|
- | 115 | } else { |
|
- | 116 | data_reg = MIPI_HS_GEN_DATA(port); |
|
- | 117 | data_mask = HS_DATA_FIFO_FULL; |
|
- | 118 | ctrl_reg = MIPI_HS_GEN_CTRL(port); |
|
- | 119 | ctrl_mask = HS_CTRL_FIFO_FULL; |
|
- | 120 | } |
|
- | 121 | ||
- | 122 | /* note: this is never true for reads */ |
|
- | 123 | if (packet.payload_length) { |
|
- | 124 | ||
- | 125 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) |
|
- | 126 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
|
- | 127 | ||
- | 128 | write_data(dev_priv, data_reg, packet.payload, |
|
- | 129 | packet.payload_length); |
|
- | 130 | } |
|
- | 131 | ||
- | 132 | if (msg->rx_len) { |
|
- | 133 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); |
|
- | 134 | } |
|
- | 135 | ||
- | 136 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { |
|
- | 137 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
|
- | 138 | } |
|
- | 139 | ||
- | 140 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); |
|
- | 141 | ||
- | 142 | /* ->rx_len is set only for reads */ |
|
- | 143 | if (msg->rx_len) { |
|
- | 144 | data_mask = GEN_READ_DATA_AVAIL; |
|
- | 145 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) |
|
- | 146 | DRM_ERROR("Timeout waiting for read data.\n"); |
|
- | 147 | ||
- | 148 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); |
|
- | 149 | } |
|
- | 150 | ||
- | 151 | /* XXX: fix for reads and writes */ |
|
- | 152 | return 4 + packet.payload_length; |
|
- | 153 | } |
|
- | 154 | ||
- | 155 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, |
|
- | 156 | struct mipi_dsi_device *dsi) |
|
- | 157 | { |
|
- | 158 | return 0; |
|
- | 159 | } |
|
- | 160 | ||
- | 161 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, |
|
- | 162 | struct mipi_dsi_device *dsi) |
|
- | 163 | { |
|
- | 164 | return 0; |
|
- | 165 | } |
|
- | 166 | ||
- | 167 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { |
|
- | 168 | .attach = intel_dsi_host_attach, |
|
- | 169 | .detach = intel_dsi_host_detach, |
|
- | 170 | .transfer = intel_dsi_host_transfer, |
|
- | 171 | }; |
|
- | 172 | ||
- | 173 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, |
|
- | 174 | enum port port) |
|
- | 175 | { |
|
- | 176 | struct intel_dsi_host *host; |
|
- | 177 | struct mipi_dsi_device *device; |
|
- | 178 | ||
- | 179 | host = kzalloc(sizeof(*host), GFP_KERNEL); |
|
- | 180 | if (!host) |
|
- | 181 | return NULL; |
|
- | 182 | ||
- | 183 | host->base.ops = &intel_dsi_host_ops; |
|
- | 184 | host->intel_dsi = intel_dsi; |
|
- | 185 | host->port = port; |
|
- | 186 | ||
- | 187 | /* |
|
- | 188 | * We should call mipi_dsi_host_register(&host->base) here, but we don't |
|
- | 189 | * have a host->dev, and we don't have OF stuff either. So just use the |
|
- | 190 | * dsi framework as a library and hope for the best. Create the dsi |
|
- | 191 | * devices by ourselves here too. Need to be careful though, because we |
|
- | 192 | * don't initialize any of the driver model devices here. |
|
- | 193 | */ |
|
- | 194 | device = kzalloc(sizeof(*device), GFP_KERNEL); |
|
- | 195 | if (!device) { |
|
- | 196 | kfree(host); |
|
- | 197 | return NULL; |
|
- | 198 | } |
|
- | 199 | ||
- | 200 | device->host = &host->base; |
|
- | 201 | host->device = device; |
|
- | 202 | ||
- | 203 | return host; |
|
- | 204 | } |
|
- | 205 | ||
- | 206 | /* |
|
- | 207 | * send a video mode command |
|
- | 208 | * |
|
- | 209 | * XXX: commands with data in MIPI_DPI_DATA? |
|
- | 210 | */ |
|
- | 211 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, |
|
- | 212 | enum port port) |
|
- | 213 | { |
|
- | 214 | struct drm_encoder *encoder = &intel_dsi->base.base; |
|
- | 215 | struct drm_device *dev = encoder->dev; |
|
- | 216 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 217 | u32 mask; |
|
- | 218 | ||
- | 219 | /* XXX: pipe, hs */ |
|
- | 220 | if (hs) |
|
- | 221 | cmd &= ~DPI_LP_MODE; |
|
- | 222 | else |
|
- | 223 | cmd |= DPI_LP_MODE; |
|
- | 224 | ||
- | 225 | /* clear bit */ |
|
- | 226 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); |
|
- | 227 | ||
- | 228 | /* XXX: old code skips write if control unchanged */ |
|
- | 229 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) |
|
- | 230 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); |
|
- | 231 | ||
- | 232 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); |
|
- | 233 | ||
- | 234 | mask = SPL_PKT_SENT_INTERRUPT; |
|
- | 235 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) |
|
- | 236 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
|
- | 237 | ||
42 | }, |
238 | return 0; |
43 | }; |
239 | } |
44 | 240 | ||
Line 45... | Line 241... | ||
45 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
241 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
46 | { |
242 | { |
47 | mutex_lock(&dev_priv->dpio_lock); |
243 | mutex_lock(&dev_priv->sb_lock); |
48 | 244 | ||
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
245 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
50 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
246 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
Line 51... | Line 247... | ||
51 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
247 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
52 | udelay(150); |
- | |
53 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
- | |
54 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
- | |
55 | - | ||
56 | mutex_unlock(&dev_priv->dpio_lock); |
- | |
57 | } |
- | |
58 | 248 | udelay(150); |
|
Line 59... | Line 249... | ||
59 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
249 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
60 | { |
250 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
61 | return container_of(intel_attached_encoder(connector), |
251 | |
Line 70... | Line 260... | ||
70 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
260 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
71 | { |
261 | { |
72 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
262 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
73 | } |
263 | } |
Line 74... | Line -... | ||
74 | - | ||
75 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) |
- | |
76 | { |
- | |
77 | DRM_DEBUG_KMS("\n"); |
- | |
78 | } |
- | |
79 | 264 | ||
80 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
265 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
81 | struct intel_crtc_config *config) |
266 | struct intel_crtc_state *config) |
82 | { |
267 | { |
83 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
268 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
84 | base); |
269 | base); |
85 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
270 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
86 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
271 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
87 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; |
- | |
Line 88... | Line 272... | ||
88 | struct drm_display_mode *mode = &config->requested_mode; |
272 | struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode; |
Line 89... | Line 273... | ||
89 | 273 | ||
90 | DRM_DEBUG_KMS("\n"); |
274 | DRM_DEBUG_KMS("\n"); |
Line 91... | Line 275... | ||
91 | 275 | ||
92 | if (fixed_mode) |
276 | if (fixed_mode) |
Line 93... | Line -... | ||
93 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
- | |
94 | - | ||
95 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
- | |
96 | adjusted_mode->flags = 0; |
- | |
97 | 277 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
|
98 | if (intel_dsi->dev.dev_ops->mode_fixup) |
278 | |
Line 99... | Line 279... | ||
99 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, |
279 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
100 | mode, adjusted_mode); |
280 | adjusted_mode->flags = 0; |
101 | 281 | ||
102 | return true; |
282 | return true; |
103 | } |
283 | } |
104 | 284 | ||
Line 105... | Line 285... | ||
105 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
285 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
Line -... | Line 286... | ||
- | 286 | { |
|
- | 287 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
|
- | 288 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
|
- | 289 | enum port port; |
|
- | 290 | u32 val; |
|
- | 291 | ||
- | 292 | DRM_DEBUG_KMS("\n"); |
|
- | 293 | ||
- | 294 | /* Exit Low power state in 4 steps*/ |
|
- | 295 | for_each_dsi_port(port, intel_dsi->ports) { |
|
- | 296 | ||
- | 297 | /* 1. Enable MIPI PHY transparent latch */ |
|
- | 298 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); |
|
- | 299 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); |
|
- | 300 | usleep_range(2000, 2500); |
|
- | 301 | ||
- | 302 | /* 2. Enter ULPS */ |
|
- | 303 | val = I915_READ(MIPI_DEVICE_READY(port)); |
|
- | 304 | val &= ~ULPS_STATE_MASK; |
|
- | 305 | val |= (ULPS_STATE_ENTER | DEVICE_READY); |
|
- | 306 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
|
- | 307 | usleep_range(2, 3); |
|
- | 308 | ||
- | 309 | /* 3. Exit ULPS */ |
|
- | 310 | val = I915_READ(MIPI_DEVICE_READY(port)); |
|
- | 311 | val &= ~ULPS_STATE_MASK; |
|
- | 312 | val |= (ULPS_STATE_EXIT | DEVICE_READY); |
|
- | 313 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
|
- | 314 | usleep_range(1000, 1500); |
|
- | 315 | ||
- | 316 | /* Clear ULPS and set device ready */ |
|
- | 317 | val = I915_READ(MIPI_DEVICE_READY(port)); |
|
- | 318 | val &= ~ULPS_STATE_MASK; |
|
- | 319 | val |= DEVICE_READY; |
|
- | 320 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
|
- | 321 | } |
|
- | 322 | } |
|
- | 323 | ||
- | 324 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
|
106 | { |
325 | { |
107 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
326 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
108 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
327 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
109 | int pipe = intel_crtc->pipe; |
328 | enum port port; |
110 | u32 val; |
329 | u32 val; |
Line 111... | Line 330... | ||
111 | 330 | ||
112 | DRM_DEBUG_KMS("\n"); |
331 | DRM_DEBUG_KMS("\n"); |
Line -... | Line 332... | ||
- | 332 | ||
- | 333 | mutex_lock(&dev_priv->sb_lock); |
|
113 | 334 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
|
114 | mutex_lock(&dev_priv->dpio_lock); |
335 | * needed everytime after power gate */ |
Line -... | Line 336... | ||
- | 336 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
|
- | 337 | mutex_unlock(&dev_priv->sb_lock); |
|
- | 338 | ||
- | 339 | /* bandgap reset is needed after everytime we do power gate */ |
|
115 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
340 | band_gap_reset(dev_priv); |
116 | * needed everytime after power gate */ |
341 | |
117 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
342 | for_each_dsi_port(port, intel_dsi->ports) { |
Line 118... | Line 343... | ||
118 | mutex_unlock(&dev_priv->dpio_lock); |
343 | |
119 | 344 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
|
Line 120... | Line 345... | ||
120 | /* bandgap reset is needed after everytime we do power gate */ |
345 | usleep_range(2500, 3000); |
121 | band_gap_reset(dev_priv); |
346 | |
122 | 347 | /* Enable MIPI PHY transparent latch |
|
- | 348 | * Common bit for both MIPI Port A & MIPI Port C |
|
Line -... | Line 349... | ||
- | 349 | * No similar bit in MIPI Port C reg |
|
- | 350 | */ |
|
- | 351 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
|
- | 352 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
|
- | 353 | usleep_range(1000, 1500); |
|
- | 354 | ||
- | 355 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
|
- | 356 | usleep_range(2500, 3000); |
|
- | 357 | ||
- | 358 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); |
|
123 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); |
359 | usleep_range(2500, 3000); |
124 | usleep_range(2500, 3000); |
360 | } |
125 | 361 | } |
|
126 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
362 | |
127 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); |
363 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
128 | usleep_range(1000, 1500); |
364 | { |
- | 365 | struct drm_device *dev = encoder->base.dev; |
|
- | 366 | ||
- | 367 | if (IS_VALLEYVIEW(dev)) |
|
- | 368 | vlv_dsi_device_ready(encoder); |
|
- | 369 | else if (IS_BROXTON(dev)) |
|
- | 370 | bxt_dsi_device_ready(encoder); |
|
- | 371 | } |
|
- | 372 | ||
- | 373 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
|
- | 374 | { |
|
- | 375 | struct drm_device *dev = encoder->base.dev; |
|
- | 376 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 377 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
|
- | 378 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
|
- | 379 | enum port port; |
|
- | 380 | u32 temp; |
|
- | 381 | u32 port_ctrl; |
|
- | 382 | ||
- | 383 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
|
- | 384 | temp = I915_READ(VLV_CHICKEN_3); |
|
- | 385 | temp &= ~PIXEL_OVERLAP_CNT_MASK | |
|
- | 386 | intel_dsi->pixel_overlap << |
|
- | 387 | PIXEL_OVERLAP_CNT_SHIFT; |
|
- | 388 | I915_WRITE(VLV_CHICKEN_3, temp); |
|
129 | 389 | } |
|
- | 390 | ||
- | 391 | for_each_dsi_port(port, intel_dsi->ports) { |
|
- | 392 | port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) : |
|
- | 393 | MIPI_PORT_CTRL(port); |
|
- | 394 | ||
- | 395 | temp = I915_READ(port_ctrl); |
|
- | 396 | ||
- | 397 | temp &= ~LANE_CONFIGURATION_MASK; |
|
- | 398 | temp &= ~DUAL_LINK_MODE_MASK; |
|
- | 399 | ||
- | 400 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { |
|
- | 401 | temp |= (intel_dsi->dual_link - 1) |
|
- | 402 | << DUAL_LINK_MODE_SHIFT; |
|
- | 403 | temp |= intel_crtc->pipe ? |
|
- | 404 | LANE_CONFIGURATION_DUAL_LINK_B : |
|
130 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); |
405 | LANE_CONFIGURATION_DUAL_LINK_A; |
- | 406 | } |
|
- | 407 | /* assert ip_tg_enable signal */ |
|
- | 408 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); |
|
- | 409 | POSTING_READ(port_ctrl); |
|
- | 410 | } |
|
- | 411 | } |
|
- | 412 | ||
- | 413 | static void intel_dsi_port_disable(struct intel_encoder *encoder) |
|
- | 414 | { |
|
- | 415 | struct drm_device *dev = encoder->base.dev; |
|
- | 416 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 417 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
|
- | 418 | enum port port; |
|
- | 419 | u32 temp; |
|
- | 420 | u32 port_ctrl; |
|
- | 421 | ||
- | 422 | for_each_dsi_port(port, intel_dsi->ports) { |
|
- | 423 | /* de-assert ip_tg_enable signal */ |
|
Line 131... | Line 424... | ||
131 | usleep_range(2500, 3000); |
424 | port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) : |
Line 132... | Line 425... | ||
132 | 425 | MIPI_PORT_CTRL(port); |
|
- | 426 | temp = I915_READ(port_ctrl); |
|
133 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
427 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); |
134 | usleep_range(2500, 3000); |
428 | POSTING_READ(port_ctrl); |
135 | } |
429 | } |
- | 430 | } |
|
136 | 431 | ||
137 | static void intel_dsi_enable(struct intel_encoder *encoder) |
432 | static void intel_dsi_enable(struct intel_encoder *encoder) |
Line 138... | Line -... | ||
138 | { |
- | |
139 | struct drm_device *dev = encoder->base.dev; |
433 | { |
Line -... | Line 434... | ||
- | 434 | struct drm_device *dev = encoder->base.dev; |
|
140 | struct drm_i915_private *dev_priv = dev->dev_private; |
435 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 141... | Line 436... | ||
141 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
436 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
142 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
- | |
143 | int pipe = intel_crtc->pipe; |
- | |
144 | u32 temp; |
- | |
145 | - | ||
146 | DRM_DEBUG_KMS("\n"); |
437 | enum port port; |
- | 438 | ||
- | 439 | DRM_DEBUG_KMS("\n"); |
|
147 | 440 | ||
Line 148... | Line 441... | ||
148 | if (is_cmd_mode(intel_dsi)) |
441 | if (is_cmd_mode(intel_dsi)) { |
149 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); |
442 | for_each_dsi_port(port, intel_dsi->ports) |
150 | else { |
443 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); |
151 | msleep(20); /* XXX */ |
444 | } else { |
152 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); |
445 | msleep(20); /* XXX */ |
153 | msleep(100); |
446 | for_each_dsi_port(port, intel_dsi->ports) |
154 | 447 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
|
- | 448 | msleep(100); |
|
155 | if (intel_dsi->dev.dev_ops->enable) |
449 | |
Line 156... | Line 450... | ||
156 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); |
450 | drm_panel_enable(intel_dsi->panel); |
Line -... | Line 451... | ||
- | 451 | ||
- | 452 | for_each_dsi_port(port, intel_dsi->ports) |
|
- | 453 | wait_for_dsi_fifo_empty(intel_dsi, port); |
|
- | 454 | ||
- | 455 | intel_dsi_port_enable(encoder); |
|
- | 456 | } |
|
- | 457 | ||
- | 458 | intel_panel_enable_backlight(intel_dsi->attached_connector); |
|
157 | 459 | } |
|
158 | wait_for_dsi_fifo_empty(intel_dsi); |
460 | |
- | 461 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
|
159 | 462 | { |
|
160 | /* assert ip_tg_enable signal */ |
463 | struct drm_device *dev = encoder->base.dev; |
161 | temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; |
464 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 162... | Line 465... | ||
162 | temp = temp | intel_dsi->port_bits; |
465 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
163 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); |
466 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
- | 467 | enum pipe pipe = intel_crtc->pipe; |
|
164 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
468 | enum port port; |
Line 165... | Line 469... | ||
165 | } |
469 | u32 tmp; |
166 | } |
470 | |
167 | 471 | DRM_DEBUG_KMS("\n"); |
|
- | 472 | ||
Line 168... | Line 473... | ||
168 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
473 | /* Panel Enable over CRC PMIC */ |
169 | { |
474 | if (intel_dsi->gpio_panel) |
Line 170... | Line 475... | ||
170 | struct drm_device *dev = encoder->base.dev; |
475 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); |
Line 171... | Line -... | ||
171 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
172 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
476 | |
173 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
- | |
174 | enum pipe pipe = intel_crtc->pipe; |
- | |
175 | u32 tmp; |
- | |
176 | - | ||
177 | DRM_DEBUG_KMS("\n"); |
477 | msleep(intel_dsi->panel_on_delay); |
Line 178... | Line 478... | ||
178 | 478 | ||
179 | /* Disable DPOunit clock gating, can stall pipe |
479 | if (IS_VALLEYVIEW(dev)) { |
180 | * and we need DPLL REFA always enabled */ |
480 | /* |
181 | tmp = I915_READ(DPLL(pipe)); |
481 | * Disable DPOunit clock gating, can stall pipe |
Line 219... | Line 519... | ||
219 | } |
519 | } |
Line 220... | Line 520... | ||
220 | 520 | ||
221 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
521 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
222 | { |
522 | { |
- | 523 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
|
Line 223... | Line 524... | ||
223 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
524 | enum port port; |
Line -... | Line 525... | ||
- | 525 | ||
- | 526 | DRM_DEBUG_KMS("\n"); |
|
224 | 527 | ||
225 | DRM_DEBUG_KMS("\n"); |
528 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
- | 529 | ||
226 | 530 | if (is_vid_mode(intel_dsi)) { |
|
227 | if (is_vid_mode(intel_dsi)) { |
531 | /* Send Shutdown command to the panel in LP mode */ |
228 | /* Send Shutdown command to the panel in LP mode */ |
532 | for_each_dsi_port(port, intel_dsi->ports) |
229 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); |
533 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
Line 230... | Line 534... | ||
230 | msleep(10); |
534 | msleep(10); |
231 | } |
535 | } |
232 | } |
536 | } |
233 | 537 | ||
234 | static void intel_dsi_disable(struct intel_encoder *encoder) |
- | |
235 | { |
538 | static void intel_dsi_disable(struct intel_encoder *encoder) |
236 | struct drm_device *dev = encoder->base.dev; |
539 | { |
237 | struct drm_i915_private *dev_priv = dev->dev_private; |
540 | struct drm_device *dev = encoder->base.dev; |
Line 238... | Line 541... | ||
238 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
541 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 239... | Line 542... | ||
239 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
542 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
240 | int pipe = intel_crtc->pipe; |
543 | enum port port; |
241 | u32 temp; |
- | |
242 | 544 | u32 temp; |
|
243 | DRM_DEBUG_KMS("\n"); |
- | |
244 | - | ||
245 | if (is_vid_mode(intel_dsi)) { |
- | |
Line -... | Line 545... | ||
- | 545 | ||
246 | wait_for_dsi_fifo_empty(intel_dsi); |
546 | DRM_DEBUG_KMS("\n"); |
247 | 547 | ||
Line -... | Line 548... | ||
- | 548 | if (is_vid_mode(intel_dsi)) { |
|
248 | /* de-assert ip_tg_enable signal */ |
549 | for_each_dsi_port(port, intel_dsi->ports) |
249 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); |
550 | wait_for_dsi_fifo_empty(intel_dsi, port); |
250 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); |
- | |
251 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
- | |
252 | - | ||
253 | msleep(2); |
- | |
254 | } |
- | |
255 | - | ||
Line -... | Line 551... | ||
- | 551 | ||
256 | /* Panel commands can be sent when clock is in LP11 */ |
552 | intel_dsi_port_disable(encoder); |
Line 257... | Line 553... | ||
257 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); |
553 | msleep(2); |
258 | 554 | } |
|
259 | temp = I915_READ(MIPI_CTRL(pipe)); |
555 | |
260 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
- | |
261 | I915_WRITE(MIPI_CTRL(pipe), temp | |
- | |
Line -... | Line 556... | ||
- | 556 | for_each_dsi_port(port, intel_dsi->ports) { |
|
- | 557 | /* Panel commands can be sent when clock is in LP11 */ |
|
262 | intel_dsi->escape_clk_div << |
558 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); |
263 | ESCAPE_CLOCK_DIVIDER_SHIFT); |
559 | |
264 | - | ||
265 | I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); |
560 | intel_dsi_reset_clocks(encoder, port); |
Line -... | Line 561... | ||
- | 561 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
|
266 | 562 | ||
267 | temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); |
563 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
Line 268... | Line 564... | ||
268 | temp &= ~VID_MODE_FORMAT_MASK; |
564 | temp &= ~VID_MODE_FORMAT_MASK; |
269 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); |
565 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); |
- | 566 | ||
270 | 567 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
|
271 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); |
568 | } |
272 | 569 | /* if disable packets are sent before sending shutdown packet then in |
|
273 | /* if disable packets are sent before sending shutdown packet then in |
570 | * some next enable sequence send turn on packet error is observed */ |
- | 571 | drm_panel_disable(intel_dsi->panel); |
|
Line 274... | Line 572... | ||
274 | * some next enable sequence send turn on packet error is observed */ |
572 | |
- | 573 | for_each_dsi_port(port, intel_dsi->ports) |
|
Line 275... | Line 574... | ||
275 | if (intel_dsi->dev.dev_ops->disable) |
574 | wait_for_dsi_fifo_empty(intel_dsi, port); |
- | 575 | } |
|
276 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); |
576 | |
Line 277... | Line 577... | ||
277 | 577 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
|
- | 578 | { |
|
278 | wait_for_dsi_fifo_empty(intel_dsi); |
579 | struct drm_device *dev = encoder->base.dev; |
Line 279... | Line 580... | ||
279 | } |
580 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
- | 581 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
|
280 | 582 | enum port port; |
|
Line -... | Line 583... | ||
- | 583 | u32 val; |
|
- | 584 | u32 port_ctrl = 0; |
|
- | 585 | ||
- | 586 | DRM_DEBUG_KMS("\n"); |
|
- | 587 | for_each_dsi_port(port, intel_dsi->ports) { |
|
- | 588 | ||
- | 589 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
|
- | 590 | ULPS_STATE_ENTER); |
|
- | 591 | usleep_range(2000, 2500); |
|
281 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
592 | |
282 | { |
593 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
283 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
594 | ULPS_STATE_EXIT); |
Line -... | Line 595... | ||
- | 595 | usleep_range(2000, 2500); |
|
284 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
596 | |
285 | int pipe = intel_crtc->pipe; |
597 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
286 | u32 val; |
598 | ULPS_STATE_ENTER); |
Line 287... | Line 599... | ||
287 | 599 | usleep_range(2000, 2500); |
|
288 | DRM_DEBUG_KMS("\n"); |
600 | |
- | 601 | if (IS_BROXTON(dev)) |
|
Line 289... | Line 602... | ||
289 | 602 | port_ctrl = BXT_MIPI_PORT_CTRL(port); |
|
290 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
603 | else if (IS_VALLEYVIEW(dev)) |
Line 291... | Line 604... | ||
291 | usleep_range(2000, 2500); |
604 | /* Common bit for both MIPI Port A & MIPI Port C */ |
292 | 605 | port_ctrl = MIPI_PORT_CTRL(PORT_A); |
|
293 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); |
606 | |
Line 324... | Line 637... | ||
324 | 637 | ||
325 | val = I915_READ(DSPCLK_GATE_D); |
638 | val = I915_READ(DSPCLK_GATE_D); |
326 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
639 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
Line 327... | Line -... | ||
327 | I915_WRITE(DSPCLK_GATE_D, val); |
- | |
328 | 640 | I915_WRITE(DSPCLK_GATE_D, val); |
|
Line 329... | Line 641... | ||
329 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
641 | |
330 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); |
642 | drm_panel_unprepare(intel_dsi->panel); |
- | 643 | ||
- | 644 | msleep(intel_dsi->panel_off_delay); |
|
- | 645 | msleep(intel_dsi->panel_pwr_cycle_delay); |
|
- | 646 | ||
331 | 647 | /* Panel Disable over CRC PMIC */ |
|
Line 332... | Line 648... | ||
332 | msleep(intel_dsi->panel_off_delay); |
648 | if (intel_dsi->gpio_panel) |
333 | msleep(intel_dsi->panel_pwr_cycle_delay); |
649 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); |
334 | } |
650 | } |
335 | 651 | ||
- | 652 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
|
- | 653 | enum pipe *pipe) |
|
336 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
654 | { |
337 | enum pipe *pipe) |
655 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
338 | { |
656 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Line 339... | Line 657... | ||
339 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
657 | struct drm_device *dev = encoder->base.dev; |
Line 340... | Line 658... | ||
340 | enum intel_display_power_domain power_domain; |
658 | enum intel_display_power_domain power_domain; |
341 | u32 port, func; |
659 | u32 dpi_enabled, func, ctrl_reg; |
342 | enum pipe p; |
660 | enum port port; |
Line 343... | Line 661... | ||
343 | 661 | ||
344 | DRM_DEBUG_KMS("\n"); |
662 | DRM_DEBUG_KMS("\n"); |
345 | 663 | ||
- | 664 | power_domain = intel_display_port_power_domain(encoder); |
|
- | 665 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
|
- | 666 | return false; |
|
- | 667 | ||
- | 668 | /* XXX: this only works for one DSI output */ |
|
- | 669 | for_each_dsi_port(port, intel_dsi->ports) { |
|
- | 670 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
|
- | 671 | ctrl_reg = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) : |
|
- | 672 | MIPI_PORT_CTRL(port); |
|
- | 673 | dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
|
346 | power_domain = intel_display_port_power_domain(encoder); |
674 | |
- | 675 | /* Due to some hardware limitations on BYT, MIPI Port C DPI |
|
347 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
676 | * Enable bit does not get set. To check whether DSI Port C |
348 | return false; |
677 | * was enabled in BIOS, check the Pipe B enable bit |
349 | 678 | */ |
|
350 | /* XXX: this only works for one DSI output */ |
679 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
351 | for (p = PIPE_A; p <= PIPE_B; p++) { |
680 | (port == PORT_C)) |
352 | port = I915_READ(MIPI_PORT_CTRL(p)); |
681 | dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & |
353 | func = I915_READ(MIPI_DSI_FUNC_PRG(p)); |
682 | PIPECONF_ENABLE; |
354 | 683 | ||
Line 355... | Line 684... | ||
355 | if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
684 | if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
356 | if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { |
685 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { |
Line 357... | Line 686... | ||
357 | *pipe = p; |
686 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
358 | return true; |
687 | return true; |
359 | } |
688 | } |
360 | } |
689 | } |
361 | } |
690 | } |
Line 362... | Line 691... | ||
362 | 691 | ||
363 | return false; |
692 | return false; |
364 | } |
693 | } |
365 | 694 | ||
366 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
695 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
Line -... | Line 696... | ||
- | 696 | struct intel_crtc_state *pipe_config) |
|
- | 697 | { |
|
- | 698 | u32 pclk = 0; |
|
367 | struct intel_crtc_config *pipe_config) |
699 | DRM_DEBUG_KMS("\n"); |
- | 700 | ||
368 | { |
701 | /* |
369 | u32 pclk; |
702 | * DPLL_MD is not used in case of DSI, reading will get some default value |
Line 370... | Line 703... | ||
370 | DRM_DEBUG_KMS("\n"); |
703 | * set dpll_md = 0 |
371 | 704 | */ |
|
372 | /* |
705 | pipe_config->dpll_hw_state.dpll_md = 0; |
Line 373... | Line 706... | ||
373 | * DPLL_MD is not used in case of DSI, reading will get some default value |
706 | |
374 | * set dpll_md = 0 |
707 | if (IS_BROXTON(encoder->base.dev)) |
375 | */ |
708 | pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
376 | pipe_config->dpll_hw_state.dpll_md = 0; |
709 | else if (IS_VALLEYVIEW(encoder->base.dev)) |
377 | 710 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
|
378 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
711 | |
379 | if (!pclk) |
712 | if (!pclk) |
Line 380... | Line 713... | ||
380 | return; |
713 | return; |
Line 381... | Line 714... | ||
381 | 714 | ||
382 | pipe_config->adjusted_mode.crtc_clock = pclk; |
715 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
Line 401... | Line 734... | ||
401 | if (fixed_mode) { |
734 | if (fixed_mode) { |
402 | if (mode->hdisplay > fixed_mode->hdisplay) |
735 | if (mode->hdisplay > fixed_mode->hdisplay) |
403 | return MODE_PANEL; |
736 | return MODE_PANEL; |
404 | if (mode->vdisplay > fixed_mode->vdisplay) |
737 | if (mode->vdisplay > fixed_mode->vdisplay) |
405 | return MODE_PANEL; |
738 | return MODE_PANEL; |
- | 739 | if (fixed_mode->clock > max_dotclk) |
|
- | 740 | return MODE_CLOCK_HIGH; |
|
406 | } |
741 | } |
Line 407... | Line 742... | ||
407 | 742 | ||
408 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); |
743 | return MODE_OK; |
Line 409... | Line 744... | ||
409 | } |
744 | } |
410 | 745 | ||
411 | /* return txclkesc cycles in terms of divider and duration in us */ |
746 | /* return txclkesc cycles in terms of divider and duration in us */ |
Line 429... | Line 764... | ||
429 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
764 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
430 | 8 * 100), lane_count); |
765 | 8 * 100), lane_count); |
431 | } |
766 | } |
Line 432... | Line 767... | ||
432 | 767 | ||
433 | static void set_dsi_timings(struct drm_encoder *encoder, |
768 | static void set_dsi_timings(struct drm_encoder *encoder, |
434 | const struct drm_display_mode *mode) |
769 | const struct drm_display_mode *adjusted_mode) |
435 | { |
770 | { |
436 | struct drm_device *dev = encoder->dev; |
771 | struct drm_device *dev = encoder->dev; |
437 | struct drm_i915_private *dev_priv = dev->dev_private; |
772 | struct drm_i915_private *dev_priv = dev->dev_private; |
438 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
773 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
439 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
774 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
440 | int pipe = intel_crtc->pipe; |
775 | enum port port; |
441 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
776 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
Line 442... | Line 777... | ||
442 | unsigned int lane_count = intel_dsi->lane_count; |
777 | unsigned int lane_count = intel_dsi->lane_count; |
Line 443... | Line 778... | ||
443 | 778 | ||
444 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
779 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
445 | 780 | ||
446 | hactive = mode->hdisplay; |
781 | hactive = adjusted_mode->crtc_hdisplay; |
- | 782 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; |
|
- | 783 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
|
- | 784 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; |
|
- | 785 | ||
- | 786 | if (intel_dsi->dual_link) { |
|
- | 787 | hactive /= 2; |
|
- | 788 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
|
- | 789 | hactive += intel_dsi->pixel_overlap; |
|
- | 790 | hfp /= 2; |
|
447 | hfp = mode->hsync_start - mode->hdisplay; |
791 | hsync /= 2; |
448 | hsync = mode->hsync_end - mode->hsync_start; |
792 | hbp /= 2; |
449 | hbp = mode->htotal - mode->hsync_end; |
793 | } |
450 | 794 | ||
Line 451... | Line 795... | ||
451 | vfp = mode->vsync_start - mode->vdisplay; |
795 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
452 | vsync = mode->vsync_end - mode->vsync_start; |
796 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
453 | vbp = mode->vtotal - mode->vsync_end; |
797 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; |
454 | 798 | ||
455 | /* horizontal values are in terms of high speed byte clock */ |
799 | /* horizontal values are in terms of high speed byte clock */ |
456 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
800 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
457 | intel_dsi->burst_mode_ratio); |
801 | intel_dsi->burst_mode_ratio); |
Line -... | Line 802... | ||
- | 802 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
|
- | 803 | hsync = txbyteclkhs(hsync, bpp, lane_count, |
|
- | 804 | intel_dsi->burst_mode_ratio); |
|
- | 805 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
|
- | 806 | ||
- | 807 | for_each_dsi_port(port, intel_dsi->ports) { |
|
- | 808 | if (IS_BROXTON(dev)) { |
|
- | 809 | /* |
|
458 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
810 | * Program hdisplay and vdisplay on MIPI transcoder. |
- | 811 | * This is different from calculated hactive and |
|
- | 812 | * vactive, as they are calculated per channel basis, |
|
- | 813 | * whereas these values should be based on resolution. |
|
459 | hsync = txbyteclkhs(hsync, bpp, lane_count, |
814 | */ |
- | 815 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), |
|
- | 816 | adjusted_mode->crtc_hdisplay); |
|
Line -... | Line 817... | ||
- | 817 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
|
- | 818 | adjusted_mode->crtc_vdisplay); |
|
- | 819 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
|
460 | intel_dsi->burst_mode_ratio); |
820 | adjusted_mode->crtc_vtotal); |
461 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
821 | } |
462 | 822 | ||
463 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); |
823 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
Line 464... | Line 824... | ||
464 | I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); |
824 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); |
465 | 825 | ||
466 | /* meaningful for video mode non-burst sync pulse mode only, can be zero |
826 | /* meaningful for video mode non-burst sync pulse mode only, |
467 | * for non-burst sync events and burst modes */ |
827 | * can be zero for non-burst sync events and burst modes */ |
- | 828 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); |
|
468 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); |
829 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); |
Line 469... | Line 830... | ||
469 | I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); |
830 | |
470 | 831 | /* vertical values are in terms of lines */ |
|
471 | /* vertical values are in terms of lines */ |
832 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); |
472 | I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); |
833 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); |
473 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); |
834 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); |
474 | I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); |
835 | } |
475 | } |
836 | } |
476 | 837 | ||
477 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
- | |
478 | { |
838 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
479 | struct drm_encoder *encoder = &intel_encoder->base; |
839 | { |
480 | struct drm_device *dev = encoder->dev; |
840 | struct drm_encoder *encoder = &intel_encoder->base; |
- | 841 | struct drm_device *dev = encoder->dev; |
|
- | 842 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 843 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
|
Line -... | Line 844... | ||
- | 844 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
|
- | 845 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
|
- | 846 | enum port port; |
|
- | 847 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
|
- | 848 | u32 val, tmp; |
|
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
849 | u16 mode_hdisplay; |
- | 850 | ||
Line -... | Line 851... | ||
- | 851 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
|
- | 852 | ||
- | 853 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
|
482 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
854 | |
483 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
855 | if (intel_dsi->dual_link) { |
- | 856 | mode_hdisplay /= 2; |
|
484 | struct drm_display_mode *adjusted_mode = |
857 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
485 | &intel_crtc->config.adjusted_mode; |
858 | mode_hdisplay += intel_dsi->pixel_overlap; |
486 | int pipe = intel_crtc->pipe; |
859 | } |
- | 860 | ||
Line 487... | Line 861... | ||
487 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
861 | for_each_dsi_port(port, intel_dsi->ports) { |
488 | u32 val, tmp; |
862 | if (IS_VALLEYVIEW(dev)) { |
489 | 863 | /* |
|
490 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
864 | * escape clock divider, 20MHz, shared for A and C. |
- | 865 | * device ready must be off when doing this! txclkesc? |
|
- | 866 | */ |
|
- | 867 | tmp = I915_READ(MIPI_CTRL(PORT_A)); |
|
- | 868 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
|
- | 869 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | |
|
- | 870 | ESCAPE_CLOCK_DIVIDER_1); |
|
- | 871 | ||
- | 872 | /* read request priority is per pipe */ |
|
- | 873 | tmp = I915_READ(MIPI_CTRL(port)); |
|
- | 874 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
|
- | 875 | I915_WRITE(MIPI_CTRL(port), tmp | |
|
- | 876 | READ_REQUEST_PRIORITY_HIGH); |
|
- | 877 | } else if (IS_BROXTON(dev)) { |
|
- | 878 | /* |
|
- | 879 | * FIXME: |
|
- | 880 | * BXT can connect any PIPE to any MIPI port. |
|
- | 881 | * Select the pipe based on the MIPI port read from |
|
- | 882 | * VBT for now. Pick PIPE A for MIPI port A and C |
|
- | 883 | * for port C. |
|
Line 491... | Line 884... | ||
491 | 884 | */ |
|
492 | /* escape clock divider, 20MHz, shared for A and C. device ready must be |
885 | tmp = I915_READ(MIPI_CTRL(port)); |
493 | * off when doing this! txclkesc? */ |
886 | tmp &= ~BXT_PIPE_SELECT_MASK; |
Line 494... | Line 887... | ||
494 | tmp = I915_READ(MIPI_CTRL(0)); |
887 | |
Line 495... | Line 888... | ||
495 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
888 | if (port == PORT_A) |
496 | I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); |
889 | tmp |= BXT_PIPE_SELECT_A; |
497 | 890 | else if (port == PORT_C) |
|
- | 891 | tmp |= BXT_PIPE_SELECT_C; |
|
Line 498... | Line 892... | ||
498 | /* read request priority is per pipe */ |
892 | |
Line 499... | Line 893... | ||
499 | tmp = I915_READ(MIPI_CTRL(pipe)); |
893 | I915_WRITE(MIPI_CTRL(port), tmp); |
500 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
894 | } |
Line 520... | Line 914... | ||
520 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
914 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
Line 521... | Line 915... | ||
521 | 915 | ||
522 | /* XXX: cross-check bpp vs. pixel format? */ |
916 | /* XXX: cross-check bpp vs. pixel format? */ |
523 | val |= intel_dsi->pixel_format; |
917 | val |= intel_dsi->pixel_format; |
524 | } |
- | |
Line -... | Line 918... | ||
- | 918 | } |
|
- | 919 | ||
- | 920 | tmp = 0; |
|
- | 921 | if (intel_dsi->eotp_pkt == 0) |
|
- | 922 | tmp |= EOT_DISABLE; |
|
- | 923 | if (intel_dsi->clock_stop) |
|
- | 924 | tmp |= CLOCKSTOP; |
|
- | 925 | ||
- | 926 | for_each_dsi_port(port, intel_dsi->ports) { |
|
525 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); |
927 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); |
526 | 928 | ||
Line 527... | Line 929... | ||
527 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and |
929 | /* timeouts for recovery. one frame IIUC. if counter expires, |
528 | * stop state. */ |
930 | * EOT and stop state. */ |
529 | 931 | ||
530 | /* |
932 | /* |
531 | * In burst mode, value greater than one DPI line Time in byte clock |
933 | * In burst mode, value greater than one DPI line Time in byte |
532 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is |
934 | * clock (txbyteclkhs) To timeout this timer 1+ of the above |
533 | * recommended. |
935 | * said value is recommended. |
534 | * |
936 | * |
535 | * In non-burst mode, Value greater than one DPI frame time in byte |
937 | * In non-burst mode, Value greater than one DPI frame time in |
536 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
938 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
537 | * is recommended. |
939 | * said value is recommended. |
538 | * |
940 | * |
539 | * In DBI only mode, value greater than one DBI frame time in byte |
941 | * In DBI only mode, value greater than one DBI frame time in |
Line 540... | Line 942... | ||
540 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
942 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
541 | * is recommended. |
943 | * said value is recommended. |
542 | */ |
944 | */ |
543 | 945 | ||
544 | if (is_vid_mode(intel_dsi) && |
946 | if (is_vid_mode(intel_dsi) && |
545 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
947 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
546 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
948 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
547 | txbyteclkhs(adjusted_mode->htotal, bpp, |
949 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
548 | intel_dsi->lane_count, |
950 | intel_dsi->lane_count, |
549 | intel_dsi->burst_mode_ratio) + 1); |
951 | intel_dsi->burst_mode_ratio) + 1); |
550 | } else { |
952 | } else { |
551 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
953 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
552 | txbyteclkhs(adjusted_mode->vtotal * |
954 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
553 | adjusted_mode->htotal, |
955 | adjusted_mode->crtc_htotal, |
554 | bpp, intel_dsi->lane_count, |
956 | bpp, intel_dsi->lane_count, |
- | 957 | intel_dsi->burst_mode_ratio) + 1); |
|
555 | intel_dsi->burst_mode_ratio) + 1); |
958 | } |
- | 959 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); |
|
Line 556... | Line 960... | ||
556 | } |
960 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), |
Line 557... | Line 961... | ||
557 | I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); |
961 | intel_dsi->turn_arnd_val); |
- | 962 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), |
|
558 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); |
963 | intel_dsi->rst_timer_val); |
Line -... | Line 964... | ||
- | 964 | ||
559 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); |
965 | /* dphy stuff */ |
- | 966 | ||
560 | 967 | /* in terms of low power clock */ |
|
- | 968 | I915_WRITE(MIPI_INIT_COUNT(port), |
|
561 | /* dphy stuff */ |
969 | txclkesc(intel_dsi->escape_clk_div, 100)); |
562 | 970 | ||
- | 971 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
|
- | 972 | /* |
|
563 | /* in terms of low power clock */ |
973 | * BXT spec says write MIPI_INIT_COUNT for |
564 | I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); |
974 | * both the ports, even if only one is |
Line 565... | Line 975... | ||
565 | 975 | * getting used. So write the other port |
|
566 | val = 0; |
976 | * if not in dual link mode. |
Line 567... | Line 977... | ||
567 | if (intel_dsi->eotp_pkt == 0) |
977 | */ |
568 | val |= EOT_DISABLE; |
978 | I915_WRITE(MIPI_INIT_COUNT(port == |
Line 569... | Line 979... | ||
569 | 979 | PORT_A ? PORT_C : PORT_A), |
|
570 | if (intel_dsi->clock_stop) |
980 | intel_dsi->init_count); |
571 | val |= CLOCKSTOP; |
981 | } |
572 | 982 | ||
573 | /* recovery disables */ |
983 | /* recovery disables */ |
574 | I915_WRITE(MIPI_EOT_DISABLE(pipe), val); |
984 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
575 | 985 | ||
Line 576... | Line 986... | ||
576 | /* in terms of low power clock */ |
986 | /* in terms of low power clock */ |
577 | I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); |
987 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); |
- | 988 | ||
578 | 989 | /* in terms of txbyteclkhs. actual high to low switch + |
|
579 | /* in terms of txbyteclkhs. actual high to low switch + |
990 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
580 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
991 | * |
581 | * |
992 | * XXX: write MIPI_STOP_STATE_STALL? |
582 | * XXX: write MIPI_STOP_STATE_STALL? |
993 | */ |
583 | */ |
994 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), |
584 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), |
995 | intel_dsi->hs_to_lp_count); |
585 | intel_dsi->hs_to_lp_count); |
996 | |
586 | 997 | /* XXX: low power clock equivalence in terms of byte clock. |
|
587 | /* XXX: low power clock equivalence in terms of byte clock. the number |
998 | * the number of byte clocks occupied in one low power clock. |
588 | * of byte clocks occupied in one low power clock. based on txbyteclkhs |
999 | * based on txbyteclkhs and txclkesc. |
Line 589... | Line 1000... | ||
589 | * and txclkesc. txclkesc time / txbyteclk time * (105 + |
1000 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL |
590 | * MIPI_STOP_STATE_STALL) / 105.??? |
1001 | * ) / 105.??? |
591 | */ |
1002 | */ |
Line 592... | Line 1003... | ||
592 | I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); |
1003 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); |
593 | 1004 | ||
594 | /* the bw essential for transmitting 16 long packets containing 252 |
1005 | /* the bw essential for transmitting 16 long packets containing |
595 | * bytes meant for dcs write memory command is programmed in this |
1006 | * 252 bytes meant for dcs write memory command is programmed in |
596 | * register in terms of byte clocks. based on dsi transfer rate and the |
1007 | * this register in terms of byte clocks. based on dsi transfer |
597 | * number of lanes configured the time taken to transmit 16 long packets |
1008 | * rate and the number of lanes configured the time taken to |
598 | * in a dsi stream varies. */ |
1009 | * transmit 16 long packets in a dsi stream varies. */ |
599 | I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); |
1010 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); |
600 | 1011 | ||
601 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), |
1012 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), |
- | 1013 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
|
Line 602... | Line 1014... | ||
602 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
1014 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
603 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
1015 | |
604 | 1016 | if (is_vid_mode(intel_dsi)) |
|
Line 605... | Line 1017... | ||
605 | if (is_vid_mode(intel_dsi)) |
1017 | /* Some panels might have resolution which is not a |
- | 1018 | * multiple of 64 like 1366 x 768. Enable RANDOM |
|
Line 606... | Line -... | ||
606 | /* Some panels might have resolution which is not a multiple of |
- | |
607 | * 64 like 1366 x 768. Enable RANDOM resolution support for such |
1019 | * resolution support for such panels by default */ |
Line 608... | Line 1020... | ||
608 | * panels by default */ |
1020 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), |
609 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), |
1021 | intel_dsi->video_frmt_cfg_bits | |
610 | intel_dsi->video_frmt_cfg_bits | |
1022 | intel_dsi->video_mode_format | |
611 | intel_dsi->video_mode_format | |
- | |
612 | IP_TG_CONFIG | |
- | |
613 | RANDOM_DPI_DISPLAY_RESOLUTION); |
- | |
614 | } |
- | |
615 | - | ||
616 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
- | |
617 | { |
- | |
618 | DRM_DEBUG_KMS("\n"); |
- | |
619 | - | ||
620 | intel_dsi_prepare(encoder); |
- | |
621 | - | ||
622 | vlv_enable_dsi_pll(encoder); |
- | |
623 | } |
- | |
624 | 1023 | IP_TG_CONFIG | |
|
625 | static enum drm_connector_status |
1024 | RANDOM_DPI_DISPLAY_RESOLUTION); |
Line 626... | Line 1025... | ||
626 | intel_dsi_detect(struct drm_connector *connector, bool force) |
1025 | } |
627 | { |
1026 | } |
628 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
1027 | |
Line 662... | Line 1061... | ||
662 | 1061 | ||
663 | drm_mode_probed_add(connector, mode); |
1062 | drm_mode_probed_add(connector, mode); |
664 | return 1; |
1063 | return 1; |
Line 665... | Line 1064... | ||
665 | } |
1064 | } |
666 | 1065 | ||
667 | static void intel_dsi_destroy(struct drm_connector *connector) |
1066 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
Line 668... | Line 1067... | ||
668 | { |
1067 | { |
669 | struct intel_connector *intel_connector = to_intel_connector(connector); |
1068 | struct intel_connector *intel_connector = to_intel_connector(connector); |
670 | 1069 | ||
671 | DRM_DEBUG_KMS("\n"); |
1070 | DRM_DEBUG_KMS("\n"); |
672 | intel_panel_fini(&intel_connector->panel); |
1071 | intel_panel_fini(&intel_connector->panel); |
Line -... | Line 1072... | ||
- | 1072 | drm_connector_cleanup(connector); |
|
- | 1073 | kfree(connector); |
|
- | 1074 | } |
|
- | 1075 | ||
- | 1076 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
|
- | 1077 | { |
|
- | 1078 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
|
- | 1079 | ||
- | 1080 | if (intel_dsi->panel) { |
|
- | 1081 | drm_panel_detach(intel_dsi->panel); |
|
- | 1082 | /* XXX: Logically this call belongs in the panel driver. */ |
|
- | 1083 | drm_panel_remove(intel_dsi->panel); |
|
- | 1084 | } |
|
- | 1085 | ||
- | 1086 | /* dispose of the gpios */ |
|
- | 1087 | if (intel_dsi->gpio_panel) |
|
- | 1088 | gpiod_put(intel_dsi->gpio_panel); |
|
673 | drm_connector_cleanup(connector); |
1089 | |
674 | kfree(connector); |
1090 | intel_encoder_destroy(encoder); |
675 | } |
1091 | } |
Line 676... | Line 1092... | ||
676 | 1092 | ||
677 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
1093 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
678 | .destroy = intel_encoder_destroy, |
1094 | .destroy = intel_dsi_encoder_destroy, |
679 | }; |
1095 | }; |
680 | 1096 | ||
Line 681... | Line 1097... | ||
681 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
1097 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
682 | .get_modes = intel_dsi_get_modes, |
1098 | .get_modes = intel_dsi_get_modes, |
683 | .mode_valid = intel_dsi_mode_valid, |
1099 | .mode_valid = intel_dsi_mode_valid, |
684 | .best_encoder = intel_best_encoder, |
1100 | .best_encoder = intel_best_encoder, |
685 | }; |
1101 | }; |
- | 1102 | ||
- | 1103 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
|
- | 1104 | .dpms = drm_atomic_helper_connector_dpms, |
|
686 | 1105 | .detect = intel_dsi_detect, |
|
Line 687... | Line 1106... | ||
687 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
1106 | .destroy = intel_dsi_connector_destroy, |
688 | .dpms = intel_connector_dpms, |
1107 | .fill_modes = drm_helper_probe_single_connector_modes, |
689 | .detect = intel_dsi_detect, |
1108 | .atomic_get_property = intel_connector_atomic_get_property, |
690 | .destroy = intel_dsi_destroy, |
1109 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
691 | .fill_modes = drm_helper_probe_single_connector_modes, |
1110 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
692 | }; |
1111 | }; |
693 | 1112 | ||
694 | void intel_dsi_init(struct drm_device *dev) |
1113 | void intel_dsi_init(struct drm_device *dev) |
695 | { |
1114 | { |
696 | struct intel_dsi *intel_dsi; |
1115 | struct intel_dsi *intel_dsi; |
697 | struct intel_encoder *intel_encoder; |
1116 | struct intel_encoder *intel_encoder; |
Line 698... | Line 1117... | ||
698 | struct drm_encoder *encoder; |
1117 | struct drm_encoder *encoder; |
Line 699... | Line 1118... | ||
699 | struct intel_connector *intel_connector; |
1118 | struct intel_connector *intel_connector; |
Line 718... | Line 1137... | ||
718 | 1137 | ||
719 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1138 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
720 | if (!intel_dsi) |
1139 | if (!intel_dsi) |
Line 721... | Line 1140... | ||
721 | return; |
1140 | return; |
722 | 1141 | ||
723 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
1142 | intel_connector = intel_connector_alloc(); |
724 | if (!intel_connector) { |
1143 | if (!intel_connector) { |
725 | kfree(intel_dsi); |
1144 | kfree(intel_dsi); |
Line 733... | Line 1152... | ||
733 | connector = &intel_connector->base; |
1152 | connector = &intel_connector->base; |
Line 734... | Line 1153... | ||
734 | 1153 | ||
Line 735... | Line 1154... | ||
735 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); |
1154 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); |
736 | - | ||
737 | /* XXX: very likely not all of these are needed */ |
1155 | |
738 | intel_encoder->hot_plug = intel_dsi_hot_plug; |
1156 | /* XXX: very likely not all of these are needed */ |
739 | intel_encoder->compute_config = intel_dsi_compute_config; |
1157 | intel_encoder->compute_config = intel_dsi_compute_config; |
740 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; |
1158 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; |
741 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
1159 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
Line 746... | Line 1164... | ||
746 | intel_encoder->get_config = intel_dsi_get_config; |
1164 | intel_encoder->get_config = intel_dsi_get_config; |
Line 747... | Line 1165... | ||
747 | 1165 | ||
748 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
1166 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Line -... | Line 1167... | ||
- | 1167 | intel_connector->unregister = intel_connector_unregister; |
|
- | 1168 | ||
- | 1169 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
|
- | 1170 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
|
- | 1171 | intel_encoder->crtc_mask = (1 << PIPE_A); |
|
- | 1172 | intel_dsi->ports = (1 << PORT_A); |
|
- | 1173 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { |
|
- | 1174 | intel_encoder->crtc_mask = (1 << PIPE_B); |
|
- | 1175 | intel_dsi->ports = (1 << PORT_C); |
|
- | 1176 | } |
|
- | 1177 | ||
- | 1178 | if (dev_priv->vbt.dsi.config->dual_link) |
|
- | 1179 | intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); |
|
749 | intel_connector->unregister = intel_connector_unregister; |
1180 | |
750 | 1181 | /* Create a DSI host (and a device) for each port. */ |
|
- | 1182 | for_each_dsi_port(port, intel_dsi->ports) { |
|
751 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
1183 | struct intel_dsi_host *host; |
- | 1184 | ||
- | 1185 | host = intel_dsi_host_init(intel_dsi, port); |
|
Line -... | Line 1186... | ||
- | 1186 | if (!host) |
|
- | 1187 | goto err; |
|
- | 1188 | ||
- | 1189 | intel_dsi->dsi_hosts[port] = host; |
|
- | 1190 | } |
|
- | 1191 | ||
752 | dsi = &intel_dsi_devices[i]; |
1192 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
753 | intel_dsi->dev = *dsi; |
1193 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, |
754 | 1194 | intel_dsi_drivers[i].panel_id); |
|
Line 755... | Line 1195... | ||
755 | if (dsi->dev_ops->init(&intel_dsi->dev)) |
1195 | if (intel_dsi->panel) |
756 | break; |
1196 | break; |
757 | } |
1197 | } |
758 | 1198 | ||
Line -... | Line 1199... | ||
- | 1199 | if (!intel_dsi->panel) { |
|
- | 1200 | DRM_DEBUG_KMS("no device found\n"); |
|
- | 1201 | goto err; |
|
- | 1202 | } |
|
- | 1203 | ||
- | 1204 | /* |
|
759 | if (i == ARRAY_SIZE(intel_dsi_devices)) { |
1205 | * In case of BYT with CRC PMIC, we need to use GPIO for |
- | 1206 | * Panel control. |
|
- | 1207 | */ |
|
- | 1208 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { |
|
760 | DRM_DEBUG_KMS("no device found\n"); |
1209 | intel_dsi->gpio_panel = |
- | 1210 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); |
|
- | 1211 | ||
Line -... | Line 1212... | ||
- | 1212 | if (IS_ERR(intel_dsi->gpio_panel)) { |
|
761 | goto err; |
1213 | DRM_ERROR("Failed to own gpio for panel control\n"); |
762 | } |
1214 | intel_dsi->gpio_panel = NULL; |
763 | 1215 | } |
|
Line 764... | Line 1216... | ||
764 | intel_encoder->type = INTEL_OUTPUT_DSI; |
1216 | } |
Line 776... | Line 1228... | ||
776 | 1228 | ||
Line 777... | Line 1229... | ||
777 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
1229 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Line -... | Line 1230... | ||
- | 1230 | ||
- | 1231 | drm_connector_register(connector); |
|
- | 1232 | ||
778 | 1233 | drm_panel_attach(intel_dsi->panel, connector); |
|
- | 1234 | ||
- | 1235 | mutex_lock(&dev->mode_config.mutex); |
|
- | 1236 | drm_panel_get_modes(intel_dsi->panel); |
|
- | 1237 | list_for_each_entry(scan, &connector->probed_modes, head) { |
|
- | 1238 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
|
- | 1239 | fixed_mode = drm_mode_duplicate(dev, scan); |
|
- | 1240 | break; |
|
- | 1241 | } |
|
779 | drm_connector_register(connector); |
1242 | } |
780 | 1243 | mutex_unlock(&dev->mode_config.mutex); |
|
781 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); |
1244 | |
782 | if (!fixed_mode) { |
1245 | if (!fixed_mode) { |
Line 783... | Line -... | ||
783 | DRM_DEBUG_KMS("no fixed mode\n"); |
- | |
784 | goto err; |
1246 | DRM_DEBUG_KMS("no fixed mode\n"); |
- | 1247 | goto err; |
|
Line 785... | Line 1248... | ||
785 | } |
1248 | } |
Line 786... | Line 1249... | ||
786 | 1249 | ||
787 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
1250 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |