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Rev 6937 Rev 7144
Line 83... Line 83...
83
 
83
 
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static bool
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static bool
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intel_dp_reset_link_train(struct intel_dp *intel_dp,
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intel_dp_reset_link_train(struct intel_dp *intel_dp,
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			uint8_t dp_train_pat)
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			uint8_t dp_train_pat)
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{
-
 
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	if (!intel_dp->train_set_valid)
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{
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		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
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	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
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	intel_dp_set_signal_levels(intel_dp);
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	intel_dp_set_signal_levels(intel_dp);
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	return intel_dp_set_link_train(intel_dp, dp_train_pat);
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	return intel_dp_set_link_train(intel_dp, dp_train_pat);
Line 159... Line 158...
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		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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			DRM_DEBUG_KMS("clock recovery OK\n");
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			DRM_DEBUG_KMS("clock recovery OK\n");
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			break;
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			break;
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		}
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		}
Line 163... Line -...
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-
 
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		/*
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		 * if we used previously trained voltage and pre-emphasis values
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		 * and we don't get clock recovery, reset link training values
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		 */
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		if (intel_dp->train_set_valid) {
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			DRM_DEBUG_KMS("clock recovery not ok, reset");
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			/* clear the flag as we are not reusing train set */
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			intel_dp->train_set_valid = false;
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			if (!intel_dp_reset_link_train(intel_dp,
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						       DP_TRAINING_PATTERN_1 |
-
 
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						       DP_LINK_SCRAMBLING_DISABLE)) {
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				DRM_ERROR("failed to enable link training\n");
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				return;
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			}
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			continue;
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Line 179... Line 162...
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		}
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180
 
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		/* Check to see if we've tried the max voltage */
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		/* Check to see if we've tried the max voltage */
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		for (i = 0; i < intel_dp->lane_count; i++)
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		for (i = 0; i < intel_dp->lane_count; i++)
Line 282... Line 265...
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		}
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		}
Line 283... Line 266...
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266
 
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		/* Make sure clock is still ok */
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		/* Make sure clock is still ok */
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		if (!drm_dp_clock_recovery_ok(link_status,
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		if (!drm_dp_clock_recovery_ok(link_status,
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					      intel_dp->lane_count)) {
-
 
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			intel_dp->train_set_valid = false;
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					      intel_dp->lane_count)) {
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			intel_dp_link_training_clock_recovery(intel_dp);
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			intel_dp_link_training_clock_recovery(intel_dp);
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			intel_dp_set_link_train(intel_dp,
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			intel_dp_set_link_train(intel_dp,
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						training_pattern |
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						training_pattern |
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						DP_LINK_SCRAMBLING_DISABLE);
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						DP_LINK_SCRAMBLING_DISABLE);
Line 299... Line 281...
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			break;
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			break;
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		}
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		}
Line 301... Line 283...
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283
 
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		/* Try 5 times, then try clock recovery if that fails */
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		/* Try 5 times, then try clock recovery if that fails */
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		if (tries > 5) {
-
 
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			intel_dp->train_set_valid = false;
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		if (tries > 5) {
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			intel_dp_link_training_clock_recovery(intel_dp);
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			intel_dp_link_training_clock_recovery(intel_dp);
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			intel_dp_set_link_train(intel_dp,
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			intel_dp_set_link_train(intel_dp,
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						training_pattern |
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						training_pattern |
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						DP_LINK_SCRAMBLING_DISABLE);
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						DP_LINK_SCRAMBLING_DISABLE);
Line 320... Line 301...
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		++tries;
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		++tries;
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	}
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	}
Line 322... Line 303...
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303
 
Line 323... Line 304...
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	intel_dp_set_idle_link_train(intel_dp);
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	intel_dp_set_idle_link_train(intel_dp);
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-
 
325
	if (channel_eq) {
305
 
326
		intel_dp->train_set_valid = true;
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	if (channel_eq)
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		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
-
 
Line 328... Line 307...
328
	}
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		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
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}
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}
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309
 
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void intel_dp_stop_link_train(struct intel_dp *intel_dp)
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void intel_dp_stop_link_train(struct intel_dp *intel_dp)