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Line 154... Line 154...
154
}
154
}
Line 155... Line 155...
155
 
155
 
156
static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
156
static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
157
{
157
{
158
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-
 
159
	struct drm_device *dev = intel_dig_port->base.base.dev;
158
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Line 160... Line -...
160
	u8 source_max, sink_max;
-
 
161
 
159
	u8 source_max, sink_max;
162
	source_max = 4;
-
 
163
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
-
 
164
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
-
 
165
		source_max = 2;
160
 
Line 166... Line 161...
166
 
161
	source_max = intel_dig_port->max_lanes;
167
	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
162
	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
Line 205... Line 200...
205
	struct intel_dp *intel_dp = intel_attached_dp(connector);
200
	struct intel_dp *intel_dp = intel_attached_dp(connector);
206
	struct intel_connector *intel_connector = to_intel_connector(connector);
201
	struct intel_connector *intel_connector = to_intel_connector(connector);
207
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
202
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
208
	int target_clock = mode->clock;
203
	int target_clock = mode->clock;
209
	int max_rate, mode_rate, max_lanes, max_link_clock;
204
	int max_rate, mode_rate, max_lanes, max_link_clock;
-
 
205
	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
Line 210... Line 206...
210
 
206
 
211
	if (is_edp(intel_dp) && fixed_mode) {
207
	if (is_edp(intel_dp) && fixed_mode) {
212
		if (mode->hdisplay > fixed_mode->hdisplay)
208
		if (mode->hdisplay > fixed_mode->hdisplay)
Line 222... Line 218...
222
	max_lanes = intel_dp_max_lane_count(intel_dp);
218
	max_lanes = intel_dp_max_lane_count(intel_dp);
Line 223... Line 219...
223
 
219
 
224
	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
220
	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
Line 225... Line 221...
225
	mode_rate = intel_dp_link_required(target_clock, 18);
221
	mode_rate = intel_dp_link_required(target_clock, 18);
226
 
222
 
Line 227... Line 223...
227
	if (mode_rate > max_rate)
223
	if (mode_rate > max_rate || target_clock > max_dotclk)
228
		return MODE_CLOCK_HIGH;
224
		return MODE_CLOCK_HIGH;
Line 337... Line 333...
337
	 */
333
	 */
338
	if (!pll_enabled) {
334
	if (!pll_enabled) {
339
		release_cl_override = IS_CHERRYVIEW(dev) &&
335
		release_cl_override = IS_CHERRYVIEW(dev) &&
340
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);
336
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);
Line 341... Line 337...
341
 
337
 
342
		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
338
		if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
-
 
339
				     &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
-
 
340
			DRM_ERROR("Failed to force on pll for pipe %c!\n",
-
 
341
				  pipe_name(pipe));
-
 
342
			return;
343
				 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
343
		}
Line 344... Line 344...
344
	}
344
	}
345
 
345
 
346
	/*
346
	/*
Line 977... Line 977...
977
		rxsize = 2; /* 0 or 1 data bytes */
977
		rxsize = 2; /* 0 or 1 data bytes */
Line 978... Line 978...
978
 
978
 
979
		if (WARN_ON(txsize > 20))
979
		if (WARN_ON(txsize > 20))
Line -... Line 980...
-
 
980
			return -E2BIG;
980
			return -E2BIG;
981
 
-
 
982
		if (msg->buffer)
-
 
983
			memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
Line 981... Line 984...
981
 
984
		else
982
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
985
			WARN_ON(msg->size);
983
 
986
 
Line 1186... Line 1189...
1186
}
1189
}
Line 1187... Line 1190...
1187
 
1190
 
1188
static int
1191
static int
1189
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1192
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1190
{
-
 
1191
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1193
{
1192
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1194
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1193
	enum port port = intel_dig_port->port;
1195
	enum port port = intel_dig_port->port;
Line 1194... Line 1196...
1194
	int ret;
1196
	int ret;
Line 1195... Line 1197...
1195
 
1197
 
1196
	intel_aux_reg_init(intel_dp);
1198
	intel_aux_reg_init(intel_dp);
1197
 
1199
 
Line 1198... Line 1200...
1198
	intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1200
	intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1199
	if (!intel_dp->aux.name)
1201
	if (!intel_dp->aux.name)
Line 1200... Line -...
1200
		return -ENOMEM;
-
 
1201
 
-
 
1202
	intel_dp->aux.dev = dev->dev;
-
 
1203
	intel_dp->aux.transfer = intel_dp_aux_transfer;
-
 
1204
 
1202
		return -ENOMEM;
1205
	DRM_DEBUG_KMS("registering %s bus for %s\n",
1203
 
1206
		      intel_dp->aux.name,
1204
	intel_dp->aux.dev = connector->base.kdev;
1207
		      connector->base.kdev->kobj.name);
1205
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1208
 
1206
 
1209
	ret = drm_dp_aux_register(&intel_dp->aux);
1207
	ret = drm_dp_aux_register(&intel_dp->aux);
1210
	if (ret < 0) {
1208
	if (ret < 0) {
Line 1211... Line -...
1211
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
-
 
1212
			  intel_dp->aux.name, ret);
-
 
1213
		kfree(intel_dp->aux.name);
-
 
1214
		return ret;
-
 
1215
	}
-
 
1216
 
-
 
1217
	ret = sysfs_create_link(&connector->base.kdev->kobj,
-
 
1218
				&intel_dp->aux.ddc.dev.kobj,
-
 
1219
				intel_dp->aux.ddc.dev.kobj.name);
-
 
1220
	if (ret < 0) {
-
 
1221
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
1209
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1222
			  intel_dp->aux.name, ret);
1210
			  intel_dp->aux.name, ret);
Line 1223... Line 1211...
1223
		intel_dp_aux_fini(intel_dp);
1211
		kfree(intel_dp->aux.name);
1224
		return ret;
1212
		return ret;
1225
	}
1213
	}
1226
 
1214
 
Line 1227... Line -...
1227
	return 0;
-
 
1228
}
-
 
1229
 
1215
	return 0;
1230
static void
1216
}
1231
intel_dp_connector_unregister(struct intel_connector *intel_connector)
1217
 
Line 1232... Line 1218...
1232
{
1218
static void
1233
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1219
intel_dp_connector_unregister(struct intel_connector *intel_connector)
Line 1809... Line 1795...
1809
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1795
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1810
}
1796
}
Line 1811... Line 1797...
1811
 
1797
 
1812
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1798
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
-
 
1799
{
-
 
1800
	ktime_t panel_power_on_time;
-
 
1801
	s64 panel_power_off_duration;
1813
{
1802
 
Line -... Line 1803...
-
 
1803
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
-
 
1804
 
-
 
1805
	/* take the difference of currrent time and panel power off time
-
 
1806
	 * and then make panel wait for t11_t12 if needed. */
-
 
1807
	panel_power_on_time = ktime_get();
1814
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1808
	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1815
 
1809
 
-
 
1810
	/* When we disable the VDD override bit last we have to do the manual
1816
	/* When we disable the VDD override bit last we have to do the manual
1811
	 * wait. */
1817
	 * wait. */
1812
	if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
Line 1818... Line 1813...
1818
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1813
		wait_remaining_ms_from_jiffies(jiffies,
1819
				       intel_dp->panel_power_cycle_delay);
1814
				       intel_dp->panel_power_cycle_delay - panel_power_off_duration);
Line 1820... Line 1815...
1820
 
1815
 
Line 1872... Line 1867...
1872
	lockdep_assert_held(&dev_priv->pps_mutex);
1867
	lockdep_assert_held(&dev_priv->pps_mutex);
Line 1873... Line 1868...
1873
 
1868
 
1874
	if (!is_edp(intel_dp))
1869
	if (!is_edp(intel_dp))
Line 1875... Line 1870...
1875
		return false;
1870
		return false;
1876
 
1871
 
Line 1877... Line 1872...
1877
//	cancel_delayed_work(&intel_dp->panel_vdd_work);
1872
	cancel_delayed_work(&intel_dp->panel_vdd_work);
1878
	intel_dp->want_panel_vdd = true;
1873
	intel_dp->want_panel_vdd = true;
Line 1966... Line 1961...
1966
	/* Make sure sequencer is idle before allowing subsequent activity */
1961
	/* Make sure sequencer is idle before allowing subsequent activity */
1967
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1962
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1968
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1963
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Line 1969... Line 1964...
1969
 
1964
 
1970
	if ((pp & POWER_TARGET_ON) == 0)
1965
	if ((pp & POWER_TARGET_ON) == 0)
Line 1971... Line 1966...
1971
		intel_dp->last_power_cycle = jiffies;
1966
		intel_dp->panel_power_off_time = ktime_get();
1972
 
1967
 
1973
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
1968
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
Line 2115... Line 2110...
2115
	intel_dp->want_panel_vdd = false;
2110
	intel_dp->want_panel_vdd = false;
Line 2116... Line 2111...
2116
 
2111
 
2117
	I915_WRITE(pp_ctrl_reg, pp);
2112
	I915_WRITE(pp_ctrl_reg, pp);
Line 2118... Line 2113...
2118
	POSTING_READ(pp_ctrl_reg);
2113
	POSTING_READ(pp_ctrl_reg);
2119
 
2114
 
Line 2120... Line 2115...
2120
	intel_dp->last_power_cycle = jiffies;
2115
	intel_dp->panel_power_off_time = ktime_get();
2121
	wait_panel_off(intel_dp);
2116
	wait_panel_off(intel_dp);
2122
 
2117
 
Line 2240... Line 2235...
2240
		_intel_edp_backlight_on(intel_dp);
2235
		_intel_edp_backlight_on(intel_dp);
2241
	else
2236
	else
2242
		_intel_edp_backlight_off(intel_dp);
2237
		_intel_edp_backlight_off(intel_dp);
2243
}
2238
}
Line 2244... Line -...
2244
 
-
 
2245
static const char *state_string(bool enabled)
-
 
2246
{
-
 
2247
	return enabled ? "on" : "off";
-
 
2248
}
-
 
2249
 
2239
 
2250
static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2240
static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2251
{
2241
{
2252
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2242
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2253
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2243
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
Line 2254... Line 2244...
2254
	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2244
	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2255
 
2245
 
2256
	I915_STATE_WARN(cur_state != state,
2246
	I915_STATE_WARN(cur_state != state,
2257
			"DP port %c state assertion failure (expected %s, current %s)\n",
2247
			"DP port %c state assertion failure (expected %s, current %s)\n",
2258
			port_name(dig_port->port),
2248
			port_name(dig_port->port),
2259
			state_string(state), state_string(cur_state));
2249
			onoff(state), onoff(cur_state));
Line 2260... Line 2250...
2260
}
2250
}
2261
#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2251
#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2262
 
2252
 
Line 2263... Line 2253...
2263
static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2253
static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2264
{
2254
{
2265
	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2255
	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2266
 
2256
 
2267
	I915_STATE_WARN(cur_state != state,
2257
	I915_STATE_WARN(cur_state != state,
2268
			"eDP PLL state assertion failure (expected %s, current %s)\n",
2258
			"eDP PLL state assertion failure (expected %s, current %s)\n",
Line 2269... Line 2259...
2269
			state_string(state), state_string(cur_state));
2259
			onoff(state), onoff(cur_state));
Line 4021... Line 4011...
4021
		}
4011
		}
4022
		count = buf & DP_TEST_COUNT_MASK;
4012
		count = buf & DP_TEST_COUNT_MASK;
4023
	} while (--attempts && count);
4013
	} while (--attempts && count);
Line 4024... Line 4014...
4024
 
4014
 
4025
	if (attempts == 0) {
4015
	if (attempts == 0) {
4026
		DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
4016
		DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
4027
		ret = -ETIMEDOUT;
4017
		ret = -ETIMEDOUT;
Line 4028... Line 4018...
4028
	}
4018
	}
4029
 
4019
 
Line 4561... Line 4551...
4561
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4551
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4562
					 struct intel_digital_port *port)
4552
					 struct intel_digital_port *port)
4563
{
4553
{
4564
	if (HAS_PCH_IBX(dev_priv))
4554
	if (HAS_PCH_IBX(dev_priv))
4565
		return ibx_digital_port_connected(dev_priv, port);
4555
		return ibx_digital_port_connected(dev_priv, port);
4566
	if (HAS_PCH_SPLIT(dev_priv))
4556
	else if (HAS_PCH_SPLIT(dev_priv))
4567
		return cpt_digital_port_connected(dev_priv, port);
4557
		return cpt_digital_port_connected(dev_priv, port);
4568
	else if (IS_BROXTON(dev_priv))
4558
	else if (IS_BROXTON(dev_priv))
4569
		return bxt_digital_port_connected(dev_priv, port);
4559
		return bxt_digital_port_connected(dev_priv, port);
4570
	else if (IS_GM45(dev_priv))
4560
	else if (IS_GM45(dev_priv))
4571
		return gm45_digital_port_connected(dev_priv, port);
4561
		return gm45_digital_port_connected(dev_priv, port);
Line 4881... Line 4871...
4881
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4871
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4882
{
4872
{
4883
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4873
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4884
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4874
	struct intel_dp *intel_dp = &intel_dig_port->dp;
Line 4885... Line -...
4885
 
-
 
4886
	intel_dp_aux_fini(intel_dp);
4875
 
4887
	intel_dp_mst_encoder_cleanup(intel_dig_port);
4876
	intel_dp_mst_encoder_cleanup(intel_dig_port);
4888
	if (is_edp(intel_dp)) {
4877
	if (is_edp(intel_dp)) {
4889
//		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4878
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4890
		/*
4879
		/*
4891
		 * vdd might still be enabled do to the delayed vdd off.
4880
		 * vdd might still be enabled do to the delayed vdd off.
4892
		 * Make sure vdd is actually turned off here.
4881
		 * Make sure vdd is actually turned off here.
4893
		 */
4882
		 */
Line 4912... Line 4901...
4912
 
4901
 
4913
	/*
4902
	/*
4914
	 * vdd might still be enabled do to the delayed vdd off.
4903
	 * vdd might still be enabled do to the delayed vdd off.
4915
	 * Make sure vdd is actually turned off here.
4904
	 * Make sure vdd is actually turned off here.
4916
	 */
4905
	 */
4917
//	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4906
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4918
	pps_lock(intel_dp);
4907
	pps_lock(intel_dp);
4919
	edp_panel_vdd_off_sync(intel_dp);
4908
	edp_panel_vdd_off_sync(intel_dp);
4920
	pps_unlock(intel_dp);
4909
	pps_unlock(intel_dp);
Line 4945... Line 4934...
4945
	edp_panel_vdd_schedule_off(intel_dp);
4934
	edp_panel_vdd_schedule_off(intel_dp);
4946
}
4935
}
Line 4947... Line 4936...
4947
 
4936
 
4948
void intel_dp_encoder_reset(struct drm_encoder *encoder)
4937
void intel_dp_encoder_reset(struct drm_encoder *encoder)
-
 
4938
{
4949
{
4939
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
-
 
4940
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
 
4941
 
-
 
4942
	if (!HAS_DDI(dev_priv))
Line 4950... Line 4943...
4950
	struct intel_dp *intel_dp;
4943
		intel_dp->DP = I915_READ(intel_dp->output_reg);
4951
 
4944
 
Line 4952... Line -...
4952
	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
-
 
4953
		return;
-
 
4954
 
4945
	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
Line 4955... Line 4946...
4955
	intel_dp = enc_to_intel_dp(encoder);
4946
		return;
4956
 
4947
 
4957
	pps_lock(intel_dp);
4948
	pps_lock(intel_dp);
Line 5023... Line 5014...
5023
 
5014
 
5024
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
5015
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
Line 5025... Line 5016...
5025
	intel_display_power_get(dev_priv, power_domain);
5016
	intel_display_power_get(dev_priv, power_domain);
5026
 
-
 
5027
	if (long_hpd) {
-
 
5028
		/* indicate that we need to restart link training */
-
 
5029
		intel_dp->train_set_valid = false;
5017
 
5030
 
5018
	if (long_hpd) {
Line 5031... Line 5019...
5031
		if (!intel_digital_port_connected(dev_priv, intel_dig_port))
5019
		if (!intel_digital_port_connected(dev_priv, intel_dig_port))
5032
			goto mst_fail;
5020
			goto mst_fail;
Line 5128... Line 5116...
5128
	}
5116
	}
5129
}
5117
}
Line 5130... Line 5118...
5130
 
5118
 
5131
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5119
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5132
{
5120
{
5133
	intel_dp->last_power_cycle = jiffies;
5121
	intel_dp->panel_power_off_time = ktime_get();
5134
	intel_dp->last_power_on = jiffies;
5122
	intel_dp->last_power_on = jiffies;
5135
	intel_dp->last_backlight_off = jiffies;
5123
	intel_dp->last_backlight_off = jiffies;
Line 5136... Line 5124...
5136
}
5124
}
Line 5511... Line 5499...
5511
			fixed_mode->vrefresh);
5499
			fixed_mode->vrefresh);
Line 5512... Line 5500...
5512
 
5500
 
5513
	dev_priv->drrs.dp = NULL;
5501
	dev_priv->drrs.dp = NULL;
Line 5514... Line 5502...
5514
	mutex_unlock(&dev_priv->drrs.mutex);
5502
	mutex_unlock(&dev_priv->drrs.mutex);
5515
 
5503
 
Line 5516... Line 5504...
5516
//	cancel_delayed_work_sync(&dev_priv->drrs.work);
5504
	cancel_delayed_work_sync(&dev_priv->drrs.work);
5517
}
5505
}
5518
 
5506
 
Line 5564... Line 5552...
5564
	enum pipe pipe;
5552
	enum pipe pipe;
Line 5565... Line 5553...
5565
 
5553
 
5566
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5554
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
Line 5567... Line 5555...
5567
		return;
5555
		return;
Line 5568... Line 5556...
5568
 
5556
 
5569
//	cancel_delayed_work(&dev_priv->drrs.work);
5557
	cancel_delayed_work(&dev_priv->drrs.work);
5570
 
5558
 
5571
	mutex_lock(&dev_priv->drrs.mutex);
5559
	mutex_lock(&dev_priv->drrs.mutex);
Line 5609... Line 5597...
5609
	enum pipe pipe;
5597
	enum pipe pipe;
Line 5610... Line 5598...
5610
 
5598
 
5611
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5599
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
Line 5612... Line 5600...
5612
		return;
5600
		return;
Line 5613... Line 5601...
5613
 
5601
 
5614
//	cancel_delayed_work(&dev_priv->drrs.work);
5602
	cancel_delayed_work(&dev_priv->drrs.work);
5615
 
5603
 
5616
	mutex_lock(&dev_priv->drrs.mutex);
5604
	mutex_lock(&dev_priv->drrs.mutex);
Line 5845... Line 5833...
5845
	struct drm_device *dev = intel_encoder->base.dev;
5833
	struct drm_device *dev = intel_encoder->base.dev;
5846
	struct drm_i915_private *dev_priv = dev->dev_private;
5834
	struct drm_i915_private *dev_priv = dev->dev_private;
5847
	enum port port = intel_dig_port->port;
5835
	enum port port = intel_dig_port->port;
5848
	int type, ret;
5836
	int type, ret;
Line -... Line 5837...
-
 
5837
 
-
 
5838
	if (WARN(intel_dig_port->max_lanes < 1,
-
 
5839
		 "Not enough lanes (%d) for DP on port %c\n",
-
 
5840
		 intel_dig_port->max_lanes, port_name(port)))
-
 
5841
		return false;
5849
 
5842
 
Line 5850... Line 5843...
5850
	intel_dp->pps_pipe = INVALID_PIPE;
5843
	intel_dp->pps_pipe = INVALID_PIPE;
5851
 
5844
 
5852
	/* intel_dp vfuncs */
5845
	/* intel_dp vfuncs */
Line 5977... Line 5970...
5977
 
5970
 
Line 5978... Line 5971...
5978
	return true;
5971
	return true;
5979
 
5972
 
5980
fail:
5973
fail:
5981
	if (is_edp(intel_dp)) {
5974
	if (is_edp(intel_dp)) {
5982
//		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5975
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5983
		/*
5976
		/*
5984
		 * vdd might still be enabled do to the delayed vdd off.
5977
		 * vdd might still be enabled do to the delayed vdd off.
5985
		 * Make sure vdd is actually turned off here.
5978
		 * Make sure vdd is actually turned off here.
Line 6042... Line 6035...
6042
			intel_encoder->post_disable = ilk_post_disable_dp;
6035
			intel_encoder->post_disable = ilk_post_disable_dp;
6043
	}
6036
	}
Line 6044... Line 6037...
6044
 
6037
 
6045
	intel_dig_port->port = port;
6038
	intel_dig_port->port = port;
-
 
6039
	intel_dig_port->dp.output_reg = output_reg;
Line 6046... Line 6040...
6046
	intel_dig_port->dp.output_reg = output_reg;
6040
	intel_dig_port->max_lanes = 4;
6047
 
6041
 
6048
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6042
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6049
	if (IS_CHERRYVIEW(dev)) {
6043
	if (IS_CHERRYVIEW(dev)) {