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Line 26... | Line 26... | ||
26 | */ |
26 | */ |
Line 27... | Line 27... | ||
27 | 27 | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
- | 30 | #include |
|
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
Line 385... | Line 386... | ||
385 | 386 | ||
386 | /* |
387 | /* |
387 | * We don't have power sequencer currently. |
388 | * We don't have power sequencer currently. |
388 | * Pick one that's not used by other ports. |
389 | * Pick one that's not used by other ports. |
389 | */ |
390 | */ |
390 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
- | |
391 | base.head) { |
391 | for_each_intel_encoder(dev, encoder) { |
Line 392... | Line 392... | ||
392 | struct intel_dp *tmp; |
392 | struct intel_dp *tmp; |
393 | 393 | ||
Line 513... | Line 513... | ||
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
514 | { |
514 | { |
515 | struct drm_device *dev = dev_priv->dev; |
515 | struct drm_device *dev = dev_priv->dev; |
516 | struct intel_encoder *encoder; |
516 | struct intel_encoder *encoder; |
Line 517... | Line 517... | ||
517 | 517 | ||
518 | if (WARN_ON(!IS_VALLEYVIEW(dev))) |
518 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
Line 519... | Line 519... | ||
519 | return; |
519 | return; |
520 | 520 | ||
521 | /* |
521 | /* |
Line 526... | Line 526... | ||
526 | * reference get/put must be done while _not_ holding pps_mutex. |
526 | * reference get/put must be done while _not_ holding pps_mutex. |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
528 | * should use them always. |
528 | * should use them always. |
529 | */ |
529 | */ |
Line 530... | Line 530... | ||
530 | 530 | ||
531 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
531 | for_each_intel_encoder(dev, encoder) { |
Line 532... | Line 532... | ||
532 | struct intel_dp *intel_dp; |
532 | struct intel_dp *intel_dp; |
533 | 533 | ||
Line 534... | Line 534... | ||
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
535 | continue; |
535 | continue; |
536 | 536 | ||
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
Line -... | Line 538... | ||
- | 538 | intel_dp->pps_pipe = INVALID_PIPE; |
|
538 | intel_dp->pps_pipe = INVALID_PIPE; |
539 | } |
539 | } |
540 | } |
540 | } |
541 | |
Line 541... | Line 542... | ||
541 | 542 | static i915_reg_t |
|
542 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
543 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
Line 549... | Line 550... | ||
549 | return PCH_PP_CONTROL; |
550 | return PCH_PP_CONTROL; |
550 | else |
551 | else |
551 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
552 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
552 | } |
553 | } |
Line -... | Line 554... | ||
- | 554 | ||
553 | 555 | static i915_reg_t |
|
554 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
556 | _pp_stat_reg(struct intel_dp *intel_dp) |
555 | { |
557 | { |
Line 556... | Line 558... | ||
556 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
558 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
557 | 559 | ||
Line 577... | Line 579... | ||
577 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
579 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
578 | return 0; |
580 | return 0; |
Line 579... | Line 581... | ||
579 | 581 | ||
Line 580... | Line 582... | ||
580 | pps_lock(intel_dp); |
582 | pps_lock(intel_dp); |
581 | 583 | ||
582 | if (IS_VALLEYVIEW(dev)) { |
584 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
583 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
585 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
Line 584... | Line 586... | ||
584 | u32 pp_ctrl_reg, pp_div_reg; |
586 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
585 | u32 pp_div; |
587 | u32 pp_div; |
586 | 588 | ||
Line 606... | Line 608... | ||
606 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
608 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
607 | struct drm_i915_private *dev_priv = dev->dev_private; |
609 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 608... | Line 610... | ||
608 | 610 | ||
Line 609... | Line 611... | ||
609 | lockdep_assert_held(&dev_priv->pps_mutex); |
611 | lockdep_assert_held(&dev_priv->pps_mutex); |
610 | 612 | ||
611 | if (IS_VALLEYVIEW(dev) && |
613 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Line 612... | Line 614... | ||
612 | intel_dp->pps_pipe == INVALID_PIPE) |
614 | intel_dp->pps_pipe == INVALID_PIPE) |
613 | return false; |
615 | return false; |
Line 620... | Line 622... | ||
620 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
622 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
621 | struct drm_i915_private *dev_priv = dev->dev_private; |
623 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 622... | Line 624... | ||
622 | 624 | ||
Line 623... | Line 625... | ||
623 | lockdep_assert_held(&dev_priv->pps_mutex); |
625 | lockdep_assert_held(&dev_priv->pps_mutex); |
624 | 626 | ||
625 | if (IS_VALLEYVIEW(dev) && |
627 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Line 626... | Line 628... | ||
626 | intel_dp->pps_pipe == INVALID_PIPE) |
628 | intel_dp->pps_pipe == INVALID_PIPE) |
627 | return false; |
629 | return false; |
Line 650... | Line 652... | ||
650 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
652 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
651 | { |
653 | { |
652 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
654 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
653 | struct drm_device *dev = intel_dig_port->base.base.dev; |
655 | struct drm_device *dev = intel_dig_port->base.base.dev; |
654 | struct drm_i915_private *dev_priv = dev->dev_private; |
656 | struct drm_i915_private *dev_priv = dev->dev_private; |
655 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
657 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
656 | uint32_t status; |
658 | uint32_t status; |
657 | bool done; |
659 | bool done; |
Line 658... | Line 660... | ||
658 | 660 | ||
659 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
661 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Line 677... | Line 679... | ||
677 | 679 | ||
678 | /* |
680 | /* |
679 | * The clock divider is based off the hrawclk, and would like to run at |
681 | * The clock divider is based off the hrawclk, and would like to run at |
680 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
682 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
681 | */ |
683 | */ |
682 | return index ? 0 : intel_hrawclk(dev) / 2; |
684 | return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2); |
Line 683... | Line 685... | ||
683 | } |
685 | } |
684 | 686 | ||
685 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
687 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Line 690... | Line 692... | ||
690 | 692 | ||
691 | if (index) |
693 | if (index) |
Line 692... | Line 694... | ||
692 | return 0; |
694 | return 0; |
693 | 695 | ||
Line 694... | Line 696... | ||
694 | if (intel_dig_port->port == PORT_A) { |
696 | if (intel_dig_port->port == PORT_A) { |
695 | return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); |
697 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
696 | 698 | ||
697 | } else { |
699 | } else { |
Line 698... | Line 700... | ||
698 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
700 | return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
699 | } |
701 | } |
Line 707... | Line 709... | ||
707 | 709 | ||
708 | if (intel_dig_port->port == PORT_A) { |
710 | if (intel_dig_port->port == PORT_A) { |
709 | if (index) |
711 | if (index) |
710 | return 0; |
712 | return 0; |
711 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
713 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
712 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
714 | } else if (HAS_PCH_LPT_H(dev_priv)) { |
713 | /* Workaround for non-ULT HSW */ |
715 | /* Workaround for non-ULT HSW */ |
714 | switch (index) { |
716 | switch (index) { |
715 | case 0: return 63; |
717 | case 0: return 63; |
716 | case 1: return 72; |
718 | case 1: return 72; |
717 | default: return 0; |
719 | default: return 0; |
718 | } |
720 | } |
719 | } else { |
721 | } else { |
720 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
722 | return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
721 | } |
723 | } |
Line 722... | Line 724... | ||
722 | } |
724 | } |
723 | 725 | ||
Line 748... | Line 750... | ||
748 | if (IS_GEN6(dev)) |
750 | if (IS_GEN6(dev)) |
749 | precharge = 3; |
751 | precharge = 3; |
750 | else |
752 | else |
751 | precharge = 5; |
753 | precharge = 5; |
Line 752... | Line 754... | ||
752 | 754 | ||
753 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
755 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
754 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
755 | else |
757 | else |
Line 756... | Line 758... | ||
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
758 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
Line 787... | Line 789... | ||
787 | uint8_t *recv, int recv_size) |
789 | uint8_t *recv, int recv_size) |
788 | { |
790 | { |
789 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
791 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
790 | struct drm_device *dev = intel_dig_port->base.base.dev; |
792 | struct drm_device *dev = intel_dig_port->base.base.dev; |
791 | struct drm_i915_private *dev_priv = dev->dev_private; |
793 | struct drm_i915_private *dev_priv = dev->dev_private; |
792 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
794 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
793 | uint32_t ch_data = ch_ctl + 4; |
- | |
794 | uint32_t aux_clock_divider; |
795 | uint32_t aux_clock_divider; |
795 | int i, ret, recv_bytes; |
796 | int i, ret, recv_bytes; |
796 | uint32_t status; |
797 | uint32_t status; |
797 | int try, clock = 0; |
798 | int try, clock = 0; |
798 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
799 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
Line 851... | Line 852... | ||
851 | 852 | ||
852 | /* Must try at least 3 times according to DP spec */ |
853 | /* Must try at least 3 times according to DP spec */ |
853 | for (try = 0; try < 5; try++) { |
854 | for (try = 0; try < 5; try++) { |
854 | /* Load the send data into the aux channel data registers */ |
855 | /* Load the send data into the aux channel data registers */ |
855 | for (i = 0; i < send_bytes; i += 4) |
856 | for (i = 0; i < send_bytes; i += 4) |
856 | I915_WRITE(ch_data + i, |
857 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
857 | intel_dp_pack_aux(send + i, |
858 | intel_dp_pack_aux(send + i, |
Line 858... | Line 859... | ||
858 | send_bytes - i)); |
859 | send_bytes - i)); |
859 | 860 | ||
Line 911... | Line 912... | ||
911 | } |
912 | } |
Line 912... | Line 913... | ||
912 | 913 | ||
913 | /* Unload any bytes sent back from the other side */ |
914 | /* Unload any bytes sent back from the other side */ |
914 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
915 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
- | 916 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
|
- | 917 | ||
- | 918 | /* |
|
- | 919 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
|
- | 920 | * We have no idea of what happened so we return -EBUSY so |
|
- | 921 | * drm layer takes care for the necessary retries. |
|
- | 922 | */ |
|
- | 923 | if (recv_bytes == 0 || recv_bytes > 20) { |
|
- | 924 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
|
- | 925 | recv_bytes); |
|
- | 926 | /* |
|
- | 927 | * FIXME: This patch was created on top of a series that |
|
- | 928 | * organize the retries at drm level. There EBUSY should |
|
- | 929 | * also take care for 1ms wait before retrying. |
|
- | 930 | * That aux retries re-org is still needed and after that is |
|
- | 931 | * merged we remove this sleep from here. |
|
- | 932 | */ |
|
- | 933 | usleep_range(1000, 1500); |
|
- | 934 | ret = -EBUSY; |
|
- | 935 | goto out; |
|
- | 936 | } |
|
915 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
937 | |
916 | if (recv_bytes > recv_size) |
938 | if (recv_bytes > recv_size) |
Line 917... | Line 939... | ||
917 | recv_bytes = recv_size; |
939 | recv_bytes = recv_size; |
918 | 940 | ||
919 | for (i = 0; i < recv_bytes; i += 4) |
941 | for (i = 0; i < recv_bytes; i += 4) |