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Rev 5139 | Rev 5354 | ||
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Line 107... | Line 107... | ||
107 | { |
107 | { |
108 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
108 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
109 | } |
109 | } |
Line 110... | Line 110... | ||
110 | 110 | ||
111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
112 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); |
112 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
- | 113 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
|
- | 114 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
|
- | 115 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
|
Line 113... | Line 116... | ||
113 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
116 | enum pipe pipe); |
114 | 117 | ||
115 | int |
118 | int |
116 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
119 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Line 220... | Line 223... | ||
220 | return MODE_H_ILLEGAL; |
223 | return MODE_H_ILLEGAL; |
Line 221... | Line 224... | ||
221 | 224 | ||
222 | return MODE_OK; |
225 | return MODE_OK; |
Line 223... | Line -... | ||
223 | } |
- | |
224 | 226 | } |
|
225 | static uint32_t |
227 | |
226 | pack_aux(uint8_t *src, int src_bytes) |
228 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
227 | { |
229 | { |
Line 228... | Line 230... | ||
228 | int i; |
230 | int i; |
Line 233... | Line 235... | ||
233 | for (i = 0; i < src_bytes; i++) |
235 | for (i = 0; i < src_bytes; i++) |
234 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
236 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
235 | return v; |
237 | return v; |
236 | } |
238 | } |
Line 237... | Line -... | ||
237 | - | ||
238 | static void |
239 | |
239 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
240 | void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
240 | { |
241 | { |
241 | int i; |
242 | int i; |
242 | if (dst_bytes > 4) |
243 | if (dst_bytes > 4) |
243 | dst_bytes = 4; |
244 | dst_bytes = 4; |
Line 279... | Line 280... | ||
279 | } |
280 | } |
280 | } |
281 | } |
Line 281... | Line 282... | ||
281 | 282 | ||
282 | static void |
283 | static void |
283 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
284 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
284 | struct intel_dp *intel_dp, |
- | |
285 | struct edp_power_seq *out); |
285 | struct intel_dp *intel_dp); |
286 | static void |
286 | static void |
287 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
287 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
- | 288 | struct intel_dp *intel_dp); |
|
- | 289 | ||
- | 290 | static void pps_lock(struct intel_dp *intel_dp) |
|
- | 291 | { |
|
- | 292 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 293 | struct intel_encoder *encoder = &intel_dig_port->base; |
|
- | 294 | struct drm_device *dev = encoder->base.dev; |
|
- | 295 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 296 | enum intel_display_power_domain power_domain; |
|
- | 297 | ||
- | 298 | /* |
|
- | 299 | * See vlv_power_sequencer_reset() why we need |
|
- | 300 | * a power domain reference here. |
|
- | 301 | */ |
|
- | 302 | power_domain = intel_display_port_power_domain(encoder); |
|
- | 303 | intel_display_power_get(dev_priv, power_domain); |
|
- | 304 | ||
- | 305 | mutex_lock(&dev_priv->pps_mutex); |
|
- | 306 | } |
|
- | 307 | ||
- | 308 | static void pps_unlock(struct intel_dp *intel_dp) |
|
- | 309 | { |
|
- | 310 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 311 | struct intel_encoder *encoder = &intel_dig_port->base; |
|
- | 312 | struct drm_device *dev = encoder->base.dev; |
|
- | 313 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 314 | enum intel_display_power_domain power_domain; |
|
- | 315 | ||
- | 316 | mutex_unlock(&dev_priv->pps_mutex); |
|
- | 317 | ||
- | 318 | power_domain = intel_display_port_power_domain(encoder); |
|
- | 319 | intel_display_power_put(dev_priv, power_domain); |
|
- | 320 | } |
|
- | 321 | ||
- | 322 | static void |
|
- | 323 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
|
- | 324 | { |
|
- | 325 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 326 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 327 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 328 | enum pipe pipe = intel_dp->pps_pipe; |
|
- | 329 | bool pll_enabled; |
|
- | 330 | uint32_t DP; |
|
- | 331 | ||
- | 332 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
|
- | 333 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
|
- | 334 | pipe_name(pipe), port_name(intel_dig_port->port))) |
|
- | 335 | return; |
|
- | 336 | ||
- | 337 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
|
- | 338 | pipe_name(pipe), port_name(intel_dig_port->port)); |
|
- | 339 | ||
- | 340 | /* Preserve the BIOS-computed detected bit. This is |
|
- | 341 | * supposed to be read-only. |
|
- | 342 | */ |
|
- | 343 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
|
- | 344 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
|
- | 345 | DP |= DP_PORT_WIDTH(1); |
|
- | 346 | DP |= DP_LINK_TRAIN_PAT_1; |
|
- | 347 | ||
- | 348 | if (IS_CHERRYVIEW(dev)) |
|
- | 349 | DP |= DP_PIPE_SELECT_CHV(pipe); |
|
- | 350 | else if (pipe == PIPE_B) |
|
- | 351 | DP |= DP_PIPEB_SELECT; |
|
- | 352 | ||
- | 353 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
|
- | 354 | ||
- | 355 | /* |
|
- | 356 | * The DPLL for the pipe must be enabled for this to work. |
|
- | 357 | * So enable temporarily it if it's not already enabled. |
|
- | 358 | */ |
|
- | 359 | if (!pll_enabled) |
|
- | 360 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
|
- | 361 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); |
|
- | 362 | ||
- | 363 | /* |
|
- | 364 | * Similar magic as in intel_dp_enable_port(). |
|
- | 365 | * We _must_ do this port enable + disable trick |
|
- | 366 | * to make this power seqeuencer lock onto the port. |
|
- | 367 | * Otherwise even VDD force bit won't work. |
|
- | 368 | */ |
|
- | 369 | I915_WRITE(intel_dp->output_reg, DP); |
|
- | 370 | POSTING_READ(intel_dp->output_reg); |
|
- | 371 | ||
- | 372 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
|
- | 373 | POSTING_READ(intel_dp->output_reg); |
|
- | 374 | ||
- | 375 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
|
- | 376 | POSTING_READ(intel_dp->output_reg); |
|
- | 377 | ||
288 | struct intel_dp *intel_dp, |
378 | if (!pll_enabled) |
- | 379 | vlv_force_pll_off(dev, pipe); |
|
Line 289... | Line 380... | ||
289 | struct edp_power_seq *out); |
380 | } |
290 | 381 | ||
291 | static enum pipe |
382 | static enum pipe |
292 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
383 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
293 | { |
- | |
294 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
384 | { |
295 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
385 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
296 | struct drm_device *dev = intel_dig_port->base.base.dev; |
386 | struct drm_device *dev = intel_dig_port->base.base.dev; |
- | 387 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
297 | struct drm_i915_private *dev_priv = dev->dev_private; |
388 | struct intel_encoder *encoder; |
Line -... | Line 389... | ||
- | 389 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
|
- | 390 | enum pipe pipe; |
|
- | 391 | ||
- | 392 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 393 | ||
- | 394 | /* We should never land here with regular DP ports */ |
|
- | 395 | WARN_ON(!is_edp(intel_dp)); |
|
- | 396 | ||
- | 397 | if (intel_dp->pps_pipe != INVALID_PIPE) |
|
- | 398 | return intel_dp->pps_pipe; |
|
- | 399 | ||
- | 400 | /* |
|
- | 401 | * We don't have power sequencer currently. |
|
- | 402 | * Pick one that's not used by other ports. |
|
- | 403 | */ |
|
- | 404 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
|
- | 405 | base.head) { |
|
- | 406 | struct intel_dp *tmp; |
|
- | 407 | ||
- | 408 | if (encoder->type != INTEL_OUTPUT_EDP) |
|
- | 409 | continue; |
|
- | 410 | ||
- | 411 | tmp = enc_to_intel_dp(&encoder->base); |
|
- | 412 | ||
- | 413 | if (tmp->pps_pipe != INVALID_PIPE) |
|
- | 414 | pipes &= ~(1 << tmp->pps_pipe); |
|
- | 415 | } |
|
- | 416 | ||
- | 417 | /* |
|
- | 418 | * Didn't find one. This should not happen since there |
|
- | 419 | * are two power sequencers and up to two eDP ports. |
|
- | 420 | */ |
|
- | 421 | if (WARN_ON(pipes == 0)) |
|
- | 422 | pipe = PIPE_A; |
|
- | 423 | else |
|
298 | enum port port = intel_dig_port->port; |
424 | pipe = ffs(pipes) - 1; |
- | 425 | ||
- | 426 | vlv_steal_power_sequencer(dev, pipe); |
|
- | 427 | intel_dp->pps_pipe = pipe; |
|
- | 428 | ||
- | 429 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
|
- | 430 | pipe_name(intel_dp->pps_pipe), |
|
- | 431 | port_name(intel_dig_port->port)); |
|
- | 432 | ||
- | 433 | /* init power sequencer on this pipe and port */ |
|
- | 434 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
|
- | 435 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
|
- | 436 | ||
299 | enum pipe pipe; |
437 | /* |
- | 438 | * Even vdd force doesn't work until we've made |
|
- | 439 | * the power sequencer lock in on the port. |
|
300 | 440 | */ |
|
- | 441 | vlv_power_sequencer_kick(intel_dp); |
|
- | 442 | ||
- | 443 | return intel_dp->pps_pipe; |
|
- | 444 | } |
|
- | 445 | ||
- | 446 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
|
- | 447 | enum pipe pipe); |
|
- | 448 | ||
- | 449 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
|
- | 450 | enum pipe pipe) |
|
- | 451 | { |
|
- | 452 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
|
- | 453 | } |
|
- | 454 | ||
- | 455 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
|
- | 456 | enum pipe pipe) |
|
- | 457 | { |
|
- | 458 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
|
- | 459 | } |
|
- | 460 | ||
- | 461 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
|
- | 462 | enum pipe pipe) |
|
- | 463 | { |
|
- | 464 | return true; |
|
- | 465 | } |
|
- | 466 | ||
- | 467 | static enum pipe |
|
- | 468 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
|
- | 469 | enum port port, |
|
Line 301... | Line -... | ||
301 | /* modeset should have pipe */ |
- | |
302 | if (crtc) |
470 | vlv_pipe_check pipe_check) |
303 | return to_intel_crtc(crtc)->pipe; |
471 | { |
304 | 472 | enum pipe pipe; |
|
- | 473 | ||
305 | /* init time, try to find a pipe with this port selected */ |
474 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
306 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
475 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
- | 476 | PANEL_PORT_SELECT_MASK; |
|
307 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
477 | |
- | 478 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
|
- | 479 | continue; |
|
308 | PANEL_PORT_SELECT_MASK; |
480 | |
309 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) |
481 | if (!pipe_check(dev_priv, pipe)) |
Line -... | Line 482... | ||
- | 482 | continue; |
|
- | 483 | ||
- | 484 | return pipe; |
|
- | 485 | } |
|
- | 486 | ||
- | 487 | return INVALID_PIPE; |
|
- | 488 | } |
|
- | 489 | ||
- | 490 | static void |
|
- | 491 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
|
- | 492 | { |
|
- | 493 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 494 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 495 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 496 | enum port port = intel_dig_port->port; |
|
- | 497 | ||
- | 498 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 499 | ||
- | 500 | /* try to find a pipe with this port selected */ |
|
- | 501 | /* first pick one where the panel is on */ |
|
- | 502 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
|
- | 503 | vlv_pipe_has_pp_on); |
|
- | 504 | /* didn't find one? pick one where vdd is on */ |
|
- | 505 | if (intel_dp->pps_pipe == INVALID_PIPE) |
|
- | 506 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
|
- | 507 | vlv_pipe_has_vdd_on); |
|
- | 508 | /* didn't find one? pick one with just the correct port */ |
|
- | 509 | if (intel_dp->pps_pipe == INVALID_PIPE) |
|
- | 510 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
|
- | 511 | vlv_pipe_any); |
|
310 | return pipe; |
512 | |
- | 513 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
|
- | 514 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
|
- | 515 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
|
- | 516 | port_name(port)); |
|
- | 517 | return; |
|
- | 518 | } |
|
- | 519 | ||
- | 520 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
|
- | 521 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
|
- | 522 | ||
- | 523 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
|
- | 524 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
|
- | 525 | } |
|
- | 526 | ||
- | 527 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
|
311 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) |
528 | { |
- | 529 | struct drm_device *dev = dev_priv->dev; |
|
- | 530 | struct intel_encoder *encoder; |
|
- | 531 | ||
- | 532 | if (WARN_ON(!IS_VALLEYVIEW(dev))) |
|
- | 533 | return; |
|
- | 534 | ||
- | 535 | /* |
|
- | 536 | * We can't grab pps_mutex here due to deadlock with power_domain |
|
- | 537 | * mutex when power_domain functions are called while holding pps_mutex. |
|
- | 538 | * That also means that in order to use pps_pipe the code needs to |
|
- | 539 | * hold both a power domain reference and pps_mutex, and the power domain |
|
- | 540 | * reference get/put must be done while _not_ holding pps_mutex. |
|
- | 541 | * pps_{lock,unlock}() do these steps in the correct order, so one |
|
- | 542 | * should use them always. |
|
- | 543 | */ |
|
- | 544 | ||
- | 545 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
|
- | 546 | struct intel_dp *intel_dp; |
|
- | 547 | ||
- | 548 | if (encoder->type != INTEL_OUTPUT_EDP) |
|
312 | return pipe; |
549 | continue; |
Line 313... | Line 550... | ||
313 | } |
550 | |
314 | 551 | intel_dp = enc_to_intel_dp(&encoder->base); |
|
315 | /* shrug */ |
552 | intel_dp->pps_pipe = INVALID_PIPE; |
Line 334... | Line 571... | ||
334 | return PCH_PP_STATUS; |
571 | return PCH_PP_STATUS; |
335 | else |
572 | else |
336 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
573 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
337 | } |
574 | } |
Line -... | Line 575... | ||
- | 575 | ||
- | 576 | #if 0 |
|
- | 577 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
|
- | 578 | This function only applicable when panel PM state is not to be tracked */ |
|
- | 579 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
|
- | 580 | void *unused) |
|
- | 581 | { |
|
- | 582 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
|
- | 583 | edp_notifier); |
|
- | 584 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 585 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 586 | u32 pp_div; |
|
- | 587 | u32 pp_ctrl_reg, pp_div_reg; |
|
- | 588 | ||
- | 589 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
|
- | 590 | return 0; |
|
- | 591 | ||
- | 592 | pps_lock(intel_dp); |
|
- | 593 | ||
- | 594 | if (IS_VALLEYVIEW(dev)) { |
|
- | 595 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
|
- | 596 | ||
- | 597 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
|
- | 598 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
|
- | 599 | pp_div = I915_READ(pp_div_reg); |
|
- | 600 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
|
- | 601 | ||
- | 602 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
|
- | 603 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
|
- | 604 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
|
- | 605 | msleep(intel_dp->panel_power_cycle_delay); |
|
- | 606 | } |
|
- | 607 | ||
- | 608 | pps_unlock(intel_dp); |
|
- | 609 | ||
- | 610 | return 0; |
|
- | 611 | } |
|
Line 338... | Line 612... | ||
338 | 612 | #endif |
|
339 | 613 | ||
340 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
614 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
341 | { |
615 | { |
Line -... | Line 616... | ||
- | 616 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 617 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 618 | ||
- | 619 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 620 | ||
- | 621 | if (IS_VALLEYVIEW(dev) && |
|
342 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
622 | intel_dp->pps_pipe == INVALID_PIPE) |
343 | struct drm_i915_private *dev_priv = dev->dev_private; |
623 | return false; |
Line 344... | Line 624... | ||
344 | 624 | ||
345 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
625 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
346 | } |
626 | } |
347 | 627 | ||
348 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
- | |
349 | { |
- | |
350 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
Line 351... | Line 628... | ||
351 | struct drm_i915_private *dev_priv = dev->dev_private; |
628 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
- | 629 | { |
|
- | 630 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
352 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
631 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 632 | ||
- | 633 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
353 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
634 | |
354 | enum intel_display_power_domain power_domain; |
635 | if (IS_VALLEYVIEW(dev) && |
Line 355... | Line 636... | ||
355 | 636 | intel_dp->pps_pipe == INVALID_PIPE) |
|
356 | power_domain = intel_display_port_power_domain(intel_encoder); |
637 | return false; |
357 | return intel_display_power_enabled(dev_priv, power_domain) && |
638 | |
Line 454... | Line 735... | ||
454 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
735 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
455 | { |
736 | { |
456 | return index ? 0 : 100; |
737 | return index ? 0 : 100; |
457 | } |
738 | } |
Line -... | Line 739... | ||
- | 739 | ||
- | 740 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
|
- | 741 | { |
|
- | 742 | /* |
|
- | 743 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
|
- | 744 | * derive the clock from CDCLK automatically). We still implement the |
|
- | 745 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
|
- | 746 | */ |
|
- | 747 | return index ? 0 : 1; |
|
- | 748 | } |
|
458 | 749 | ||
459 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
750 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
460 | bool has_aux_irq, |
751 | bool has_aux_irq, |
461 | int send_bytes, |
752 | int send_bytes, |
462 | uint32_t aux_clock_divider) |
753 | uint32_t aux_clock_divider) |
Line 484... | Line 775... | ||
484 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
775 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
485 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
776 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
486 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
777 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
487 | } |
778 | } |
Line -... | Line 779... | ||
- | 779 | ||
- | 780 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
|
- | 781 | bool has_aux_irq, |
|
- | 782 | int send_bytes, |
|
- | 783 | uint32_t unused) |
|
- | 784 | { |
|
- | 785 | return DP_AUX_CH_CTL_SEND_BUSY | |
|
- | 786 | DP_AUX_CH_CTL_DONE | |
|
- | 787 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
|
- | 788 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
|
- | 789 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
|
- | 790 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
|
- | 791 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
|
- | 792 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
|
- | 793 | } |
|
488 | 794 | ||
489 | static int |
795 | static int |
490 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
796 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
491 | uint8_t *send, int send_bytes, |
797 | const uint8_t *send, int send_bytes, |
492 | uint8_t *recv, int recv_size) |
798 | uint8_t *recv, int recv_size) |
493 | { |
799 | { |
494 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
800 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
495 | struct drm_device *dev = intel_dig_port->base.base.dev; |
801 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Line 501... | Line 807... | ||
501 | uint32_t status; |
807 | uint32_t status; |
502 | int try, clock = 0; |
808 | int try, clock = 0; |
503 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
809 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
504 | bool vdd; |
810 | bool vdd; |
Line -... | Line 811... | ||
- | 811 | ||
- | 812 | pps_lock(intel_dp); |
|
- | 813 | ||
- | 814 | /* |
|
- | 815 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
|
- | 816 | * In such cases we want to leave VDD enabled and it's up to upper layers |
|
- | 817 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
|
- | 818 | * ourselves. |
|
505 | 819 | */ |
|
Line 506... | Line 820... | ||
506 | vdd = _edp_panel_vdd_on(intel_dp); |
820 | vdd = edp_panel_vdd_on(intel_dp); |
507 | 821 | ||
508 | /* dp aux is extremely sensitive to irq latency, hence request the |
822 | /* dp aux is extremely sensitive to irq latency, hence request the |
509 | * lowest possible wakeup latency and so prevent the cpu from going into |
823 | * lowest possible wakeup latency and so prevent the cpu from going into |
Line 544... | Line 858... | ||
544 | /* Must try at least 3 times according to DP spec */ |
858 | /* Must try at least 3 times according to DP spec */ |
545 | for (try = 0; try < 5; try++) { |
859 | for (try = 0; try < 5; try++) { |
546 | /* Load the send data into the aux channel data registers */ |
860 | /* Load the send data into the aux channel data registers */ |
547 | for (i = 0; i < send_bytes; i += 4) |
861 | for (i = 0; i < send_bytes; i += 4) |
548 | I915_WRITE(ch_data + i, |
862 | I915_WRITE(ch_data + i, |
- | 863 | intel_dp_pack_aux(send + i, |
|
549 | pack_aux(send + i, send_bytes - i)); |
864 | send_bytes - i)); |
Line 550... | Line 865... | ||
550 | 865 | ||
551 | /* Send the command and wait for it to complete */ |
866 | /* Send the command and wait for it to complete */ |
Line 552... | Line 867... | ||
552 | I915_WRITE(ch_ctl, send_ctl); |
867 | I915_WRITE(ch_ctl, send_ctl); |
Line 598... | Line 913... | ||
598 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
913 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
599 | if (recv_bytes > recv_size) |
914 | if (recv_bytes > recv_size) |
600 | recv_bytes = recv_size; |
915 | recv_bytes = recv_size; |
Line 601... | Line 916... | ||
601 | 916 | ||
602 | for (i = 0; i < recv_bytes; i += 4) |
917 | for (i = 0; i < recv_bytes; i += 4) |
603 | unpack_aux(I915_READ(ch_data + i), |
918 | intel_dp_unpack_aux(I915_READ(ch_data + i), |
Line 604... | Line 919... | ||
604 | recv + i, recv_bytes - i); |
919 | recv + i, recv_bytes - i); |
605 | 920 | ||
606 | ret = recv_bytes; |
921 | ret = recv_bytes; |
607 | out: |
922 | out: |
Line 608... | Line 923... | ||
608 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
923 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
609 | intel_aux_display_runtime_put(dev_priv); |
924 | intel_aux_display_runtime_put(dev_priv); |
Line -... | Line 925... | ||
- | 925 | ||
- | 926 | if (vdd) |
|
610 | 927 | edp_panel_vdd_off(intel_dp, false); |
|
611 | if (vdd) |
928 | |
Line 612... | Line 929... | ||
612 | edp_panel_vdd_off(intel_dp, false); |
929 | pps_unlock(intel_dp); |
613 | 930 | ||
Line 707... | Line 1024... | ||
707 | break; |
1024 | break; |
708 | default: |
1025 | default: |
709 | BUG(); |
1026 | BUG(); |
710 | } |
1027 | } |
Line -... | Line 1028... | ||
- | 1028 | ||
- | 1029 | /* |
|
- | 1030 | * The AUX_CTL register is usually DP_CTL + 0x10. |
|
- | 1031 | * |
|
- | 1032 | * On Haswell and Broadwell though: |
|
- | 1033 | * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU |
|
- | 1034 | * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU |
|
- | 1035 | * |
|
- | 1036 | * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU. |
|
711 | 1037 | */ |
|
712 | if (!HAS_DDI(dev)) |
1038 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
Line 713... | Line 1039... | ||
713 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
1039 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
714 | 1040 | ||
715 | intel_dp->aux.name = name; |
1041 | intel_dp->aux.name = name; |
Line -... | Line 1042... | ||
- | 1042 | intel_dp->aux.dev = dev->dev; |
|
- | 1043 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
|
Line 716... | Line 1044... | ||
716 | intel_dp->aux.dev = dev->dev; |
1044 | |
717 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
1045 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
718 | 1046 | connector->base.kdev->kobj.name); |
|
719 | 1047 | ||
Line 732... | Line 1060... | ||
732 | 1060 | ||
733 | intel_connector_unregister(intel_connector); |
1061 | intel_connector_unregister(intel_connector); |
Line 734... | Line 1062... | ||
734 | } |
1062 | } |
- | 1063 | ||
- | 1064 | static void |
|
- | 1065 | skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw) |
|
- | 1066 | { |
|
- | 1067 | u32 ctrl1; |
|
- | 1068 | ||
- | 1069 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
|
- | 1070 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
|
- | 1071 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
|
- | 1072 | ||
- | 1073 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
|
- | 1074 | switch (link_bw) { |
|
- | 1075 | case DP_LINK_BW_1_62: |
|
- | 1076 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, |
|
- | 1077 | SKL_DPLL0); |
|
- | 1078 | break; |
|
- | 1079 | case DP_LINK_BW_2_7: |
|
- | 1080 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, |
|
- | 1081 | SKL_DPLL0); |
|
- | 1082 | break; |
|
- | 1083 | case DP_LINK_BW_5_4: |
|
- | 1084 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, |
|
- | 1085 | SKL_DPLL0); |
|
- | 1086 | break; |
|
- | 1087 | } |
|
- | 1088 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
|
- | 1089 | } |
|
735 | 1090 | ||
736 | static void |
1091 | static void |
737 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) |
1092 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) |
738 | { |
1093 | { |
739 | switch (link_bw) { |
1094 | switch (link_bw) { |
Line 780... | Line 1135... | ||
780 | } |
1135 | } |
781 | } |
1136 | } |
782 | } |
1137 | } |
783 | } |
1138 | } |
Line 784... | Line -... | ||
784 | - | ||
785 | static void |
- | |
786 | intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) |
- | |
787 | { |
- | |
788 | struct drm_device *dev = crtc->base.dev; |
- | |
789 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
790 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
- | |
791 | - | ||
792 | I915_WRITE(PIPE_DATA_M2(transcoder), |
- | |
793 | TU_SIZE(m_n->tu) | m_n->gmch_m); |
- | |
794 | I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); |
- | |
795 | I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); |
- | |
796 | I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); |
- | |
797 | } |
- | |
798 | 1139 | ||
799 | bool |
1140 | bool |
800 | intel_dp_compute_config(struct intel_encoder *encoder, |
1141 | intel_dp_compute_config(struct intel_encoder *encoder, |
801 | struct intel_crtc_config *pipe_config) |
1142 | struct intel_crtc_config *pipe_config) |
802 | { |
1143 | { |
Line 819... | Line 1160... | ||
819 | 1160 | ||
820 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
1161 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Line 821... | Line 1162... | ||
821 | pipe_config->has_pch_encoder = true; |
1162 | pipe_config->has_pch_encoder = true; |
- | 1163 | ||
822 | 1164 | pipe_config->has_dp_encoder = true; |
|
Line 823... | Line 1165... | ||
823 | pipe_config->has_dp_encoder = true; |
1165 | pipe_config->has_drrs = false; |
824 | pipe_config->has_audio = intel_dp->has_audio; |
1166 | pipe_config->has_audio = intel_dp->has_audio; |
825 | 1167 | ||
Line 850... | Line 1192... | ||
850 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1192 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
851 | dev_priv->vbt.edp_bpp); |
1193 | dev_priv->vbt.edp_bpp); |
852 | bpp = dev_priv->vbt.edp_bpp; |
1194 | bpp = dev_priv->vbt.edp_bpp; |
853 | } |
1195 | } |
Line -... | Line 1196... | ||
- | 1196 | ||
- | 1197 | /* |
|
- | 1198 | * Use the maximum clock and number of lanes the eDP panel |
|
854 | 1199 | * advertizes being capable of. The panels are generally |
|
- | 1200 | * designed to support only a single clock and lane |
|
855 | if (IS_BROADWELL(dev)) { |
1201 | * configuration, and typically these values correspond to the |
- | 1202 | * native resolution of the panel. |
|
856 | /* Yes, it's an ugly hack. */ |
1203 | */ |
857 | min_lane_count = max_lane_count; |
- | |
858 | DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", |
- | |
859 | min_lane_count); |
- | |
860 | } else if (dev_priv->vbt.edp_lanes) { |
- | |
861 | min_lane_count = min(dev_priv->vbt.edp_lanes, |
- | |
862 | max_lane_count); |
- | |
863 | DRM_DEBUG_KMS("using min %u lanes per VBT\n", |
- | |
864 | min_lane_count); |
- | |
865 | } |
- | |
866 | - | ||
867 | if (dev_priv->vbt.edp_rate) { |
- | |
868 | min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); |
- | |
869 | DRM_DEBUG_KMS("using min %02x link bw per VBT\n", |
1204 | min_lane_count = max_lane_count; |
870 | bws[min_clock]); |
- | |
871 | } |
1205 | min_clock = max_clock; |
Line 872... | Line 1206... | ||
872 | } |
1206 | } |
873 | 1207 | ||
874 | for (; bpp >= 6*3; bpp -= 2*3) { |
1208 | for (; bpp >= 6*3; bpp -= 2*3) { |
Line 922... | Line 1256... | ||
922 | pipe_config->port_clock, |
1256 | pipe_config->port_clock, |
923 | &pipe_config->dp_m_n); |
1257 | &pipe_config->dp_m_n); |
Line 924... | Line 1258... | ||
924 | 1258 | ||
925 | if (intel_connector->panel.downclock_mode != NULL && |
1259 | if (intel_connector->panel.downclock_mode != NULL && |
- | 1260 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { |
|
926 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { |
1261 | pipe_config->has_drrs = true; |
927 | intel_link_compute_m_n(bpp, lane_count, |
1262 | intel_link_compute_m_n(bpp, lane_count, |
928 | intel_connector->panel.downclock_mode->clock, |
1263 | intel_connector->panel.downclock_mode->clock, |
929 | pipe_config->port_clock, |
1264 | pipe_config->port_clock, |
930 | &pipe_config->dp_m2_n2); |
1265 | &pipe_config->dp_m2_n2); |
Line -... | Line 1266... | ||
- | 1266 | } |
|
- | 1267 | ||
931 | } |
1268 | if (IS_SKYLAKE(dev) && is_edp(intel_dp)) |
932 | 1269 | skl_edp_set_pll_config(pipe_config, intel_dp->link_bw); |
|
933 | if (HAS_DDI(dev)) |
1270 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
934 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
1271 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
Line 935... | Line 1272... | ||
935 | else |
1272 | else |
Line 1001... | Line 1338... | ||
1001 | 1338 | ||
1002 | /* Handle DP bits in common between all three register formats */ |
1339 | /* Handle DP bits in common between all three register formats */ |
1003 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1340 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Line 1004... | Line 1341... | ||
1004 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
1341 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
1005 | - | ||
1006 | if (crtc->config.has_audio) { |
- | |
1007 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
1342 | |
1008 | pipe_name(crtc->pipe)); |
- | |
1009 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
- | |
Line 1010... | Line 1343... | ||
1010 | intel_write_eld(&encoder->base, adjusted_mode); |
1343 | if (crtc->config.has_audio) |
Line 1011... | Line 1344... | ||
1011 | } |
1344 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
1012 | 1345 | ||
Line 1062... | Line 1395... | ||
1062 | { |
1395 | { |
1063 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1396 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1064 | struct drm_i915_private *dev_priv = dev->dev_private; |
1397 | struct drm_i915_private *dev_priv = dev->dev_private; |
1065 | u32 pp_stat_reg, pp_ctrl_reg; |
1398 | u32 pp_stat_reg, pp_ctrl_reg; |
Line -... | Line 1399... | ||
- | 1399 | ||
- | 1400 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
1066 | 1401 | ||
1067 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1402 | pp_stat_reg = _pp_stat_reg(intel_dp); |
Line 1068... | Line 1403... | ||
1068 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1403 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1069 | 1404 | ||
Line 1125... | Line 1460... | ||
1125 | { |
1460 | { |
1126 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1461 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
1462 | struct drm_i915_private *dev_priv = dev->dev_private; |
1128 | u32 control; |
1463 | u32 control; |
Line -... | Line 1464... | ||
- | 1464 | ||
- | 1465 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
1129 | 1466 | ||
1130 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1467 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1131 | control &= ~PANEL_UNLOCK_MASK; |
1468 | control &= ~PANEL_UNLOCK_MASK; |
1132 | control |= PANEL_UNLOCK_REGS; |
1469 | control |= PANEL_UNLOCK_REGS; |
1133 | return control; |
1470 | return control; |
Line -... | Line 1471... | ||
- | 1471 | } |
|
- | 1472 | ||
- | 1473 | /* |
|
- | 1474 | * Must be paired with edp_panel_vdd_off(). |
|
- | 1475 | * Must hold pps_mutex around the whole on/off sequence. |
|
1134 | } |
1476 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1135 | 1477 | */ |
|
1136 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
1478 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
1137 | { |
1479 | { |
1138 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1480 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1139 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1481 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1140 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1482 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
1483 | struct drm_i915_private *dev_priv = dev->dev_private; |
1142 | enum intel_display_power_domain power_domain; |
1484 | enum intel_display_power_domain power_domain; |
1143 | u32 pp; |
1485 | u32 pp; |
Line -... | Line 1486... | ||
- | 1486 | u32 pp_stat_reg, pp_ctrl_reg; |
|
- | 1487 | bool need_to_disable = !intel_dp->want_panel_vdd; |
|
1144 | u32 pp_stat_reg, pp_ctrl_reg; |
1488 | |
1145 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1489 | lockdep_assert_held(&dev_priv->pps_mutex); |
Line 1146... | Line 1490... | ||
1146 | 1490 | ||
Line 1153... | Line 1497... | ||
1153 | return need_to_disable; |
1497 | return need_to_disable; |
Line 1154... | Line 1498... | ||
1154 | 1498 | ||
1155 | power_domain = intel_display_port_power_domain(intel_encoder); |
1499 | power_domain = intel_display_port_power_domain(intel_encoder); |
Line 1156... | Line 1500... | ||
1156 | intel_display_power_get(dev_priv, power_domain); |
1500 | intel_display_power_get(dev_priv, power_domain); |
- | 1501 | ||
Line 1157... | Line 1502... | ||
1157 | 1502 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
|
1158 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
1503 | port_name(intel_dig_port->port)); |
Line 1159... | Line 1504... | ||
1159 | 1504 | ||
Line 1172... | Line 1517... | ||
1172 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1517 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1173 | /* |
1518 | /* |
1174 | * If the panel wasn't on, delay before accessing aux channel |
1519 | * If the panel wasn't on, delay before accessing aux channel |
1175 | */ |
1520 | */ |
1176 | if (!edp_have_panel_power(intel_dp)) { |
1521 | if (!edp_have_panel_power(intel_dp)) { |
1177 | DRM_DEBUG_KMS("eDP was not running\n"); |
1522 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
- | 1523 | port_name(intel_dig_port->port)); |
|
1178 | msleep(intel_dp->panel_power_up_delay); |
1524 | msleep(intel_dp->panel_power_up_delay); |
1179 | } |
1525 | } |
Line 1180... | Line 1526... | ||
1180 | 1526 | ||
1181 | return need_to_disable; |
1527 | return need_to_disable; |
Line -... | Line 1528... | ||
- | 1528 | } |
|
- | 1529 | ||
- | 1530 | /* |
|
- | 1531 | * Must be paired with intel_edp_panel_vdd_off() or |
|
- | 1532 | * intel_edp_panel_off(). |
|
- | 1533 | * Nested calls to these functions are not allowed since |
|
- | 1534 | * we drop the lock. Caller must use some higher level |
|
1182 | } |
1535 | * locking to prevent nested calls from other threads. |
1183 | 1536 | */ |
|
1184 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1537 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1185 | { |
- | |
Line -... | Line 1538... | ||
- | 1538 | { |
|
- | 1539 | bool vdd; |
|
- | 1540 | ||
- | 1541 | if (!is_edp(intel_dp)) |
|
1186 | if (is_edp(intel_dp)) { |
1542 | return; |
- | 1543 | ||
1187 | bool vdd = _edp_panel_vdd_on(intel_dp); |
1544 | pps_lock(intel_dp); |
- | 1545 | vdd = edp_panel_vdd_on(intel_dp); |
|
- | 1546 | pps_unlock(intel_dp); |
|
1188 | 1547 | ||
Line 1189... | Line 1548... | ||
1189 | WARN(!vdd, "eDP VDD already requested on\n"); |
1548 | WARN(!vdd, "eDP port %c VDD already requested on\n", |
1190 | } |
1549 | port_name(dp_to_dig_port(intel_dp)->port)); |
1191 | } |
1550 | } |
1192 | 1551 | ||
1193 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
- | |
1194 | { |
- | |
1195 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
1196 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1197 | u32 pp; |
- | |
1198 | u32 pp_stat_reg, pp_ctrl_reg; |
- | |
1199 | 1552 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
|
1200 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
1553 | { |
1201 | 1554 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
1202 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
1555 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 1556 | struct intel_digital_port *intel_dig_port = |
|
- | 1557 | dp_to_dig_port(intel_dp); |
|
- | 1558 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
- | 1559 | enum intel_display_power_domain power_domain; |
|
- | 1560 | u32 pp; |
|
- | 1561 | u32 pp_stat_reg, pp_ctrl_reg; |
|
- | 1562 | ||
- | 1563 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 1564 | ||
Line 1203... | Line 1565... | ||
1203 | struct intel_digital_port *intel_dig_port = |
1565 | WARN_ON(intel_dp->want_panel_vdd); |
- | 1566 | ||
Line 1204... | Line 1567... | ||
1204 | dp_to_dig_port(intel_dp); |
1567 | if (!edp_have_panel_vdd(intel_dp)) |
1205 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1568 | return; |
Line 1206... | Line 1569... | ||
1206 | enum intel_display_power_domain power_domain; |
1569 | |
Line 1224... | Line 1587... | ||
1224 | intel_dp->last_power_cycle = jiffies; |
1587 | intel_dp->last_power_cycle = jiffies; |
Line 1225... | Line 1588... | ||
1225 | 1588 | ||
1226 | power_domain = intel_display_port_power_domain(intel_encoder); |
1589 | power_domain = intel_display_port_power_domain(intel_encoder); |
1227 | intel_display_power_put(dev_priv, power_domain); |
1590 | intel_display_power_put(dev_priv, power_domain); |
1228 | } |
- | |
Line 1229... | Line 1591... | ||
1229 | } |
1591 | } |
1230 | 1592 | ||
1231 | static void edp_panel_vdd_work(struct work_struct *__work) |
1593 | static void edp_panel_vdd_work(struct work_struct *__work) |
1232 | { |
1594 | { |
1233 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
- | |
Line -... | Line 1595... | ||
- | 1595 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
|
1234 | struct intel_dp, panel_vdd_work); |
1596 | struct intel_dp, panel_vdd_work); |
1235 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1597 | |
1236 | 1598 | pps_lock(intel_dp); |
|
1237 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
1599 | if (!intel_dp->want_panel_vdd) |
Line 1238... | Line 1600... | ||
1238 | edp_panel_vdd_off_sync(intel_dp); |
1600 | edp_panel_vdd_off_sync(intel_dp); |
1239 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
1601 | pps_unlock(intel_dp); |
1240 | } |
1602 | } |
Line 1250... | Line 1612... | ||
1250 | */ |
1612 | */ |
1251 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1613 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1252 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1614 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1253 | } |
1615 | } |
Line -... | Line 1616... | ||
- | 1616 | ||
- | 1617 | /* |
|
- | 1618 | * Must be paired with edp_panel_vdd_on(). |
|
- | 1619 | * Must hold pps_mutex around the whole on/off sequence. |
|
- | 1620 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
|
1254 | 1621 | */ |
|
1255 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1622 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
- | 1623 | { |
|
- | 1624 | struct drm_i915_private *dev_priv = |
|
- | 1625 | intel_dp_to_dev(intel_dp)->dev_private; |
|
- | 1626 | ||
- | 1627 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
1256 | { |
1628 | |
1257 | if (!is_edp(intel_dp)) |
1629 | if (!is_edp(intel_dp)) |
Line 1258... | Line 1630... | ||
1258 | return; |
1630 | return; |
- | 1631 | ||
Line 1259... | Line 1632... | ||
1259 | 1632 | WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
|
Line 1260... | Line 1633... | ||
1260 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
1633 | port_name(dp_to_dig_port(intel_dp)->port)); |
1261 | 1634 | ||
1262 | intel_dp->want_panel_vdd = false; |
1635 | intel_dp->want_panel_vdd = false; |
1263 | 1636 | ||
1264 | if (sync) |
1637 | if (sync) |
Line 1265... | Line 1638... | ||
1265 | edp_panel_vdd_off_sync(intel_dp); |
1638 | edp_panel_vdd_off_sync(intel_dp); |
1266 | else |
1639 | else |
1267 | edp_panel_vdd_schedule_off(intel_dp); |
1640 | edp_panel_vdd_schedule_off(intel_dp); |
1268 | } |
1641 | } |
1269 | 1642 | ||
1270 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1643 | static void edp_panel_on(struct intel_dp *intel_dp) |
Line -... | Line 1644... | ||
- | 1644 | { |
|
- | 1645 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
1271 | { |
1646 | struct drm_i915_private *dev_priv = dev->dev_private; |
1272 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1647 | u32 pp; |
Line 1273... | Line 1648... | ||
1273 | struct drm_i915_private *dev_priv = dev->dev_private; |
1648 | u32 pp_ctrl_reg; |
- | 1649 | ||
Line 1274... | Line 1650... | ||
1274 | u32 pp; |
1650 | lockdep_assert_held(&dev_priv->pps_mutex); |
1275 | u32 pp_ctrl_reg; |
1651 | |
- | 1652 | if (!is_edp(intel_dp)) |
|
1276 | 1653 | return; |
|
1277 | if (!is_edp(intel_dp)) |
- | |
Line 1278... | Line 1654... | ||
1278 | return; |
1654 | |
Line 1279... | Line 1655... | ||
1279 | 1655 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
|
1280 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
1656 | port_name(dp_to_dig_port(intel_dp)->port)); |
Line 1310... | Line 1686... | ||
1310 | I915_WRITE(pp_ctrl_reg, pp); |
1686 | I915_WRITE(pp_ctrl_reg, pp); |
1311 | POSTING_READ(pp_ctrl_reg); |
1687 | POSTING_READ(pp_ctrl_reg); |
1312 | } |
1688 | } |
1313 | } |
1689 | } |
Line 1314... | Line 1690... | ||
1314 | 1690 | ||
- | 1691 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
|
- | 1692 | { |
|
- | 1693 | if (!is_edp(intel_dp)) |
|
- | 1694 | return; |
|
- | 1695 | ||
- | 1696 | pps_lock(intel_dp); |
|
- | 1697 | edp_panel_on(intel_dp); |
|
- | 1698 | pps_unlock(intel_dp); |
|
- | 1699 | } |
|
- | 1700 | ||
- | 1701 | ||
1315 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
1702 | static void edp_panel_off(struct intel_dp *intel_dp) |
1316 | { |
1703 | { |
1317 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1704 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1318 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1705 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1319 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1706 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1320 | struct drm_i915_private *dev_priv = dev->dev_private; |
1707 | struct drm_i915_private *dev_priv = dev->dev_private; |
1321 | enum intel_display_power_domain power_domain; |
1708 | enum intel_display_power_domain power_domain; |
1322 | u32 pp; |
1709 | u32 pp; |
Line -... | Line 1710... | ||
- | 1710 | u32 pp_ctrl_reg; |
|
- | 1711 | ||
1323 | u32 pp_ctrl_reg; |
1712 | lockdep_assert_held(&dev_priv->pps_mutex); |
1324 | 1713 | ||
Line 1325... | Line 1714... | ||
1325 | if (!is_edp(intel_dp)) |
1714 | if (!is_edp(intel_dp)) |
- | 1715 | return; |
|
Line 1326... | Line 1716... | ||
1326 | return; |
1716 | |
- | 1717 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
|
Line 1327... | Line 1718... | ||
1327 | 1718 | port_name(dp_to_dig_port(intel_dp)->port)); |
|
1328 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
1719 | |
1329 | 1720 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
|
1330 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
1721 | port_name(dp_to_dig_port(intel_dp)->port)); |
Line 1348... | Line 1739... | ||
1348 | /* We got a reference when we enabled the VDD. */ |
1739 | /* We got a reference when we enabled the VDD. */ |
1349 | power_domain = intel_display_port_power_domain(intel_encoder); |
1740 | power_domain = intel_display_port_power_domain(intel_encoder); |
1350 | intel_display_power_put(dev_priv, power_domain); |
1741 | intel_display_power_put(dev_priv, power_domain); |
1351 | } |
1742 | } |
Line -... | Line 1743... | ||
- | 1743 | ||
- | 1744 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
|
- | 1745 | { |
|
- | 1746 | if (!is_edp(intel_dp)) |
|
- | 1747 | return; |
|
- | 1748 | ||
- | 1749 | pps_lock(intel_dp); |
|
- | 1750 | edp_panel_off(intel_dp); |
|
- | 1751 | pps_unlock(intel_dp); |
|
- | 1752 | } |
|
- | 1753 | ||
1352 | 1754 | /* Enable backlight in the panel power control. */ |
|
1353 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
1755 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
1354 | { |
1756 | { |
1355 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1757 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1356 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1758 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1357 | struct drm_i915_private *dev_priv = dev->dev_private; |
1759 | struct drm_i915_private *dev_priv = dev->dev_private; |
1358 | u32 pp; |
1760 | u32 pp; |
Line 1359... | Line -... | ||
1359 | u32 pp_ctrl_reg; |
- | |
1360 | - | ||
1361 | if (!is_edp(intel_dp)) |
- | |
1362 | return; |
- | |
1363 | - | ||
1364 | DRM_DEBUG_KMS("\n"); |
- | |
1365 | - | ||
1366 | intel_panel_enable_backlight(intel_dp->attached_connector); |
1761 | u32 pp_ctrl_reg; |
1367 | 1762 | ||
1368 | /* |
1763 | /* |
1369 | * If we enable the backlight right away following a panel power |
1764 | * If we enable the backlight right away following a panel power |
1370 | * on, we may see slight flicker as the panel syncs with the eDP |
1765 | * on, we may see slight flicker as the panel syncs with the eDP |
1371 | * link. So delay a bit to make sure the image is solid before |
1766 | * link. So delay a bit to make sure the image is solid before |
1372 | * allowing it to appear. |
1767 | * allowing it to appear. |
- | 1768 | */ |
|
- | 1769 | wait_backlight_on(intel_dp); |
|
- | 1770 | ||
1373 | */ |
1771 | pps_lock(intel_dp); |
1374 | wait_backlight_on(intel_dp); |
1772 | |
Line 1375... | Line 1773... | ||
1375 | pp = ironlake_get_pp_control(intel_dp); |
1773 | pp = ironlake_get_pp_control(intel_dp); |
Line 1376... | Line 1774... | ||
1376 | pp |= EDP_BLC_ENABLE; |
1774 | pp |= EDP_BLC_ENABLE; |
1377 | 1775 | ||
- | 1776 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
|
- | 1777 | ||
1378 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1778 | I915_WRITE(pp_ctrl_reg, pp); |
Line -... | Line 1779... | ||
- | 1779 | POSTING_READ(pp_ctrl_reg); |
|
1379 | 1780 | ||
- | 1781 | pps_unlock(intel_dp); |
|
- | 1782 | } |
|
- | 1783 | ||
- | 1784 | /* Enable backlight PWM and backlight PP control. */ |
|
- | 1785 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
|
- | 1786 | { |
|
- | 1787 | if (!is_edp(intel_dp)) |
|
- | 1788 | return; |
|
- | 1789 | ||
- | 1790 | DRM_DEBUG_KMS("\n"); |
|
- | 1791 | ||
- | 1792 | intel_panel_enable_backlight(intel_dp->attached_connector); |
|
1380 | I915_WRITE(pp_ctrl_reg, pp); |
1793 | _intel_edp_backlight_on(intel_dp); |
1381 | POSTING_READ(pp_ctrl_reg); |
1794 | } |
1382 | } |
1795 | |
1383 | 1796 | /* Disable backlight in the panel power control. */ |
|
1384 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
1797 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
Line 1385... | Line 1798... | ||
1385 | { |
1798 | { |
1386 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1799 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 1387... | Line 1800... | ||
1387 | struct drm_i915_private *dev_priv = dev->dev_private; |
1800 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 1801 | u32 pp; |
|
1388 | u32 pp; |
1802 | u32 pp_ctrl_reg; |
1389 | u32 pp_ctrl_reg; |
1803 | |
Line 1390... | Line 1804... | ||
1390 | 1804 | if (!is_edp(intel_dp)) |
|
Line 1391... | Line 1805... | ||
1391 | if (!is_edp(intel_dp)) |
1805 | return; |
1392 | return; |
1806 | |
1393 | - | ||
Line -... | Line 1807... | ||
- | 1807 | pps_lock(intel_dp); |
|
- | 1808 | ||
- | 1809 | pp = ironlake_get_pp_control(intel_dp); |
|
1394 | DRM_DEBUG_KMS("\n"); |
1810 | pp &= ~EDP_BLC_ENABLE; |
- | 1811 | ||
- | 1812 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
|
- | 1813 | ||
- | 1814 | I915_WRITE(pp_ctrl_reg, pp); |
|
- | 1815 | POSTING_READ(pp_ctrl_reg); |
|
- | 1816 | ||
- | 1817 | pps_unlock(intel_dp); |
|
- | 1818 | ||
- | 1819 | intel_dp->last_backlight_off = jiffies; |
|
Line -... | Line 1820... | ||
- | 1820 | edp_wait_backlight_off(intel_dp); |
|
1395 | pp = ironlake_get_pp_control(intel_dp); |
1821 | } |
1396 | pp &= ~EDP_BLC_ENABLE; |
1822 | |
Line -... | Line 1823... | ||
- | 1823 | /* Disable backlight PP control and backlight PWM. */ |
|
- | 1824 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
|
- | 1825 | { |
|
- | 1826 | if (!is_edp(intel_dp)) |
|
- | 1827 | return; |
|
- | 1828 | ||
- | 1829 | DRM_DEBUG_KMS("\n"); |
|
- | 1830 | ||
- | 1831 | _intel_edp_backlight_off(intel_dp); |
|
- | 1832 | intel_panel_disable_backlight(intel_dp->attached_connector); |
|
- | 1833 | } |
|
- | 1834 | ||
- | 1835 | /* |
|
- | 1836 | * Hook for controlling the panel power control backlight through the bl_power |
|
- | 1837 | * sysfs attribute. Take care to handle multiple calls. |
|
- | 1838 | */ |
|
- | 1839 | static void intel_edp_backlight_power(struct intel_connector *connector, |
|
- | 1840 | bool enable) |
|
- | 1841 | { |
|
- | 1842 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
|
- | 1843 | bool is_enabled; |
|
- | 1844 | ||
- | 1845 | pps_lock(intel_dp); |
|
- | 1846 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
|
- | 1847 | pps_unlock(intel_dp); |
|
- | 1848 | ||
1397 | 1849 | if (is_enabled == enable) |
|
1398 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1850 | return; |
1399 | 1851 | ||
1400 | I915_WRITE(pp_ctrl_reg, pp); |
1852 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
1401 | POSTING_READ(pp_ctrl_reg); |
1853 | enable ? "enable" : "disable"); |
Line 1467... | Line 1919... | ||
1467 | return; |
1919 | return; |
Line 1468... | Line 1920... | ||
1468 | 1920 | ||
1469 | if (mode != DRM_MODE_DPMS_ON) { |
1921 | if (mode != DRM_MODE_DPMS_ON) { |
1470 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1922 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1471 | DP_SET_POWER_D3); |
- | |
1472 | if (ret != 1) |
- | |
1473 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
1923 | DP_SET_POWER_D3); |
1474 | } else { |
1924 | } else { |
1475 | /* |
1925 | /* |
1476 | * When turning on, we need to retry for 1ms to give the sink |
1926 | * When turning on, we need to retry for 1ms to give the sink |
1477 | * time to wake up. |
1927 | * time to wake up. |
Line 1482... | Line 1932... | ||
1482 | if (ret == 1) |
1932 | if (ret == 1) |
1483 | break; |
1933 | break; |
1484 | msleep(1); |
1934 | msleep(1); |
1485 | } |
1935 | } |
1486 | } |
1936 | } |
- | 1937 | ||
- | 1938 | if (ret != 1) |
|
- | 1939 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
|
- | 1940 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
|
1487 | } |
1941 | } |
Line 1488... | Line 1942... | ||
1488 | 1942 | ||
1489 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1943 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1490 | enum pipe *pipe) |
1944 | enum pipe *pipe) |
Line 1495... | Line 1949... | ||
1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
1949 | struct drm_i915_private *dev_priv = dev->dev_private; |
1496 | enum intel_display_power_domain power_domain; |
1950 | enum intel_display_power_domain power_domain; |
1497 | u32 tmp; |
1951 | u32 tmp; |
Line 1498... | Line 1952... | ||
1498 | 1952 | ||
1499 | power_domain = intel_display_port_power_domain(encoder); |
1953 | power_domain = intel_display_port_power_domain(encoder); |
1500 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
1954 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
Line 1501... | Line 1955... | ||
1501 | return false; |
1955 | return false; |
Line 1502... | Line 1956... | ||
1502 | 1956 | ||
Line 1528... | Line 1982... | ||
1528 | break; |
1982 | break; |
1529 | default: |
1983 | default: |
1530 | return true; |
1984 | return true; |
1531 | } |
1985 | } |
Line 1532... | Line 1986... | ||
1532 | 1986 | ||
1533 | for_each_pipe(i) { |
1987 | for_each_pipe(dev_priv, i) { |
1534 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
1988 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
1535 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
1989 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
1536 | *pipe = i; |
1990 | *pipe = i; |
1537 | return true; |
1991 | return true; |
Line 1627... | Line 2081... | ||
1627 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
2081 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
1628 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
2082 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
1629 | } |
2083 | } |
1630 | } |
2084 | } |
Line 1631... | Line -... | ||
1631 | - | ||
1632 | static bool is_edp_psr(struct intel_dp *intel_dp) |
- | |
1633 | { |
- | |
1634 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; |
- | |
1635 | } |
- | |
1636 | - | ||
1637 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
- | |
1638 | { |
- | |
1639 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1640 | - | ||
1641 | if (!HAS_PSR(dev)) |
- | |
1642 | return false; |
- | |
1643 | - | ||
1644 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
- | |
1645 | } |
- | |
1646 | - | ||
1647 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
- | |
1648 | struct edp_vsc_psr *vsc_psr) |
- | |
1649 | { |
- | |
1650 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | |
1651 | struct drm_device *dev = dig_port->base.base.dev; |
- | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1653 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
- | |
1654 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
- | |
1655 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
- | |
1656 | uint32_t *data = (uint32_t *) vsc_psr; |
- | |
1657 | unsigned int i; |
- | |
1658 | - | ||
1659 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
- | |
1660 | the video DIP being updated before program video DIP data buffer |
- | |
1661 | registers for DIP being updated. */ |
- | |
1662 | I915_WRITE(ctl_reg, 0); |
- | |
1663 | POSTING_READ(ctl_reg); |
- | |
1664 | - | ||
1665 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
- | |
1666 | if (i < sizeof(struct edp_vsc_psr)) |
- | |
1667 | I915_WRITE(data_reg + i, *data++); |
- | |
1668 | else |
- | |
1669 | I915_WRITE(data_reg + i, 0); |
- | |
1670 | } |
- | |
1671 | - | ||
1672 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
- | |
1673 | POSTING_READ(ctl_reg); |
- | |
1674 | } |
- | |
1675 | - | ||
1676 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) |
- | |
1677 | { |
- | |
1678 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
1679 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1680 | struct edp_vsc_psr psr_vsc; |
- | |
1681 | - | ||
1682 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
- | |
1683 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
- | |
1684 | psr_vsc.sdp_header.HB0 = 0; |
- | |
1685 | psr_vsc.sdp_header.HB1 = 0x7; |
- | |
1686 | psr_vsc.sdp_header.HB2 = 0x2; |
- | |
1687 | psr_vsc.sdp_header.HB3 = 0x8; |
- | |
1688 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
- | |
1689 | - | ||
1690 | /* Avoid continuous PSR exit by masking memup and hpd */ |
- | |
1691 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
- | |
1692 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
- | |
1693 | } |
- | |
1694 | - | ||
1695 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
- | |
1696 | { |
- | |
1697 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | |
1698 | struct drm_device *dev = dig_port->base.base.dev; |
- | |
1699 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1700 | uint32_t aux_clock_divider; |
- | |
1701 | int precharge = 0x3; |
- | |
1702 | int msg_size = 5; /* Header(4) + Message(1) */ |
- | |
1703 | bool only_standby = false; |
- | |
1704 | - | ||
1705 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
- | |
1706 | - | ||
1707 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
- | |
1708 | only_standby = true; |
- | |
1709 | - | ||
1710 | /* Enable PSR in sink */ |
- | |
1711 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) |
- | |
1712 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
- | |
1713 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
- | |
1714 | else |
- | |
1715 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
- | |
1716 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
- | |
1717 | - | ||
1718 | /* Setup AUX registers */ |
- | |
1719 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
- | |
1720 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); |
- | |
1721 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
- | |
1722 | DP_AUX_CH_CTL_TIME_OUT_400us | |
- | |
1723 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
- | |
1724 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
- | |
1725 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
- | |
1726 | } |
- | |
1727 | - | ||
1728 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
- | |
1729 | { |
- | |
1730 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | |
1731 | struct drm_device *dev = dig_port->base.base.dev; |
- | |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1733 | uint32_t max_sleep_time = 0x1f; |
- | |
1734 | uint32_t idle_frames = 1; |
- | |
1735 | uint32_t val = 0x0; |
- | |
1736 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
- | |
1737 | bool only_standby = false; |
- | |
1738 | - | ||
1739 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
- | |
1740 | only_standby = true; |
- | |
1741 | - | ||
1742 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { |
- | |
1743 | val |= EDP_PSR_LINK_STANDBY; |
- | |
1744 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
- | |
1745 | val |= EDP_PSR_TP1_TIME_0us; |
- | |
1746 | val |= EDP_PSR_SKIP_AUX_EXIT; |
- | |
1747 | val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; |
- | |
1748 | } else |
- | |
1749 | val |= EDP_PSR_LINK_DISABLE; |
- | |
1750 | - | ||
1751 | I915_WRITE(EDP_PSR_CTL(dev), val | |
- | |
1752 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
- | |
1753 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
- | |
1754 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
- | |
1755 | EDP_PSR_ENABLE); |
- | |
1756 | } |
- | |
1757 | - | ||
1758 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
- | |
1759 | { |
- | |
1760 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
- | |
1761 | struct drm_device *dev = dig_port->base.base.dev; |
- | |
1762 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1763 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
- | |
1764 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
1765 | - | ||
1766 | lockdep_assert_held(&dev_priv->psr.lock); |
- | |
1767 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
- | |
1768 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
- | |
1769 | - | ||
1770 | dev_priv->psr.source_ok = false; |
- | |
1771 | - | ||
1772 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { |
- | |
1773 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
- | |
1774 | return false; |
- | |
1775 | } |
- | |
1776 | - | ||
1777 | if (!i915.enable_psr) { |
- | |
1778 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
- | |
1779 | return false; |
- | |
1780 | } |
- | |
1781 | - | ||
1782 | /* Below limitations aren't valid for Broadwell */ |
- | |
1783 | if (IS_BROADWELL(dev)) |
- | |
1784 | goto out; |
- | |
1785 | - | ||
1786 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
- | |
1787 | S3D_ENABLE) { |
- | |
1788 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
- | |
1789 | return false; |
- | |
1790 | } |
- | |
1791 | - | ||
1792 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
- | |
1793 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
- | |
1794 | return false; |
- | |
1795 | } |
- | |
1796 | - | ||
1797 | out: |
- | |
1798 | dev_priv->psr.source_ok = true; |
- | |
1799 | return true; |
- | |
1800 | } |
- | |
1801 | - | ||
1802 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
- | |
1803 | { |
- | |
1804 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
1805 | struct drm_device *dev = intel_dig_port->base.base.dev; |
- | |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1807 | - | ||
1808 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
- | |
1809 | WARN_ON(dev_priv->psr.active); |
- | |
1810 | lockdep_assert_held(&dev_priv->psr.lock); |
- | |
1811 | - | ||
1812 | /* Enable PSR on the panel */ |
- | |
1813 | intel_edp_psr_enable_sink(intel_dp); |
- | |
1814 | - | ||
1815 | /* Enable PSR on the host */ |
- | |
1816 | intel_edp_psr_enable_source(intel_dp); |
- | |
1817 | - | ||
1818 | dev_priv->psr.active = true; |
- | |
1819 | } |
- | |
1820 | - | ||
1821 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
- | |
1822 | { |
- | |
1823 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
1824 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1825 | - | ||
1826 | if (!HAS_PSR(dev)) { |
- | |
1827 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
- | |
1828 | return; |
- | |
1829 | } |
- | |
1830 | - | ||
1831 | if (!is_edp_psr(intel_dp)) { |
- | |
1832 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); |
- | |
1833 | return; |
- | |
1834 | } |
- | |
1835 | - | ||
1836 | mutex_lock(&dev_priv->psr.lock); |
- | |
1837 | if (dev_priv->psr.enabled) { |
- | |
1838 | DRM_DEBUG_KMS("PSR already in use\n"); |
- | |
1839 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1840 | return; |
- | |
1841 | } |
- | |
1842 | - | ||
1843 | dev_priv->psr.busy_frontbuffer_bits = 0; |
- | |
1844 | - | ||
1845 | /* Setup PSR once */ |
- | |
1846 | intel_edp_psr_setup(intel_dp); |
- | |
1847 | - | ||
1848 | if (intel_edp_psr_match_conditions(intel_dp)) |
- | |
1849 | dev_priv->psr.enabled = intel_dp; |
- | |
1850 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1851 | } |
- | |
1852 | - | ||
1853 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
- | |
1854 | { |
- | |
1855 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
1856 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1857 | - | ||
1858 | mutex_lock(&dev_priv->psr.lock); |
- | |
1859 | if (!dev_priv->psr.enabled) { |
- | |
1860 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1861 | return; |
- | |
1862 | } |
- | |
1863 | - | ||
1864 | if (dev_priv->psr.active) { |
- | |
1865 | I915_WRITE(EDP_PSR_CTL(dev), |
- | |
1866 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
- | |
1867 | - | ||
1868 | /* Wait till PSR is idle */ |
- | |
1869 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
- | |
1870 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
- | |
1871 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
- | |
1872 | - | ||
1873 | dev_priv->psr.active = false; |
- | |
1874 | } else { |
- | |
1875 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
- | |
1876 | } |
- | |
1877 | - | ||
1878 | dev_priv->psr.enabled = NULL; |
- | |
1879 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1880 | - | ||
1881 | cancel_delayed_work_sync(&dev_priv->psr.work); |
- | |
1882 | } |
- | |
1883 | - | ||
1884 | static void intel_edp_psr_work(struct work_struct *work) |
- | |
1885 | { |
- | |
1886 | struct drm_i915_private *dev_priv = |
- | |
1887 | container_of(work, typeof(*dev_priv), psr.work.work); |
- | |
1888 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
- | |
1889 | - | ||
1890 | mutex_lock(&dev_priv->psr.lock); |
- | |
1891 | intel_dp = dev_priv->psr.enabled; |
- | |
1892 | - | ||
1893 | if (!intel_dp) |
- | |
1894 | goto unlock; |
- | |
1895 | - | ||
1896 | /* |
- | |
1897 | * The delayed work can race with an invalidate hence we need to |
- | |
1898 | * recheck. Since psr_flush first clears this and then reschedules we |
- | |
1899 | * won't ever miss a flush when bailing out here. |
- | |
1900 | */ |
- | |
1901 | if (dev_priv->psr.busy_frontbuffer_bits) |
- | |
1902 | goto unlock; |
- | |
1903 | - | ||
1904 | intel_edp_psr_do_enable(intel_dp); |
- | |
1905 | unlock: |
- | |
1906 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1907 | } |
- | |
1908 | - | ||
1909 | static void intel_edp_psr_do_exit(struct drm_device *dev) |
- | |
1910 | { |
- | |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1912 | - | ||
1913 | if (dev_priv->psr.active) { |
- | |
1914 | u32 val = I915_READ(EDP_PSR_CTL(dev)); |
- | |
1915 | - | ||
1916 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
- | |
1917 | - | ||
1918 | I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); |
- | |
1919 | - | ||
1920 | dev_priv->psr.active = false; |
- | |
1921 | } |
- | |
1922 | - | ||
1923 | } |
- | |
1924 | - | ||
1925 | void intel_edp_psr_invalidate(struct drm_device *dev, |
- | |
1926 | unsigned frontbuffer_bits) |
- | |
1927 | { |
- | |
1928 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1929 | struct drm_crtc *crtc; |
- | |
1930 | enum pipe pipe; |
- | |
1931 | - | ||
1932 | mutex_lock(&dev_priv->psr.lock); |
- | |
1933 | if (!dev_priv->psr.enabled) { |
- | |
1934 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1935 | return; |
- | |
1936 | } |
- | |
1937 | - | ||
1938 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
- | |
1939 | pipe = to_intel_crtc(crtc)->pipe; |
- | |
1940 | - | ||
1941 | intel_edp_psr_do_exit(dev); |
- | |
1942 | - | ||
1943 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
- | |
1944 | - | ||
1945 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
- | |
1946 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1947 | } |
- | |
1948 | - | ||
1949 | void intel_edp_psr_flush(struct drm_device *dev, |
- | |
1950 | unsigned frontbuffer_bits) |
- | |
1951 | { |
- | |
1952 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1953 | struct drm_crtc *crtc; |
- | |
1954 | enum pipe pipe; |
- | |
1955 | - | ||
1956 | mutex_lock(&dev_priv->psr.lock); |
- | |
1957 | if (!dev_priv->psr.enabled) { |
- | |
1958 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1959 | return; |
- | |
1960 | } |
- | |
1961 | - | ||
1962 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
- | |
1963 | pipe = to_intel_crtc(crtc)->pipe; |
- | |
1964 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
- | |
1965 | - | ||
1966 | /* |
- | |
1967 | * On Haswell sprite plane updates don't result in a psr invalidating |
- | |
1968 | * signal in the hardware. Which means we need to manually fake this in |
- | |
1969 | * software for all flushes, not just when we've seen a preceding |
- | |
1970 | * invalidation through frontbuffer rendering. |
- | |
1971 | */ |
- | |
1972 | if (IS_HASWELL(dev) && |
- | |
1973 | (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) |
- | |
1974 | intel_edp_psr_do_exit(dev); |
- | |
1975 | - | ||
1976 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
- | |
1977 | schedule_delayed_work(&dev_priv->psr.work, |
- | |
1978 | msecs_to_jiffies(100)); |
- | |
1979 | mutex_unlock(&dev_priv->psr.lock); |
- | |
1980 | } |
- | |
1981 | - | ||
1982 | void intel_edp_psr_init(struct drm_device *dev) |
- | |
1983 | { |
- | |
1984 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1985 | - | ||
1986 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); |
- | |
1987 | mutex_init(&dev_priv->psr.lock); |
- | |
1988 | } |
- | |
1989 | 2085 | ||
1990 | static void intel_disable_dp(struct intel_encoder *encoder) |
2086 | static void intel_disable_dp(struct intel_encoder *encoder) |
1991 | { |
2087 | { |
1992 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
- | |
1993 | enum port port = dp_to_dig_port(intel_dp)->port; |
2088 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
- | 2089 | struct drm_device *dev = encoder->base.dev; |
|
- | 2090 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
|
- | 2091 | ||
- | 2092 | if (crtc->config.has_audio) |
|
Line 1994... | Line 2093... | ||
1994 | struct drm_device *dev = encoder->base.dev; |
2093 | intel_audio_codec_disable(encoder); |
1995 | 2094 | ||
1996 | /* Make sure the panel is off before trying to change the mode. But also |
2095 | /* Make sure the panel is off before trying to change the mode. But also |
1997 | * ensure that we have vdd while we switch off the panel. */ |
2096 | * ensure that we have vdd while we switch off the panel. */ |
1998 | intel_edp_panel_vdd_on(intel_dp); |
2097 | intel_edp_panel_vdd_on(intel_dp); |
1999 | intel_edp_backlight_off(intel_dp); |
2098 | intel_edp_backlight_off(intel_dp); |
Line 2000... | Line 2099... | ||
2000 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2099 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2001 | intel_edp_panel_off(intel_dp); |
2100 | intel_edp_panel_off(intel_dp); |
2002 | 2101 | ||
2003 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
2102 | /* disable the port before the pipe on g4x */ |
Line 2004... | Line 2103... | ||
2004 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
2103 | if (INTEL_INFO(dev)->gen < 5) |
2005 | intel_dp_link_down(intel_dp); |
2104 | intel_dp_link_down(intel_dp); |
2006 | } |
2105 | } |
2007 | 2106 | ||
Line 2008... | Line -... | ||
2008 | static void g4x_post_disable_dp(struct intel_encoder *encoder) |
- | |
2009 | { |
- | |
2010 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
- | |
2011 | enum port port = dp_to_dig_port(intel_dp)->port; |
2107 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
- | 2108 | { |
|
2012 | 2109 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
2013 | if (port != PORT_A) |
2110 | enum port port = dp_to_dig_port(intel_dp)->port; |
Line 2014... | Line 2111... | ||
2014 | return; |
2111 | |
2015 | 2112 | intel_dp_link_down(intel_dp); |
|
Line 2058... | Line 2155... | ||
2058 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
2155 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
Line 2059... | Line 2156... | ||
2059 | 2156 | ||
2060 | mutex_unlock(&dev_priv->dpio_lock); |
2157 | mutex_unlock(&dev_priv->dpio_lock); |
Line -... | Line 2158... | ||
- | 2158 | } |
|
- | 2159 | ||
- | 2160 | static void |
|
- | 2161 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
|
- | 2162 | uint32_t *DP, |
|
- | 2163 | uint8_t dp_train_pat) |
|
- | 2164 | { |
|
- | 2165 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 2166 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 2167 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2168 | enum port port = intel_dig_port->port; |
|
- | 2169 | ||
- | 2170 | if (HAS_DDI(dev)) { |
|
- | 2171 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
|
- | 2172 | ||
- | 2173 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
|
- | 2174 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
|
- | 2175 | else |
|
- | 2176 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
|
- | 2177 | ||
- | 2178 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
|
- | 2179 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
|
- | 2180 | case DP_TRAINING_PATTERN_DISABLE: |
|
- | 2181 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
|
- | 2182 | ||
- | 2183 | break; |
|
- | 2184 | case DP_TRAINING_PATTERN_1: |
|
- | 2185 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
|
- | 2186 | break; |
|
- | 2187 | case DP_TRAINING_PATTERN_2: |
|
- | 2188 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
|
- | 2189 | break; |
|
- | 2190 | case DP_TRAINING_PATTERN_3: |
|
- | 2191 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
|
- | 2192 | break; |
|
- | 2193 | } |
|
- | 2194 | I915_WRITE(DP_TP_CTL(port), temp); |
|
- | 2195 | ||
- | 2196 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
|
- | 2197 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
|
- | 2198 | ||
- | 2199 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
|
- | 2200 | case DP_TRAINING_PATTERN_DISABLE: |
|
- | 2201 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
|
- | 2202 | break; |
|
- | 2203 | case DP_TRAINING_PATTERN_1: |
|
- | 2204 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
|
- | 2205 | break; |
|
- | 2206 | case DP_TRAINING_PATTERN_2: |
|
- | 2207 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
|
- | 2208 | break; |
|
- | 2209 | case DP_TRAINING_PATTERN_3: |
|
- | 2210 | DRM_ERROR("DP training pattern 3 not supported\n"); |
|
- | 2211 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
|
- | 2212 | break; |
|
- | 2213 | } |
|
- | 2214 | ||
- | 2215 | } else { |
|
- | 2216 | if (IS_CHERRYVIEW(dev)) |
|
- | 2217 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
|
- | 2218 | else |
|
- | 2219 | *DP &= ~DP_LINK_TRAIN_MASK; |
|
- | 2220 | ||
- | 2221 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
|
- | 2222 | case DP_TRAINING_PATTERN_DISABLE: |
|
- | 2223 | *DP |= DP_LINK_TRAIN_OFF; |
|
- | 2224 | break; |
|
- | 2225 | case DP_TRAINING_PATTERN_1: |
|
- | 2226 | *DP |= DP_LINK_TRAIN_PAT_1; |
|
- | 2227 | break; |
|
- | 2228 | case DP_TRAINING_PATTERN_2: |
|
- | 2229 | *DP |= DP_LINK_TRAIN_PAT_2; |
|
- | 2230 | break; |
|
- | 2231 | case DP_TRAINING_PATTERN_3: |
|
- | 2232 | if (IS_CHERRYVIEW(dev)) { |
|
- | 2233 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
|
- | 2234 | } else { |
|
- | 2235 | DRM_ERROR("DP training pattern 3 not supported\n"); |
|
- | 2236 | *DP |= DP_LINK_TRAIN_PAT_2; |
|
- | 2237 | } |
|
- | 2238 | break; |
|
- | 2239 | } |
|
- | 2240 | } |
|
- | 2241 | } |
|
- | 2242 | ||
- | 2243 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
|
- | 2244 | { |
|
- | 2245 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 2246 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2247 | ||
- | 2248 | /* enable with pattern 1 (as per spec) */ |
|
- | 2249 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
|
- | 2250 | DP_TRAINING_PATTERN_1); |
|
- | 2251 | ||
- | 2252 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
|
- | 2253 | POSTING_READ(intel_dp->output_reg); |
|
- | 2254 | ||
- | 2255 | /* |
|
- | 2256 | * Magic for VLV/CHV. We _must_ first set up the register |
|
- | 2257 | * without actually enabling the port, and then do another |
|
- | 2258 | * write to enable the port. Otherwise link training will |
|
- | 2259 | * fail when the power sequencer is freshly used for this port. |
|
- | 2260 | */ |
|
- | 2261 | intel_dp->DP |= DP_PORT_EN; |
|
- | 2262 | ||
- | 2263 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
|
- | 2264 | POSTING_READ(intel_dp->output_reg); |
|
2061 | } |
2265 | } |
2062 | 2266 | ||
2063 | static void intel_enable_dp(struct intel_encoder *encoder) |
2267 | static void intel_enable_dp(struct intel_encoder *encoder) |
2064 | { |
2268 | { |
2065 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2269 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
- | 2270 | struct drm_device *dev = encoder->base.dev; |
|
2066 | struct drm_device *dev = encoder->base.dev; |
2271 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 2067... | Line 2272... | ||
2067 | struct drm_i915_private *dev_priv = dev->dev_private; |
2272 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2068 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2273 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Line -... | Line 2274... | ||
- | 2274 | ||
- | 2275 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
|
- | 2276 | return; |
|
- | 2277 | ||
- | 2278 | pps_lock(intel_dp); |
|
- | 2279 | ||
- | 2280 | if (IS_VALLEYVIEW(dev)) |
|
2069 | 2281 | vlv_init_panel_power_sequencer(intel_dp); |
|
- | 2282 | ||
- | 2283 | intel_dp_enable_port(intel_dp); |
|
- | 2284 | ||
- | 2285 | edp_panel_vdd_on(intel_dp); |
|
- | 2286 | edp_panel_on(intel_dp); |
|
- | 2287 | edp_panel_vdd_off(intel_dp, true); |
|
- | 2288 | ||
- | 2289 | pps_unlock(intel_dp); |
|
2070 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2290 | |
2071 | return; |
2291 | if (IS_VALLEYVIEW(dev)) |
2072 | - | ||
2073 | intel_edp_panel_vdd_on(intel_dp); |
- | |
2074 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2292 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp)); |
2075 | intel_dp_start_link_train(intel_dp); |
2293 | |
- | 2294 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
|
- | 2295 | intel_dp_start_link_train(intel_dp); |
|
- | 2296 | intel_dp_complete_link_train(intel_dp); |
|
- | 2297 | intel_dp_stop_link_train(intel_dp); |
|
- | 2298 | ||
- | 2299 | if (crtc->config.has_audio) { |
|
2076 | intel_edp_panel_on(intel_dp); |
2300 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
Line 2077... | Line 2301... | ||
2077 | edp_panel_vdd_off(intel_dp, true); |
2301 | pipe_name(crtc->pipe)); |
2078 | intel_dp_complete_link_train(intel_dp); |
2302 | intel_audio_codec_enable(encoder); |
2079 | intel_dp_stop_link_train(intel_dp); |
2303 | } |
Line 2106... | Line 2330... | ||
2106 | ironlake_set_pll_cpu_edp(intel_dp); |
2330 | ironlake_set_pll_cpu_edp(intel_dp); |
2107 | ironlake_edp_pll_on(intel_dp); |
2331 | ironlake_edp_pll_on(intel_dp); |
2108 | } |
2332 | } |
2109 | } |
2333 | } |
Line -... | Line 2334... | ||
- | 2334 | ||
- | 2335 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
|
- | 2336 | { |
|
- | 2337 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 2338 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
|
- | 2339 | enum pipe pipe = intel_dp->pps_pipe; |
|
- | 2340 | int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
|
- | 2341 | ||
- | 2342 | edp_panel_vdd_off_sync(intel_dp); |
|
- | 2343 | ||
- | 2344 | /* |
|
- | 2345 | * VLV seems to get confused when multiple power seqeuencers |
|
- | 2346 | * have the same port selected (even if only one has power/vdd |
|
- | 2347 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
|
- | 2348 | * CHV on the other hand doesn't seem to mind having the same port |
|
- | 2349 | * selected in multiple power seqeuencers, but let's clear the |
|
- | 2350 | * port select always when logically disconnecting a power sequencer |
|
- | 2351 | * from a port. |
|
- | 2352 | */ |
|
- | 2353 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
|
- | 2354 | pipe_name(pipe), port_name(intel_dig_port->port)); |
|
- | 2355 | I915_WRITE(pp_on_reg, 0); |
|
- | 2356 | POSTING_READ(pp_on_reg); |
|
- | 2357 | ||
- | 2358 | intel_dp->pps_pipe = INVALID_PIPE; |
|
- | 2359 | } |
|
- | 2360 | ||
- | 2361 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
|
- | 2362 | enum pipe pipe) |
|
- | 2363 | { |
|
- | 2364 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2365 | struct intel_encoder *encoder; |
|
- | 2366 | ||
- | 2367 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 2368 | ||
- | 2369 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
|
- | 2370 | return; |
|
- | 2371 | ||
- | 2372 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
|
- | 2373 | base.head) { |
|
- | 2374 | struct intel_dp *intel_dp; |
|
- | 2375 | enum port port; |
|
- | 2376 | ||
- | 2377 | if (encoder->type != INTEL_OUTPUT_EDP) |
|
- | 2378 | continue; |
|
- | 2379 | ||
- | 2380 | intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2381 | port = dp_to_dig_port(intel_dp)->port; |
|
- | 2382 | ||
- | 2383 | if (intel_dp->pps_pipe != pipe) |
|
- | 2384 | continue; |
|
- | 2385 | ||
- | 2386 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
|
- | 2387 | pipe_name(pipe), port_name(port)); |
|
- | 2388 | ||
- | 2389 | WARN(encoder->connectors_active, |
|
- | 2390 | "stealing pipe %c power sequencer from active eDP port %c\n", |
|
- | 2391 | pipe_name(pipe), port_name(port)); |
|
- | 2392 | ||
- | 2393 | /* make sure vdd is off before we steal it */ |
|
- | 2394 | vlv_detach_power_sequencer(intel_dp); |
|
- | 2395 | } |
|
- | 2396 | } |
|
- | 2397 | ||
- | 2398 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
|
- | 2399 | { |
|
- | 2400 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 2401 | struct intel_encoder *encoder = &intel_dig_port->base; |
|
- | 2402 | struct drm_device *dev = encoder->base.dev; |
|
- | 2403 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2404 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
|
- | 2405 | ||
- | 2406 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 2407 | ||
- | 2408 | if (!is_edp(intel_dp)) |
|
- | 2409 | return; |
|
- | 2410 | ||
- | 2411 | if (intel_dp->pps_pipe == crtc->pipe) |
|
- | 2412 | return; |
|
- | 2413 | ||
- | 2414 | /* |
|
- | 2415 | * If another power sequencer was being used on this |
|
- | 2416 | * port previously make sure to turn off vdd there while |
|
- | 2417 | * we still have control of it. |
|
- | 2418 | */ |
|
- | 2419 | if (intel_dp->pps_pipe != INVALID_PIPE) |
|
- | 2420 | vlv_detach_power_sequencer(intel_dp); |
|
- | 2421 | ||
- | 2422 | /* |
|
- | 2423 | * We may be stealing the power |
|
- | 2424 | * sequencer from another port. |
|
- | 2425 | */ |
|
- | 2426 | vlv_steal_power_sequencer(dev, crtc->pipe); |
|
- | 2427 | ||
- | 2428 | /* now it's all ours */ |
|
- | 2429 | intel_dp->pps_pipe = crtc->pipe; |
|
- | 2430 | ||
- | 2431 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
|
- | 2432 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
|
- | 2433 | ||
- | 2434 | /* init power sequencer on this pipe and port */ |
|
- | 2435 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
|
- | 2436 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
|
- | 2437 | } |
|
2110 | 2438 | ||
2111 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2439 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2112 | { |
2440 | { |
2113 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2441 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2114 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2442 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2115 | struct drm_device *dev = encoder->base.dev; |
2443 | struct drm_device *dev = encoder->base.dev; |
2116 | struct drm_i915_private *dev_priv = dev->dev_private; |
2444 | struct drm_i915_private *dev_priv = dev->dev_private; |
2117 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2445 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2118 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2446 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2119 | int pipe = intel_crtc->pipe; |
- | |
2120 | struct edp_power_seq power_seq; |
2447 | int pipe = intel_crtc->pipe; |
Line 2121... | Line 2448... | ||
2121 | u32 val; |
2448 | u32 val; |
Line 2122... | Line 2449... | ||
2122 | 2449 | ||
Line 2133... | Line 2460... | ||
2133 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2460 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2134 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2461 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
Line 2135... | Line 2462... | ||
2135 | 2462 | ||
Line 2136... | Line -... | ||
2136 | mutex_unlock(&dev_priv->dpio_lock); |
- | |
2137 | - | ||
2138 | if (is_edp(intel_dp)) { |
- | |
2139 | /* init power sequencer on this pipe and port */ |
- | |
2140 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
- | |
2141 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
- | |
2142 | &power_seq); |
- | |
2143 | } |
2463 | mutex_unlock(&dev_priv->dpio_lock); |
2144 | - | ||
2145 | intel_enable_dp(encoder); |
- | |
2146 | 2464 | ||
Line 2147... | Line 2465... | ||
2147 | vlv_wait_port_ready(dev_priv, dport); |
2465 | intel_enable_dp(encoder); |
2148 | } |
2466 | } |
2149 | 2467 | ||
Line 2181... | Line 2499... | ||
2181 | { |
2499 | { |
2182 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2500 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2183 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2501 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2184 | struct drm_device *dev = encoder->base.dev; |
2502 | struct drm_device *dev = encoder->base.dev; |
2185 | struct drm_i915_private *dev_priv = dev->dev_private; |
2503 | struct drm_i915_private *dev_priv = dev->dev_private; |
2186 | struct edp_power_seq power_seq; |
- | |
2187 | struct intel_crtc *intel_crtc = |
2504 | struct intel_crtc *intel_crtc = |
2188 | to_intel_crtc(encoder->base.crtc); |
2505 | to_intel_crtc(encoder->base.crtc); |
2189 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2506 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2190 | int pipe = intel_crtc->pipe; |
2507 | int pipe = intel_crtc->pipe; |
2191 | int data, i; |
2508 | int data, i; |
2192 | u32 val; |
2509 | u32 val; |
Line 2193... | Line 2510... | ||
2193 | 2510 | ||
Line -... | Line 2511... | ||
- | 2511 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2512 | ||
- | 2513 | /* allow hardware to manage TX FIFO reset source */ |
|
- | 2514 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
|
- | 2515 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
|
- | 2516 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
|
- | 2517 | ||
- | 2518 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
|
- | 2519 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
|
2194 | mutex_lock(&dev_priv->dpio_lock); |
2520 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2195 | 2521 | ||
2196 | /* Deassert soft data lane reset*/ |
2522 | /* Deassert soft data lane reset*/ |
2197 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
2523 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
Line 2226... | Line 2552... | ||
2226 | /* Data lane stagger programming */ |
2552 | /* Data lane stagger programming */ |
2227 | /* FIXME: Fix up value only after power analysis */ |
2553 | /* FIXME: Fix up value only after power analysis */ |
Line 2228... | Line 2554... | ||
2228 | 2554 | ||
Line 2229... | Line -... | ||
2229 | mutex_unlock(&dev_priv->dpio_lock); |
- | |
2230 | - | ||
2231 | if (is_edp(intel_dp)) { |
- | |
2232 | /* init power sequencer on this pipe and port */ |
- | |
2233 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
- | |
2234 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
- | |
2235 | &power_seq); |
- | |
2236 | } |
2555 | mutex_unlock(&dev_priv->dpio_lock); |
2237 | - | ||
2238 | intel_enable_dp(encoder); |
- | |
2239 | 2556 | ||
Line 2240... | Line 2557... | ||
2240 | vlv_wait_port_ready(dev_priv, dport); |
2557 | intel_enable_dp(encoder); |
2241 | } |
2558 | } |
2242 | 2559 | ||
Line 2249... | Line 2566... | ||
2249 | to_intel_crtc(encoder->base.crtc); |
2566 | to_intel_crtc(encoder->base.crtc); |
2250 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2567 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2251 | enum pipe pipe = intel_crtc->pipe; |
2568 | enum pipe pipe = intel_crtc->pipe; |
2252 | u32 val; |
2569 | u32 val; |
Line -... | Line 2570... | ||
- | 2570 | ||
- | 2571 | intel_dp_prepare(encoder); |
|
2253 | 2572 | ||
Line 2254... | Line 2573... | ||
2254 | mutex_lock(&dev_priv->dpio_lock); |
2573 | mutex_lock(&dev_priv->dpio_lock); |
2255 | 2574 | ||
2256 | /* program left/right clock distribution */ |
2575 | /* program left/right clock distribution */ |
Line 2316... | Line 2635... | ||
2316 | void *buffer, size_t size) |
2635 | void *buffer, size_t size) |
2317 | { |
2636 | { |
2318 | ssize_t ret; |
2637 | ssize_t ret; |
2319 | int i; |
2638 | int i; |
Line -... | Line 2639... | ||
- | 2639 | ||
- | 2640 | /* |
|
- | 2641 | * Sometime we just get the same incorrect byte repeated |
|
- | 2642 | * over the entire buffer. Doing just one throw away read |
|
- | 2643 | * initially seems to "solve" it. |
|
- | 2644 | */ |
|
- | 2645 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
|
2320 | 2646 | ||
2321 | for (i = 0; i < 3; i++) { |
2647 | for (i = 0; i < 3; i++) { |
2322 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
2648 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
2323 | if (ret == size) |
2649 | if (ret == size) |
2324 | return ret; |
2650 | return ret; |
Line 2346... | Line 2672... | ||
2346 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
2672 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
2347 | { |
2673 | { |
2348 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2674 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2349 | enum port port = dp_to_dig_port(intel_dp)->port; |
2675 | enum port port = dp_to_dig_port(intel_dp)->port; |
Line -... | Line 2676... | ||
- | 2676 | ||
- | 2677 | if (INTEL_INFO(dev)->gen >= 9) |
|
2350 | 2678 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
|
2351 | if (IS_VALLEYVIEW(dev)) |
2679 | else if (IS_VALLEYVIEW(dev)) |
2352 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2680 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
2353 | else if (IS_GEN7(dev) && port == PORT_A) |
2681 | else if (IS_GEN7(dev) && port == PORT_A) |
2354 | return DP_TRAIN_VOLTAGE_SWING_800; |
2682 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
2355 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
2683 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
2356 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2684 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
2357 | else |
2685 | else |
2358 | return DP_TRAIN_VOLTAGE_SWING_800; |
2686 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Line 2359... | Line 2687... | ||
2359 | } |
2687 | } |
2360 | 2688 | ||
2361 | static uint8_t |
2689 | static uint8_t |
2362 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2690 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2363 | { |
2691 | { |
Line -... | Line 2692... | ||
- | 2692 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 2693 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
- | 2694 | ||
- | 2695 | if (INTEL_INFO(dev)->gen >= 9) { |
|
- | 2696 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2697 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
|
- | 2698 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
|
- | 2699 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
|
- | 2700 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
|
- | 2701 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
|
- | 2702 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
|
2364 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2703 | default: |
2365 | enum port port = dp_to_dig_port(intel_dp)->port; |
2704 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
2366 | 2705 | } |
|
2367 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2706 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2368 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2707 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2369 | case DP_TRAIN_VOLTAGE_SWING_400: |
2708 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2370 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
2709 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
2371 | case DP_TRAIN_VOLTAGE_SWING_600: |
2710 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2372 | return DP_TRAIN_PRE_EMPHASIS_6; |
2711 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
2373 | case DP_TRAIN_VOLTAGE_SWING_800: |
2712 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2374 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2713 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
2375 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2714 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2376 | default: |
2715 | default: |
2377 | return DP_TRAIN_PRE_EMPHASIS_0; |
2716 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
2378 | } |
2717 | } |
2379 | } else if (IS_VALLEYVIEW(dev)) { |
2718 | } else if (IS_VALLEYVIEW(dev)) { |
2380 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2719 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2381 | case DP_TRAIN_VOLTAGE_SWING_400: |
2720 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2382 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
2721 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
2383 | case DP_TRAIN_VOLTAGE_SWING_600: |
2722 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2384 | return DP_TRAIN_PRE_EMPHASIS_6; |
2723 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
2385 | case DP_TRAIN_VOLTAGE_SWING_800: |
2724 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2386 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2725 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
2387 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2726 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2388 | default: |
2727 | default: |
2389 | return DP_TRAIN_PRE_EMPHASIS_0; |
2728 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
2390 | } |
2729 | } |
2391 | } else if (IS_GEN7(dev) && port == PORT_A) { |
2730 | } else if (IS_GEN7(dev) && port == PORT_A) { |
2392 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2731 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2393 | case DP_TRAIN_VOLTAGE_SWING_400: |
2732 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2394 | return DP_TRAIN_PRE_EMPHASIS_6; |
2733 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
2395 | case DP_TRAIN_VOLTAGE_SWING_600: |
2734 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2396 | case DP_TRAIN_VOLTAGE_SWING_800: |
2735 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2397 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2736 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
2398 | default: |
2737 | default: |
2399 | return DP_TRAIN_PRE_EMPHASIS_0; |
2738 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
2400 | } |
2739 | } |
2401 | } else { |
2740 | } else { |
2402 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2741 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2403 | case DP_TRAIN_VOLTAGE_SWING_400: |
2742 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2404 | return DP_TRAIN_PRE_EMPHASIS_6; |
2743 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
2405 | case DP_TRAIN_VOLTAGE_SWING_600: |
2744 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2406 | return DP_TRAIN_PRE_EMPHASIS_6; |
2745 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
2407 | case DP_TRAIN_VOLTAGE_SWING_800: |
2746 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2408 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2747 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
2409 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2748 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2410 | default: |
2749 | default: |
2411 | return DP_TRAIN_PRE_EMPHASIS_0; |
2750 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Line 2412... | Line 2751... | ||
2412 | } |
2751 | } |
Line 2425... | Line 2764... | ||
2425 | uint8_t train_set = intel_dp->train_set[0]; |
2764 | uint8_t train_set = intel_dp->train_set[0]; |
2426 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2765 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2427 | int pipe = intel_crtc->pipe; |
2766 | int pipe = intel_crtc->pipe; |
Line 2428... | Line 2767... | ||
2428 | 2767 | ||
2429 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2768 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2430 | case DP_TRAIN_PRE_EMPHASIS_0: |
2769 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
2431 | preemph_reg_value = 0x0004000; |
2770 | preemph_reg_value = 0x0004000; |
2432 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2771 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2433 | case DP_TRAIN_VOLTAGE_SWING_400: |
2772 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2434 | demph_reg_value = 0x2B405555; |
2773 | demph_reg_value = 0x2B405555; |
2435 | uniqtranscale_reg_value = 0x552AB83A; |
2774 | uniqtranscale_reg_value = 0x552AB83A; |
2436 | break; |
2775 | break; |
2437 | case DP_TRAIN_VOLTAGE_SWING_600: |
2776 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2438 | demph_reg_value = 0x2B404040; |
2777 | demph_reg_value = 0x2B404040; |
2439 | uniqtranscale_reg_value = 0x5548B83A; |
2778 | uniqtranscale_reg_value = 0x5548B83A; |
2440 | break; |
2779 | break; |
2441 | case DP_TRAIN_VOLTAGE_SWING_800: |
2780 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2442 | demph_reg_value = 0x2B245555; |
2781 | demph_reg_value = 0x2B245555; |
2443 | uniqtranscale_reg_value = 0x5560B83A; |
2782 | uniqtranscale_reg_value = 0x5560B83A; |
2444 | break; |
2783 | break; |
2445 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2784 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2446 | demph_reg_value = 0x2B405555; |
2785 | demph_reg_value = 0x2B405555; |
2447 | uniqtranscale_reg_value = 0x5598DA3A; |
2786 | uniqtranscale_reg_value = 0x5598DA3A; |
2448 | break; |
2787 | break; |
2449 | default: |
2788 | default: |
2450 | return 0; |
2789 | return 0; |
2451 | } |
2790 | } |
2452 | break; |
2791 | break; |
2453 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
2792 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
2454 | preemph_reg_value = 0x0002000; |
2793 | preemph_reg_value = 0x0002000; |
2455 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2794 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2456 | case DP_TRAIN_VOLTAGE_SWING_400: |
2795 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2457 | demph_reg_value = 0x2B404040; |
2796 | demph_reg_value = 0x2B404040; |
2458 | uniqtranscale_reg_value = 0x5552B83A; |
2797 | uniqtranscale_reg_value = 0x5552B83A; |
2459 | break; |
2798 | break; |
2460 | case DP_TRAIN_VOLTAGE_SWING_600: |
2799 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2461 | demph_reg_value = 0x2B404848; |
2800 | demph_reg_value = 0x2B404848; |
2462 | uniqtranscale_reg_value = 0x5580B83A; |
2801 | uniqtranscale_reg_value = 0x5580B83A; |
2463 | break; |
2802 | break; |
2464 | case DP_TRAIN_VOLTAGE_SWING_800: |
2803 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2465 | demph_reg_value = 0x2B404040; |
2804 | demph_reg_value = 0x2B404040; |
2466 | uniqtranscale_reg_value = 0x55ADDA3A; |
2805 | uniqtranscale_reg_value = 0x55ADDA3A; |
2467 | break; |
2806 | break; |
2468 | default: |
2807 | default: |
2469 | return 0; |
2808 | return 0; |
2470 | } |
2809 | } |
2471 | break; |
2810 | break; |
2472 | case DP_TRAIN_PRE_EMPHASIS_6: |
2811 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
2473 | preemph_reg_value = 0x0000000; |
2812 | preemph_reg_value = 0x0000000; |
2474 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2813 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2475 | case DP_TRAIN_VOLTAGE_SWING_400: |
2814 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2476 | demph_reg_value = 0x2B305555; |
2815 | demph_reg_value = 0x2B305555; |
2477 | uniqtranscale_reg_value = 0x5570B83A; |
2816 | uniqtranscale_reg_value = 0x5570B83A; |
2478 | break; |
2817 | break; |
2479 | case DP_TRAIN_VOLTAGE_SWING_600: |
2818 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2480 | demph_reg_value = 0x2B2B4040; |
2819 | demph_reg_value = 0x2B2B4040; |
2481 | uniqtranscale_reg_value = 0x55ADDA3A; |
2820 | uniqtranscale_reg_value = 0x55ADDA3A; |
2482 | break; |
2821 | break; |
2483 | default: |
2822 | default: |
2484 | return 0; |
2823 | return 0; |
2485 | } |
2824 | } |
2486 | break; |
2825 | break; |
2487 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
2826 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
2488 | preemph_reg_value = 0x0006000; |
2827 | preemph_reg_value = 0x0006000; |
2489 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2828 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2490 | case DP_TRAIN_VOLTAGE_SWING_400: |
2829 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2491 | demph_reg_value = 0x1B405555; |
2830 | demph_reg_value = 0x1B405555; |
2492 | uniqtranscale_reg_value = 0x55ADDA3A; |
2831 | uniqtranscale_reg_value = 0x55ADDA3A; |
2493 | break; |
2832 | break; |
2494 | default: |
2833 | default: |
Line 2524... | Line 2863... | ||
2524 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2863 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2525 | enum pipe pipe = intel_crtc->pipe; |
2864 | enum pipe pipe = intel_crtc->pipe; |
2526 | int i; |
2865 | int i; |
Line 2527... | Line 2866... | ||
2527 | 2866 | ||
2528 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2867 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2529 | case DP_TRAIN_PRE_EMPHASIS_0: |
2868 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
2530 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2869 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2531 | case DP_TRAIN_VOLTAGE_SWING_400: |
2870 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2532 | deemph_reg_value = 128; |
2871 | deemph_reg_value = 128; |
2533 | margin_reg_value = 52; |
2872 | margin_reg_value = 52; |
2534 | break; |
2873 | break; |
2535 | case DP_TRAIN_VOLTAGE_SWING_600: |
2874 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2536 | deemph_reg_value = 128; |
2875 | deemph_reg_value = 128; |
2537 | margin_reg_value = 77; |
2876 | margin_reg_value = 77; |
2538 | break; |
2877 | break; |
2539 | case DP_TRAIN_VOLTAGE_SWING_800: |
2878 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2540 | deemph_reg_value = 128; |
2879 | deemph_reg_value = 128; |
2541 | margin_reg_value = 102; |
2880 | margin_reg_value = 102; |
2542 | break; |
2881 | break; |
2543 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2882 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2544 | deemph_reg_value = 128; |
2883 | deemph_reg_value = 128; |
2545 | margin_reg_value = 154; |
2884 | margin_reg_value = 154; |
2546 | /* FIXME extra to set for 1200 */ |
2885 | /* FIXME extra to set for 1200 */ |
2547 | break; |
2886 | break; |
2548 | default: |
2887 | default: |
2549 | return 0; |
2888 | return 0; |
2550 | } |
2889 | } |
2551 | break; |
2890 | break; |
2552 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
2891 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
2553 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2892 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2554 | case DP_TRAIN_VOLTAGE_SWING_400: |
2893 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2555 | deemph_reg_value = 85; |
2894 | deemph_reg_value = 85; |
2556 | margin_reg_value = 78; |
2895 | margin_reg_value = 78; |
2557 | break; |
2896 | break; |
2558 | case DP_TRAIN_VOLTAGE_SWING_600: |
2897 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2559 | deemph_reg_value = 85; |
2898 | deemph_reg_value = 85; |
2560 | margin_reg_value = 116; |
2899 | margin_reg_value = 116; |
2561 | break; |
2900 | break; |
2562 | case DP_TRAIN_VOLTAGE_SWING_800: |
2901 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2563 | deemph_reg_value = 85; |
2902 | deemph_reg_value = 85; |
2564 | margin_reg_value = 154; |
2903 | margin_reg_value = 154; |
2565 | break; |
2904 | break; |
2566 | default: |
2905 | default: |
2567 | return 0; |
2906 | return 0; |
2568 | } |
2907 | } |
2569 | break; |
2908 | break; |
2570 | case DP_TRAIN_PRE_EMPHASIS_6: |
2909 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
2571 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2910 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2572 | case DP_TRAIN_VOLTAGE_SWING_400: |
2911 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2573 | deemph_reg_value = 64; |
2912 | deemph_reg_value = 64; |
2574 | margin_reg_value = 104; |
2913 | margin_reg_value = 104; |
2575 | break; |
2914 | break; |
2576 | case DP_TRAIN_VOLTAGE_SWING_600: |
2915 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2577 | deemph_reg_value = 64; |
2916 | deemph_reg_value = 64; |
2578 | margin_reg_value = 154; |
2917 | margin_reg_value = 154; |
2579 | break; |
2918 | break; |
2580 | default: |
2919 | default: |
2581 | return 0; |
2920 | return 0; |
2582 | } |
2921 | } |
2583 | break; |
2922 | break; |
2584 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
2923 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
2585 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2924 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2586 | case DP_TRAIN_VOLTAGE_SWING_400: |
2925 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2587 | deemph_reg_value = 43; |
2926 | deemph_reg_value = 43; |
2588 | margin_reg_value = 154; |
2927 | margin_reg_value = 154; |
2589 | break; |
2928 | break; |
2590 | default: |
2929 | default: |
Line 2598... | Line 2937... | ||
2598 | mutex_lock(&dev_priv->dpio_lock); |
2937 | mutex_lock(&dev_priv->dpio_lock); |
Line 2599... | Line 2938... | ||
2599 | 2938 | ||
2600 | /* Clear calc init */ |
2939 | /* Clear calc init */ |
2601 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
2940 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
- | 2941 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
- | 2942 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
|
2602 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
2943 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
Line 2603... | Line 2944... | ||
2603 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
2944 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
2604 | 2945 | ||
- | 2946 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
|
- | 2947 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
2605 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
2948 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
Line -... | Line 2949... | ||
- | 2949 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
|
- | 2950 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
|
- | 2951 | ||
- | 2952 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
|
- | 2953 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
|
- | 2954 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
|
- | 2955 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
|
- | 2956 | ||
- | 2957 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
|
- | 2958 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
|
2606 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
2959 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
2607 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
2960 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
2608 | 2961 | ||
2609 | /* Program swing deemph */ |
2962 | /* Program swing deemph */ |
2610 | for (i = 0; i < 4; i++) { |
2963 | for (i = 0; i < 4; i++) { |
Line 2615... | Line 2968... | ||
2615 | } |
2968 | } |
Line 2616... | Line 2969... | ||
2616 | 2969 | ||
2617 | /* Program swing margin */ |
2970 | /* Program swing margin */ |
2618 | for (i = 0; i < 4; i++) { |
2971 | for (i = 0; i < 4; i++) { |
2619 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
2972 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
2620 | val &= ~DPIO_SWING_MARGIN_MASK; |
2973 | val &= ~DPIO_SWING_MARGIN000_MASK; |
2621 | val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; |
2974 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
2622 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
2975 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
Line 2623... | Line 2976... | ||
2623 | } |
2976 | } |
2624 | 2977 | ||
Line 2628... | Line 2981... | ||
2628 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
2981 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
2629 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
2982 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
2630 | } |
2983 | } |
Line 2631... | Line 2984... | ||
2631 | 2984 | ||
2632 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) |
2985 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) |
2633 | == DP_TRAIN_PRE_EMPHASIS_0) && |
2986 | == DP_TRAIN_PRE_EMPH_LEVEL_0) && |
2634 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
2987 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
Line 2635... | Line 2988... | ||
2635 | == DP_TRAIN_VOLTAGE_SWING_1200)) { |
2988 | == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) { |
2636 | 2989 | ||
2637 | /* |
2990 | /* |
2638 | * The document said it needs to set bit 27 for ch0 and bit 26 |
2991 | * The document said it needs to set bit 27 for ch0 and bit 26 |
Line 2709... | Line 3062... | ||
2709 | intel_gen4_signal_levels(uint8_t train_set) |
3062 | intel_gen4_signal_levels(uint8_t train_set) |
2710 | { |
3063 | { |
2711 | uint32_t signal_levels = 0; |
3064 | uint32_t signal_levels = 0; |
Line 2712... | Line 3065... | ||
2712 | 3065 | ||
2713 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3066 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2714 | case DP_TRAIN_VOLTAGE_SWING_400: |
3067 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2715 | default: |
3068 | default: |
2716 | signal_levels |= DP_VOLTAGE_0_4; |
3069 | signal_levels |= DP_VOLTAGE_0_4; |
2717 | break; |
3070 | break; |
2718 | case DP_TRAIN_VOLTAGE_SWING_600: |
3071 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
2719 | signal_levels |= DP_VOLTAGE_0_6; |
3072 | signal_levels |= DP_VOLTAGE_0_6; |
2720 | break; |
3073 | break; |
2721 | case DP_TRAIN_VOLTAGE_SWING_800: |
3074 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
2722 | signal_levels |= DP_VOLTAGE_0_8; |
3075 | signal_levels |= DP_VOLTAGE_0_8; |
2723 | break; |
3076 | break; |
2724 | case DP_TRAIN_VOLTAGE_SWING_1200: |
3077 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2725 | signal_levels |= DP_VOLTAGE_1_2; |
3078 | signal_levels |= DP_VOLTAGE_1_2; |
2726 | break; |
3079 | break; |
2727 | } |
3080 | } |
2728 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3081 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2729 | case DP_TRAIN_PRE_EMPHASIS_0: |
3082 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
2730 | default: |
3083 | default: |
2731 | signal_levels |= DP_PRE_EMPHASIS_0; |
3084 | signal_levels |= DP_PRE_EMPHASIS_0; |
2732 | break; |
3085 | break; |
2733 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
3086 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
2734 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3087 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
2735 | break; |
3088 | break; |
2736 | case DP_TRAIN_PRE_EMPHASIS_6: |
3089 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
2737 | signal_levels |= DP_PRE_EMPHASIS_6; |
3090 | signal_levels |= DP_PRE_EMPHASIS_6; |
2738 | break; |
3091 | break; |
2739 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
3092 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
2740 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3093 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
2741 | break; |
3094 | break; |
2742 | } |
3095 | } |
2743 | return signal_levels; |
3096 | return signal_levels; |
Line 2748... | Line 3101... | ||
2748 | intel_gen6_edp_signal_levels(uint8_t train_set) |
3101 | intel_gen6_edp_signal_levels(uint8_t train_set) |
2749 | { |
3102 | { |
2750 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3103 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2751 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3104 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2752 | switch (signal_levels) { |
3105 | switch (signal_levels) { |
2753 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3106 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2754 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
3107 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2755 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3108 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
2756 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3109 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2757 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
3110 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
2758 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3111 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2759 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
3112 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2760 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
3113 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
2761 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3114 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2762 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3115 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2763 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
3116 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
2764 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3117 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2765 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
3118 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2766 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
3119 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
2767 | default: |
3120 | default: |
2768 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3121 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2769 | "0x%x\n", signal_levels); |
3122 | "0x%x\n", signal_levels); |
2770 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3123 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Line 2776... | Line 3129... | ||
2776 | intel_gen7_edp_signal_levels(uint8_t train_set) |
3129 | intel_gen7_edp_signal_levels(uint8_t train_set) |
2777 | { |
3130 | { |
2778 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3131 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2779 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3132 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2780 | switch (signal_levels) { |
3133 | switch (signal_levels) { |
2781 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3134 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2782 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
3135 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
2783 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3136 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2784 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
3137 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
2785 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3138 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2786 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3139 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
Line 2787... | Line 3140... | ||
2787 | 3140 | ||
2788 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
3141 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2789 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
3142 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
2790 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3143 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Line 2791... | Line 3144... | ||
2791 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3144 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
2792 | 3145 | ||
2793 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3146 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2794 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
3147 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
Line 2795... | Line 3148... | ||
2795 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3148 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2796 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3149 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
2797 | 3150 | ||
Line 2807... | Line 3160... | ||
2807 | intel_hsw_signal_levels(uint8_t train_set) |
3160 | intel_hsw_signal_levels(uint8_t train_set) |
2808 | { |
3161 | { |
2809 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3162 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2810 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3163 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2811 | switch (signal_levels) { |
3164 | switch (signal_levels) { |
2812 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3165 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2813 | return DDI_BUF_EMP_400MV_0DB_HSW; |
3166 | return DDI_BUF_TRANS_SELECT(0); |
2814 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3167 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2815 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
3168 | return DDI_BUF_TRANS_SELECT(1); |
2816 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3169 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2817 | return DDI_BUF_EMP_400MV_6DB_HSW; |
3170 | return DDI_BUF_TRANS_SELECT(2); |
2818 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
3171 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: |
2819 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
3172 | return DDI_BUF_TRANS_SELECT(3); |
2820 | 3173 | ||
2821 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2822 | return DDI_BUF_EMP_600MV_0DB_HSW; |
3175 | return DDI_BUF_TRANS_SELECT(4); |
2823 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3176 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2824 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
3177 | return DDI_BUF_TRANS_SELECT(5); |
2825 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
3178 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
2826 | return DDI_BUF_EMP_600MV_6DB_HSW; |
3179 | return DDI_BUF_TRANS_SELECT(6); |
2827 | 3180 | ||
2828 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3181 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
2829 | return DDI_BUF_EMP_800MV_0DB_HSW; |
3182 | return DDI_BUF_TRANS_SELECT(7); |
2830 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3183 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
2831 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
3184 | return DDI_BUF_TRANS_SELECT(8); |
2832 | default: |
3185 | default: |
2833 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3186 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2834 | "0x%x\n", signal_levels); |
3187 | "0x%x\n", signal_levels); |
2835 | return DDI_BUF_EMP_400MV_0DB_HSW; |
3188 | return DDI_BUF_TRANS_SELECT(0); |
2836 | } |
3189 | } |
2837 | } |
3190 | } |
Line 2838... | Line 3191... | ||
2838 | 3191 | ||
2839 | /* Properly updates "DP" with the correct signal levels. */ |
3192 | /* Properly updates "DP" with the correct signal levels. */ |
Line 2844... | Line 3197... | ||
2844 | enum port port = intel_dig_port->port; |
3197 | enum port port = intel_dig_port->port; |
2845 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3198 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2846 | uint32_t signal_levels, mask; |
3199 | uint32_t signal_levels, mask; |
2847 | uint8_t train_set = intel_dp->train_set[0]; |
3200 | uint8_t train_set = intel_dp->train_set[0]; |
Line 2848... | Line 3201... | ||
2848 | 3201 | ||
2849 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3202 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
2850 | signal_levels = intel_hsw_signal_levels(train_set); |
3203 | signal_levels = intel_hsw_signal_levels(train_set); |
2851 | mask = DDI_BUF_EMP_MASK; |
3204 | mask = DDI_BUF_EMP_MASK; |
2852 | } else if (IS_CHERRYVIEW(dev)) { |
3205 | } else if (IS_CHERRYVIEW(dev)) { |
2853 | signal_levels = intel_chv_signal_levels(intel_dp); |
3206 | signal_levels = intel_chv_signal_levels(intel_dp); |
Line 2877... | Line 3230... | ||
2877 | uint8_t dp_train_pat) |
3230 | uint8_t dp_train_pat) |
2878 | { |
3231 | { |
2879 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3232 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2880 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3233 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2881 | struct drm_i915_private *dev_priv = dev->dev_private; |
3234 | struct drm_i915_private *dev_priv = dev->dev_private; |
2882 | enum port port = intel_dig_port->port; |
- | |
2883 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
3235 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2884 | int ret, len; |
3236 | int ret, len; |
Line 2885... | Line -... | ||
2885 | - | ||
2886 | if (HAS_DDI(dev)) { |
- | |
2887 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
- | |
2888 | - | ||
2889 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
- | |
2890 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
- | |
2891 | else |
- | |
2892 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
- | |
2893 | - | ||
2894 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
- | |
2895 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
- | |
2896 | case DP_TRAINING_PATTERN_DISABLE: |
- | |
2897 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
- | |
2898 | - | ||
2899 | break; |
- | |
2900 | case DP_TRAINING_PATTERN_1: |
- | |
2901 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
- | |
2902 | break; |
- | |
2903 | case DP_TRAINING_PATTERN_2: |
- | |
2904 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
- | |
2905 | break; |
- | |
2906 | case DP_TRAINING_PATTERN_3: |
- | |
2907 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
- | |
2908 | break; |
- | |
2909 | } |
- | |
2910 | I915_WRITE(DP_TP_CTL(port), temp); |
- | |
2911 | - | ||
2912 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
- | |
2913 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
- | |
2914 | - | ||
2915 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
- | |
2916 | case DP_TRAINING_PATTERN_DISABLE: |
- | |
2917 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
- | |
2918 | break; |
- | |
2919 | case DP_TRAINING_PATTERN_1: |
- | |
2920 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
- | |
2921 | break; |
- | |
2922 | case DP_TRAINING_PATTERN_2: |
- | |
2923 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
- | |
2924 | break; |
- | |
2925 | case DP_TRAINING_PATTERN_3: |
- | |
2926 | DRM_ERROR("DP training pattern 3 not supported\n"); |
- | |
2927 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
- | |
2928 | break; |
- | |
2929 | } |
- | |
2930 | - | ||
2931 | } else { |
- | |
2932 | *DP &= ~DP_LINK_TRAIN_MASK; |
- | |
2933 | - | ||
2934 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
- | |
2935 | case DP_TRAINING_PATTERN_DISABLE: |
- | |
2936 | *DP |= DP_LINK_TRAIN_OFF; |
- | |
2937 | break; |
- | |
2938 | case DP_TRAINING_PATTERN_1: |
- | |
2939 | *DP |= DP_LINK_TRAIN_PAT_1; |
- | |
2940 | break; |
- | |
2941 | case DP_TRAINING_PATTERN_2: |
- | |
2942 | *DP |= DP_LINK_TRAIN_PAT_2; |
- | |
2943 | break; |
- | |
2944 | case DP_TRAINING_PATTERN_3: |
3237 | |
2945 | DRM_ERROR("DP training pattern 3 not supported\n"); |
- | |
2946 | *DP |= DP_LINK_TRAIN_PAT_2; |
- | |
2947 | break; |
- | |
2948 | } |
- | |
Line 2949... | Line 3238... | ||
2949 | } |
3238 | _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
2950 | 3239 | ||
Line 2951... | Line 3240... | ||
2951 | I915_WRITE(intel_dp->output_reg, *DP); |
3240 | I915_WRITE(intel_dp->output_reg, *DP); |
Line 3172... | Line 3461... | ||
3172 | break; |
3461 | break; |
3173 | } |
3462 | } |
Line 3174... | Line 3463... | ||
3174 | 3463 | ||
3175 | /* Try 5 times, then try clock recovery if that fails */ |
3464 | /* Try 5 times, then try clock recovery if that fails */ |
3176 | if (tries > 5) { |
- | |
3177 | intel_dp_link_down(intel_dp); |
3465 | if (tries > 5) { |
3178 | intel_dp_start_link_train(intel_dp); |
3466 | intel_dp_start_link_train(intel_dp); |
3179 | intel_dp_set_link_train(intel_dp, &DP, |
3467 | intel_dp_set_link_train(intel_dp, &DP, |
3180 | training_pattern | |
3468 | training_pattern | |
3181 | DP_LINK_SCRAMBLING_DISABLE); |
3469 | DP_LINK_SCRAMBLING_DISABLE); |
Line 3228... | Line 3516... | ||
3228 | 3516 | ||
3229 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
3517 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
3230 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3518 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3231 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
3519 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
- | 3520 | } else { |
|
- | 3521 | if (IS_CHERRYVIEW(dev)) |
|
- | 3522 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
|
3232 | } else { |
3523 | else |
3233 | DP &= ~DP_LINK_TRAIN_MASK; |
3524 | DP &= ~DP_LINK_TRAIN_MASK; |
3234 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
3525 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
3235 | } |
3526 | } |
Line 3274... | Line 3565... | ||
3274 | { |
3565 | { |
3275 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3566 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3276 | struct drm_device *dev = dig_port->base.base.dev; |
3567 | struct drm_device *dev = dig_port->base.base.dev; |
3277 | struct drm_i915_private *dev_priv = dev->dev_private; |
3568 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 3278... | Line -... | ||
3278 | - | ||
3279 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
- | |
3280 | 3569 | ||
3281 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3570 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3282 | sizeof(intel_dp->dpcd)) < 0) |
3571 | sizeof(intel_dp->dpcd)) < 0) |
Line 3283... | Line -... | ||
3283 | return false; /* aux transfer failed */ |
- | |
3284 | - | ||
3285 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
3572 | return false; /* aux transfer failed */ |
Line 3286... | Line 3573... | ||
3286 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
3573 | |
3287 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
3574 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
Line 3288... | Line 3575... | ||
3288 | 3575 | ||
Line 3299... | Line 3586... | ||
3299 | dev_priv->psr.sink_support = true; |
3586 | dev_priv->psr.sink_support = true; |
3300 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3587 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3301 | } |
3588 | } |
3302 | } |
3589 | } |
Line 3303... | Line 3590... | ||
3303 | 3590 | ||
3304 | /* Training Pattern 3 support */ |
3591 | /* Training Pattern 3 support, both source and sink */ |
3305 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
3592 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
- | 3593 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && |
|
3306 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { |
3594 | (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) { |
3307 | intel_dp->use_tps3 = true; |
3595 | intel_dp->use_tps3 = true; |
3308 | DRM_DEBUG_KMS("Displayport TPS3 supported"); |
3596 | DRM_DEBUG_KMS("Displayport TPS3 supported\n"); |
3309 | } else |
3597 | } else |
Line 3310... | Line 3598... | ||
3310 | intel_dp->use_tps3 = false; |
3598 | intel_dp->use_tps3 = false; |
3311 | 3599 | ||
Line 3330... | Line 3618... | ||
3330 | u8 buf[3]; |
3618 | u8 buf[3]; |
Line 3331... | Line 3619... | ||
3331 | 3619 | ||
3332 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
3620 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
Line 3333... | Line -... | ||
3333 | return; |
- | |
3334 | - | ||
3335 | intel_edp_panel_vdd_on(intel_dp); |
3621 | return; |
3336 | 3622 | ||
3337 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
3623 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
Line 3338... | Line 3624... | ||
3338 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3624 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3339 | buf[0], buf[1], buf[2]); |
3625 | buf[0], buf[1], buf[2]); |
3340 | 3626 | ||
3341 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
- | |
3342 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
- | |
3343 | buf[0], buf[1], buf[2]); |
3627 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
Line 3344... | Line 3628... | ||
3344 | 3628 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
|
3345 | edp_panel_vdd_off(intel_dp, false); |
3629 | buf[0], buf[1], buf[2]); |
3346 | } |
3630 | } |
Line 3354... | Line 3638... | ||
3354 | return false; |
3638 | return false; |
Line 3355... | Line 3639... | ||
3355 | 3639 | ||
3356 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
3640 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
Line 3357... | Line -... | ||
3357 | return false; |
- | |
3358 | 3641 | return false; |
|
3359 | _edp_panel_vdd_on(intel_dp); |
3642 | |
3360 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3643 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3361 | if (buf[0] & DP_MST_CAP) { |
3644 | if (buf[0] & DP_MST_CAP) { |
3362 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
3645 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
3363 | intel_dp->is_mst = true; |
3646 | intel_dp->is_mst = true; |
3364 | } else { |
3647 | } else { |
3365 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
3648 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
3366 | intel_dp->is_mst = false; |
3649 | intel_dp->is_mst = false; |
3367 | } |
- | |
Line 3368... | Line 3650... | ||
3368 | } |
3650 | } |
3369 | edp_panel_vdd_off(intel_dp, false); |
3651 | } |
3370 | 3652 | ||
Line 3376... | Line 3658... | ||
3376 | { |
3658 | { |
3377 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3659 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3378 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3660 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3379 | struct intel_crtc *intel_crtc = |
3661 | struct intel_crtc *intel_crtc = |
3380 | to_intel_crtc(intel_dig_port->base.base.crtc); |
3662 | to_intel_crtc(intel_dig_port->base.base.crtc); |
3381 | u8 buf[1]; |
3663 | u8 buf; |
- | 3664 | int test_crc_count; |
|
- | 3665 | int attempts = 6; |
|
Line 3382... | Line 3666... | ||
3382 | 3666 | ||
3383 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
3667 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
Line 3384... | Line 3668... | ||
3384 | return -EAGAIN; |
3668 | return -EIO; |
3385 | 3669 | ||
Line -... | Line 3670... | ||
- | 3670 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
|
- | 3671 | return -ENOTTY; |
|
- | 3672 | ||
3386 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) |
3673 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
3387 | return -ENOTTY; |
3674 | return -EIO; |
3388 | 3675 | ||
Line 3389... | Line 3676... | ||
3389 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
3676 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
- | 3677 | buf | DP_TEST_SINK_START) < 0) |
|
- | 3678 | return -EIO; |
|
- | 3679 | ||
- | 3680 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
|
3390 | DP_TEST_SINK_START) < 0) |
3681 | return -EIO; |
- | 3682 | test_crc_count = buf & DP_TEST_COUNT_MASK; |
|
- | 3683 | ||
3391 | return -EAGAIN; |
3684 | do { |
- | 3685 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
|
- | 3686 | DP_TEST_SINK_MISC, &buf) < 0) |
|
- | 3687 | return -EIO; |
|
- | 3688 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 3689 | } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count); |
|
- | 3690 | ||
Line 3392... | Line 3691... | ||
3392 | 3691 | if (attempts == 0) { |
|
- | 3692 | DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n"); |
|
- | 3693 | return -ETIMEDOUT; |
|
- | 3694 | } |
|
3393 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ |
3695 | |
- | 3696 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
|
- | 3697 | return -EIO; |
|
- | 3698 | ||
Line 3394... | Line -... | ||
3394 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
- | |
3395 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3699 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
3396 | 3700 | return -EIO; |
|
Line 3397... | Line 3701... | ||
3397 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
3701 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
3398 | return -EAGAIN; |
3702 | buf & ~DP_TEST_SINK_START) < 0) |
Line 3596... | Line 3900... | ||
3596 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
3900 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
3597 | return connector_status_disconnected; |
3901 | return connector_status_disconnected; |
3598 | } |
3902 | } |
Line 3599... | Line 3903... | ||
3599 | 3903 | ||
3600 | static enum drm_connector_status |
3904 | static enum drm_connector_status |
3601 | ironlake_dp_detect(struct intel_dp *intel_dp) |
3905 | edp_detect(struct intel_dp *intel_dp) |
3602 | { |
3906 | { |
3603 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
3604 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
3605 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3907 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 3606... | Line -... | ||
3606 | enum drm_connector_status status; |
- | |
3607 | - | ||
3608 | /* Can't disconnect eDP, but you can close the lid... */ |
3908 | enum drm_connector_status status; |
3609 | if (is_edp(intel_dp)) { |
3909 | |
3610 | status = intel_panel_detect(dev); |
3910 | status = intel_panel_detect(dev); |
- | 3911 | if (status == connector_status_unknown) |
|
3611 | if (status == connector_status_unknown) |
3912 | status = connector_status_connected; |
3612 | status = connector_status_connected; |
3913 | |
Line -... | Line 3914... | ||
- | 3914 | return status; |
|
- | 3915 | } |
|
- | 3916 | ||
- | 3917 | static enum drm_connector_status |
|
- | 3918 | ironlake_dp_detect(struct intel_dp *intel_dp) |
|
- | 3919 | { |
|
- | 3920 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
3613 | return status; |
3921 | struct drm_i915_private *dev_priv = dev->dev_private; |
3614 | } |
3922 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Line 3615... | Line 3923... | ||
3615 | 3923 | ||
3616 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
3924 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
Line 3685... | Line 3993... | ||
3685 | 3993 | ||
3686 | return intel_dp_detect_dpcd(intel_dp); |
3994 | return intel_dp_detect_dpcd(intel_dp); |
Line 3687... | Line 3995... | ||
3687 | } |
3995 | } |
3688 | 3996 | ||
3689 | static struct edid * |
3997 | static struct edid * |
3690 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
3998 | intel_dp_get_edid(struct intel_dp *intel_dp) |
Line 3691... | Line 3999... | ||
3691 | { |
3999 | { |
3692 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4000 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
3693 | 4001 | ||
3694 | /* use cached edid if we have one */ |
4002 | /* use cached edid if we have one */ |
3695 | if (intel_connector->edid) { |
4003 | if (intel_connector->edid) { |
Line 3696... | Line 4004... | ||
3696 | /* invalid edid */ |
4004 | /* invalid edid */ |
- | 4005 | if (IS_ERR(intel_connector->edid)) |
|
- | 4006 | return NULL; |
|
- | 4007 | ||
3697 | if (IS_ERR(intel_connector->edid)) |
4008 | return drm_edid_duplicate(intel_connector->edid); |
Line -... | Line 4009... | ||
- | 4009 | } else |
|
- | 4010 | return drm_get_edid(&intel_connector->base, |
|
- | 4011 | &intel_dp->aux.ddc); |
|
- | 4012 | } |
|
- | 4013 | ||
- | 4014 | static void |
|
3698 | return NULL; |
4015 | intel_dp_set_edid(struct intel_dp *intel_dp) |
- | 4016 | { |
|
- | 4017 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
|
- | 4018 | struct edid *edid; |
|
- | 4019 | ||
- | 4020 | edid = intel_dp_get_edid(intel_dp); |
|
- | 4021 | intel_connector->detect_edid = edid; |
|
3699 | 4022 | ||
Line 3700... | Line 4023... | ||
3700 | return drm_edid_duplicate(intel_connector->edid); |
4023 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
3701 | } |
4024 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
3702 | 4025 | else |
|
3703 | return drm_get_edid(connector, adapter); |
4026 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
Line 3704... | Line 4027... | ||
3704 | } |
4027 | } |
3705 | 4028 | ||
- | 4029 | static void |
|
3706 | static int |
4030 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
- | 4031 | { |
|
- | 4032 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
|
3707 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
4033 | |
3708 | { |
4034 | kfree(intel_connector->detect_edid); |
- | 4035 | intel_connector->detect_edid = NULL; |
|
- | 4036 | ||
- | 4037 | intel_dp->has_audio = false; |
|
- | 4038 | } |
|
- | 4039 | ||
- | 4040 | static enum intel_display_power_domain |
|
Line 3709... | Line -... | ||
3709 | struct intel_connector *intel_connector = to_intel_connector(connector); |
- | |
3710 | 4041 | intel_dp_power_get(struct intel_dp *dp) |
|
3711 | /* use cached edid if we have one */ |
4042 | { |
Line -... | Line 4043... | ||
- | 4043 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; |
|
- | 4044 | enum intel_display_power_domain power_domain; |
|
3712 | if (intel_connector->edid) { |
4045 | |
- | 4046 | power_domain = intel_display_port_power_domain(encoder); |
|
- | 4047 | intel_display_power_get(to_i915(encoder->base.dev), power_domain); |
|
- | 4048 | ||
3713 | /* invalid edid */ |
4049 | return power_domain; |
Line 3714... | Line 4050... | ||
3714 | if (IS_ERR(intel_connector->edid)) |
4050 | } |
3715 | return 0; |
4051 | |
3716 | 4052 | static void |
|
3717 | return intel_connector_update_modes(connector, |
4053 | intel_dp_power_put(struct intel_dp *dp, |
3718 | intel_connector->edid); |
4054 | enum intel_display_power_domain power_domain) |
3719 | } |
4055 | { |
3720 | 4056 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; |
|
3721 | return intel_ddc_get_modes(connector, adapter); |
- | |
3722 | } |
4057 | intel_display_power_put(to_i915(encoder->base.dev), power_domain); |
3723 | 4058 | } |
|
3724 | static enum drm_connector_status |
- | |
3725 | intel_dp_detect(struct drm_connector *connector, bool force) |
4059 | |
Line 3726... | Line -... | ||
3726 | { |
- | |
3727 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | |
3728 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
3729 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4060 | static enum drm_connector_status |
3730 | struct drm_device *dev = connector->dev; |
4061 | intel_dp_detect(struct drm_connector *connector, bool force) |
- | 4062 | { |
|
Line 3731... | Line 4063... | ||
3731 | struct drm_i915_private *dev_priv = dev->dev_private; |
4063 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3732 | enum drm_connector_status status; |
4064 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3733 | enum intel_display_power_domain power_domain; |
4065 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3734 | struct edid *edid = NULL; |
4066 | struct drm_device *dev = connector->dev; |
3735 | bool ret; |
4067 | enum drm_connector_status status; |
3736 | - | ||
3737 | power_domain = intel_display_port_power_domain(intel_encoder); |
4068 | enum intel_display_power_domain power_domain; |
Line 3738... | Line 4069... | ||
3738 | intel_display_power_get(dev_priv, power_domain); |
4069 | bool ret; |
Line -... | Line 4070... | ||
- | 4070 | ||
- | 4071 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
|
- | 4072 | connector->base.id, connector->name); |
|
3739 | 4073 | intel_dp_unset_edid(intel_dp); |
|
3740 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4074 | |
3741 | connector->base.id, connector->name); |
4075 | if (intel_dp->is_mst) { |
3742 | 4076 | /* MST devices are disconnected from a monitor POV */ |
|
3743 | if (intel_dp->is_mst) { |
- | |
3744 | /* MST devices are disconnected from a monitor POV */ |
4077 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3745 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4078 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Line 3746... | Line 4079... | ||
3746 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4079 | return connector_status_disconnected; |
Line 3768... | Line 4101... | ||
3768 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4101 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
3769 | status = connector_status_disconnected; |
4102 | status = connector_status_disconnected; |
3770 | goto out; |
4103 | goto out; |
3771 | } |
4104 | } |
Line 3772... | Line -... | ||
3772 | - | ||
3773 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
- | |
3774 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
- | |
3775 | } else { |
4105 | |
3776 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
- | |
3777 | if (edid) { |
- | |
3778 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
- | |
3779 | kfree(edid); |
- | |
3780 | } |
- | |
Line 3781... | Line 4106... | ||
3781 | } |
4106 | intel_dp_set_edid(intel_dp); |
3782 | 4107 | ||
3783 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4108 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
Line 3784... | Line 4109... | ||
3784 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4109 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
3785 | status = connector_status_connected; |
4110 | status = connector_status_connected; |
3786 | 4111 | ||
3787 | out: |
4112 | out: |
Line -... | Line 4113... | ||
- | 4113 | intel_dp_power_put(intel_dp, power_domain); |
|
3788 | intel_display_power_put(dev_priv, power_domain); |
4114 | return status; |
3789 | return status; |
4115 | } |
3790 | } |
4116 | |
3791 | - | ||
3792 | static int intel_dp_get_modes(struct drm_connector *connector) |
4117 | static void |
3793 | { |
- | |
3794 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | |
3795 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
3796 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4118 | intel_dp_force(struct drm_connector *connector) |
3797 | struct intel_connector *intel_connector = to_intel_connector(connector); |
- | |
Line -... | Line 4119... | ||
- | 4119 | { |
|
3798 | struct drm_device *dev = connector->dev; |
4120 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3799 | struct drm_i915_private *dev_priv = dev->dev_private; |
4121 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Line 3800... | Line 4122... | ||
3800 | enum intel_display_power_domain power_domain; |
4122 | enum intel_display_power_domain power_domain; |
3801 | int ret; |
4123 | |
Line -... | Line 4124... | ||
- | 4124 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
|
- | 4125 | connector->base.id, connector->name); |
|
3802 | 4126 | intel_dp_unset_edid(intel_dp); |
|
- | 4127 | ||
3803 | /* We should parse the EDID data and find out if it has an audio sink |
4128 | if (connector->status != connector_status_connected) |
- | 4129 | return; |
|
- | 4130 | ||
- | 4131 | power_domain = intel_dp_power_get(intel_dp); |
|
- | 4132 | ||
- | 4133 | intel_dp_set_edid(intel_dp); |
|
- | 4134 | ||
- | 4135 | intel_dp_power_put(intel_dp, power_domain); |
|
- | 4136 | ||
- | 4137 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
|
- | 4138 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 4139 | } |
|
- | 4140 | ||
- | 4141 | static int intel_dp_get_modes(struct drm_connector *connector) |
|
3804 | */ |
4142 | { |
3805 | 4143 | struct intel_connector *intel_connector = to_intel_connector(connector); |
|
- | 4144 | struct edid *edid; |
|
Line 3806... | Line 4145... | ||
3806 | power_domain = intel_display_port_power_domain(intel_encoder); |
4145 | |
- | 4146 | edid = intel_connector->detect_edid; |
|
3807 | intel_display_power_get(dev_priv, power_domain); |
4147 | if (edid) { |
3808 | 4148 | int ret = intel_connector_update_modes(connector, edid); |
|
- | 4149 | if (ret) |
|
3809 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
4150 | return ret; |
3810 | intel_display_power_put(dev_priv, power_domain); |
4151 | } |
3811 | if (ret) |
4152 | |
3812 | return ret; |
4153 | /* if eDP has no EDID, fall back to fixed mode */ |
3813 | 4154 | if (is_edp(intel_attached_dp(connector)) && |
|
3814 | /* if eDP has no EDID, fall back to fixed mode */ |
4155 | intel_connector->panel.fixed_mode) { |
3815 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
4156 | struct drm_display_mode *mode; |
- | 4157 | ||
3816 | struct drm_display_mode *mode; |
4158 | mode = drm_mode_duplicate(connector->dev, |
3817 | mode = drm_mode_duplicate(dev, |
4159 | intel_connector->panel.fixed_mode); |
Line 3818... | Line 4160... | ||
3818 | intel_connector->panel.fixed_mode); |
4160 | if (mode) { |
3819 | if (mode) { |
4161 | drm_mode_probed_add(connector, mode); |
3820 | drm_mode_probed_add(connector, mode); |
4162 | return 1; |
3821 | return 1; |
- | |
3822 | } |
- | |
3823 | } |
- | |
3824 | return 0; |
- | |
3825 | } |
- | |
3826 | - | ||
3827 | static bool |
- | |
3828 | intel_dp_detect_audio(struct drm_connector *connector) |
4163 | } |
- | 4164 | } |
|
Line 3829... | Line -... | ||
3829 | { |
- | |
3830 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | |
3831 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | |
3832 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4165 | |
3833 | struct drm_device *dev = connector->dev; |
4166 | return 0; |
3834 | struct drm_i915_private *dev_priv = dev->dev_private; |
4167 | } |
3835 | enum intel_display_power_domain power_domain; |
- | |
3836 | struct edid *edid; |
- | |
3837 | bool has_audio = false; |
- | |
3838 | - | ||
Line 3839... | Line 4168... | ||
3839 | power_domain = intel_display_port_power_domain(intel_encoder); |
4168 | |
3840 | intel_display_power_get(dev_priv, power_domain); |
4169 | static bool |
Line 3841... | Line 4170... | ||
3841 | 4170 | intel_dp_detect_audio(struct drm_connector *connector) |
|
Line 3941... | Line 4270... | ||
3941 | static void |
4270 | static void |
3942 | intel_dp_connector_destroy(struct drm_connector *connector) |
4271 | intel_dp_connector_destroy(struct drm_connector *connector) |
3943 | { |
4272 | { |
3944 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4273 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Line -... | Line 4274... | ||
- | 4274 | ||
- | 4275 | kfree(intel_connector->detect_edid); |
|
3945 | 4276 | ||
3946 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4277 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
Line 3947... | Line 4278... | ||
3947 | kfree(intel_connector->edid); |
4278 | kfree(intel_connector->edid); |
3948 | 4279 | ||
Line 3957... | Line 4288... | ||
3957 | 4288 | ||
3958 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
4289 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
3959 | { |
4290 | { |
3960 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4291 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3961 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
- | |
Line 3962... | Line 4292... | ||
3962 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4292 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3963 | 4293 | ||
3964 | drm_dp_aux_unregister(&intel_dp->aux); |
4294 | drm_dp_aux_unregister(&intel_dp->aux); |
3965 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
4295 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
3966 | drm_encoder_cleanup(encoder); |
4296 | drm_encoder_cleanup(encoder); |
- | 4297 | if (is_edp(intel_dp)) { |
|
3967 | if (is_edp(intel_dp)) { |
4298 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
- | 4299 | /* |
|
- | 4300 | * vdd might still be enabled do to the delayed vdd off. |
|
- | 4301 | * Make sure vdd is actually turned off here. |
|
3968 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4302 | */ |
3969 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4303 | pps_lock(intel_dp); |
- | 4304 | edp_panel_vdd_off_sync(intel_dp); |
|
3970 | edp_panel_vdd_off_sync(intel_dp); |
4305 | pps_unlock(intel_dp); |
3971 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
4306 | |
3972 | } |
4307 | } |
Line 3973... | Line 4308... | ||
3973 | kfree(intel_dig_port); |
4308 | kfree(intel_dig_port); |
Line 3978... | Line 4313... | ||
3978 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4313 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Line 3979... | Line 4314... | ||
3979 | 4314 | ||
3980 | if (!is_edp(intel_dp)) |
4315 | if (!is_edp(intel_dp)) |
Line -... | Line 4316... | ||
- | 4316 | return; |
|
- | 4317 | ||
- | 4318 | /* |
|
- | 4319 | * vdd might still be enabled do to the delayed vdd off. |
|
- | 4320 | * Make sure vdd is actually turned off here. |
|
- | 4321 | */ |
|
3981 | return; |
4322 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
- | 4323 | pps_lock(intel_dp); |
|
- | 4324 | edp_panel_vdd_off_sync(intel_dp); |
|
- | 4325 | pps_unlock(intel_dp); |
|
- | 4326 | } |
|
- | 4327 | ||
- | 4328 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
|
- | 4329 | { |
|
- | 4330 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 4331 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 4332 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4333 | enum intel_display_power_domain power_domain; |
|
- | 4334 | ||
- | 4335 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 4336 | ||
- | 4337 | if (!edp_have_panel_vdd(intel_dp)) |
|
- | 4338 | return; |
|
- | 4339 | ||
- | 4340 | /* |
|
- | 4341 | * The VDD bit needs a power domain reference, so if the bit is |
|
- | 4342 | * already enabled when we boot or resume, grab this reference and |
|
- | 4343 | * schedule a vdd off, so we don't hold on to the reference |
|
- | 4344 | * indefinitely. |
|
- | 4345 | */ |
|
- | 4346 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
|
- | 4347 | power_domain = intel_display_port_power_domain(&intel_dig_port->base); |
|
- | 4348 | intel_display_power_get(dev_priv, power_domain); |
|
3982 | 4349 | ||
Line 3983... | Line 4350... | ||
3983 | edp_panel_vdd_off_sync(intel_dp); |
4350 | edp_panel_vdd_schedule_off(intel_dp); |
3984 | } |
4351 | } |
- | 4352 | ||
- | 4353 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
|
- | 4354 | { |
|
- | 4355 | struct intel_dp *intel_dp; |
|
- | 4356 | ||
- | 4357 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
|
- | 4358 | return; |
|
- | 4359 | ||
- | 4360 | intel_dp = enc_to_intel_dp(encoder); |
|
- | 4361 | ||
- | 4362 | pps_lock(intel_dp); |
|
- | 4363 | ||
- | 4364 | /* |
|
- | 4365 | * Read out the current power sequencer assignment, |
|
- | 4366 | * in case the BIOS did something with it. |
|
- | 4367 | */ |
|
3985 | 4368 | if (IS_VALLEYVIEW(encoder->dev)) |
|
- | 4369 | vlv_initial_power_sequencer_setup(intel_dp); |
|
- | 4370 | ||
3986 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
4371 | intel_edp_panel_vdd_sanitize(intel_dp); |
Line 3987... | Line 4372... | ||
3987 | { |
4372 | |
3988 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); |
4373 | pps_unlock(intel_dp); |
3989 | } |
4374 | } |
- | 4375 | ||
3990 | 4376 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
|
3991 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4377 | .dpms = intel_connector_dpms, |
3992 | .dpms = intel_connector_dpms, |
4378 | .detect = intel_dp_detect, |
3993 | .detect = intel_dp_detect, |
4379 | .force = intel_dp_force, |
Line 4024... | Line 4410... | ||
4024 | bool ret = true; |
4410 | bool ret = true; |
Line 4025... | Line 4411... | ||
4025 | 4411 | ||
4026 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
4412 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
Line -... | Line 4413... | ||
- | 4413 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 4414 | ||
- | 4415 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
|
- | 4416 | /* |
|
- | 4417 | * vdd off can generate a long pulse on eDP which |
|
- | 4418 | * would require vdd on to handle it, and thus we |
|
- | 4419 | * would end up in an endless cycle of |
|
- | 4420 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
|
- | 4421 | */ |
|
- | 4422 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
|
- | 4423 | port_name(intel_dig_port->port)); |
|
- | 4424 | return false; |
|
4027 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
4425 | } |
- | 4426 | ||
4028 | 4427 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
|
Line 4029... | Line 4428... | ||
4029 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, |
4428 | port_name(intel_dig_port->port), |
4030 | long_hpd ? "long" : "short"); |
4429 | long_hpd ? "long" : "short"); |
Line 4156... | Line 4555... | ||
4156 | intel_dp->last_backlight_off = jiffies; |
4555 | intel_dp->last_backlight_off = jiffies; |
4157 | } |
4556 | } |
Line 4158... | Line 4557... | ||
4158 | 4557 | ||
4159 | static void |
4558 | static void |
4160 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
4559 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
4161 | struct intel_dp *intel_dp, |
- | |
4162 | struct edp_power_seq *out) |
4560 | struct intel_dp *intel_dp) |
4163 | { |
4561 | { |
4164 | struct drm_i915_private *dev_priv = dev->dev_private; |
4562 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 4563 | struct edp_power_seq cur, vbt, spec, |
|
4165 | struct edp_power_seq cur, vbt, spec, final; |
4564 | *final = &intel_dp->pps_delays; |
4166 | u32 pp_on, pp_off, pp_div, pp; |
4565 | u32 pp_on, pp_off, pp_div, pp; |
Line -... | Line 4566... | ||
- | 4566 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
|
- | 4567 | ||
- | 4568 | lockdep_assert_held(&dev_priv->pps_mutex); |
|
- | 4569 | ||
- | 4570 | /* already initialized? */ |
|
- | 4571 | if (final->t11_t12 != 0) |
|
4167 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
4572 | return; |
4168 | 4573 | ||
4169 | if (HAS_PCH_SPLIT(dev)) { |
4574 | if (HAS_PCH_SPLIT(dev)) { |
4170 | pp_ctrl_reg = PCH_PP_CONTROL; |
4575 | pp_ctrl_reg = PCH_PP_CONTROL; |
4171 | pp_on_reg = PCH_PP_ON_DELAYS; |
4576 | pp_on_reg = PCH_PP_ON_DELAYS; |
Line 4225... | Line 4630... | ||
4225 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
4630 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
4226 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
4631 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
Line 4227... | Line 4632... | ||
4227 | 4632 | ||
4228 | /* Use the max of the register settings and vbt. If both are |
4633 | /* Use the max of the register settings and vbt. If both are |
4229 | * unset, fall back to the spec limits. */ |
4634 | * unset, fall back to the spec limits. */ |
4230 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
4635 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
4231 | spec.field : \ |
4636 | spec.field : \ |
4232 | max(cur.field, vbt.field)) |
4637 | max(cur.field, vbt.field)) |
4233 | assign_final(t1_t3); |
4638 | assign_final(t1_t3); |
4234 | assign_final(t8); |
4639 | assign_final(t8); |
4235 | assign_final(t9); |
4640 | assign_final(t9); |
4236 | assign_final(t10); |
4641 | assign_final(t10); |
4237 | assign_final(t11_t12); |
4642 | assign_final(t11_t12); |
Line 4238... | Line 4643... | ||
4238 | #undef assign_final |
4643 | #undef assign_final |
4239 | 4644 | ||
4240 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
4645 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
4241 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4646 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4242 | intel_dp->backlight_on_delay = get_delay(t8); |
4647 | intel_dp->backlight_on_delay = get_delay(t8); |
4243 | intel_dp->backlight_off_delay = get_delay(t9); |
4648 | intel_dp->backlight_off_delay = get_delay(t9); |
Line 4249... | Line 4654... | ||
4249 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
4654 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
4250 | intel_dp->panel_power_cycle_delay); |
4655 | intel_dp->panel_power_cycle_delay); |
Line 4251... | Line 4656... | ||
4251 | 4656 | ||
4252 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
4657 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
4253 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
- | |
4254 | - | ||
4255 | if (out) |
- | |
4256 | *out = final; |
4658 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
Line 4257... | Line 4659... | ||
4257 | } |
4659 | } |
4258 | 4660 | ||
4259 | static void |
4661 | static void |
4260 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
- | |
4261 | struct intel_dp *intel_dp, |
4662 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
4262 | struct edp_power_seq *seq) |
4663 | struct intel_dp *intel_dp) |
4263 | { |
4664 | { |
4264 | struct drm_i915_private *dev_priv = dev->dev_private; |
4665 | struct drm_i915_private *dev_priv = dev->dev_private; |
4265 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
4666 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
- | 4667 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
|
- | 4668 | int pp_on_reg, pp_off_reg, pp_div_reg; |
|
- | 4669 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
- | 4670 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
|
Line 4266... | Line 4671... | ||
4266 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
4671 | |
4267 | int pp_on_reg, pp_off_reg, pp_div_reg; |
4672 | lockdep_assert_held(&dev_priv->pps_mutex); |
4268 | 4673 | ||
4269 | if (HAS_PCH_SPLIT(dev)) { |
4674 | if (HAS_PCH_SPLIT(dev)) { |
Line 4297... | Line 4702... | ||
4297 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
4702 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
Line 4298... | Line 4703... | ||
4298 | 4703 | ||
4299 | /* Haswell doesn't have any port selection bits for the panel |
4704 | /* Haswell doesn't have any port selection bits for the panel |
4300 | * power sequencer any more. */ |
4705 | * power sequencer any more. */ |
4301 | if (IS_VALLEYVIEW(dev)) { |
- | |
4302 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
- | |
4303 | port_sel = PANEL_PORT_SELECT_DPB_VLV; |
- | |
4304 | else |
4706 | if (IS_VALLEYVIEW(dev)) { |
4305 | port_sel = PANEL_PORT_SELECT_DPC_VLV; |
4707 | port_sel = PANEL_PORT_SELECT_VLV(port); |
4306 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
4708 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
4307 | if (dp_to_dig_port(intel_dp)->port == PORT_A) |
4709 | if (port == PORT_A) |
4308 | port_sel = PANEL_PORT_SELECT_DPA; |
4710 | port_sel = PANEL_PORT_SELECT_DPA; |
4309 | else |
4711 | else |
4310 | port_sel = PANEL_PORT_SELECT_DPD; |
4712 | port_sel = PANEL_PORT_SELECT_DPD; |
Line 4346... | Line 4748... | ||
4346 | /* |
4748 | /* |
4347 | * FIXME: This needs proper synchronization with psr state. But really |
4749 | * FIXME: This needs proper synchronization with psr state. But really |
4348 | * hard to tell without seeing the user of this function of this code. |
4750 | * hard to tell without seeing the user of this function of this code. |
4349 | * Check locking and ordering once that lands. |
4751 | * Check locking and ordering once that lands. |
4350 | */ |
4752 | */ |
4351 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { |
4753 | if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) { |
4352 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); |
4754 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); |
4353 | return; |
4755 | return; |
4354 | } |
4756 | } |
Line 4355... | Line 4757... | ||
4355 | 4757 | ||
Line 4386... | Line 4788... | ||
4386 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { |
4788 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { |
4387 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); |
4789 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); |
4388 | val = I915_READ(reg); |
4790 | val = I915_READ(reg); |
4389 | if (index > DRRS_HIGH_RR) { |
4791 | if (index > DRRS_HIGH_RR) { |
4390 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
4792 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
4391 | intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); |
4793 | intel_dp_set_m_n(intel_crtc); |
4392 | } else { |
4794 | } else { |
4393 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
4795 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
4394 | } |
4796 | } |
4395 | I915_WRITE(reg, val); |
4797 | I915_WRITE(reg, val); |
4396 | } |
4798 | } |
Line 4426... | Line 4828... | ||
4426 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
4828 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
4427 | return NULL; |
4829 | return NULL; |
4428 | } |
4830 | } |
Line 4429... | Line 4831... | ||
4429 | 4831 | ||
4430 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
4832 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
4431 | DRM_INFO("VBT doesn't support DRRS\n"); |
4833 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4432 | return NULL; |
4834 | return NULL; |
Line 4433... | Line 4835... | ||
4433 | } |
4835 | } |
4434 | 4836 | ||
Line 4435... | Line 4837... | ||
4435 | downclock_mode = intel_find_panel_downclock |
4837 | downclock_mode = intel_find_panel_downclock |
4436 | (dev, fixed_mode, connector); |
4838 | (dev, fixed_mode, connector); |
4437 | 4839 | ||
4438 | if (!downclock_mode) { |
4840 | if (!downclock_mode) { |
Line 4439... | Line 4841... | ||
4439 | DRM_INFO("DRRS not supported\n"); |
4841 | DRM_DEBUG_KMS("DRRS not supported\n"); |
Line 4440... | Line 4842... | ||
4440 | return NULL; |
4842 | return NULL; |
Line 4441... | Line 4843... | ||
4441 | } |
4843 | } |
Line 4442... | Line 4844... | ||
4442 | 4844 | ||
4443 | dev_priv->drrs.connector = intel_connector; |
4845 | dev_priv->drrs.connector = intel_connector; |
4444 | 4846 | ||
4445 | mutex_init(&intel_dp->drrs_state.mutex); |
4847 | mutex_init(&intel_dp->drrs_state.mutex); |
Line 4446... | Line -... | ||
4446 | - | ||
4447 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
- | |
4448 | - | ||
4449 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; |
- | |
4450 | DRM_INFO("seamless DRRS supported for eDP panel.\n"); |
- | |
4451 | return downclock_mode; |
- | |
4452 | } |
- | |
4453 | - | ||
4454 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) |
- | |
4455 | { |
- | |
4456 | struct drm_device *dev = intel_encoder->base.dev; |
- | |
4457 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4458 | struct intel_dp *intel_dp; |
- | |
4459 | enum intel_display_power_domain power_domain; |
- | |
4460 | - | ||
4461 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
- | |
4462 | return; |
- | |
4463 | - | ||
4464 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
- | |
4465 | if (!edp_have_panel_vdd(intel_dp)) |
- | |
4466 | return; |
- | |
4467 | /* |
- | |
4468 | * The VDD bit needs a power domain reference, so if the bit is |
- | |
4469 | * already enabled when we boot or resume, grab this reference and |
- | |
4470 | * schedule a vdd off, so we don't hold on to the reference |
- | |
4471 | * indefinitely. |
- | |
4472 | */ |
4848 | |
4473 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
4849 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
4474 | power_domain = intel_display_port_power_domain(intel_encoder); |
- | |
4475 | intel_display_power_get(dev_priv, power_domain); |
4850 | |
4476 | 4851 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; |
|
4477 | edp_panel_vdd_schedule_off(intel_dp); |
4852 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4478 | } |
4853 | return downclock_mode; |
4479 | 4854 | } |
|
Line 4489... | Line 4864... | ||
4489 | struct drm_display_mode *fixed_mode = NULL; |
4864 | struct drm_display_mode *fixed_mode = NULL; |
4490 | struct drm_display_mode *downclock_mode = NULL; |
4865 | struct drm_display_mode *downclock_mode = NULL; |
4491 | bool has_dpcd; |
4866 | bool has_dpcd; |
4492 | struct drm_display_mode *scan; |
4867 | struct drm_display_mode *scan; |
4493 | struct edid *edid; |
4868 | struct edid *edid; |
- | 4869 | enum pipe pipe = INVALID_PIPE; |
|
Line 4494... | Line 4870... | ||
4494 | 4870 | ||
Line 4495... | Line 4871... | ||
4495 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
4871 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
4496 | 4872 | ||
Line -... | Line 4873... | ||
- | 4873 | if (!is_edp(intel_dp)) |
|
4497 | if (!is_edp(intel_dp)) |
4874 | return true; |
- | 4875 | ||
Line 4498... | Line 4876... | ||
4498 | return true; |
4876 | pps_lock(intel_dp); |
4499 | - | ||
4500 | intel_edp_panel_vdd_sanitize(intel_encoder); |
4877 | intel_edp_panel_vdd_sanitize(intel_dp); |
4501 | - | ||
Line 4502... | Line 4878... | ||
4502 | /* Cache DPCD and EDID for edp. */ |
4878 | pps_unlock(intel_dp); |
4503 | intel_edp_panel_vdd_on(intel_dp); |
4879 | |
4504 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
4880 | /* Cache DPCD and EDID for edp. */ |
4505 | edp_panel_vdd_off(intel_dp, false); |
4881 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
Line 4514... | Line 4890... | ||
4514 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
4890 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
4515 | return false; |
4891 | return false; |
4516 | } |
4892 | } |
Line 4517... | Line 4893... | ||
4517 | 4893 | ||
- | 4894 | /* We now know it's not a ghost, init power sequence regs. */ |
|
4518 | /* We now know it's not a ghost, init power sequence regs. */ |
4895 | pps_lock(intel_dp); |
- | 4896 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
|
Line 4519... | Line 4897... | ||
4519 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
4897 | pps_unlock(intel_dp); |
4520 | 4898 | ||
4521 | mutex_lock(&dev->mode_config.mutex); |
4899 | mutex_lock(&dev->mode_config.mutex); |
4522 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
4900 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
Line 4552... | Line 4930... | ||
4552 | if (fixed_mode) |
4930 | if (fixed_mode) |
4553 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
4931 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
4554 | } |
4932 | } |
4555 | mutex_unlock(&dev->mode_config.mutex); |
4933 | mutex_unlock(&dev->mode_config.mutex); |
Line -... | Line 4934... | ||
- | 4934 | ||
- | 4935 | if (IS_VALLEYVIEW(dev)) { |
|
- | 4936 | ||
- | 4937 | /* |
|
- | 4938 | * Figure out the current pipe for the initial backlight setup. |
|
- | 4939 | * If the current pipe isn't valid, try the PPS pipe, and if that |
|
- | 4940 | * fails just assume pipe A. |
|
- | 4941 | */ |
|
- | 4942 | if (IS_CHERRYVIEW(dev)) |
|
- | 4943 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
|
- | 4944 | else |
|
- | 4945 | pipe = PORT_TO_PIPE(intel_dp->DP); |
|
- | 4946 | ||
- | 4947 | if (pipe != PIPE_A && pipe != PIPE_B) |
|
- | 4948 | pipe = intel_dp->pps_pipe; |
|
- | 4949 | ||
- | 4950 | if (pipe != PIPE_A && pipe != PIPE_B) |
|
- | 4951 | pipe = PIPE_A; |
|
- | 4952 | ||
- | 4953 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
|
- | 4954 | pipe_name(pipe)); |
|
- | 4955 | } |
|
4556 | 4956 | ||
- | 4957 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
|
4557 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
4958 | intel_connector->panel.backlight_power = intel_edp_backlight_power; |
Line 4558... | Line 4959... | ||
4558 | intel_panel_setup_backlight(connector); |
4959 | intel_panel_setup_backlight(connector, pipe); |
4559 | 4960 | ||
Line 4560... | Line 4961... | ||
4560 | return true; |
4961 | return true; |
Line 4568... | Line 4969... | ||
4568 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4969 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4569 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4970 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4570 | struct drm_device *dev = intel_encoder->base.dev; |
4971 | struct drm_device *dev = intel_encoder->base.dev; |
4571 | struct drm_i915_private *dev_priv = dev->dev_private; |
4972 | struct drm_i915_private *dev_priv = dev->dev_private; |
4572 | enum port port = intel_dig_port->port; |
4973 | enum port port = intel_dig_port->port; |
4573 | struct edp_power_seq power_seq = { 0 }; |
- | |
4574 | int type; |
4974 | int type; |
Line -... | Line 4975... | ||
- | 4975 | ||
- | 4976 | intel_dp->pps_pipe = INVALID_PIPE; |
|
4575 | 4977 | ||
- | 4978 | /* intel_dp vfuncs */ |
|
- | 4979 | if (INTEL_INFO(dev)->gen >= 9) |
|
4576 | /* intel_dp vfuncs */ |
4980 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
4577 | if (IS_VALLEYVIEW(dev)) |
4981 | else if (IS_VALLEYVIEW(dev)) |
4578 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
4982 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
4579 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4983 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4580 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
4984 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
4581 | else if (HAS_PCH_SPLIT(dev)) |
4985 | else if (HAS_PCH_SPLIT(dev)) |
4582 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
4986 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
4583 | else |
4987 | else |
Line -... | Line 4988... | ||
- | 4988 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
|
- | 4989 | ||
- | 4990 | if (INTEL_INFO(dev)->gen >= 9) |
|
4584 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
4991 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
Line 4585... | Line 4992... | ||
4585 | 4992 | else |
|
4586 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
4993 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
4587 | 4994 | ||
Line 4600... | Line 5007... | ||
4600 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
5007 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
4601 | */ |
5008 | */ |
4602 | if (type == DRM_MODE_CONNECTOR_eDP) |
5009 | if (type == DRM_MODE_CONNECTOR_eDP) |
4603 | intel_encoder->type = INTEL_OUTPUT_EDP; |
5010 | intel_encoder->type = INTEL_OUTPUT_EDP; |
Line -... | Line 5011... | ||
- | 5011 | ||
- | 5012 | /* eDP only on port B and/or C on vlv/chv */ |
|
- | 5013 | if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && |
|
- | 5014 | port != PORT_B && port != PORT_C)) |
|
- | 5015 | return false; |
|
4604 | 5016 | ||
4605 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5017 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
4606 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
5018 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
Line 4607... | Line 5019... | ||
4607 | port_name(port)); |
5019 | port_name(port)); |
Line 4641... | Line 5053... | ||
4641 | default: |
5053 | default: |
4642 | BUG(); |
5054 | BUG(); |
4643 | } |
5055 | } |
Line 4644... | Line 5056... | ||
4644 | 5056 | ||
- | 5057 | if (is_edp(intel_dp)) { |
|
4645 | if (is_edp(intel_dp)) { |
5058 | pps_lock(intel_dp); |
- | 5059 | intel_dp_init_panel_power_timestamps(intel_dp); |
|
- | 5060 | if (IS_VALLEYVIEW(dev)) |
|
- | 5061 | vlv_initial_power_sequencer_setup(intel_dp); |
|
4646 | intel_dp_init_panel_power_timestamps(intel_dp); |
5062 | else |
- | 5063 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
|
4647 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
5064 | pps_unlock(intel_dp); |
Line 4648... | Line 5065... | ||
4648 | } |
5065 | } |
Line 4649... | Line 5066... | ||
4649 | 5066 | ||
4650 | intel_dp_aux_init(intel_dp, intel_connector); |
5067 | intel_dp_aux_init(intel_dp, intel_connector); |
4651 | 5068 | ||
4652 | /* init MST on ports that can support it */ |
5069 | /* init MST on ports that can support it */ |
- | 5070 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
|
4653 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
5071 | if (port == PORT_B || port == PORT_C || port == PORT_D) { |
4654 | if (port == PORT_B || port == PORT_C || port == PORT_D) { |
5072 | intel_dp_mst_encoder_init(intel_dig_port, |
Line 4655... | Line 5073... | ||
4655 | intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); |
5073 | intel_connector->base.base.id); |
4656 | } |
5074 | } |
4657 | } |
5075 | } |
4658 | 5076 | ||
- | 5077 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
|
4659 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
5078 | drm_dp_aux_unregister(&intel_dp->aux); |
- | 5079 | if (is_edp(intel_dp)) { |
|
- | 5080 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
|
- | 5081 | /* |
|
4660 | drm_dp_aux_unregister(&intel_dp->aux); |
5082 | * vdd might still be enabled do to the delayed vdd off. |
4661 | if (is_edp(intel_dp)) { |
5083 | * Make sure vdd is actually turned off here. |
4662 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5084 | */ |
4663 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5085 | pps_lock(intel_dp); |
4664 | edp_panel_vdd_off_sync(intel_dp); |
5086 | edp_panel_vdd_off_sync(intel_dp); |
4665 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5087 | pps_unlock(intel_dp); |
4666 | } |
5088 | } |
Line 4724... | Line 5146... | ||
4724 | intel_encoder->enable = vlv_enable_dp; |
5146 | intel_encoder->enable = vlv_enable_dp; |
4725 | intel_encoder->post_disable = vlv_post_disable_dp; |
5147 | intel_encoder->post_disable = vlv_post_disable_dp; |
4726 | } else { |
5148 | } else { |
4727 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5149 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
4728 | intel_encoder->enable = g4x_enable_dp; |
5150 | intel_encoder->enable = g4x_enable_dp; |
- | 5151 | if (INTEL_INFO(dev)->gen >= 5) |
|
4729 | intel_encoder->post_disable = g4x_post_disable_dp; |
5152 | intel_encoder->post_disable = ilk_post_disable_dp; |
4730 | } |
5153 | } |
Line 4731... | Line 5154... | ||
4731 | 5154 | ||
4732 | intel_dig_port->port = port; |
5155 | intel_dig_port->port = port; |