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Rev 3746 | Rev 4104 | ||
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Line 50... | Line 50... | ||
50 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
50 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Line 51... | Line 51... | ||
51 | 51 | ||
52 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
52 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Line 53... | Line -... | ||
53 | } |
- | |
54 | - | ||
55 | /** |
- | |
56 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
- | |
57 | * @intel_dp: DP struct |
- | |
58 | * |
- | |
59 | * Returns true if the given DP struct corresponds to a PCH DP port attached |
- | |
60 | * to an eDP panel, false otherwise. Helpful for determining whether we |
- | |
61 | * may need FDI resources for a given DP output or not. |
- | |
62 | */ |
- | |
63 | static bool is_pch_edp(struct intel_dp *intel_dp) |
- | |
64 | { |
- | |
65 | return intel_dp->is_pch_edp; |
- | |
66 | } |
- | |
67 | - | ||
68 | /** |
- | |
69 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? |
- | |
70 | * @intel_dp: DP struct |
- | |
71 | * |
- | |
72 | * Returns true if the given DP struct corresponds to a CPU eDP port. |
- | |
73 | */ |
- | |
74 | static bool is_cpu_edp(struct intel_dp *intel_dp) |
- | |
75 | { |
- | |
76 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); |
- | |
77 | } |
53 | } |
78 | 54 | ||
79 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
55 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
Line 80... | Line 56... | ||
80 | { |
56 | { |
Line 86... | Line 62... | ||
86 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
62 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
87 | { |
63 | { |
88 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
64 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
89 | } |
65 | } |
Line 90... | Line -... | ||
90 | - | ||
91 | /** |
- | |
92 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? |
- | |
93 | * @encoder: DRM encoder |
- | |
94 | * |
- | |
95 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed |
- | |
96 | * by intel_display.c. |
- | |
97 | */ |
- | |
98 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) |
- | |
99 | { |
- | |
100 | struct intel_dp *intel_dp; |
- | |
101 | - | ||
102 | if (!encoder) |
- | |
103 | return false; |
- | |
104 | - | ||
105 | intel_dp = enc_to_intel_dp(encoder); |
- | |
106 | - | ||
107 | return is_pch_edp(intel_dp); |
- | |
108 | } |
- | |
109 | 66 | ||
Line 110... | Line 67... | ||
110 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
67 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
111 | 68 | ||
112 | static int |
69 | static int |
Line 116... | Line 73... | ||
116 | 73 | ||
117 | switch (max_link_bw) { |
74 | switch (max_link_bw) { |
118 | case DP_LINK_BW_1_62: |
75 | case DP_LINK_BW_1_62: |
119 | case DP_LINK_BW_2_7: |
76 | case DP_LINK_BW_2_7: |
- | 77 | break; |
|
- | 78 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
|
- | 79 | max_link_bw = DP_LINK_BW_2_7; |
|
120 | break; |
80 | break; |
- | 81 | default: |
|
- | 82 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
|
121 | default: |
83 | max_link_bw); |
122 | max_link_bw = DP_LINK_BW_1_62; |
84 | max_link_bw = DP_LINK_BW_1_62; |
123 | break; |
85 | break; |
124 | } |
86 | } |
125 | return max_link_bw; |
87 | return max_link_bw; |
Line 301... | Line 263... | ||
301 | bool done; |
263 | bool done; |
Line 302... | Line 264... | ||
302 | 264 | ||
303 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
265 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
304 | if (has_aux_irq) |
266 | if (has_aux_irq) |
305 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
267 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
306 | msecs_to_jiffies(10)); |
268 | msecs_to_jiffies_timeout(10)); |
307 | else |
269 | else |
308 | done = wait_for_atomic(C, 10) == 0; |
270 | done = wait_for_atomic(C, 10) == 0; |
309 | if (!done) |
271 | if (!done) |
310 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
272 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
311 | has_aux_irq); |
273 | has_aux_irq); |
Line 312... | Line 274... | ||
312 | #undef C |
274 | #undef C |
313 | 275 | ||
Line -... | Line 276... | ||
- | 276 | return status; |
|
- | 277 | } |
|
- | 278 | ||
- | 279 | static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, |
|
- | 280 | int index) |
|
- | 281 | { |
|
- | 282 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 283 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 284 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 285 | ||
- | 286 | /* The clock divider is based off the hrawclk, |
|
- | 287 | * and would like to run at 2MHz. So, take the |
|
- | 288 | * hrawclk value and divide by 2 and use that |
|
- | 289 | * |
|
- | 290 | * Note that PCH attached eDP panels should use a 125MHz input |
|
- | 291 | * clock divider. |
|
- | 292 | */ |
|
- | 293 | if (IS_VALLEYVIEW(dev)) { |
|
- | 294 | return index ? 0 : 100; |
|
- | 295 | } else if (intel_dig_port->port == PORT_A) { |
|
- | 296 | if (index) |
|
- | 297 | return 0; |
|
- | 298 | if (HAS_DDI(dev)) |
|
- | 299 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
|
- | 300 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
|
- | 301 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
|
- | 302 | else |
|
- | 303 | return 225; /* eDP input clock at 450Mhz */ |
|
- | 304 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
|
- | 305 | /* Workaround for non-ULT HSW */ |
|
- | 306 | switch (index) { |
|
- | 307 | case 0: return 63; |
|
- | 308 | case 1: return 72; |
|
- | 309 | default: return 0; |
|
- | 310 | } |
|
- | 311 | } else if (HAS_PCH_SPLIT(dev)) { |
|
- | 312 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
|
- | 313 | } else { |
|
- | 314 | return index ? 0 :intel_hrawclk(dev) / 2; |
|
314 | return status; |
315 | } |
315 | } |
316 | } |
316 | 317 | ||
317 | static int |
318 | static int |
318 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
319 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
319 | uint8_t *send, int send_bytes, |
320 | uint8_t *send, int send_bytes, |
320 | uint8_t *recv, int recv_size) |
321 | uint8_t *recv, int recv_size) |
321 | { |
322 | { |
322 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
323 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
323 | struct drm_device *dev = intel_dig_port->base.base.dev; |
324 | struct drm_device *dev = intel_dig_port->base.base.dev; |
- | 325 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
324 | struct drm_i915_private *dev_priv = dev->dev_private; |
326 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
325 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
327 | uint32_t ch_data = ch_ctl + 4; |
326 | uint32_t ch_data = ch_ctl + 4; |
- | |
327 | int i, ret, recv_bytes; |
328 | uint32_t aux_clock_divider; |
328 | uint32_t status; |
329 | int i, ret, recv_bytes; |
Line 329... | Line 330... | ||
329 | uint32_t aux_clock_divider; |
330 | uint32_t status; |
330 | int try, precharge; |
331 | int try, precharge, clock = 0; |
331 | bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); |
332 | bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); |
332 | 333 | ||
333 | /* dp aux is extremely sensitive to irq latency, hence request the |
334 | /* dp aux is extremely sensitive to irq latency, hence request the |
Line 334... | Line 335... | ||
334 | * lowest possible wakeup latency and so prevent the cpu from going into |
335 | * lowest possible wakeup latency and so prevent the cpu from going into |
335 | * deep sleep states. |
- | |
336 | */ |
- | |
337 | // pm_qos_update_request(&dev_priv->pm_qos, 0); |
- | |
338 | - | ||
339 | intel_dp_check_edp(intel_dp); |
- | |
340 | /* The clock divider is based off the hrawclk, |
- | |
341 | * and would like to run at 2MHz. So, take the |
- | |
342 | * hrawclk value and divide by 2 and use that |
- | |
343 | * |
- | |
344 | * Note that PCH attached eDP panels should use a 125MHz input |
- | |
345 | * clock divider. |
- | |
346 | */ |
- | |
347 | if (is_cpu_edp(intel_dp)) { |
- | |
348 | if (HAS_DDI(dev)) |
- | |
349 | aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; |
- | |
350 | else if (IS_VALLEYVIEW(dev)) |
- | |
351 | aux_clock_divider = 100; |
- | |
352 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
- | |
353 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
- | |
354 | else |
- | |
355 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
- | |
356 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
- | |
357 | /* Workaround for non-ULT HSW */ |
- | |
358 | aux_clock_divider = 74; |
- | |
Line 359... | Line 336... | ||
359 | } else if (HAS_PCH_SPLIT(dev)) { |
336 | * deep sleep states. |
360 | aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
337 | */ |
361 | } else { |
338 | // pm_qos_update_request(&dev_priv->pm_qos, 0); |
362 | aux_clock_divider = intel_hrawclk(dev) / 2; |
339 | |
Line -... | Line 340... | ||
- | 340 | intel_dp_check_edp(intel_dp); |
|
- | 341 | ||
363 | } |
342 | if (IS_GEN6(dev)) |
364 | 343 | precharge = 3; |
|
365 | if (IS_GEN6(dev)) |
344 | else |
366 | precharge = 3; |
345 | precharge = 5; |
367 | else |
346 | |
Line 380... | Line 359... | ||
380 | I915_READ(ch_ctl)); |
359 | I915_READ(ch_ctl)); |
381 | ret = -EBUSY; |
360 | ret = -EBUSY; |
382 | goto out; |
361 | goto out; |
383 | } |
362 | } |
Line -... | Line 363... | ||
- | 363 | ||
384 | 364 | while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) { |
|
385 | /* Must try at least 3 times according to DP spec */ |
365 | /* Must try at least 3 times according to DP spec */ |
386 | for (try = 0; try < 5; try++) { |
366 | for (try = 0; try < 5; try++) { |
387 | /* Load the send data into the aux channel data registers */ |
367 | /* Load the send data into the aux channel data registers */ |
388 | for (i = 0; i < send_bytes; i += 4) |
368 | for (i = 0; i < send_bytes; i += 4) |
Line 414... | Line 394... | ||
414 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
394 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
415 | continue; |
395 | continue; |
416 | if (status & DP_AUX_CH_CTL_DONE) |
396 | if (status & DP_AUX_CH_CTL_DONE) |
417 | break; |
397 | break; |
418 | } |
398 | } |
- | 399 | if (status & DP_AUX_CH_CTL_DONE) |
|
- | 400 | break; |
|
- | 401 | } |
|
Line 419... | Line 402... | ||
419 | 402 | ||
420 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
403 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
421 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
404 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
422 | ret = -EBUSY; |
405 | ret = -EBUSY; |
Line 451... | Line 434... | ||
451 | recv + i, recv_bytes - i); |
434 | recv + i, recv_bytes - i); |
Line 452... | Line 435... | ||
452 | 435 | ||
453 | ret = recv_bytes; |
436 | ret = recv_bytes; |
454 | out: |
437 | out: |
- | 438 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
|
Line 455... | Line 439... | ||
455 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
439 | intel_aux_display_runtime_put(dev_priv); |
456 | 440 | ||
Line 457... | Line 441... | ||
457 | return ret; |
441 | return ret; |
Line 602... | Line 586... | ||
602 | break; |
586 | break; |
603 | case AUX_NATIVE_REPLY_NACK: |
587 | case AUX_NATIVE_REPLY_NACK: |
604 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
588 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
605 | return -EREMOTEIO; |
589 | return -EREMOTEIO; |
606 | case AUX_NATIVE_REPLY_DEFER: |
590 | case AUX_NATIVE_REPLY_DEFER: |
607 | udelay(100); |
591 | udelay(500); |
608 | continue; |
592 | continue; |
609 | default: |
593 | default: |
610 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
594 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
611 | reply[0]); |
595 | reply[0]); |
612 | return -EREMOTEIO; |
596 | return -EREMOTEIO; |
Line 658... | Line 642... | ||
658 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
642 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
659 | ironlake_edp_panel_vdd_off(intel_dp, false); |
643 | ironlake_edp_panel_vdd_off(intel_dp, false); |
660 | return ret; |
644 | return ret; |
661 | } |
645 | } |
Line -... | Line 646... | ||
- | 646 | ||
- | 647 | static void |
|
- | 648 | intel_dp_set_clock(struct intel_encoder *encoder, |
|
- | 649 | struct intel_crtc_config *pipe_config, int link_bw) |
|
- | 650 | { |
|
- | 651 | struct drm_device *dev = encoder->base.dev; |
|
- | 652 | ||
- | 653 | if (IS_G4X(dev)) { |
|
- | 654 | if (link_bw == DP_LINK_BW_1_62) { |
|
- | 655 | pipe_config->dpll.p1 = 2; |
|
- | 656 | pipe_config->dpll.p2 = 10; |
|
- | 657 | pipe_config->dpll.n = 2; |
|
- | 658 | pipe_config->dpll.m1 = 23; |
|
- | 659 | pipe_config->dpll.m2 = 8; |
|
- | 660 | } else { |
|
- | 661 | pipe_config->dpll.p1 = 1; |
|
- | 662 | pipe_config->dpll.p2 = 10; |
|
- | 663 | pipe_config->dpll.n = 1; |
|
- | 664 | pipe_config->dpll.m1 = 14; |
|
- | 665 | pipe_config->dpll.m2 = 2; |
|
- | 666 | } |
|
- | 667 | pipe_config->clock_set = true; |
|
- | 668 | } else if (IS_HASWELL(dev)) { |
|
- | 669 | /* Haswell has special-purpose DP DDI clocks. */ |
|
- | 670 | } else if (HAS_PCH_SPLIT(dev)) { |
|
- | 671 | if (link_bw == DP_LINK_BW_1_62) { |
|
- | 672 | pipe_config->dpll.n = 1; |
|
- | 673 | pipe_config->dpll.p1 = 2; |
|
- | 674 | pipe_config->dpll.p2 = 10; |
|
- | 675 | pipe_config->dpll.m1 = 12; |
|
- | 676 | pipe_config->dpll.m2 = 9; |
|
- | 677 | } else { |
|
- | 678 | pipe_config->dpll.n = 2; |
|
- | 679 | pipe_config->dpll.p1 = 1; |
|
- | 680 | pipe_config->dpll.p2 = 10; |
|
- | 681 | pipe_config->dpll.m1 = 14; |
|
- | 682 | pipe_config->dpll.m2 = 8; |
|
- | 683 | } |
|
- | 684 | pipe_config->clock_set = true; |
|
- | 685 | } else if (IS_VALLEYVIEW(dev)) { |
|
- | 686 | /* FIXME: Need to figure out optimized DP clocks for vlv. */ |
|
- | 687 | } |
|
- | 688 | } |
|
662 | 689 | ||
663 | bool |
690 | bool |
664 | intel_dp_compute_config(struct intel_encoder *encoder, |
691 | intel_dp_compute_config(struct intel_encoder *encoder, |
665 | struct intel_crtc_config *pipe_config) |
692 | struct intel_crtc_config *pipe_config) |
666 | { |
693 | { |
667 | struct drm_device *dev = encoder->base.dev; |
694 | struct drm_device *dev = encoder->base.dev; |
668 | struct drm_i915_private *dev_priv = dev->dev_private; |
695 | struct drm_i915_private *dev_priv = dev->dev_private; |
669 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
- | |
670 | struct drm_display_mode *mode = &pipe_config->requested_mode; |
696 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
- | 697 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 698 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
671 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
699 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
672 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
700 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
673 | int lane_count, clock; |
701 | int lane_count, clock; |
674 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
702 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
675 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
703 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
676 | int bpp, mode_rate; |
704 | int bpp, mode_rate; |
677 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
705 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
Line 678... | Line 706... | ||
678 | int target_clock, link_avail, link_clock; |
706 | int link_avail, link_clock; |
679 | 707 | ||
Line 680... | Line 708... | ||
680 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp)) |
708 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Line 681... | Line 709... | ||
681 | pipe_config->has_pch_encoder = true; |
709 | pipe_config->has_pch_encoder = true; |
682 | 710 | ||
683 | pipe_config->has_dp_encoder = true; |
711 | pipe_config->has_dp_encoder = true; |
- | 712 | ||
684 | 713 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
|
685 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
714 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
- | 715 | adjusted_mode); |
|
- | 716 | if (!HAS_PCH_SPLIT(dev)) |
|
686 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
717 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
687 | adjusted_mode); |
718 | intel_connector->panel.fitting_mode); |
688 | intel_pch_panel_fitting(dev, |
- | |
689 | intel_connector->panel.fitting_mode, |
- | |
Line 690... | Line 719... | ||
690 | mode, adjusted_mode); |
719 | else |
691 | } |
720 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
Line 692... | Line 721... | ||
692 | /* We need to take the panel's fixed mode into account. */ |
721 | intel_connector->panel.fitting_mode); |
693 | target_clock = adjusted_mode->clock; |
722 | } |
694 | 723 | ||
Line 695... | Line 724... | ||
695 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
724 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
696 | return false; |
725 | return false; |
697 | 726 | ||
698 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
727 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
- | 728 | "max bw %02x pixel clock %iKHz\n", |
|
- | 729 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
|
699 | "max bw %02x pixel clock %iKHz\n", |
730 | |
- | 731 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
|
Line 700... | Line 732... | ||
700 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
732 | * bpc in between. */ |
701 | 733 | bpp = pipe_config->pipe_bpp; |
|
Line 702... | Line 734... | ||
702 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
734 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) { |
703 | * bpc in between. */ |
735 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
704 | bpp = min_t(int, 8*3, pipe_config->pipe_bpp); |
736 | dev_priv->vbt.edp_bpp); |
705 | if (is_edp(intel_dp) && dev_priv->edp.bpp) |
737 | bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp); |
Line 739... | Line 771... | ||
739 | if (intel_dp->color_range) |
771 | if (intel_dp->color_range) |
740 | pipe_config->limited_color_range = true; |
772 | pipe_config->limited_color_range = true; |
Line 741... | Line 773... | ||
741 | 773 | ||
742 | intel_dp->link_bw = bws[clock]; |
774 | intel_dp->link_bw = bws[clock]; |
743 | intel_dp->lane_count = lane_count; |
- | |
744 | adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
775 | intel_dp->lane_count = lane_count; |
745 | pipe_config->pipe_bpp = bpp; |
776 | pipe_config->pipe_bpp = bpp; |
Line 746... | Line 777... | ||
746 | pipe_config->pixel_target_clock = target_clock; |
777 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
747 | 778 | ||
748 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
779 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
749 | intel_dp->link_bw, intel_dp->lane_count, |
780 | intel_dp->link_bw, intel_dp->lane_count, |
750 | adjusted_mode->clock, bpp); |
781 | pipe_config->port_clock, bpp); |
Line 751... | Line 782... | ||
751 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
782 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
752 | mode_rate, link_avail); |
783 | mode_rate, link_avail); |
753 | 784 | ||
Line -... | Line 785... | ||
- | 785 | intel_link_compute_m_n(bpp, lane_count, |
|
- | 786 | adjusted_mode->clock, pipe_config->port_clock, |
|
754 | intel_link_compute_m_n(bpp, lane_count, |
787 | &pipe_config->dp_m_n); |
755 | target_clock, adjusted_mode->clock, |
788 | |
Line 756... | Line 789... | ||
756 | &pipe_config->dp_m_n); |
789 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
757 | 790 | ||
Line 771... | Line 804... | ||
771 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
804 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
772 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
805 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
773 | } |
806 | } |
774 | } |
807 | } |
Line 775... | Line 808... | ||
775 | 808 | ||
776 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
809 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
- | 810 | { |
|
- | 811 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
777 | { |
812 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
778 | struct drm_device *dev = crtc->dev; |
813 | struct drm_device *dev = crtc->base.dev; |
779 | struct drm_i915_private *dev_priv = dev->dev_private; |
814 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 780... | Line 815... | ||
780 | u32 dpa_ctl; |
815 | u32 dpa_ctl; |
781 | 816 | ||
782 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
817 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
Line 783... | Line 818... | ||
783 | dpa_ctl = I915_READ(DP_A); |
818 | dpa_ctl = I915_READ(DP_A); |
784 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
819 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
785 | 820 | ||
786 | if (clock < 200000) { |
821 | if (crtc->config.port_clock == 162000) { |
787 | /* For a long time we've carried around a ILK-DevA w/a for the |
822 | /* For a long time we've carried around a ILK-DevA w/a for the |
788 | * 160MHz clock. If we're really unlucky, it's still required. |
823 | * 160MHz clock. If we're really unlucky, it's still required. |
- | 824 | */ |
|
789 | */ |
825 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
790 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
826 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
- | 827 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
|
791 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
828 | } else { |
Line 792... | Line 829... | ||
792 | } else { |
829 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
Line 793... | Line 830... | ||
793 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
830 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
794 | } |
831 | } |
795 | 832 | ||
Line 796... | Line -... | ||
796 | I915_WRITE(DP_A, dpa_ctl); |
- | |
797 | 833 | I915_WRITE(DP_A, dpa_ctl); |
|
798 | POSTING_READ(DP_A); |
- | |
799 | udelay(500); |
834 | |
800 | } |
835 | POSTING_READ(DP_A); |
801 | 836 | udelay(500); |
|
802 | static void |
837 | } |
803 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
838 | |
804 | struct drm_display_mode *adjusted_mode) |
839 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
- | 840 | { |
|
Line 805... | Line 841... | ||
805 | { |
841 | struct drm_device *dev = encoder->base.dev; |
806 | struct drm_device *dev = encoder->dev; |
842 | struct drm_i915_private *dev_priv = dev->dev_private; |
807 | struct drm_i915_private *dev_priv = dev->dev_private; |
843 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
808 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
844 | enum port port = dp_to_dig_port(intel_dp)->port; |
Line 831... | Line 867... | ||
831 | */ |
867 | */ |
832 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
868 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Line 833... | Line 869... | ||
833 | 869 | ||
834 | /* Handle DP bits in common between all three register formats */ |
870 | /* Handle DP bits in common between all three register formats */ |
- | 871 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
|
Line 835... | Line -... | ||
835 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
- | |
836 | - | ||
837 | switch (intel_dp->lane_count) { |
- | |
838 | case 1: |
- | |
839 | intel_dp->DP |= DP_PORT_WIDTH_1; |
- | |
840 | break; |
- | |
841 | case 2: |
- | |
842 | intel_dp->DP |= DP_PORT_WIDTH_2; |
- | |
843 | break; |
- | |
844 | case 4: |
- | |
845 | intel_dp->DP |= DP_PORT_WIDTH_4; |
- | |
846 | break; |
872 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
847 | } |
873 | |
848 | if (intel_dp->has_audio) { |
874 | if (intel_dp->has_audio) { |
849 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
875 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
850 | pipe_name(intel_crtc->pipe)); |
876 | pipe_name(crtc->pipe)); |
851 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
877 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Line 852... | Line 878... | ||
852 | intel_write_eld(encoder, adjusted_mode); |
878 | intel_write_eld(&encoder->base, adjusted_mode); |
Line 853... | Line 879... | ||
853 | } |
879 | } |
Line 854... | Line 880... | ||
854 | 880 | ||
855 | intel_dp_init_link_config(intel_dp); |
881 | intel_dp_init_link_config(intel_dp); |
856 | 882 | ||
857 | /* Split out the IBX/CPU vs CPT settings */ |
883 | /* Split out the IBX/CPU vs CPT settings */ |
858 | 884 | ||
859 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
885 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Line 860... | Line 886... | ||
860 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
886 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
861 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
887 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
Line 862... | Line 888... | ||
862 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
888 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
863 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
- | |
864 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
- | |
865 | - | ||
866 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
- | |
867 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
- | |
868 | - | ||
869 | intel_dp->DP |= intel_crtc->pipe << 29; |
889 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
870 | 890 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
|
871 | /* don't miss out required setting for eDP */ |
891 | |
Line 872... | Line 892... | ||
872 | if (adjusted_mode->clock < 200000) |
892 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
873 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
893 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
Line 884... | Line 904... | ||
884 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
904 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
Line 885... | Line 905... | ||
885 | 905 | ||
886 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
906 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
Line 887... | Line 907... | ||
887 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
907 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
888 | 908 | ||
889 | if (intel_crtc->pipe == 1) |
- | |
890 | intel_dp->DP |= DP_PIPEB_SELECT; |
- | |
891 | - | ||
892 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
- | |
893 | /* don't miss out required setting for eDP */ |
- | |
894 | if (adjusted_mode->clock < 200000) |
- | |
895 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
- | |
896 | else |
- | |
897 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
909 | if (crtc->pipe == 1) |
898 | } |
910 | intel_dp->DP |= DP_PIPEB_SELECT; |
899 | } else { |
911 | } else { |
Line 900... | Line 912... | ||
900 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
912 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
901 | } |
913 | } |
902 | 914 | ||
Line 903... | Line 915... | ||
903 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) |
915 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
904 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
916 | ironlake_set_pll_cpu_edp(intel_dp); |
Line 1070... | Line 1082... | ||
1070 | /* |
1082 | /* |
1071 | * Queue the timer to fire a long |
1083 | * Queue the timer to fire a long |
1072 | * time from now (relative to the power down delay) |
1084 | * time from now (relative to the power down delay) |
1073 | * to keep the panel power up across a sequence of operations |
1085 | * to keep the panel power up across a sequence of operations |
1074 | */ |
1086 | */ |
1075 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
1087 | // schedule_delayed_work(&intel_dp->panel_vdd_work, |
1076 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
1088 | // msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
1077 | } |
1089 | } |
1078 | } |
1090 | } |
Line 1079... | Line 1091... | ||
1079 | 1091 | ||
1080 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
1092 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
Line 1288... | Line 1300... | ||
1288 | 1300 | ||
1289 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1301 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1290 | enum pipe *pipe) |
1302 | enum pipe *pipe) |
1291 | { |
1303 | { |
- | 1304 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
1292 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1305 | enum port port = dp_to_dig_port(intel_dp)->port; |
1293 | struct drm_device *dev = encoder->base.dev; |
1306 | struct drm_device *dev = encoder->base.dev; |
1294 | struct drm_i915_private *dev_priv = dev->dev_private; |
1307 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1295... | Line 1308... | ||
1295 | u32 tmp = I915_READ(intel_dp->output_reg); |
1308 | u32 tmp = I915_READ(intel_dp->output_reg); |
1296 | 1309 | ||
Line 1297... | Line 1310... | ||
1297 | if (!(tmp & DP_PORT_EN)) |
1310 | if (!(tmp & DP_PORT_EN)) |
1298 | return false; |
1311 | return false; |
1299 | 1312 | ||
1300 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1313 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1301 | *pipe = PORT_TO_PIPE_CPT(tmp); |
1314 | *pipe = PORT_TO_PIPE_CPT(tmp); |
1302 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
1315 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
1303 | *pipe = PORT_TO_PIPE(tmp); |
1316 | *pipe = PORT_TO_PIPE(tmp); |
1304 | } else { |
1317 | } else { |
Line 1333... | Line 1346... | ||
1333 | } |
1346 | } |
Line 1334... | Line 1347... | ||
1334 | 1347 | ||
1335 | return true; |
1348 | return true; |
Line -... | Line 1349... | ||
- | 1349 | } |
|
- | 1350 | ||
- | 1351 | static void intel_dp_get_config(struct intel_encoder *encoder, |
|
- | 1352 | struct intel_crtc_config *pipe_config) |
|
- | 1353 | { |
|
- | 1354 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 1355 | u32 tmp, flags = 0; |
|
- | 1356 | struct drm_device *dev = encoder->base.dev; |
|
- | 1357 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1358 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
- | 1359 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
|
- | 1360 | ||
- | 1361 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
|
- | 1362 | tmp = I915_READ(intel_dp->output_reg); |
|
- | 1363 | if (tmp & DP_SYNC_HS_HIGH) |
|
- | 1364 | flags |= DRM_MODE_FLAG_PHSYNC; |
|
- | 1365 | else |
|
- | 1366 | flags |= DRM_MODE_FLAG_NHSYNC; |
|
- | 1367 | ||
- | 1368 | if (tmp & DP_SYNC_VS_HIGH) |
|
- | 1369 | flags |= DRM_MODE_FLAG_PVSYNC; |
|
- | 1370 | else |
|
- | 1371 | flags |= DRM_MODE_FLAG_NVSYNC; |
|
- | 1372 | } else { |
|
- | 1373 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
|
- | 1374 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
|
- | 1375 | flags |= DRM_MODE_FLAG_PHSYNC; |
|
- | 1376 | else |
|
- | 1377 | flags |= DRM_MODE_FLAG_NHSYNC; |
|
- | 1378 | ||
- | 1379 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
|
- | 1380 | flags |= DRM_MODE_FLAG_PVSYNC; |
|
- | 1381 | else |
|
- | 1382 | flags |= DRM_MODE_FLAG_NVSYNC; |
|
- | 1383 | } |
|
- | 1384 | ||
- | 1385 | pipe_config->adjusted_mode.flags |= flags; |
|
- | 1386 | ||
- | 1387 | if (dp_to_dig_port(intel_dp)->port == PORT_A) { |
|
- | 1388 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
|
- | 1389 | pipe_config->port_clock = 162000; |
|
- | 1390 | else |
|
- | 1391 | pipe_config->port_clock = 270000; |
|
- | 1392 | } |
|
- | 1393 | } |
|
- | 1394 | ||
- | 1395 | static bool is_edp_psr(struct intel_dp *intel_dp) |
|
- | 1396 | { |
|
- | 1397 | return is_edp(intel_dp) && |
|
- | 1398 | intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; |
|
- | 1399 | } |
|
- | 1400 | ||
- | 1401 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
|
- | 1402 | { |
|
- | 1403 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1404 | ||
- | 1405 | if (!IS_HASWELL(dev)) |
|
- | 1406 | return false; |
|
- | 1407 | ||
- | 1408 | return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
|
- | 1409 | } |
|
- | 1410 | ||
- | 1411 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
|
- | 1412 | struct edp_vsc_psr *vsc_psr) |
|
- | 1413 | { |
|
- | 1414 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
- | 1415 | struct drm_device *dev = dig_port->base.base.dev; |
|
- | 1416 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1417 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
|
- | 1418 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
|
- | 1419 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
|
- | 1420 | uint32_t *data = (uint32_t *) vsc_psr; |
|
- | 1421 | unsigned int i; |
|
- | 1422 | ||
- | 1423 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
|
- | 1424 | the video DIP being updated before program video DIP data buffer |
|
- | 1425 | registers for DIP being updated. */ |
|
- | 1426 | I915_WRITE(ctl_reg, 0); |
|
- | 1427 | POSTING_READ(ctl_reg); |
|
- | 1428 | ||
- | 1429 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
|
- | 1430 | if (i < sizeof(struct edp_vsc_psr)) |
|
- | 1431 | I915_WRITE(data_reg + i, *data++); |
|
- | 1432 | else |
|
- | 1433 | I915_WRITE(data_reg + i, 0); |
|
- | 1434 | } |
|
- | 1435 | ||
- | 1436 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
|
- | 1437 | POSTING_READ(ctl_reg); |
|
- | 1438 | } |
|
- | 1439 | ||
- | 1440 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) |
|
- | 1441 | { |
|
- | 1442 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1443 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1444 | struct edp_vsc_psr psr_vsc; |
|
- | 1445 | ||
- | 1446 | if (intel_dp->psr_setup_done) |
|
- | 1447 | return; |
|
- | 1448 | ||
- | 1449 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
|
- | 1450 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
|
- | 1451 | psr_vsc.sdp_header.HB0 = 0; |
|
- | 1452 | psr_vsc.sdp_header.HB1 = 0x7; |
|
- | 1453 | psr_vsc.sdp_header.HB2 = 0x2; |
|
- | 1454 | psr_vsc.sdp_header.HB3 = 0x8; |
|
- | 1455 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
|
- | 1456 | ||
- | 1457 | /* Avoid continuous PSR exit by masking memup and hpd */ |
|
- | 1458 | I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP | |
|
- | 1459 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
|
- | 1460 | ||
- | 1461 | intel_dp->psr_setup_done = true; |
|
- | 1462 | } |
|
- | 1463 | ||
- | 1464 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
|
- | 1465 | { |
|
- | 1466 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1467 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1468 | uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0); |
|
- | 1469 | int precharge = 0x3; |
|
- | 1470 | int msg_size = 5; /* Header(4) + Message(1) */ |
|
- | 1471 | ||
- | 1472 | /* Enable PSR in sink */ |
|
- | 1473 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) |
|
- | 1474 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
|
- | 1475 | DP_PSR_ENABLE & |
|
- | 1476 | ~DP_PSR_MAIN_LINK_ACTIVE); |
|
- | 1477 | else |
|
- | 1478 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
|
- | 1479 | DP_PSR_ENABLE | |
|
- | 1480 | DP_PSR_MAIN_LINK_ACTIVE); |
|
- | 1481 | ||
- | 1482 | /* Setup AUX registers */ |
|
- | 1483 | I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND); |
|
- | 1484 | I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION); |
|
- | 1485 | I915_WRITE(EDP_PSR_AUX_CTL, |
|
- | 1486 | DP_AUX_CH_CTL_TIME_OUT_400us | |
|
- | 1487 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
|
- | 1488 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
|
- | 1489 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
|
- | 1490 | } |
|
- | 1491 | ||
- | 1492 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
|
- | 1493 | { |
|
- | 1494 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1496 | uint32_t max_sleep_time = 0x1f; |
|
- | 1497 | uint32_t idle_frames = 1; |
|
- | 1498 | uint32_t val = 0x0; |
|
- | 1499 | ||
- | 1500 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { |
|
- | 1501 | val |= EDP_PSR_LINK_STANDBY; |
|
- | 1502 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
|
- | 1503 | val |= EDP_PSR_TP1_TIME_0us; |
|
- | 1504 | val |= EDP_PSR_SKIP_AUX_EXIT; |
|
- | 1505 | } else |
|
- | 1506 | val |= EDP_PSR_LINK_DISABLE; |
|
- | 1507 | ||
- | 1508 | I915_WRITE(EDP_PSR_CTL, val | |
|
- | 1509 | EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES | |
|
- | 1510 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
|
- | 1511 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
|
- | 1512 | EDP_PSR_ENABLE); |
|
- | 1513 | } |
|
- | 1514 | ||
- | 1515 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
|
- | 1516 | { |
|
- | 1517 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
- | 1518 | struct drm_device *dev = dig_port->base.base.dev; |
|
- | 1519 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1520 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
|
- | 1521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 1522 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; |
|
- | 1523 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
|
- | 1524 | ||
- | 1525 | if (!IS_HASWELL(dev)) { |
|
- | 1526 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
|
- | 1527 | dev_priv->no_psr_reason = PSR_NO_SOURCE; |
|
- | 1528 | return false; |
|
- | 1529 | } |
|
- | 1530 | ||
- | 1531 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || |
|
- | 1532 | (dig_port->port != PORT_A)) { |
|
- | 1533 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
|
- | 1534 | dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA; |
|
- | 1535 | return false; |
|
- | 1536 | } |
|
- | 1537 | ||
- | 1538 | if (!is_edp_psr(intel_dp)) { |
|
- | 1539 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); |
|
- | 1540 | dev_priv->no_psr_reason = PSR_NO_SINK; |
|
- | 1541 | return false; |
|
- | 1542 | } |
|
- | 1543 | ||
- | 1544 | if (!i915_enable_psr) { |
|
- | 1545 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
|
- | 1546 | dev_priv->no_psr_reason = PSR_MODULE_PARAM; |
|
- | 1547 | return false; |
|
- | 1548 | } |
|
- | 1549 | ||
- | 1550 | crtc = dig_port->base.base.crtc; |
|
- | 1551 | if (crtc == NULL) { |
|
- | 1552 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
|
- | 1553 | dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE; |
|
- | 1554 | return false; |
|
- | 1555 | } |
|
- | 1556 | ||
- | 1557 | intel_crtc = to_intel_crtc(crtc); |
|
- | 1558 | if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) { |
|
- | 1559 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
|
- | 1560 | dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE; |
|
- | 1561 | return false; |
|
- | 1562 | } |
|
- | 1563 | ||
- | 1564 | obj = to_intel_framebuffer(crtc->fb)->obj; |
|
- | 1565 | if (obj->tiling_mode != I915_TILING_X || |
|
- | 1566 | obj->fence_reg == I915_FENCE_REG_NONE) { |
|
- | 1567 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); |
|
- | 1568 | dev_priv->no_psr_reason = PSR_NOT_TILED; |
|
- | 1569 | return false; |
|
- | 1570 | } |
|
- | 1571 | ||
- | 1572 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { |
|
- | 1573 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); |
|
- | 1574 | dev_priv->no_psr_reason = PSR_SPRITE_ENABLED; |
|
- | 1575 | return false; |
|
- | 1576 | } |
|
- | 1577 | ||
- | 1578 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
|
- | 1579 | S3D_ENABLE) { |
|
- | 1580 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
|
- | 1581 | dev_priv->no_psr_reason = PSR_S3D_ENABLED; |
|
- | 1582 | return false; |
|
- | 1583 | } |
|
- | 1584 | ||
- | 1585 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { |
|
- | 1586 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
|
- | 1587 | dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED; |
|
- | 1588 | return false; |
|
- | 1589 | } |
|
- | 1590 | ||
- | 1591 | return true; |
|
- | 1592 | } |
|
- | 1593 | ||
- | 1594 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
|
- | 1595 | { |
|
- | 1596 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1597 | ||
- | 1598 | if (!intel_edp_psr_match_conditions(intel_dp) || |
|
- | 1599 | intel_edp_is_psr_enabled(dev)) |
|
- | 1600 | return; |
|
- | 1601 | ||
- | 1602 | /* Setup PSR once */ |
|
- | 1603 | intel_edp_psr_setup(intel_dp); |
|
- | 1604 | ||
- | 1605 | /* Enable PSR on the panel */ |
|
- | 1606 | intel_edp_psr_enable_sink(intel_dp); |
|
- | 1607 | ||
- | 1608 | /* Enable PSR on the host */ |
|
- | 1609 | intel_edp_psr_enable_source(intel_dp); |
|
- | 1610 | } |
|
- | 1611 | ||
- | 1612 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
|
- | 1613 | { |
|
- | 1614 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1615 | ||
- | 1616 | if (intel_edp_psr_match_conditions(intel_dp) && |
|
- | 1617 | !intel_edp_is_psr_enabled(dev)) |
|
- | 1618 | intel_edp_psr_do_enable(intel_dp); |
|
- | 1619 | } |
|
- | 1620 | ||
- | 1621 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
|
- | 1622 | { |
|
- | 1623 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1624 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1625 | ||
- | 1626 | if (!intel_edp_is_psr_enabled(dev)) |
|
- | 1627 | return; |
|
- | 1628 | ||
- | 1629 | I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); |
|
- | 1630 | ||
- | 1631 | /* Wait till PSR is idle */ |
|
- | 1632 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) & |
|
- | 1633 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
|
- | 1634 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
|
- | 1635 | } |
|
- | 1636 | ||
- | 1637 | void intel_edp_psr_update(struct drm_device *dev) |
|
- | 1638 | { |
|
- | 1639 | struct intel_encoder *encoder; |
|
- | 1640 | struct intel_dp *intel_dp = NULL; |
|
- | 1641 | ||
- | 1642 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) |
|
- | 1643 | if (encoder->type == INTEL_OUTPUT_EDP) { |
|
- | 1644 | intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 1645 | ||
- | 1646 | if (!is_edp_psr(intel_dp)) |
|
- | 1647 | return; |
|
- | 1648 | ||
- | 1649 | if (!intel_edp_psr_match_conditions(intel_dp)) |
|
- | 1650 | intel_edp_psr_disable(intel_dp); |
|
- | 1651 | else |
|
- | 1652 | if (!intel_edp_is_psr_enabled(dev)) |
|
- | 1653 | intel_edp_psr_do_enable(intel_dp); |
|
- | 1654 | } |
|
1336 | } |
1655 | } |
1337 | 1656 | ||
1338 | static void intel_disable_dp(struct intel_encoder *encoder) |
1657 | static void intel_disable_dp(struct intel_encoder *encoder) |
- | 1658 | { |
|
- | 1659 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
Line 1339... | Line 1660... | ||
1339 | { |
1660 | enum port port = dp_to_dig_port(intel_dp)->port; |
1340 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1661 | struct drm_device *dev = encoder->base.dev; |
1341 | 1662 | ||
1342 | /* Make sure the panel is off before trying to change the mode. But also |
1663 | /* Make sure the panel is off before trying to change the mode. But also |
1343 | * ensure that we have vdd while we switch off the panel. */ |
1664 | * ensure that we have vdd while we switch off the panel. */ |
1344 | ironlake_edp_panel_vdd_on(intel_dp); |
1665 | ironlake_edp_panel_vdd_on(intel_dp); |
Line 1345... | Line 1666... | ||
1345 | ironlake_edp_backlight_off(intel_dp); |
1666 | ironlake_edp_backlight_off(intel_dp); |
1346 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
1667 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
1347 | ironlake_edp_panel_off(intel_dp); |
1668 | ironlake_edp_panel_off(intel_dp); |
1348 | 1669 | ||
Line 1349... | Line 1670... | ||
1349 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
1670 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
1350 | if (!is_cpu_edp(intel_dp)) |
1671 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
1351 | intel_dp_link_down(intel_dp); |
1672 | intel_dp_link_down(intel_dp); |
- | 1673 | } |
|
1352 | } |
1674 | |
Line 1353... | Line 1675... | ||
1353 | 1675 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
|
1354 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
1676 | { |
1355 | { |
1677 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1356 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1678 | enum port port = dp_to_dig_port(intel_dp)->port; |
1357 | struct drm_device *dev = encoder->base.dev; |
1679 | struct drm_device *dev = encoder->base.dev; |
1358 | 1680 | ||
Line 1381... | Line 1703... | ||
1381 | intel_dp_complete_link_train(intel_dp); |
1703 | intel_dp_complete_link_train(intel_dp); |
1382 | intel_dp_stop_link_train(intel_dp); |
1704 | intel_dp_stop_link_train(intel_dp); |
1383 | ironlake_edp_backlight_on(intel_dp); |
1705 | ironlake_edp_backlight_on(intel_dp); |
1384 | } |
1706 | } |
Line -... | Line 1707... | ||
- | 1707 | ||
- | 1708 | static void vlv_enable_dp(struct intel_encoder *encoder) |
|
- | 1709 | { |
|
- | 1710 | } |
|
1385 | 1711 | ||
1386 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
1712 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
1387 | { |
1713 | { |
1388 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1714 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Line 1389... | Line 1715... | ||
1389 | struct drm_device *dev = encoder->base.dev; |
1715 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
1390 | 1716 | ||
1391 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) |
1717 | if (dport->port == PORT_A) |
Line -... | Line 1718... | ||
- | 1718 | ironlake_edp_pll_on(intel_dp); |
|
- | 1719 | } |
|
- | 1720 | ||
- | 1721 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
|
- | 1722 | { |
|
- | 1723 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 1724 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 1725 | struct drm_device *dev = encoder->base.dev; |
|
- | 1726 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1727 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
|
- | 1728 | int port = vlv_dport_to_channel(dport); |
|
- | 1729 | int pipe = intel_crtc->pipe; |
|
- | 1730 | u32 val; |
|
- | 1731 | ||
- | 1732 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1733 | ||
- | 1734 | val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); |
|
- | 1735 | val = 0; |
|
- | 1736 | if (pipe) |
|
- | 1737 | val |= (1<<21); |
|
- | 1738 | else |
|
- | 1739 | val &= ~(1<<21); |
|
- | 1740 | val |= 0x001000c4; |
|
- | 1741 | vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val); |
|
- | 1742 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018); |
|
- | 1743 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888); |
|
- | 1744 | ||
- | 1745 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 1746 | ||
- | 1747 | intel_enable_dp(encoder); |
|
- | 1748 | ||
- | 1749 | vlv_wait_port_ready(dev_priv, port); |
|
- | 1750 | } |
|
- | 1751 | ||
- | 1752 | static void intel_dp_pre_pll_enable(struct intel_encoder *encoder) |
|
- | 1753 | { |
|
- | 1754 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
|
- | 1755 | struct drm_device *dev = encoder->base.dev; |
|
- | 1756 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1757 | int port = vlv_dport_to_channel(dport); |
|
- | 1758 | ||
- | 1759 | if (!IS_VALLEYVIEW(dev)) |
|
- | 1760 | return; |
|
- | 1761 | ||
- | 1762 | /* Program Tx lane resets to default */ |
|
- | 1763 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1764 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), |
|
- | 1765 | DPIO_PCS_TX_LANE2_RESET | |
|
- | 1766 | DPIO_PCS_TX_LANE1_RESET); |
|
- | 1767 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), |
|
- | 1768 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
|
- | 1769 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
|
- | 1770 | (1< |
|
- | 1771 | DPIO_PCS_CLK_SOFT_RESET); |
|
- | 1772 | ||
- | 1773 | /* Fix up inter-pair skew failure */ |
|
- | 1774 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00); |
|
- | 1775 | vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500); |
|
- | 1776 | vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000); |
|
1392 | ironlake_edp_pll_on(intel_dp); |
1777 | mutex_unlock(&dev_priv->dpio_lock); |
1393 | } |
1778 | } |
1394 | 1779 | ||
1395 | /* |
1780 | /* |
1396 | * Native read with retry for link status and receiver capability reads for |
1781 | * Native read with retry for link status and receiver capability reads for |
Line 1449... | Line 1834... | ||
1449 | 1834 | ||
1450 | static uint8_t |
1835 | static uint8_t |
1451 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
1836 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
1452 | { |
1837 | { |
- | 1838 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
Line -... | Line 1839... | ||
- | 1839 | enum port port = dp_to_dig_port(intel_dp)->port; |
|
- | 1840 | ||
1453 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1841 | if (IS_VALLEYVIEW(dev)) |
1454 | 1842 | return DP_TRAIN_VOLTAGE_SWING_1200; |
|
1455 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) |
1843 | else if (IS_GEN7(dev) && port == PORT_A) |
1456 | return DP_TRAIN_VOLTAGE_SWING_800; |
1844 | return DP_TRAIN_VOLTAGE_SWING_800; |
1457 | else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
1845 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
1458 | return DP_TRAIN_VOLTAGE_SWING_1200; |
1846 | return DP_TRAIN_VOLTAGE_SWING_1200; |
1459 | else |
1847 | else |
Line 1460... | Line 1848... | ||
1460 | return DP_TRAIN_VOLTAGE_SWING_800; |
1848 | return DP_TRAIN_VOLTAGE_SWING_800; |
1461 | } |
1849 | } |
1462 | 1850 | ||
1463 | static uint8_t |
1851 | static uint8_t |
- | 1852 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
|
Line 1464... | Line 1853... | ||
1464 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
1853 | { |
1465 | { |
1854 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1466 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1855 | enum port port = dp_to_dig_port(intel_dp)->port; |
1467 | 1856 | ||
Line 1475... | Line 1864... | ||
1475 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
1864 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
1476 | case DP_TRAIN_VOLTAGE_SWING_1200: |
1865 | case DP_TRAIN_VOLTAGE_SWING_1200: |
1477 | default: |
1866 | default: |
1478 | return DP_TRAIN_PRE_EMPHASIS_0; |
1867 | return DP_TRAIN_PRE_EMPHASIS_0; |
1479 | } |
1868 | } |
- | 1869 | } else if (IS_VALLEYVIEW(dev)) { |
|
- | 1870 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 1871 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 1872 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
|
- | 1873 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 1874 | return DP_TRAIN_PRE_EMPHASIS_6; |
|
- | 1875 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 1876 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
|
- | 1877 | case DP_TRAIN_VOLTAGE_SWING_1200: |
|
- | 1878 | default: |
|
- | 1879 | return DP_TRAIN_PRE_EMPHASIS_0; |
|
- | 1880 | } |
|
1480 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
1881 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1481 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1882 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1482 | case DP_TRAIN_VOLTAGE_SWING_400: |
1883 | case DP_TRAIN_VOLTAGE_SWING_400: |
1483 | return DP_TRAIN_PRE_EMPHASIS_6; |
1884 | return DP_TRAIN_PRE_EMPHASIS_6; |
1484 | case DP_TRAIN_VOLTAGE_SWING_600: |
1885 | case DP_TRAIN_VOLTAGE_SWING_600: |
1485 | case DP_TRAIN_VOLTAGE_SWING_800: |
1886 | case DP_TRAIN_VOLTAGE_SWING_800: |
Line 1500... | Line 1901... | ||
1500 | return DP_TRAIN_PRE_EMPHASIS_0; |
1901 | return DP_TRAIN_PRE_EMPHASIS_0; |
1501 | } |
1902 | } |
1502 | } |
1903 | } |
1503 | } |
1904 | } |
Line -... | Line 1905... | ||
- | 1905 | ||
- | 1906 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
|
- | 1907 | { |
|
- | 1908 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1909 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1910 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 1911 | unsigned long demph_reg_value, preemph_reg_value, |
|
- | 1912 | uniqtranscale_reg_value; |
|
- | 1913 | uint8_t train_set = intel_dp->train_set[0]; |
|
- | 1914 | int port = vlv_dport_to_channel(dport); |
|
- | 1915 | ||
- | 1916 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
|
- | 1917 | case DP_TRAIN_PRE_EMPHASIS_0: |
|
- | 1918 | preemph_reg_value = 0x0004000; |
|
- | 1919 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 1920 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 1921 | demph_reg_value = 0x2B405555; |
|
- | 1922 | uniqtranscale_reg_value = 0x552AB83A; |
|
- | 1923 | break; |
|
- | 1924 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 1925 | demph_reg_value = 0x2B404040; |
|
- | 1926 | uniqtranscale_reg_value = 0x5548B83A; |
|
- | 1927 | break; |
|
- | 1928 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 1929 | demph_reg_value = 0x2B245555; |
|
- | 1930 | uniqtranscale_reg_value = 0x5560B83A; |
|
- | 1931 | break; |
|
- | 1932 | case DP_TRAIN_VOLTAGE_SWING_1200: |
|
- | 1933 | demph_reg_value = 0x2B405555; |
|
- | 1934 | uniqtranscale_reg_value = 0x5598DA3A; |
|
- | 1935 | break; |
|
- | 1936 | default: |
|
- | 1937 | return 0; |
|
- | 1938 | } |
|
- | 1939 | break; |
|
- | 1940 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
|
- | 1941 | preemph_reg_value = 0x0002000; |
|
- | 1942 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 1943 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 1944 | demph_reg_value = 0x2B404040; |
|
- | 1945 | uniqtranscale_reg_value = 0x5552B83A; |
|
- | 1946 | break; |
|
- | 1947 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 1948 | demph_reg_value = 0x2B404848; |
|
- | 1949 | uniqtranscale_reg_value = 0x5580B83A; |
|
- | 1950 | break; |
|
- | 1951 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 1952 | demph_reg_value = 0x2B404040; |
|
- | 1953 | uniqtranscale_reg_value = 0x55ADDA3A; |
|
- | 1954 | break; |
|
- | 1955 | default: |
|
- | 1956 | return 0; |
|
- | 1957 | } |
|
- | 1958 | break; |
|
- | 1959 | case DP_TRAIN_PRE_EMPHASIS_6: |
|
- | 1960 | preemph_reg_value = 0x0000000; |
|
- | 1961 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 1962 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 1963 | demph_reg_value = 0x2B305555; |
|
- | 1964 | uniqtranscale_reg_value = 0x5570B83A; |
|
- | 1965 | break; |
|
- | 1966 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 1967 | demph_reg_value = 0x2B2B4040; |
|
- | 1968 | uniqtranscale_reg_value = 0x55ADDA3A; |
|
- | 1969 | break; |
|
- | 1970 | default: |
|
- | 1971 | return 0; |
|
- | 1972 | } |
|
- | 1973 | break; |
|
- | 1974 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
|
- | 1975 | preemph_reg_value = 0x0006000; |
|
- | 1976 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 1977 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 1978 | demph_reg_value = 0x1B405555; |
|
- | 1979 | uniqtranscale_reg_value = 0x55ADDA3A; |
|
- | 1980 | break; |
|
- | 1981 | default: |
|
- | 1982 | return 0; |
|
- | 1983 | } |
|
- | 1984 | break; |
|
- | 1985 | default: |
|
- | 1986 | return 0; |
|
- | 1987 | } |
|
- | 1988 | ||
- | 1989 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 1990 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000); |
|
- | 1991 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value); |
|
- | 1992 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port), |
|
- | 1993 | uniqtranscale_reg_value); |
|
- | 1994 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040); |
|
- | 1995 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000); |
|
- | 1996 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value); |
|
- | 1997 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000); |
|
- | 1998 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 1999 | ||
- | 2000 | return 0; |
|
- | 2001 | } |
|
1504 | 2002 | ||
1505 | static void |
2003 | static void |
1506 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2004 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
1507 | { |
2005 | { |
1508 | uint8_t v = 0; |
2006 | uint8_t v = 0; |
Line 1667... | Line 2165... | ||
1667 | /* Properly updates "DP" with the correct signal levels. */ |
2165 | /* Properly updates "DP" with the correct signal levels. */ |
1668 | static void |
2166 | static void |
1669 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
2167 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
1670 | { |
2168 | { |
1671 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2169 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | 2170 | enum port port = intel_dig_port->port; |
|
1672 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2171 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1673 | uint32_t signal_levels, mask; |
2172 | uint32_t signal_levels, mask; |
1674 | uint8_t train_set = intel_dp->train_set[0]; |
2173 | uint8_t train_set = intel_dp->train_set[0]; |
Line 1675... | Line 2174... | ||
1675 | 2174 | ||
1676 | if (HAS_DDI(dev)) { |
2175 | if (HAS_DDI(dev)) { |
1677 | signal_levels = intel_hsw_signal_levels(train_set); |
2176 | signal_levels = intel_hsw_signal_levels(train_set); |
- | 2177 | mask = DDI_BUF_EMP_MASK; |
|
- | 2178 | } else if (IS_VALLEYVIEW(dev)) { |
|
- | 2179 | signal_levels = intel_vlv_signal_levels(intel_dp); |
|
1678 | mask = DDI_BUF_EMP_MASK; |
2180 | mask = 0; |
1679 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
2181 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1680 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2182 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
1681 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
2183 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
1682 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
2184 | } else if (IS_GEN6(dev) && port == PORT_A) { |
1683 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2185 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
1684 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
2186 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
1685 | } else { |
2187 | } else { |
1686 | signal_levels = intel_gen4_signal_levels(train_set); |
2188 | signal_levels = intel_gen4_signal_levels(train_set); |
Line 1727... | Line 2229... | ||
1727 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2229 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
1728 | break; |
2230 | break; |
1729 | } |
2231 | } |
1730 | I915_WRITE(DP_TP_CTL(port), temp); |
2232 | I915_WRITE(DP_TP_CTL(port), temp); |
Line 1731... | Line 2233... | ||
1731 | 2233 | ||
1732 | } else if (HAS_PCH_CPT(dev) && |
- | |
1733 | (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
2234 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
Line 1734... | Line 2235... | ||
1734 | dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; |
2235 | dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; |
1735 | 2236 | ||
1736 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2237 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
Line 1826... | Line 2327... | ||
1826 | { |
2327 | { |
1827 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
2328 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
1828 | struct drm_device *dev = encoder->dev; |
2329 | struct drm_device *dev = encoder->dev; |
1829 | int i; |
2330 | int i; |
1830 | uint8_t voltage; |
2331 | uint8_t voltage; |
1831 | bool clock_recovery = false; |
- | |
1832 | int voltage_tries, loop_tries; |
2332 | int voltage_tries, loop_tries; |
1833 | uint32_t DP = intel_dp->DP; |
2333 | uint32_t DP = intel_dp->DP; |
Line 1834... | Line 2334... | ||
1834 | 2334 | ||
1835 | if (HAS_DDI(dev)) |
2335 | if (HAS_DDI(dev)) |
Line 1844... | Line 2344... | ||
1844 | 2344 | ||
1845 | memset(intel_dp->train_set, 0, 4); |
2345 | memset(intel_dp->train_set, 0, 4); |
1846 | voltage = 0xff; |
2346 | voltage = 0xff; |
1847 | voltage_tries = 0; |
2347 | voltage_tries = 0; |
1848 | loop_tries = 0; |
- | |
1849 | clock_recovery = false; |
2348 | loop_tries = 0; |
1850 | for (;;) { |
2349 | for (;;) { |
1851 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
2350 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Line 1852... | Line 2351... | ||
1852 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
2351 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Line 1865... | Line 2364... | ||
1865 | break; |
2364 | break; |
1866 | } |
2365 | } |
Line 1867... | Line 2366... | ||
1867 | 2366 | ||
1868 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2367 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1869 | DRM_DEBUG_KMS("clock recovery OK\n"); |
- | |
1870 | clock_recovery = true; |
2368 | DRM_DEBUG_KMS("clock recovery OK\n"); |
1871 | break; |
2369 | break; |
Line 1872... | Line 2370... | ||
1872 | } |
2370 | } |
1873 | 2371 | ||
Line 1979... | Line 2477... | ||
1979 | 2477 | ||
1980 | static void |
2478 | static void |
1981 | intel_dp_link_down(struct intel_dp *intel_dp) |
2479 | intel_dp_link_down(struct intel_dp *intel_dp) |
1982 | { |
2480 | { |
- | 2481 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
1983 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2482 | enum port port = intel_dig_port->port; |
1984 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2483 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1985 | struct drm_i915_private *dev_priv = dev->dev_private; |
2484 | struct drm_i915_private *dev_priv = dev->dev_private; |
1986 | struct intel_crtc *intel_crtc = |
2485 | struct intel_crtc *intel_crtc = |
1987 | to_intel_crtc(intel_dig_port->base.base.crtc); |
2486 | to_intel_crtc(intel_dig_port->base.base.crtc); |
Line 2008... | Line 2507... | ||
2008 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
2507 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
2009 | return; |
2508 | return; |
Line 2010... | Line 2509... | ||
2010 | 2509 | ||
Line 2011... | Line 2510... | ||
2011 | DRM_DEBUG_KMS("\n"); |
2510 | DRM_DEBUG_KMS("\n"); |
2012 | 2511 | ||
2013 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
2512 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
2014 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2513 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2015 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
2514 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
2016 | } else { |
2515 | } else { |
Line 2070... | Line 2569... | ||
2070 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
2569 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
Line 2071... | Line 2570... | ||
2071 | 2570 | ||
2072 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2571 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
Line -... | Line 2572... | ||
- | 2572 | return false; /* DPCD not present */ |
|
- | 2573 | ||
- | 2574 | /* Check if the panel supports PSR */ |
|
- | 2575 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
|
- | 2576 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, |
|
- | 2577 | intel_dp->psr_dpcd, |
|
- | 2578 | sizeof(intel_dp->psr_dpcd)); |
|
2073 | return false; /* DPCD not present */ |
2579 | if (is_edp_psr(intel_dp)) |
2074 | 2580 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
|
2075 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
2581 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
Line 2076... | Line 2582... | ||
2076 | DP_DWN_STRM_PORT_PRESENT)) |
2582 | DP_DWN_STRM_PORT_PRESENT)) |
Line 2299... | Line 2805... | ||
2299 | /* invalid edid */ |
2805 | /* invalid edid */ |
2300 | if (IS_ERR(intel_connector->edid)) |
2806 | if (IS_ERR(intel_connector->edid)) |
2301 | return NULL; |
2807 | return NULL; |
Line 2302... | Line 2808... | ||
2302 | 2808 | ||
2303 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
2809 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
2304 | edid = kmalloc(size, GFP_KERNEL); |
2810 | edid = kmemdup(intel_connector->edid, size, GFP_KERNEL); |
2305 | if (!edid) |
2811 | if (!edid) |
Line 2306... | Line -... | ||
2306 | return NULL; |
- | |
2307 | 2812 | return NULL; |
|
2308 | memcpy(edid, intel_connector->edid, size); |
2813 | |
Line 2309... | Line 2814... | ||
2309 | return edid; |
2814 | return edid; |
2310 | } |
2815 | } |
Line 2338... | Line 2843... | ||
2338 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2843 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2339 | struct drm_device *dev = connector->dev; |
2844 | struct drm_device *dev = connector->dev; |
2340 | enum drm_connector_status status; |
2845 | enum drm_connector_status status; |
2341 | struct edid *edid = NULL; |
2846 | struct edid *edid = NULL; |
Line -... | Line 2847... | ||
- | 2847 | ||
- | 2848 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
|
- | 2849 | connector->base.id, drm_get_connector_name(connector)); |
|
2342 | 2850 | ||
Line 2343... | Line 2851... | ||
2343 | intel_dp->has_audio = false; |
2851 | intel_dp->has_audio = false; |
2344 | 2852 | ||
2345 | if (HAS_PCH_SPLIT(dev)) |
2853 | if (HAS_PCH_SPLIT(dev)) |
Line 2497... | Line 3005... | ||
2497 | 3005 | ||
2498 | return 0; |
3006 | return 0; |
Line 2499... | Line 3007... | ||
2499 | } |
3007 | } |
2500 | 3008 | ||
2501 | static void |
3009 | static void |
2502 | intel_dp_destroy(struct drm_connector *connector) |
- | |
2503 | { |
3010 | intel_dp_connector_destroy(struct drm_connector *connector) |
Line 2504... | Line 3011... | ||
2504 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3011 | { |
2505 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3012 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Line -... | Line 3013... | ||
- | 3013 | ||
2506 | 3014 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
|
- | 3015 | kfree(intel_connector->edid); |
|
2507 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3016 | |
Line 2508... | Line 3017... | ||
2508 | kfree(intel_connector->edid); |
3017 | /* Can't call is_edp() since the encoder may have been destroyed |
2509 | 3018 | * already. */ |
|
2510 | if (is_edp(intel_dp)) |
3019 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
Line 2530... | Line 3039... | ||
2530 | mutex_unlock(&dev->mode_config.mutex); |
3039 | mutex_unlock(&dev->mode_config.mutex); |
2531 | } |
3040 | } |
2532 | kfree(intel_dig_port); |
3041 | kfree(intel_dig_port); |
2533 | } |
3042 | } |
Line 2534... | Line -... | ||
2534 | - | ||
2535 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
- | |
2536 | .mode_set = intel_dp_mode_set, |
- | |
2537 | }; |
- | |
2538 | 3043 | ||
2539 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
3044 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
2540 | .dpms = intel_connector_dpms, |
3045 | .dpms = intel_connector_dpms, |
2541 | .detect = intel_dp_detect, |
3046 | .detect = intel_dp_detect, |
2542 | .fill_modes = drm_helper_probe_single_connector_modes, |
3047 | .fill_modes = drm_helper_probe_single_connector_modes, |
2543 | .set_property = intel_dp_set_property, |
3048 | .set_property = intel_dp_set_property, |
2544 | .destroy = intel_dp_destroy, |
3049 | .destroy = intel_dp_connector_destroy, |
Line 2545... | Line 3050... | ||
2545 | }; |
3050 | }; |
2546 | 3051 | ||
2547 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
3052 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
Line 2586... | Line 3091... | ||
2586 | { |
3091 | { |
2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
3092 | struct drm_i915_private *dev_priv = dev->dev_private; |
2588 | struct child_device_config *p_child; |
3093 | struct child_device_config *p_child; |
2589 | int i; |
3094 | int i; |
Line 2590... | Line 3095... | ||
2590 | 3095 | ||
2591 | if (!dev_priv->child_dev_num) |
3096 | if (!dev_priv->vbt.child_dev_num) |
Line 2592... | Line 3097... | ||
2592 | return false; |
3097 | return false; |
2593 | 3098 | ||
Line 2594... | Line 3099... | ||
2594 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
3099 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
2595 | p_child = dev_priv->child_dev + i; |
3100 | p_child = dev_priv->vbt.child_dev + i; |
2596 | 3101 | ||
2597 | if (p_child->dvo_port == PORT_IDPD && |
3102 | if (p_child->dvo_port == PORT_IDPD && |
Line 2668... | Line 3173... | ||
2668 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
3173 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
Line 2669... | Line 3174... | ||
2669 | 3174 | ||
2670 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
3175 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
Line 2671... | Line 3176... | ||
2671 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
3176 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
Line 2672... | Line 3177... | ||
2672 | 3177 | ||
2673 | vbt = dev_priv->edp.pps; |
3178 | vbt = dev_priv->vbt.edp_pps; |
2674 | 3179 | ||
2675 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
3180 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
Line 2736... | Line 3241... | ||
2736 | pp_on_reg = PIPEA_PP_ON_DELAYS; |
3241 | pp_on_reg = PIPEA_PP_ON_DELAYS; |
2737 | pp_off_reg = PIPEA_PP_OFF_DELAYS; |
3242 | pp_off_reg = PIPEA_PP_OFF_DELAYS; |
2738 | pp_div_reg = PIPEA_PP_DIVISOR; |
3243 | pp_div_reg = PIPEA_PP_DIVISOR; |
2739 | } |
3244 | } |
Line 2740... | Line -... | ||
2740 | - | ||
2741 | if (IS_VALLEYVIEW(dev)) |
- | |
2742 | port_sel = I915_READ(pp_on_reg) & 0xc0000000; |
- | |
2743 | 3245 | ||
2744 | /* And finally store the new values in the power sequencer. */ |
3246 | /* And finally store the new values in the power sequencer. */ |
2745 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
3247 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
2746 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
3248 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
2747 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
3249 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
Line 2752... | Line 3254... | ||
2752 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
3254 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
2753 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
3255 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
Line 2754... | Line 3256... | ||
2754 | 3256 | ||
2755 | /* Haswell doesn't have any port selection bits for the panel |
3257 | /* Haswell doesn't have any port selection bits for the panel |
- | 3258 | * power sequencer any more. */ |
|
- | 3259 | if (IS_VALLEYVIEW(dev)) { |
|
2756 | * power sequencer any more. */ |
3260 | port_sel = I915_READ(pp_on_reg) & 0xc0000000; |
2757 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
3261 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
2758 | if (is_cpu_edp(intel_dp)) |
3262 | if (dp_to_dig_port(intel_dp)->port == PORT_A) |
2759 | port_sel = PANEL_POWER_PORT_DP_A; |
3263 | port_sel = PANEL_POWER_PORT_DP_A; |
2760 | else |
3264 | else |
2761 | port_sel = PANEL_POWER_PORT_DP_D; |
3265 | port_sel = PANEL_POWER_PORT_DP_D; |
Line 2771... | Line 3275... | ||
2771 | I915_READ(pp_on_reg), |
3275 | I915_READ(pp_on_reg), |
2772 | I915_READ(pp_off_reg), |
3276 | I915_READ(pp_off_reg), |
2773 | I915_READ(pp_div_reg)); |
3277 | I915_READ(pp_div_reg)); |
2774 | } |
3278 | } |
Line -... | Line 3279... | ||
- | 3279 | ||
- | 3280 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
|
- | 3281 | struct intel_connector *intel_connector) |
|
- | 3282 | { |
|
- | 3283 | struct drm_connector *connector = &intel_connector->base; |
|
- | 3284 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 3285 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 3286 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3287 | struct drm_display_mode *fixed_mode = NULL; |
|
- | 3288 | struct edp_power_seq power_seq = { 0 }; |
|
- | 3289 | bool has_dpcd; |
|
- | 3290 | struct drm_display_mode *scan; |
|
- | 3291 | struct edid *edid; |
|
- | 3292 | ||
- | 3293 | if (!is_edp(intel_dp)) |
|
- | 3294 | return true; |
|
- | 3295 | ||
- | 3296 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
|
- | 3297 | ||
- | 3298 | /* Cache DPCD and EDID for edp. */ |
|
- | 3299 | ironlake_edp_panel_vdd_on(intel_dp); |
|
- | 3300 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
|
- | 3301 | ironlake_edp_panel_vdd_off(intel_dp, false); |
|
- | 3302 | ||
- | 3303 | if (has_dpcd) { |
|
- | 3304 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
|
- | 3305 | dev_priv->no_aux_handshake = |
|
- | 3306 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
|
- | 3307 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
|
- | 3308 | } else { |
|
- | 3309 | /* if this fails, presume the device is a ghost */ |
|
- | 3310 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
|
- | 3311 | return false; |
|
- | 3312 | } |
|
- | 3313 | ||
- | 3314 | /* We now know it's not a ghost, init power sequence regs. */ |
|
- | 3315 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
|
- | 3316 | &power_seq); |
|
- | 3317 | ||
- | 3318 | ironlake_edp_panel_vdd_on(intel_dp); |
|
- | 3319 | edid = drm_get_edid(connector, &intel_dp->adapter); |
|
- | 3320 | if (edid) { |
|
- | 3321 | if (drm_add_edid_modes(connector, edid)) { |
|
- | 3322 | drm_mode_connector_update_edid_property(connector, |
|
- | 3323 | edid); |
|
- | 3324 | drm_edid_to_eld(connector, edid); |
|
- | 3325 | } else { |
|
- | 3326 | kfree(edid); |
|
- | 3327 | edid = ERR_PTR(-EINVAL); |
|
- | 3328 | } |
|
- | 3329 | } else { |
|
- | 3330 | edid = ERR_PTR(-ENOENT); |
|
- | 3331 | } |
|
- | 3332 | intel_connector->edid = edid; |
|
- | 3333 | ||
- | 3334 | /* prefer fixed mode from EDID if available */ |
|
- | 3335 | list_for_each_entry(scan, &connector->probed_modes, head) { |
|
- | 3336 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
|
- | 3337 | fixed_mode = drm_mode_duplicate(dev, scan); |
|
- | 3338 | break; |
|
- | 3339 | } |
|
- | 3340 | } |
|
- | 3341 | ||
- | 3342 | /* fallback to VBT if available for eDP */ |
|
- | 3343 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
|
- | 3344 | fixed_mode = drm_mode_duplicate(dev, |
|
- | 3345 | dev_priv->vbt.lfp_lvds_vbt_mode); |
|
- | 3346 | if (fixed_mode) |
|
- | 3347 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
|
- | 3348 | } |
|
- | 3349 | ||
- | 3350 | ironlake_edp_panel_vdd_off(intel_dp, false); |
|
- | 3351 | ||
- | 3352 | intel_panel_init(&intel_connector->panel, fixed_mode); |
|
- | 3353 | intel_panel_setup_backlight(connector); |
|
- | 3354 | ||
- | 3355 | return true; |
|
- | 3356 | } |
|
2775 | 3357 | ||
2776 | void |
3358 | bool |
2777 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
3359 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
2778 | struct intel_connector *intel_connector) |
3360 | struct intel_connector *intel_connector) |
2779 | { |
3361 | { |
2780 | struct drm_connector *connector = &intel_connector->base; |
3362 | struct drm_connector *connector = &intel_connector->base; |
2781 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3363 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
2782 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3364 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2783 | struct drm_device *dev = intel_encoder->base.dev; |
3365 | struct drm_device *dev = intel_encoder->base.dev; |
2784 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
2785 | struct drm_display_mode *fixed_mode = NULL; |
- | |
2786 | struct edp_power_seq power_seq = { 0 }; |
3366 | struct drm_i915_private *dev_priv = dev->dev_private; |
2787 | enum port port = intel_dig_port->port; |
3367 | enum port port = intel_dig_port->port; |
2788 | const char *name = NULL; |
3368 | const char *name = NULL; |
Line 2789... | Line 3369... | ||
2789 | int type; |
3369 | int type, error; |
2790 | 3370 | ||
2791 | /* Preserve the current hw state. */ |
3371 | /* Preserve the current hw state. */ |
Line 2792... | Line 3372... | ||
2792 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
3372 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
2793 | intel_dp->attached_connector = intel_connector; |
- | |
2794 | - | ||
2795 | if (HAS_PCH_SPLIT(dev) && port == PORT_D) |
- | |
2796 | if (intel_dpd_is_edp(dev)) |
3373 | intel_dp->attached_connector = intel_connector; |
2797 | intel_dp->is_pch_edp = true; |
3374 | |
2798 | 3375 | type = DRM_MODE_CONNECTOR_DisplayPort; |
|
2799 | /* |
3376 | /* |
2800 | * FIXME : We need to initialize built-in panels before external panels. |
3377 | * FIXME : We need to initialize built-in panels before external panels. |
- | 3378 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup |
|
2801 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup |
3379 | */ |
- | 3380 | switch (port) { |
|
2802 | */ |
3381 | case PORT_A: |
2803 | if (IS_VALLEYVIEW(dev) && port == PORT_C) { |
3382 | type = DRM_MODE_CONNECTOR_eDP; |
2804 | type = DRM_MODE_CONNECTOR_eDP; |
3383 | break; |
2805 | intel_encoder->type = INTEL_OUTPUT_EDP; |
- | |
2806 | } else if (port == PORT_A || is_pch_edp(intel_dp)) { |
3384 | case PORT_C: |
2807 | type = DRM_MODE_CONNECTOR_eDP; |
3385 | if (IS_VALLEYVIEW(dev)) |
2808 | intel_encoder->type = INTEL_OUTPUT_EDP; |
3386 | type = DRM_MODE_CONNECTOR_eDP; |
2809 | } else { |
3387 | break; |
2810 | /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for |
3388 | case PORT_D: |
2811 | * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't |
3389 | if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev)) |
- | 3390 | type = DRM_MODE_CONNECTOR_eDP; |
|
2812 | * rewrite it. |
3391 | break; |
Line -... | Line 3392... | ||
- | 3392 | default: /* silence GCC warning */ |
|
- | 3393 | break; |
|
- | 3394 | } |
|
- | 3395 | ||
- | 3396 | /* |
|
- | 3397 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
|
- | 3398 | * for DP the encoder type can be set by the caller to |
|
- | 3399 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
|
- | 3400 | */ |
|
- | 3401 | if (type == DRM_MODE_CONNECTOR_eDP) |
|
- | 3402 | intel_encoder->type = INTEL_OUTPUT_EDP; |
|
- | 3403 | ||
2813 | */ |
3404 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
2814 | type = DRM_MODE_CONNECTOR_DisplayPort; |
3405 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
Line 2815... | Line 3406... | ||
2815 | } |
3406 | port_name(port)); |
2816 | 3407 | ||
Line 2871... | Line 3462... | ||
2871 | break; |
3462 | break; |
2872 | default: |
3463 | default: |
2873 | BUG(); |
3464 | BUG(); |
2874 | } |
3465 | } |
Line 2875... | Line 3466... | ||
2875 | 3466 | ||
2876 | if (is_edp(intel_dp)) |
3467 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); |
- | 3468 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", |
|
Line 2877... | Line 3469... | ||
2877 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
3469 | error, port_name(port)); |
Line -... | Line 3470... | ||
- | 3470 | ||
2878 | 3471 | intel_dp->psr_setup_done = false; |
|
2879 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
3472 | |
2880 | - | ||
2881 | /* Cache DPCD and EDID for edp. */ |
- | |
2882 | if (is_edp(intel_dp)) { |
- | |
2883 | bool ret; |
- | |
2884 | struct drm_display_mode *scan; |
- | |
2885 | struct edid *edid; |
- | |
2886 | - | ||
2887 | ironlake_edp_panel_vdd_on(intel_dp); |
- | |
2888 | ret = intel_dp_get_dpcd(intel_dp); |
- | |
2889 | ironlake_edp_panel_vdd_off(intel_dp, false); |
- | |
2890 | - | ||
2891 | if (ret) { |
- | |
2892 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
- | |
2893 | dev_priv->no_aux_handshake = |
- | |
2894 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
- | |
2895 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
- | |
2896 | } else { |
3473 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
2897 | /* if this fails, presume the device is a ghost */ |
3474 | i2c_del_adapter(&intel_dp->adapter); |
2898 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
- | |
2899 | intel_dp_encoder_destroy(&intel_encoder->base); |
- | |
2900 | intel_dp_destroy(connector); |
- | |
2901 | return; |
- | |
2902 | } |
- | |
2903 | - | ||
2904 | /* We now know it's not a ghost, init power sequence regs. */ |
- | |
2905 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
3475 | if (is_edp(intel_dp)) { |
2906 | &power_seq); |
- | |
2907 | - | ||
2908 | ironlake_edp_panel_vdd_on(intel_dp); |
- | |
2909 | edid = drm_get_edid(connector, &intel_dp->adapter); |
- | |
2910 | if (edid) { |
- | |
2911 | if (drm_add_edid_modes(connector, edid)) { |
- | |
2912 | drm_mode_connector_update_edid_property(connector, edid); |
- | |
2913 | drm_edid_to_eld(connector, edid); |
- | |
2914 | } else { |
- | |
2915 | kfree(edid); |
- | |
2916 | edid = ERR_PTR(-EINVAL); |
- | |
2917 | } |
- | |
2918 | } else { |
- | |
2919 | edid = ERR_PTR(-ENOENT); |
- | |
2920 | } |
- | |
2921 | intel_connector->edid = edid; |
- | |
2922 | - | ||
2923 | /* prefer fixed mode from EDID if available */ |
3476 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
2924 | list_for_each_entry(scan, &connector->probed_modes, head) { |
- | |
2925 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
- | |
2926 | fixed_mode = drm_mode_duplicate(dev, scan); |
- | |
2927 | break; |
- | |
2928 | } |
- | |
2929 | } |
- | |
2930 | - | ||
2931 | /* fallback to VBT if available for eDP */ |
- | |
2932 | if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { |
- | |
2933 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
- | |
2934 | if (fixed_mode) |
- | |
2935 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
- | |
2936 | } |
3477 | mutex_lock(&dev->mode_config.mutex); |
2937 | - | ||
2938 | ironlake_edp_panel_vdd_off(intel_dp, false); |
3478 | ironlake_panel_vdd_off_sync(intel_dp); |
2939 | } |
3479 | mutex_unlock(&dev->mode_config.mutex); |
2940 | 3480 | } |
|
2941 | if (is_edp(intel_dp)) { |
3481 | drm_sysfs_connector_remove(connector); |
Line 2942... | Line 3482... | ||
2942 | intel_panel_init(&intel_connector->panel, fixed_mode); |
3482 | drm_connector_cleanup(connector); |
Line 2943... | Line 3483... | ||
2943 | intel_panel_setup_backlight(connector); |
3483 | return false; |
Line 2951... | Line 3491... | ||
2951 | */ |
3491 | */ |
2952 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
3492 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
2953 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
3493 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2954 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
3494 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
2955 | } |
3495 | } |
- | 3496 | ||
- | 3497 | return true; |
|
2956 | } |
3498 | } |
Line 2957... | Line 3499... | ||
2957 | 3499 | ||
2958 | void |
3500 | void |
2959 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
3501 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
Line 2976... | Line 3518... | ||
2976 | intel_encoder = &intel_dig_port->base; |
3518 | intel_encoder = &intel_dig_port->base; |
2977 | encoder = &intel_encoder->base; |
3519 | encoder = &intel_encoder->base; |
Line 2978... | Line 3520... | ||
2978 | 3520 | ||
2979 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
3521 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
2980 | DRM_MODE_ENCODER_TMDS); |
- | |
Line 2981... | Line 3522... | ||
2981 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
3522 | DRM_MODE_ENCODER_TMDS); |
2982 | 3523 | ||
2983 | intel_encoder->compute_config = intel_dp_compute_config; |
- | |
2984 | intel_encoder->enable = intel_enable_dp; |
3524 | intel_encoder->compute_config = intel_dp_compute_config; |
2985 | intel_encoder->pre_enable = intel_pre_enable_dp; |
3525 | intel_encoder->mode_set = intel_dp_mode_set; |
2986 | intel_encoder->disable = intel_disable_dp; |
3526 | intel_encoder->disable = intel_disable_dp; |
- | 3527 | intel_encoder->post_disable = intel_post_disable_dp; |
|
- | 3528 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
|
- | 3529 | intel_encoder->get_config = intel_dp_get_config; |
|
- | 3530 | if (IS_VALLEYVIEW(dev)) { |
|
- | 3531 | intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable; |
|
- | 3532 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
|
- | 3533 | intel_encoder->enable = vlv_enable_dp; |
|
- | 3534 | } else { |
|
- | 3535 | intel_encoder->pre_enable = intel_pre_enable_dp; |
|
Line 2987... | Line 3536... | ||
2987 | intel_encoder->post_disable = intel_post_disable_dp; |
3536 | intel_encoder->enable = intel_enable_dp; |
2988 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
3537 | } |
Line 2989... | Line 3538... | ||
2989 | 3538 | ||
2990 | intel_dig_port->port = port; |
3539 | intel_dig_port->port = port; |
2991 | intel_dig_port->dp.output_reg = output_reg; |
3540 | intel_dig_port->dp.output_reg = output_reg; |
2992 | 3541 | ||
Line 2993... | Line 3542... | ||
2993 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
3542 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
- | 3543 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
|
- | 3544 | intel_encoder->cloneable = false; |
|
- | 3545 | intel_encoder->hot_plug = intel_dp_hot_plug; |
|
- | 3546 | ||
2994 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3547 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |