Rev 5060 | Rev 5354 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 5060 | Rev 5097 | ||
|---|---|---|---|
| Line 22... | Line 22... | ||
| 22 | * |
22 | * |
| 23 | * Authors: |
23 | * Authors: |
| 24 | * Eric Anholt |
24 | * Eric Anholt |
| 25 | */ |
25 | */ |
| Line 26... | Line 26... | ||
| 26 | 26 | ||
| 27 | //#include |
27 | #include |
| 28 | #include |
28 | #include |
| 29 | //#include |
29 | //#include |
| 30 | #include |
30 | #include |
| 31 | #include |
31 | #include |
| Line 2242... | Line 2242... | ||
| 2242 | * the VT-d warning. |
2242 | * the VT-d warning. |
| 2243 | */ |
2243 | */ |
| 2244 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
2244 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
| 2245 | alignment = 256 * 1024; |
2245 | alignment = 256 * 1024; |
| Line -... | Line 2246... | ||
| - | 2246 | ||
| - | 2247 | /* |
|
| - | 2248 | * Global gtt pte registers are special registers which actually forward |
|
| - | 2249 | * writes to a chunk of system memory. Which means that there is no risk |
|
| - | 2250 | * that the register values disappear as soon as we call |
|
| - | 2251 | * intel_runtime_pm_put(), so it is correct to wrap only the |
|
| - | 2252 | * pin/unpin/fence and not more. |
|
| - | 2253 | */ |
|
| - | 2254 | intel_runtime_pm_get(dev_priv); |
|
| 2246 | 2255 | ||
| 2247 | dev_priv->mm.interruptible = false; |
2256 | dev_priv->mm.interruptible = false; |
| 2248 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
2257 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
| 2249 | if (ret) |
2258 | if (ret) |
| Line 2259... | Line 2268... | ||
| 2259 | goto err_unpin; |
2268 | goto err_unpin; |
| Line 2260... | Line 2269... | ||
| 2260 | 2269 | ||
| Line 2261... | Line 2270... | ||
| 2261 | i915_gem_object_pin_fence(obj); |
2270 | i915_gem_object_pin_fence(obj); |
| - | 2271 | ||
| 2262 | 2272 | dev_priv->mm.interruptible = true; |
|
| Line 2263... | Line 2273... | ||
| 2263 | dev_priv->mm.interruptible = true; |
2273 | intel_runtime_pm_put(dev_priv); |
| 2264 | return 0; |
2274 | return 0; |
| 2265 | 2275 | ||
| 2266 | err_unpin: |
2276 | err_unpin: |
| - | 2277 | i915_gem_object_unpin_from_display_plane(obj); |
|
| 2267 | i915_gem_object_unpin_from_display_plane(obj); |
2278 | err_interruptible: |
| 2268 | err_interruptible: |
2279 | dev_priv->mm.interruptible = true; |
| Line 2269... | Line 2280... | ||
| 2269 | dev_priv->mm.interruptible = true; |
2280 | intel_runtime_pm_put(dev_priv); |
| 2270 | return ret; |
2281 | return ret; |
| Line 4182... | Line 4193... | ||
| 4182 | 4193 | ||
| 4183 | if (intel_crtc->config.has_pch_encoder) |
4194 | if (intel_crtc->config.has_pch_encoder) |
| Line 4184... | Line 4195... | ||
| 4184 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
4195 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
| 4185 | - | ||
| 4186 | intel_disable_pipe(dev_priv, pipe); |
- | |
| 4187 | - | ||
| 4188 | if (intel_crtc->config.dp_encoder_is_mst) |
- | |
| 4189 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4196 | |
| Line 4190... | Line 4197... | ||
| 4190 | 4197 | intel_disable_pipe(dev_priv, pipe); |
|
| 4191 | ironlake_pfit_disable(intel_crtc); |
4198 | ironlake_pfit_disable(intel_crtc); |
| 4192 | 4199 | ||
| Line 4250... | Line 4257... | ||
| 4250 | 4257 | ||
| 4251 | if (intel_crtc->config.has_pch_encoder) |
4258 | if (intel_crtc->config.has_pch_encoder) |
| 4252 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
4259 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
| Line -... | Line 4260... | ||
| - | 4260 | intel_disable_pipe(dev_priv, pipe); |
|
| - | 4261 | ||
| - | 4262 | if (intel_crtc->config.dp_encoder_is_mst) |
|
| 4253 | intel_disable_pipe(dev_priv, pipe); |
4263 | intel_ddi_set_vc_payload_alloc(crtc, false); |
| Line 4254... | Line 4264... | ||
| 4254 | 4264 | ||
| Line 4255... | Line 4265... | ||
| 4255 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4265 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
| Line 8236... | Line 8246... | ||
| 8236 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
8246 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
| 8237 | ret = -EINVAL; |
8247 | ret = -EINVAL; |
| 8238 | goto fail_locked; |
8248 | goto fail_locked; |
| 8239 | } |
8249 | } |
| Line -... | Line 8250... | ||
| - | 8250 | ||
| - | 8251 | /* |
|
| - | 8252 | * Global gtt pte registers are special registers which actually |
|
| - | 8253 | * forward writes to a chunk of system memory. Which means that |
|
| - | 8254 | * there is no risk that the register values disappear as soon |
|
| - | 8255 | * as we call intel_runtime_pm_put(), so it is correct to wrap |
|
| - | 8256 | * only the pin/unpin/fence and not more. |
|
| - | 8257 | */ |
|
| - | 8258 | intel_runtime_pm_get(dev_priv); |
|
| 8240 | 8259 | ||
| 8241 | /* Note that the w/a also requires 2 PTE of padding following |
8260 | /* Note that the w/a also requires 2 PTE of padding following |
| 8242 | * the bo. We currently fill all unused PTE with the shadow |
8261 | * the bo. We currently fill all unused PTE with the shadow |
| 8243 | * page and so we should always have valid PTE following the |
8262 | * page and so we should always have valid PTE following the |
| 8244 | * cursor preventing the VT-d warning. |
8263 | * cursor preventing the VT-d warning. |
| Line 8248... | Line 8267... | ||
| 8248 | alignment = 64*1024; |
8267 | alignment = 64*1024; |
| Line 8249... | Line 8268... | ||
| 8249 | 8268 | ||
| 8250 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
8269 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
| 8251 | if (ret) { |
8270 | if (ret) { |
| - | 8271 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
|
| 8252 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
8272 | intel_runtime_pm_put(dev_priv); |
| 8253 | goto fail_locked; |
8273 | goto fail_locked; |
| Line 8254... | Line 8274... | ||
| 8254 | } |
8274 | } |
| 8255 | 8275 | ||
| 8256 | ret = i915_gem_object_put_fence(obj); |
8276 | ret = i915_gem_object_put_fence(obj); |
| - | 8277 | if (ret) { |
|
| 8257 | if (ret) { |
8278 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
| 8258 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
8279 | intel_runtime_pm_put(dev_priv); |
| Line 8259... | Line 8280... | ||
| 8259 | goto fail_unpin; |
8280 | goto fail_unpin; |
| - | 8281 | } |
|
| - | 8282 | ||
| 8260 | } |
8283 | addr = i915_gem_obj_ggtt_offset(obj); |
| 8261 | 8284 | ||
| 8262 | addr = i915_gem_obj_ggtt_offset(obj); |
8285 | intel_runtime_pm_put(dev_priv); |
| 8263 | } else { |
8286 | } else { |
| 8264 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
8287 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
| Line 12184... | Line 12207... | ||
| 12184 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
12207 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
| Line 12185... | Line 12208... | ||
| 12185 | 12208 | ||
| 12186 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
12209 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
| Line -... | Line 12210... | ||
| - | 12210 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
|
| - | 12211 | ||
| - | 12212 | /* Acer C720 Chromebook (Core i3 4005U) */ |
|
| 12187 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
12213 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, |
| 12188 | 12214 | ||
| Line 12189... | Line 12215... | ||
| 12189 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
12215 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
| 12190 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
12216 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
| Line 12206... | Line 12232... | ||
| 12206 | q->subsystem_vendor == PCI_ANY_ID) && |
12232 | q->subsystem_vendor == PCI_ANY_ID) && |
| 12207 | (d->subsystem_device == q->subsystem_device || |
12233 | (d->subsystem_device == q->subsystem_device || |
| 12208 | q->subsystem_device == PCI_ANY_ID)) |
12234 | q->subsystem_device == PCI_ANY_ID)) |
| 12209 | q->hook(dev); |
12235 | q->hook(dev); |
| 12210 | } |
12236 | } |
| - | 12237 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
|
| - | 12238 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
|
| - | 12239 | intel_dmi_quirks[i].hook(dev); |
|
| - | 12240 | } |
|
| 12211 | } |
12241 | } |
| Line 12212... | Line 12242... | ||
| 12212 | 12242 | ||
| 12213 | /* Disable the VGA plane that we never use */ |
12243 | /* Disable the VGA plane that we never use */ |
| 12214 | static void i915_disable_vga(struct drm_device *dev) |
12244 | static void i915_disable_vga(struct drm_device *dev) |