Rev 4398 | Rev 4557 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 4398 | Rev 4539 | ||
|---|---|---|---|
| Line 1430... | Line 1430... | ||
| 1430 | 1430 | ||
| 1431 | I915_WRITE(DPLL(pipe), 0); |
1431 | I915_WRITE(DPLL(pipe), 0); |
| 1432 | POSTING_READ(DPLL(pipe)); |
1432 | POSTING_READ(DPLL(pipe)); |
| Line -... | Line 1433... | ||
| - | 1433 | } |
|
| - | 1434 | ||
| - | 1435 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
|
| - | 1436 | { |
|
| - | 1437 | u32 val = 0; |
|
| - | 1438 | ||
| - | 1439 | /* Make sure the pipe isn't still relying on us */ |
|
| - | 1440 | assert_pipe_disabled(dev_priv, pipe); |
|
| - | 1441 | ||
| - | 1442 | /* Leave integrated clock source enabled */ |
|
| - | 1443 | if (pipe == PIPE_B) |
|
| - | 1444 | val = DPLL_INTEGRATED_CRI_CLK_VLV; |
|
| - | 1445 | I915_WRITE(DPLL(pipe), val); |
|
| - | 1446 | POSTING_READ(DPLL(pipe)); |
|
| 1433 | } |
1447 | } |
| 1434 | 1448 | ||
| 1435 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1449 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
| Line 1436... | Line 1450... | ||
| 1436 | { |
1450 | { |
| Line 5997... | Line 6011... | ||
| 5997 | struct intel_crtc *crtc; |
6011 | struct intel_crtc *crtc; |
| 5998 | unsigned long irqflags; |
6012 | unsigned long irqflags; |
| 5999 | uint32_t val; |
6013 | uint32_t val; |
| Line 6000... | Line 6014... | ||
| 6000 | 6014 | ||
| 6001 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6015 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
| 6002 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", |
6016 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
| Line 6003... | Line 6017... | ||
| 6003 | pipe_name(crtc->pipe)); |
6017 | pipe_name(crtc->pipe)); |
| 6004 | 6018 | ||
| 6005 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
6019 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
| Line 10513... | Line 10527... | ||
| 10513 | { |
10527 | { |
| 10514 | intel_modeset_init_hw(dev); |
10528 | intel_modeset_init_hw(dev); |
| Line 10515... | Line 10529... | ||
| 10515 | 10529 | ||
| Line -... | Line 10530... | ||
| - | 10530 | // intel_setup_overlay(dev); |
|
| 10516 | // intel_setup_overlay(dev); |
10531 | |
| - | 10532 | mutex_lock(&dev->mode_config.mutex); |
|
| 10517 | 10533 | intel_modeset_setup_hw_state(dev, false); |
|
| Line 10518... | Line 10534... | ||
| 10518 | intel_modeset_setup_hw_state(dev, false); |
10534 | mutex_unlock(&dev->mode_config.mutex); |
| 10519 | } |
10535 | } |
| 10520 | 10536 | ||
| Line 10587... | Line 10603... | ||
| 10587 | * set vga decode state - true == enable VGA decode |
10603 | * set vga decode state - true == enable VGA decode |
| 10588 | */ |
10604 | */ |
| 10589 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
10605 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 10590 | { |
10606 | { |
| 10591 | struct drm_i915_private *dev_priv = dev->dev_private; |
10607 | struct drm_i915_private *dev_priv = dev->dev_private; |
| - | 10608 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
|
| 10592 | u16 gmch_ctrl; |
10609 | u16 gmch_ctrl; |
| Line 10593... | Line 10610... | ||
| 10593 | 10610 | ||
| 10594 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
10611 | pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl); |
| 10595 | if (state) |
10612 | if (state) |
| 10596 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
10613 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 10597 | else |
10614 | else |
| 10598 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
10615 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
| 10599 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
10616 | pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); |
| 10600 | return 0; |
10617 | return 0; |
| Line 10601... | Line 10618... | ||
| 10601 | } |
10618 | } |
| 10602 | 10619 | ||