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1 | /* |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | */ |
25 | */ |
26 | 26 | ||
27 | //#include |
27 | //#include |
28 | #include |
28 | #include |
29 | //#include |
29 | //#include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
37 | #include |
37 | #include |
38 | #include "i915_drv.h" |
38 | #include "i915_drv.h" |
39 | #include "i915_trace.h" |
39 | #include "i915_trace.h" |
40 | #include |
40 | #include |
41 | #include |
41 | #include |
42 | //#include |
42 | //#include |
43 | 43 | ||
44 | #define MAX_ERRNO 4095 |
44 | #define MAX_ERRNO 4095 |
45 | phys_addr_t get_bus_addr(void); |
45 | phys_addr_t get_bus_addr(void); |
46 | 46 | ||
47 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
47 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
50 | 50 | ||
51 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
51 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
52 | struct intel_crtc_config *pipe_config); |
52 | struct intel_crtc_config *pipe_config); |
53 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
53 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
54 | struct intel_crtc_config *pipe_config); |
54 | struct intel_crtc_config *pipe_config); |
55 | 55 | ||
56 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
56 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
57 | int x, int y, struct drm_framebuffer *old_fb); |
57 | int x, int y, struct drm_framebuffer *old_fb); |
58 | 58 | ||
59 | 59 | ||
60 | typedef struct { |
60 | typedef struct { |
61 | int min, max; |
61 | int min, max; |
62 | } intel_range_t; |
62 | } intel_range_t; |
63 | 63 | ||
64 | typedef struct { |
64 | typedef struct { |
65 | int dot_limit; |
65 | int dot_limit; |
66 | int p2_slow, p2_fast; |
66 | int p2_slow, p2_fast; |
67 | } intel_p2_t; |
67 | } intel_p2_t; |
68 | 68 | ||
69 | typedef struct intel_limit intel_limit_t; |
69 | typedef struct intel_limit intel_limit_t; |
70 | struct intel_limit { |
70 | struct intel_limit { |
71 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
71 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
72 | intel_p2_t p2; |
72 | intel_p2_t p2; |
73 | }; |
73 | }; |
74 | 74 | ||
75 | /* FDI */ |
75 | /* FDI */ |
76 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
76 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
77 | 77 | ||
78 | int |
78 | int |
79 | intel_pch_rawclk(struct drm_device *dev) |
79 | intel_pch_rawclk(struct drm_device *dev) |
80 | { |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; |
81 | struct drm_i915_private *dev_priv = dev->dev_private; |
82 | 82 | ||
83 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
83 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
84 | 84 | ||
85 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
85 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
86 | } |
86 | } |
87 | 87 | ||
88 | static inline u32 /* units of 100MHz */ |
88 | static inline u32 /* units of 100MHz */ |
89 | intel_fdi_link_freq(struct drm_device *dev) |
89 | intel_fdi_link_freq(struct drm_device *dev) |
90 | { |
90 | { |
91 | if (IS_GEN5(dev)) { |
91 | if (IS_GEN5(dev)) { |
92 | struct drm_i915_private *dev_priv = dev->dev_private; |
92 | struct drm_i915_private *dev_priv = dev->dev_private; |
93 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
93 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
94 | } else |
94 | } else |
95 | return 27; |
95 | return 27; |
96 | } |
96 | } |
97 | 97 | ||
98 | static const intel_limit_t intel_limits_i8xx_dac = { |
98 | static const intel_limit_t intel_limits_i8xx_dac = { |
99 | .dot = { .min = 25000, .max = 350000 }, |
99 | .dot = { .min = 25000, .max = 350000 }, |
100 | .vco = { .min = 930000, .max = 1400000 }, |
100 | .vco = { .min = 930000, .max = 1400000 }, |
101 | .n = { .min = 3, .max = 16 }, |
101 | .n = { .min = 3, .max = 16 }, |
102 | .m = { .min = 96, .max = 140 }, |
102 | .m = { .min = 96, .max = 140 }, |
103 | .m1 = { .min = 18, .max = 26 }, |
103 | .m1 = { .min = 18, .max = 26 }, |
104 | .m2 = { .min = 6, .max = 16 }, |
104 | .m2 = { .min = 6, .max = 16 }, |
105 | .p = { .min = 4, .max = 128 }, |
105 | .p = { .min = 4, .max = 128 }, |
106 | .p1 = { .min = 2, .max = 33 }, |
106 | .p1 = { .min = 2, .max = 33 }, |
107 | .p2 = { .dot_limit = 165000, |
107 | .p2 = { .dot_limit = 165000, |
108 | .p2_slow = 4, .p2_fast = 2 }, |
108 | .p2_slow = 4, .p2_fast = 2 }, |
109 | }; |
109 | }; |
110 | 110 | ||
111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
112 | .dot = { .min = 25000, .max = 350000 }, |
112 | .dot = { .min = 25000, .max = 350000 }, |
113 | .vco = { .min = 930000, .max = 1400000 }, |
113 | .vco = { .min = 930000, .max = 1400000 }, |
114 | .n = { .min = 3, .max = 16 }, |
114 | .n = { .min = 3, .max = 16 }, |
115 | .m = { .min = 96, .max = 140 }, |
115 | .m = { .min = 96, .max = 140 }, |
116 | .m1 = { .min = 18, .max = 26 }, |
116 | .m1 = { .min = 18, .max = 26 }, |
117 | .m2 = { .min = 6, .max = 16 }, |
117 | .m2 = { .min = 6, .max = 16 }, |
118 | .p = { .min = 4, .max = 128 }, |
118 | .p = { .min = 4, .max = 128 }, |
119 | .p1 = { .min = 2, .max = 33 }, |
119 | .p1 = { .min = 2, .max = 33 }, |
120 | .p2 = { .dot_limit = 165000, |
120 | .p2 = { .dot_limit = 165000, |
121 | .p2_slow = 4, .p2_fast = 4 }, |
121 | .p2_slow = 4, .p2_fast = 4 }, |
122 | }; |
122 | }; |
123 | 123 | ||
124 | static const intel_limit_t intel_limits_i8xx_lvds = { |
124 | static const intel_limit_t intel_limits_i8xx_lvds = { |
125 | .dot = { .min = 25000, .max = 350000 }, |
125 | .dot = { .min = 25000, .max = 350000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, |
127 | .n = { .min = 3, .max = 16 }, |
127 | .n = { .min = 3, .max = 16 }, |
128 | .m = { .min = 96, .max = 140 }, |
128 | .m = { .min = 96, .max = 140 }, |
129 | .m1 = { .min = 18, .max = 26 }, |
129 | .m1 = { .min = 18, .max = 26 }, |
130 | .m2 = { .min = 6, .max = 16 }, |
130 | .m2 = { .min = 6, .max = 16 }, |
131 | .p = { .min = 4, .max = 128 }, |
131 | .p = { .min = 4, .max = 128 }, |
132 | .p1 = { .min = 1, .max = 6 }, |
132 | .p1 = { .min = 1, .max = 6 }, |
133 | .p2 = { .dot_limit = 165000, |
133 | .p2 = { .dot_limit = 165000, |
134 | .p2_slow = 14, .p2_fast = 7 }, |
134 | .p2_slow = 14, .p2_fast = 7 }, |
135 | }; |
135 | }; |
136 | 136 | ||
137 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
137 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
138 | .dot = { .min = 20000, .max = 400000 }, |
138 | .dot = { .min = 20000, .max = 400000 }, |
139 | .vco = { .min = 1400000, .max = 2800000 }, |
139 | .vco = { .min = 1400000, .max = 2800000 }, |
140 | .n = { .min = 1, .max = 6 }, |
140 | .n = { .min = 1, .max = 6 }, |
141 | .m = { .min = 70, .max = 120 }, |
141 | .m = { .min = 70, .max = 120 }, |
142 | .m1 = { .min = 8, .max = 18 }, |
142 | .m1 = { .min = 8, .max = 18 }, |
143 | .m2 = { .min = 3, .max = 7 }, |
143 | .m2 = { .min = 3, .max = 7 }, |
144 | .p = { .min = 5, .max = 80 }, |
144 | .p = { .min = 5, .max = 80 }, |
145 | .p1 = { .min = 1, .max = 8 }, |
145 | .p1 = { .min = 1, .max = 8 }, |
146 | .p2 = { .dot_limit = 200000, |
146 | .p2 = { .dot_limit = 200000, |
147 | .p2_slow = 10, .p2_fast = 5 }, |
147 | .p2_slow = 10, .p2_fast = 5 }, |
148 | }; |
148 | }; |
149 | 149 | ||
150 | static const intel_limit_t intel_limits_i9xx_lvds = { |
150 | static const intel_limit_t intel_limits_i9xx_lvds = { |
151 | .dot = { .min = 20000, .max = 400000 }, |
151 | .dot = { .min = 20000, .max = 400000 }, |
152 | .vco = { .min = 1400000, .max = 2800000 }, |
152 | .vco = { .min = 1400000, .max = 2800000 }, |
153 | .n = { .min = 1, .max = 6 }, |
153 | .n = { .min = 1, .max = 6 }, |
154 | .m = { .min = 70, .max = 120 }, |
154 | .m = { .min = 70, .max = 120 }, |
155 | .m1 = { .min = 8, .max = 18 }, |
155 | .m1 = { .min = 8, .max = 18 }, |
156 | .m2 = { .min = 3, .max = 7 }, |
156 | .m2 = { .min = 3, .max = 7 }, |
157 | .p = { .min = 7, .max = 98 }, |
157 | .p = { .min = 7, .max = 98 }, |
158 | .p1 = { .min = 1, .max = 8 }, |
158 | .p1 = { .min = 1, .max = 8 }, |
159 | .p2 = { .dot_limit = 112000, |
159 | .p2 = { .dot_limit = 112000, |
160 | .p2_slow = 14, .p2_fast = 7 }, |
160 | .p2_slow = 14, .p2_fast = 7 }, |
161 | }; |
161 | }; |
162 | 162 | ||
163 | 163 | ||
164 | static const intel_limit_t intel_limits_g4x_sdvo = { |
164 | static const intel_limit_t intel_limits_g4x_sdvo = { |
165 | .dot = { .min = 25000, .max = 270000 }, |
165 | .dot = { .min = 25000, .max = 270000 }, |
166 | .vco = { .min = 1750000, .max = 3500000}, |
166 | .vco = { .min = 1750000, .max = 3500000}, |
167 | .n = { .min = 1, .max = 4 }, |
167 | .n = { .min = 1, .max = 4 }, |
168 | .m = { .min = 104, .max = 138 }, |
168 | .m = { .min = 104, .max = 138 }, |
169 | .m1 = { .min = 17, .max = 23 }, |
169 | .m1 = { .min = 17, .max = 23 }, |
170 | .m2 = { .min = 5, .max = 11 }, |
170 | .m2 = { .min = 5, .max = 11 }, |
171 | .p = { .min = 10, .max = 30 }, |
171 | .p = { .min = 10, .max = 30 }, |
172 | .p1 = { .min = 1, .max = 3}, |
172 | .p1 = { .min = 1, .max = 3}, |
173 | .p2 = { .dot_limit = 270000, |
173 | .p2 = { .dot_limit = 270000, |
174 | .p2_slow = 10, |
174 | .p2_slow = 10, |
175 | .p2_fast = 10 |
175 | .p2_fast = 10 |
176 | }, |
176 | }, |
177 | }; |
177 | }; |
178 | 178 | ||
179 | static const intel_limit_t intel_limits_g4x_hdmi = { |
179 | static const intel_limit_t intel_limits_g4x_hdmi = { |
180 | .dot = { .min = 22000, .max = 400000 }, |
180 | .dot = { .min = 22000, .max = 400000 }, |
181 | .vco = { .min = 1750000, .max = 3500000}, |
181 | .vco = { .min = 1750000, .max = 3500000}, |
182 | .n = { .min = 1, .max = 4 }, |
182 | .n = { .min = 1, .max = 4 }, |
183 | .m = { .min = 104, .max = 138 }, |
183 | .m = { .min = 104, .max = 138 }, |
184 | .m1 = { .min = 16, .max = 23 }, |
184 | .m1 = { .min = 16, .max = 23 }, |
185 | .m2 = { .min = 5, .max = 11 }, |
185 | .m2 = { .min = 5, .max = 11 }, |
186 | .p = { .min = 5, .max = 80 }, |
186 | .p = { .min = 5, .max = 80 }, |
187 | .p1 = { .min = 1, .max = 8}, |
187 | .p1 = { .min = 1, .max = 8}, |
188 | .p2 = { .dot_limit = 165000, |
188 | .p2 = { .dot_limit = 165000, |
189 | .p2_slow = 10, .p2_fast = 5 }, |
189 | .p2_slow = 10, .p2_fast = 5 }, |
190 | }; |
190 | }; |
191 | 191 | ||
192 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
192 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
193 | .dot = { .min = 20000, .max = 115000 }, |
193 | .dot = { .min = 20000, .max = 115000 }, |
194 | .vco = { .min = 1750000, .max = 3500000 }, |
194 | .vco = { .min = 1750000, .max = 3500000 }, |
195 | .n = { .min = 1, .max = 3 }, |
195 | .n = { .min = 1, .max = 3 }, |
196 | .m = { .min = 104, .max = 138 }, |
196 | .m = { .min = 104, .max = 138 }, |
197 | .m1 = { .min = 17, .max = 23 }, |
197 | .m1 = { .min = 17, .max = 23 }, |
198 | .m2 = { .min = 5, .max = 11 }, |
198 | .m2 = { .min = 5, .max = 11 }, |
199 | .p = { .min = 28, .max = 112 }, |
199 | .p = { .min = 28, .max = 112 }, |
200 | .p1 = { .min = 2, .max = 8 }, |
200 | .p1 = { .min = 2, .max = 8 }, |
201 | .p2 = { .dot_limit = 0, |
201 | .p2 = { .dot_limit = 0, |
202 | .p2_slow = 14, .p2_fast = 14 |
202 | .p2_slow = 14, .p2_fast = 14 |
203 | }, |
203 | }, |
204 | }; |
204 | }; |
205 | 205 | ||
206 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
206 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
207 | .dot = { .min = 80000, .max = 224000 }, |
207 | .dot = { .min = 80000, .max = 224000 }, |
208 | .vco = { .min = 1750000, .max = 3500000 }, |
208 | .vco = { .min = 1750000, .max = 3500000 }, |
209 | .n = { .min = 1, .max = 3 }, |
209 | .n = { .min = 1, .max = 3 }, |
210 | .m = { .min = 104, .max = 138 }, |
210 | .m = { .min = 104, .max = 138 }, |
211 | .m1 = { .min = 17, .max = 23 }, |
211 | .m1 = { .min = 17, .max = 23 }, |
212 | .m2 = { .min = 5, .max = 11 }, |
212 | .m2 = { .min = 5, .max = 11 }, |
213 | .p = { .min = 14, .max = 42 }, |
213 | .p = { .min = 14, .max = 42 }, |
214 | .p1 = { .min = 2, .max = 6 }, |
214 | .p1 = { .min = 2, .max = 6 }, |
215 | .p2 = { .dot_limit = 0, |
215 | .p2 = { .dot_limit = 0, |
216 | .p2_slow = 7, .p2_fast = 7 |
216 | .p2_slow = 7, .p2_fast = 7 |
217 | }, |
217 | }, |
218 | }; |
218 | }; |
219 | 219 | ||
220 | static const intel_limit_t intel_limits_pineview_sdvo = { |
220 | static const intel_limit_t intel_limits_pineview_sdvo = { |
221 | .dot = { .min = 20000, .max = 400000}, |
221 | .dot = { .min = 20000, .max = 400000}, |
222 | .vco = { .min = 1700000, .max = 3500000 }, |
222 | .vco = { .min = 1700000, .max = 3500000 }, |
223 | /* Pineview's Ncounter is a ring counter */ |
223 | /* Pineview's Ncounter is a ring counter */ |
224 | .n = { .min = 3, .max = 6 }, |
224 | .n = { .min = 3, .max = 6 }, |
225 | .m = { .min = 2, .max = 256 }, |
225 | .m = { .min = 2, .max = 256 }, |
226 | /* Pineview only has one combined m divider, which we treat as m2. */ |
226 | /* Pineview only has one combined m divider, which we treat as m2. */ |
227 | .m1 = { .min = 0, .max = 0 }, |
227 | .m1 = { .min = 0, .max = 0 }, |
228 | .m2 = { .min = 0, .max = 254 }, |
228 | .m2 = { .min = 0, .max = 254 }, |
229 | .p = { .min = 5, .max = 80 }, |
229 | .p = { .min = 5, .max = 80 }, |
230 | .p1 = { .min = 1, .max = 8 }, |
230 | .p1 = { .min = 1, .max = 8 }, |
231 | .p2 = { .dot_limit = 200000, |
231 | .p2 = { .dot_limit = 200000, |
232 | .p2_slow = 10, .p2_fast = 5 }, |
232 | .p2_slow = 10, .p2_fast = 5 }, |
233 | }; |
233 | }; |
234 | 234 | ||
235 | static const intel_limit_t intel_limits_pineview_lvds = { |
235 | static const intel_limit_t intel_limits_pineview_lvds = { |
236 | .dot = { .min = 20000, .max = 400000 }, |
236 | .dot = { .min = 20000, .max = 400000 }, |
237 | .vco = { .min = 1700000, .max = 3500000 }, |
237 | .vco = { .min = 1700000, .max = 3500000 }, |
238 | .n = { .min = 3, .max = 6 }, |
238 | .n = { .min = 3, .max = 6 }, |
239 | .m = { .min = 2, .max = 256 }, |
239 | .m = { .min = 2, .max = 256 }, |
240 | .m1 = { .min = 0, .max = 0 }, |
240 | .m1 = { .min = 0, .max = 0 }, |
241 | .m2 = { .min = 0, .max = 254 }, |
241 | .m2 = { .min = 0, .max = 254 }, |
242 | .p = { .min = 7, .max = 112 }, |
242 | .p = { .min = 7, .max = 112 }, |
243 | .p1 = { .min = 1, .max = 8 }, |
243 | .p1 = { .min = 1, .max = 8 }, |
244 | .p2 = { .dot_limit = 112000, |
244 | .p2 = { .dot_limit = 112000, |
245 | .p2_slow = 14, .p2_fast = 14 }, |
245 | .p2_slow = 14, .p2_fast = 14 }, |
246 | }; |
246 | }; |
247 | 247 | ||
248 | /* Ironlake / Sandybridge |
248 | /* Ironlake / Sandybridge |
249 | * |
249 | * |
250 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
250 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
251 | * the range value for them is (actual_value - 2). |
251 | * the range value for them is (actual_value - 2). |
252 | */ |
252 | */ |
253 | static const intel_limit_t intel_limits_ironlake_dac = { |
253 | static const intel_limit_t intel_limits_ironlake_dac = { |
254 | .dot = { .min = 25000, .max = 350000 }, |
254 | .dot = { .min = 25000, .max = 350000 }, |
255 | .vco = { .min = 1760000, .max = 3510000 }, |
255 | .vco = { .min = 1760000, .max = 3510000 }, |
256 | .n = { .min = 1, .max = 5 }, |
256 | .n = { .min = 1, .max = 5 }, |
257 | .m = { .min = 79, .max = 127 }, |
257 | .m = { .min = 79, .max = 127 }, |
258 | .m1 = { .min = 12, .max = 22 }, |
258 | .m1 = { .min = 12, .max = 22 }, |
259 | .m2 = { .min = 5, .max = 9 }, |
259 | .m2 = { .min = 5, .max = 9 }, |
260 | .p = { .min = 5, .max = 80 }, |
260 | .p = { .min = 5, .max = 80 }, |
261 | .p1 = { .min = 1, .max = 8 }, |
261 | .p1 = { .min = 1, .max = 8 }, |
262 | .p2 = { .dot_limit = 225000, |
262 | .p2 = { .dot_limit = 225000, |
263 | .p2_slow = 10, .p2_fast = 5 }, |
263 | .p2_slow = 10, .p2_fast = 5 }, |
264 | }; |
264 | }; |
265 | 265 | ||
266 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
266 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
267 | .dot = { .min = 25000, .max = 350000 }, |
267 | .dot = { .min = 25000, .max = 350000 }, |
268 | .vco = { .min = 1760000, .max = 3510000 }, |
268 | .vco = { .min = 1760000, .max = 3510000 }, |
269 | .n = { .min = 1, .max = 3 }, |
269 | .n = { .min = 1, .max = 3 }, |
270 | .m = { .min = 79, .max = 118 }, |
270 | .m = { .min = 79, .max = 118 }, |
271 | .m1 = { .min = 12, .max = 22 }, |
271 | .m1 = { .min = 12, .max = 22 }, |
272 | .m2 = { .min = 5, .max = 9 }, |
272 | .m2 = { .min = 5, .max = 9 }, |
273 | .p = { .min = 28, .max = 112 }, |
273 | .p = { .min = 28, .max = 112 }, |
274 | .p1 = { .min = 2, .max = 8 }, |
274 | .p1 = { .min = 2, .max = 8 }, |
275 | .p2 = { .dot_limit = 225000, |
275 | .p2 = { .dot_limit = 225000, |
276 | .p2_slow = 14, .p2_fast = 14 }, |
276 | .p2_slow = 14, .p2_fast = 14 }, |
277 | }; |
277 | }; |
278 | 278 | ||
279 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
279 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
280 | .dot = { .min = 25000, .max = 350000 }, |
280 | .dot = { .min = 25000, .max = 350000 }, |
281 | .vco = { .min = 1760000, .max = 3510000 }, |
281 | .vco = { .min = 1760000, .max = 3510000 }, |
282 | .n = { .min = 1, .max = 3 }, |
282 | .n = { .min = 1, .max = 3 }, |
283 | .m = { .min = 79, .max = 127 }, |
283 | .m = { .min = 79, .max = 127 }, |
284 | .m1 = { .min = 12, .max = 22 }, |
284 | .m1 = { .min = 12, .max = 22 }, |
285 | .m2 = { .min = 5, .max = 9 }, |
285 | .m2 = { .min = 5, .max = 9 }, |
286 | .p = { .min = 14, .max = 56 }, |
286 | .p = { .min = 14, .max = 56 }, |
287 | .p1 = { .min = 2, .max = 8 }, |
287 | .p1 = { .min = 2, .max = 8 }, |
288 | .p2 = { .dot_limit = 225000, |
288 | .p2 = { .dot_limit = 225000, |
289 | .p2_slow = 7, .p2_fast = 7 }, |
289 | .p2_slow = 7, .p2_fast = 7 }, |
290 | }; |
290 | }; |
291 | 291 | ||
292 | /* LVDS 100mhz refclk limits. */ |
292 | /* LVDS 100mhz refclk limits. */ |
293 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
293 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
294 | .dot = { .min = 25000, .max = 350000 }, |
294 | .dot = { .min = 25000, .max = 350000 }, |
295 | .vco = { .min = 1760000, .max = 3510000 }, |
295 | .vco = { .min = 1760000, .max = 3510000 }, |
296 | .n = { .min = 1, .max = 2 }, |
296 | .n = { .min = 1, .max = 2 }, |
297 | .m = { .min = 79, .max = 126 }, |
297 | .m = { .min = 79, .max = 126 }, |
298 | .m1 = { .min = 12, .max = 22 }, |
298 | .m1 = { .min = 12, .max = 22 }, |
299 | .m2 = { .min = 5, .max = 9 }, |
299 | .m2 = { .min = 5, .max = 9 }, |
300 | .p = { .min = 28, .max = 112 }, |
300 | .p = { .min = 28, .max = 112 }, |
301 | .p1 = { .min = 2, .max = 8 }, |
301 | .p1 = { .min = 2, .max = 8 }, |
302 | .p2 = { .dot_limit = 225000, |
302 | .p2 = { .dot_limit = 225000, |
303 | .p2_slow = 14, .p2_fast = 14 }, |
303 | .p2_slow = 14, .p2_fast = 14 }, |
304 | }; |
304 | }; |
305 | 305 | ||
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
307 | .dot = { .min = 25000, .max = 350000 }, |
307 | .dot = { .min = 25000, .max = 350000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, |
309 | .n = { .min = 1, .max = 3 }, |
309 | .n = { .min = 1, .max = 3 }, |
310 | .m = { .min = 79, .max = 126 }, |
310 | .m = { .min = 79, .max = 126 }, |
311 | .m1 = { .min = 12, .max = 22 }, |
311 | .m1 = { .min = 12, .max = 22 }, |
312 | .m2 = { .min = 5, .max = 9 }, |
312 | .m2 = { .min = 5, .max = 9 }, |
313 | .p = { .min = 14, .max = 42 }, |
313 | .p = { .min = 14, .max = 42 }, |
314 | .p1 = { .min = 2, .max = 6 }, |
314 | .p1 = { .min = 2, .max = 6 }, |
315 | .p2 = { .dot_limit = 225000, |
315 | .p2 = { .dot_limit = 225000, |
316 | .p2_slow = 7, .p2_fast = 7 }, |
316 | .p2_slow = 7, .p2_fast = 7 }, |
317 | }; |
317 | }; |
318 | 318 | ||
319 | static const intel_limit_t intel_limits_vlv_dac = { |
319 | static const intel_limit_t intel_limits_vlv_dac = { |
320 | .dot = { .min = 25000, .max = 270000 }, |
320 | .dot = { .min = 25000, .max = 270000 }, |
321 | .vco = { .min = 4000000, .max = 6000000 }, |
321 | .vco = { .min = 4000000, .max = 6000000 }, |
322 | .n = { .min = 1, .max = 7 }, |
322 | .n = { .min = 1, .max = 7 }, |
323 | .m = { .min = 22, .max = 450 }, /* guess */ |
323 | .m = { .min = 22, .max = 450 }, /* guess */ |
324 | .m1 = { .min = 2, .max = 3 }, |
324 | .m1 = { .min = 2, .max = 3 }, |
325 | .m2 = { .min = 11, .max = 156 }, |
325 | .m2 = { .min = 11, .max = 156 }, |
326 | .p = { .min = 10, .max = 30 }, |
326 | .p = { .min = 10, .max = 30 }, |
327 | .p1 = { .min = 1, .max = 3 }, |
327 | .p1 = { .min = 1, .max = 3 }, |
328 | .p2 = { .dot_limit = 270000, |
328 | .p2 = { .dot_limit = 270000, |
329 | .p2_slow = 2, .p2_fast = 20 }, |
329 | .p2_slow = 2, .p2_fast = 20 }, |
330 | }; |
330 | }; |
331 | 331 | ||
332 | static const intel_limit_t intel_limits_vlv_hdmi = { |
332 | static const intel_limit_t intel_limits_vlv_hdmi = { |
333 | .dot = { .min = 25000, .max = 270000 }, |
333 | .dot = { .min = 25000, .max = 270000 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
334 | .vco = { .min = 4000000, .max = 6000000 }, |
335 | .n = { .min = 1, .max = 7 }, |
335 | .n = { .min = 1, .max = 7 }, |
336 | .m = { .min = 60, .max = 300 }, /* guess */ |
336 | .m = { .min = 60, .max = 300 }, /* guess */ |
337 | .m1 = { .min = 2, .max = 3 }, |
337 | .m1 = { .min = 2, .max = 3 }, |
338 | .m2 = { .min = 11, .max = 156 }, |
338 | .m2 = { .min = 11, .max = 156 }, |
339 | .p = { .min = 10, .max = 30 }, |
339 | .p = { .min = 10, .max = 30 }, |
340 | .p1 = { .min = 2, .max = 3 }, |
340 | .p1 = { .min = 2, .max = 3 }, |
341 | .p2 = { .dot_limit = 270000, |
341 | .p2 = { .dot_limit = 270000, |
342 | .p2_slow = 2, .p2_fast = 20 }, |
342 | .p2_slow = 2, .p2_fast = 20 }, |
343 | }; |
343 | }; |
344 | 344 | ||
345 | static const intel_limit_t intel_limits_vlv_dp = { |
345 | static const intel_limit_t intel_limits_vlv_dp = { |
346 | .dot = { .min = 25000, .max = 270000 }, |
346 | .dot = { .min = 25000, .max = 270000 }, |
347 | .vco = { .min = 4000000, .max = 6000000 }, |
347 | .vco = { .min = 4000000, .max = 6000000 }, |
348 | .n = { .min = 1, .max = 7 }, |
348 | .n = { .min = 1, .max = 7 }, |
349 | .m = { .min = 22, .max = 450 }, |
349 | .m = { .min = 22, .max = 450 }, |
350 | .m1 = { .min = 2, .max = 3 }, |
350 | .m1 = { .min = 2, .max = 3 }, |
351 | .m2 = { .min = 11, .max = 156 }, |
351 | .m2 = { .min = 11, .max = 156 }, |
352 | .p = { .min = 10, .max = 30 }, |
352 | .p = { .min = 10, .max = 30 }, |
353 | .p1 = { .min = 1, .max = 3 }, |
353 | .p1 = { .min = 1, .max = 3 }, |
354 | .p2 = { .dot_limit = 270000, |
354 | .p2 = { .dot_limit = 270000, |
355 | .p2_slow = 2, .p2_fast = 20 }, |
355 | .p2_slow = 2, .p2_fast = 20 }, |
356 | }; |
356 | }; |
357 | 357 | ||
358 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
358 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
359 | int refclk) |
359 | int refclk) |
360 | { |
360 | { |
361 | struct drm_device *dev = crtc->dev; |
361 | struct drm_device *dev = crtc->dev; |
362 | const intel_limit_t *limit; |
362 | const intel_limit_t *limit; |
363 | 363 | ||
364 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
364 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
365 | if (intel_is_dual_link_lvds(dev)) { |
365 | if (intel_is_dual_link_lvds(dev)) { |
366 | if (refclk == 100000) |
366 | if (refclk == 100000) |
367 | limit = &intel_limits_ironlake_dual_lvds_100m; |
367 | limit = &intel_limits_ironlake_dual_lvds_100m; |
368 | else |
368 | else |
369 | limit = &intel_limits_ironlake_dual_lvds; |
369 | limit = &intel_limits_ironlake_dual_lvds; |
370 | } else { |
370 | } else { |
371 | if (refclk == 100000) |
371 | if (refclk == 100000) |
372 | limit = &intel_limits_ironlake_single_lvds_100m; |
372 | limit = &intel_limits_ironlake_single_lvds_100m; |
373 | else |
373 | else |
374 | limit = &intel_limits_ironlake_single_lvds; |
374 | limit = &intel_limits_ironlake_single_lvds; |
375 | } |
375 | } |
376 | } else |
376 | } else |
377 | limit = &intel_limits_ironlake_dac; |
377 | limit = &intel_limits_ironlake_dac; |
378 | 378 | ||
379 | return limit; |
379 | return limit; |
380 | } |
380 | } |
381 | 381 | ||
382 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
382 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
383 | { |
383 | { |
384 | struct drm_device *dev = crtc->dev; |
384 | struct drm_device *dev = crtc->dev; |
385 | const intel_limit_t *limit; |
385 | const intel_limit_t *limit; |
386 | 386 | ||
387 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
387 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
388 | if (intel_is_dual_link_lvds(dev)) |
388 | if (intel_is_dual_link_lvds(dev)) |
389 | limit = &intel_limits_g4x_dual_channel_lvds; |
389 | limit = &intel_limits_g4x_dual_channel_lvds; |
390 | else |
390 | else |
391 | limit = &intel_limits_g4x_single_channel_lvds; |
391 | limit = &intel_limits_g4x_single_channel_lvds; |
392 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
392 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
393 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
393 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
394 | limit = &intel_limits_g4x_hdmi; |
394 | limit = &intel_limits_g4x_hdmi; |
395 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
395 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
396 | limit = &intel_limits_g4x_sdvo; |
396 | limit = &intel_limits_g4x_sdvo; |
397 | } else /* The option is for other outputs */ |
397 | } else /* The option is for other outputs */ |
398 | limit = &intel_limits_i9xx_sdvo; |
398 | limit = &intel_limits_i9xx_sdvo; |
399 | 399 | ||
400 | return limit; |
400 | return limit; |
401 | } |
401 | } |
402 | 402 | ||
403 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
403 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
404 | { |
404 | { |
405 | struct drm_device *dev = crtc->dev; |
405 | struct drm_device *dev = crtc->dev; |
406 | const intel_limit_t *limit; |
406 | const intel_limit_t *limit; |
407 | 407 | ||
408 | if (HAS_PCH_SPLIT(dev)) |
408 | if (HAS_PCH_SPLIT(dev)) |
409 | limit = intel_ironlake_limit(crtc, refclk); |
409 | limit = intel_ironlake_limit(crtc, refclk); |
410 | else if (IS_G4X(dev)) { |
410 | else if (IS_G4X(dev)) { |
411 | limit = intel_g4x_limit(crtc); |
411 | limit = intel_g4x_limit(crtc); |
412 | } else if (IS_PINEVIEW(dev)) { |
412 | } else if (IS_PINEVIEW(dev)) { |
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
414 | limit = &intel_limits_pineview_lvds; |
414 | limit = &intel_limits_pineview_lvds; |
415 | else |
415 | else |
416 | limit = &intel_limits_pineview_sdvo; |
416 | limit = &intel_limits_pineview_sdvo; |
417 | } else if (IS_VALLEYVIEW(dev)) { |
417 | } else if (IS_VALLEYVIEW(dev)) { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) |
419 | limit = &intel_limits_vlv_dac; |
419 | limit = &intel_limits_vlv_dac; |
420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
421 | limit = &intel_limits_vlv_hdmi; |
421 | limit = &intel_limits_vlv_hdmi; |
422 | else |
422 | else |
423 | limit = &intel_limits_vlv_dp; |
423 | limit = &intel_limits_vlv_dp; |
424 | } else if (!IS_GEN2(dev)) { |
424 | } else if (!IS_GEN2(dev)) { |
425 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
425 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
426 | limit = &intel_limits_i9xx_lvds; |
426 | limit = &intel_limits_i9xx_lvds; |
427 | else |
427 | else |
428 | limit = &intel_limits_i9xx_sdvo; |
428 | limit = &intel_limits_i9xx_sdvo; |
429 | } else { |
429 | } else { |
430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
431 | limit = &intel_limits_i8xx_lvds; |
431 | limit = &intel_limits_i8xx_lvds; |
432 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
432 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
433 | limit = &intel_limits_i8xx_dvo; |
433 | limit = &intel_limits_i8xx_dvo; |
434 | else |
434 | else |
435 | limit = &intel_limits_i8xx_dac; |
435 | limit = &intel_limits_i8xx_dac; |
436 | } |
436 | } |
437 | return limit; |
437 | return limit; |
438 | } |
438 | } |
439 | 439 | ||
440 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
440 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
441 | static void pineview_clock(int refclk, intel_clock_t *clock) |
441 | static void pineview_clock(int refclk, intel_clock_t *clock) |
442 | { |
442 | { |
443 | clock->m = clock->m2 + 2; |
443 | clock->m = clock->m2 + 2; |
444 | clock->p = clock->p1 * clock->p2; |
444 | clock->p = clock->p1 * clock->p2; |
445 | clock->vco = refclk * clock->m / clock->n; |
445 | clock->vco = refclk * clock->m / clock->n; |
446 | clock->dot = clock->vco / clock->p; |
446 | clock->dot = clock->vco / clock->p; |
447 | } |
447 | } |
448 | 448 | ||
449 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
449 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
450 | { |
450 | { |
451 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
451 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
452 | } |
452 | } |
453 | 453 | ||
454 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
454 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
455 | { |
455 | { |
456 | clock->m = i9xx_dpll_compute_m(clock); |
456 | clock->m = i9xx_dpll_compute_m(clock); |
457 | clock->p = clock->p1 * clock->p2; |
457 | clock->p = clock->p1 * clock->p2; |
458 | clock->vco = refclk * clock->m / (clock->n + 2); |
458 | clock->vco = refclk * clock->m / (clock->n + 2); |
459 | clock->dot = clock->vco / clock->p; |
459 | clock->dot = clock->vco / clock->p; |
460 | } |
460 | } |
461 | 461 | ||
462 | /** |
462 | /** |
463 | * Returns whether any output on the specified pipe is of the specified type |
463 | * Returns whether any output on the specified pipe is of the specified type |
464 | */ |
464 | */ |
465 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
465 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
466 | { |
466 | { |
467 | struct drm_device *dev = crtc->dev; |
467 | struct drm_device *dev = crtc->dev; |
468 | struct intel_encoder *encoder; |
468 | struct intel_encoder *encoder; |
469 | 469 | ||
470 | for_each_encoder_on_crtc(dev, crtc, encoder) |
470 | for_each_encoder_on_crtc(dev, crtc, encoder) |
471 | if (encoder->type == type) |
471 | if (encoder->type == type) |
472 | return true; |
472 | return true; |
473 | 473 | ||
474 | return false; |
474 | return false; |
475 | } |
475 | } |
476 | 476 | ||
477 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
477 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
478 | /** |
478 | /** |
479 | * Returns whether the given set of divisors are valid for a given refclk with |
479 | * Returns whether the given set of divisors are valid for a given refclk with |
480 | * the given connectors. |
480 | * the given connectors. |
481 | */ |
481 | */ |
482 | 482 | ||
483 | static bool intel_PLL_is_valid(struct drm_device *dev, |
483 | static bool intel_PLL_is_valid(struct drm_device *dev, |
484 | const intel_limit_t *limit, |
484 | const intel_limit_t *limit, |
485 | const intel_clock_t *clock) |
485 | const intel_clock_t *clock) |
486 | { |
486 | { |
487 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
487 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
488 | INTELPllInvalid("p1 out of range\n"); |
488 | INTELPllInvalid("p1 out of range\n"); |
489 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
489 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
490 | INTELPllInvalid("p out of range\n"); |
490 | INTELPllInvalid("p out of range\n"); |
491 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
491 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
492 | INTELPllInvalid("m2 out of range\n"); |
492 | INTELPllInvalid("m2 out of range\n"); |
493 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
493 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
494 | INTELPllInvalid("m1 out of range\n"); |
494 | INTELPllInvalid("m1 out of range\n"); |
495 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
495 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
496 | INTELPllInvalid("m1 <= m2\n"); |
496 | INTELPllInvalid("m1 <= m2\n"); |
497 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
497 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
498 | INTELPllInvalid("m out of range\n"); |
498 | INTELPllInvalid("m out of range\n"); |
499 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
499 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
500 | INTELPllInvalid("n out of range\n"); |
500 | INTELPllInvalid("n out of range\n"); |
501 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
501 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
502 | INTELPllInvalid("vco out of range\n"); |
502 | INTELPllInvalid("vco out of range\n"); |
503 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
503 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
504 | * connector, etc., rather than just a single range. |
504 | * connector, etc., rather than just a single range. |
505 | */ |
505 | */ |
506 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
506 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
507 | INTELPllInvalid("dot out of range\n"); |
507 | INTELPllInvalid("dot out of range\n"); |
508 | 508 | ||
509 | return true; |
509 | return true; |
510 | } |
510 | } |
511 | 511 | ||
512 | static bool |
512 | static bool |
513 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
513 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
514 | int target, int refclk, intel_clock_t *match_clock, |
514 | int target, int refclk, intel_clock_t *match_clock, |
515 | intel_clock_t *best_clock) |
515 | intel_clock_t *best_clock) |
516 | { |
516 | { |
517 | struct drm_device *dev = crtc->dev; |
517 | struct drm_device *dev = crtc->dev; |
518 | intel_clock_t clock; |
518 | intel_clock_t clock; |
519 | int err = target; |
519 | int err = target; |
520 | 520 | ||
521 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
521 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
522 | /* |
522 | /* |
523 | * For LVDS just rely on its current settings for dual-channel. |
523 | * For LVDS just rely on its current settings for dual-channel. |
524 | * We haven't figured out how to reliably set up different |
524 | * We haven't figured out how to reliably set up different |
525 | * single/dual channel state, if we even can. |
525 | * single/dual channel state, if we even can. |
526 | */ |
526 | */ |
527 | if (intel_is_dual_link_lvds(dev)) |
527 | if (intel_is_dual_link_lvds(dev)) |
528 | clock.p2 = limit->p2.p2_fast; |
528 | clock.p2 = limit->p2.p2_fast; |
529 | else |
529 | else |
530 | clock.p2 = limit->p2.p2_slow; |
530 | clock.p2 = limit->p2.p2_slow; |
531 | } else { |
531 | } else { |
532 | if (target < limit->p2.dot_limit) |
532 | if (target < limit->p2.dot_limit) |
533 | clock.p2 = limit->p2.p2_slow; |
533 | clock.p2 = limit->p2.p2_slow; |
534 | else |
534 | else |
535 | clock.p2 = limit->p2.p2_fast; |
535 | clock.p2 = limit->p2.p2_fast; |
536 | } |
536 | } |
537 | 537 | ||
538 | memset(best_clock, 0, sizeof(*best_clock)); |
538 | memset(best_clock, 0, sizeof(*best_clock)); |
539 | 539 | ||
540 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
540 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
541 | clock.m1++) { |
541 | clock.m1++) { |
542 | for (clock.m2 = limit->m2.min; |
542 | for (clock.m2 = limit->m2.min; |
543 | clock.m2 <= limit->m2.max; clock.m2++) { |
543 | clock.m2 <= limit->m2.max; clock.m2++) { |
544 | if (clock.m2 >= clock.m1) |
544 | if (clock.m2 >= clock.m1) |
545 | break; |
545 | break; |
546 | for (clock.n = limit->n.min; |
546 | for (clock.n = limit->n.min; |
547 | clock.n <= limit->n.max; clock.n++) { |
547 | clock.n <= limit->n.max; clock.n++) { |
548 | for (clock.p1 = limit->p1.min; |
548 | for (clock.p1 = limit->p1.min; |
549 | clock.p1 <= limit->p1.max; clock.p1++) { |
549 | clock.p1 <= limit->p1.max; clock.p1++) { |
550 | int this_err; |
550 | int this_err; |
551 | 551 | ||
552 | i9xx_clock(refclk, &clock); |
552 | i9xx_clock(refclk, &clock); |
553 | if (!intel_PLL_is_valid(dev, limit, |
553 | if (!intel_PLL_is_valid(dev, limit, |
554 | &clock)) |
554 | &clock)) |
555 | continue; |
555 | continue; |
556 | if (match_clock && |
556 | if (match_clock && |
557 | clock.p != match_clock->p) |
557 | clock.p != match_clock->p) |
558 | continue; |
558 | continue; |
559 | 559 | ||
560 | this_err = abs(clock.dot - target); |
560 | this_err = abs(clock.dot - target); |
561 | if (this_err < err) { |
561 | if (this_err < err) { |
562 | *best_clock = clock; |
562 | *best_clock = clock; |
563 | err = this_err; |
563 | err = this_err; |
564 | } |
564 | } |
565 | } |
565 | } |
566 | } |
566 | } |
567 | } |
567 | } |
568 | } |
568 | } |
569 | 569 | ||
570 | return (err != target); |
570 | return (err != target); |
571 | } |
571 | } |
572 | 572 | ||
573 | static bool |
573 | static bool |
574 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
574 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
575 | int target, int refclk, intel_clock_t *match_clock, |
575 | int target, int refclk, intel_clock_t *match_clock, |
576 | intel_clock_t *best_clock) |
576 | intel_clock_t *best_clock) |
577 | { |
577 | { |
578 | struct drm_device *dev = crtc->dev; |
578 | struct drm_device *dev = crtc->dev; |
579 | intel_clock_t clock; |
579 | intel_clock_t clock; |
580 | int err = target; |
580 | int err = target; |
581 | 581 | ||
582 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
582 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
583 | /* |
583 | /* |
584 | * For LVDS just rely on its current settings for dual-channel. |
584 | * For LVDS just rely on its current settings for dual-channel. |
585 | * We haven't figured out how to reliably set up different |
585 | * We haven't figured out how to reliably set up different |
586 | * single/dual channel state, if we even can. |
586 | * single/dual channel state, if we even can. |
587 | */ |
587 | */ |
588 | if (intel_is_dual_link_lvds(dev)) |
588 | if (intel_is_dual_link_lvds(dev)) |
589 | clock.p2 = limit->p2.p2_fast; |
589 | clock.p2 = limit->p2.p2_fast; |
590 | else |
590 | else |
591 | clock.p2 = limit->p2.p2_slow; |
591 | clock.p2 = limit->p2.p2_slow; |
592 | } else { |
592 | } else { |
593 | if (target < limit->p2.dot_limit) |
593 | if (target < limit->p2.dot_limit) |
594 | clock.p2 = limit->p2.p2_slow; |
594 | clock.p2 = limit->p2.p2_slow; |
595 | else |
595 | else |
596 | clock.p2 = limit->p2.p2_fast; |
596 | clock.p2 = limit->p2.p2_fast; |
597 | } |
597 | } |
598 | 598 | ||
599 | memset(best_clock, 0, sizeof(*best_clock)); |
599 | memset(best_clock, 0, sizeof(*best_clock)); |
600 | 600 | ||
601 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
601 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
602 | clock.m1++) { |
602 | clock.m1++) { |
603 | for (clock.m2 = limit->m2.min; |
603 | for (clock.m2 = limit->m2.min; |
604 | clock.m2 <= limit->m2.max; clock.m2++) { |
604 | clock.m2 <= limit->m2.max; clock.m2++) { |
605 | for (clock.n = limit->n.min; |
605 | for (clock.n = limit->n.min; |
606 | clock.n <= limit->n.max; clock.n++) { |
606 | clock.n <= limit->n.max; clock.n++) { |
607 | for (clock.p1 = limit->p1.min; |
607 | for (clock.p1 = limit->p1.min; |
608 | clock.p1 <= limit->p1.max; clock.p1++) { |
608 | clock.p1 <= limit->p1.max; clock.p1++) { |
609 | int this_err; |
609 | int this_err; |
610 | 610 | ||
611 | pineview_clock(refclk, &clock); |
611 | pineview_clock(refclk, &clock); |
612 | if (!intel_PLL_is_valid(dev, limit, |
612 | if (!intel_PLL_is_valid(dev, limit, |
613 | &clock)) |
613 | &clock)) |
614 | continue; |
614 | continue; |
615 | if (match_clock && |
615 | if (match_clock && |
616 | clock.p != match_clock->p) |
616 | clock.p != match_clock->p) |
617 | continue; |
617 | continue; |
618 | 618 | ||
619 | this_err = abs(clock.dot - target); |
619 | this_err = abs(clock.dot - target); |
620 | if (this_err < err) { |
620 | if (this_err < err) { |
621 | *best_clock = clock; |
621 | *best_clock = clock; |
622 | err = this_err; |
622 | err = this_err; |
623 | } |
623 | } |
624 | } |
624 | } |
625 | } |
625 | } |
626 | } |
626 | } |
627 | } |
627 | } |
628 | 628 | ||
629 | return (err != target); |
629 | return (err != target); |
630 | } |
630 | } |
631 | 631 | ||
632 | static bool |
632 | static bool |
633 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
633 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
634 | int target, int refclk, intel_clock_t *match_clock, |
634 | int target, int refclk, intel_clock_t *match_clock, |
635 | intel_clock_t *best_clock) |
635 | intel_clock_t *best_clock) |
636 | { |
636 | { |
637 | struct drm_device *dev = crtc->dev; |
637 | struct drm_device *dev = crtc->dev; |
638 | intel_clock_t clock; |
638 | intel_clock_t clock; |
639 | int max_n; |
639 | int max_n; |
640 | bool found; |
640 | bool found; |
641 | /* approximately equals target * 0.00585 */ |
641 | /* approximately equals target * 0.00585 */ |
642 | int err_most = (target >> 8) + (target >> 9); |
642 | int err_most = (target >> 8) + (target >> 9); |
643 | found = false; |
643 | found = false; |
644 | 644 | ||
645 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
645 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
646 | if (intel_is_dual_link_lvds(dev)) |
646 | if (intel_is_dual_link_lvds(dev)) |
647 | clock.p2 = limit->p2.p2_fast; |
647 | clock.p2 = limit->p2.p2_fast; |
648 | else |
648 | else |
649 | clock.p2 = limit->p2.p2_slow; |
649 | clock.p2 = limit->p2.p2_slow; |
650 | } else { |
650 | } else { |
651 | if (target < limit->p2.dot_limit) |
651 | if (target < limit->p2.dot_limit) |
652 | clock.p2 = limit->p2.p2_slow; |
652 | clock.p2 = limit->p2.p2_slow; |
653 | else |
653 | else |
654 | clock.p2 = limit->p2.p2_fast; |
654 | clock.p2 = limit->p2.p2_fast; |
655 | } |
655 | } |
656 | 656 | ||
657 | memset(best_clock, 0, sizeof(*best_clock)); |
657 | memset(best_clock, 0, sizeof(*best_clock)); |
658 | max_n = limit->n.max; |
658 | max_n = limit->n.max; |
659 | /* based on hardware requirement, prefer smaller n to precision */ |
659 | /* based on hardware requirement, prefer smaller n to precision */ |
660 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
660 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
661 | /* based on hardware requirement, prefere larger m1,m2 */ |
661 | /* based on hardware requirement, prefere larger m1,m2 */ |
662 | for (clock.m1 = limit->m1.max; |
662 | for (clock.m1 = limit->m1.max; |
663 | clock.m1 >= limit->m1.min; clock.m1--) { |
663 | clock.m1 >= limit->m1.min; clock.m1--) { |
664 | for (clock.m2 = limit->m2.max; |
664 | for (clock.m2 = limit->m2.max; |
665 | clock.m2 >= limit->m2.min; clock.m2--) { |
665 | clock.m2 >= limit->m2.min; clock.m2--) { |
666 | for (clock.p1 = limit->p1.max; |
666 | for (clock.p1 = limit->p1.max; |
667 | clock.p1 >= limit->p1.min; clock.p1--) { |
667 | clock.p1 >= limit->p1.min; clock.p1--) { |
668 | int this_err; |
668 | int this_err; |
669 | 669 | ||
670 | i9xx_clock(refclk, &clock); |
670 | i9xx_clock(refclk, &clock); |
671 | if (!intel_PLL_is_valid(dev, limit, |
671 | if (!intel_PLL_is_valid(dev, limit, |
672 | &clock)) |
672 | &clock)) |
673 | continue; |
673 | continue; |
674 | 674 | ||
675 | this_err = abs(clock.dot - target); |
675 | this_err = abs(clock.dot - target); |
676 | if (this_err < err_most) { |
676 | if (this_err < err_most) { |
677 | *best_clock = clock; |
677 | *best_clock = clock; |
678 | err_most = this_err; |
678 | err_most = this_err; |
679 | max_n = clock.n; |
679 | max_n = clock.n; |
680 | found = true; |
680 | found = true; |
681 | } |
681 | } |
682 | } |
682 | } |
683 | } |
683 | } |
684 | } |
684 | } |
685 | } |
685 | } |
686 | return found; |
686 | return found; |
687 | } |
687 | } |
688 | 688 | ||
689 | static bool |
689 | static bool |
690 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
690 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
691 | int target, int refclk, intel_clock_t *match_clock, |
691 | int target, int refclk, intel_clock_t *match_clock, |
692 | intel_clock_t *best_clock) |
692 | intel_clock_t *best_clock) |
693 | { |
693 | { |
694 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
694 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; |
695 | u32 m, n, fastclk; |
695 | u32 m, n, fastclk; |
696 | u32 updrate, minupdate, p; |
696 | u32 updrate, minupdate, p; |
697 | unsigned long bestppm, ppm, absppm; |
697 | unsigned long bestppm, ppm, absppm; |
698 | int dotclk, flag; |
698 | int dotclk, flag; |
699 | 699 | ||
700 | flag = 0; |
700 | flag = 0; |
701 | dotclk = target * 1000; |
701 | dotclk = target * 1000; |
702 | bestppm = 1000000; |
702 | bestppm = 1000000; |
703 | ppm = absppm = 0; |
703 | ppm = absppm = 0; |
704 | fastclk = dotclk / (2*100); |
704 | fastclk = dotclk / (2*100); |
705 | updrate = 0; |
705 | updrate = 0; |
706 | minupdate = 19200; |
706 | minupdate = 19200; |
707 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
707 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
708 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
708 | bestm1 = bestm2 = bestp1 = bestp2 = 0; |
709 | 709 | ||
710 | /* based on hardware requirement, prefer smaller n to precision */ |
710 | /* based on hardware requirement, prefer smaller n to precision */ |
711 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
711 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { |
712 | updrate = refclk / n; |
712 | updrate = refclk / n; |
713 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
713 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { |
714 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
714 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { |
715 | if (p2 > 10) |
715 | if (p2 > 10) |
716 | p2 = p2 - 1; |
716 | p2 = p2 - 1; |
717 | p = p1 * p2; |
717 | p = p1 * p2; |
718 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
718 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
719 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
719 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { |
720 | m2 = (((2*(fastclk * p * n / m1 )) + |
720 | m2 = (((2*(fastclk * p * n / m1 )) + |
721 | refclk) / (2*refclk)); |
721 | refclk) / (2*refclk)); |
722 | m = m1 * m2; |
722 | m = m1 * m2; |
723 | vco = updrate * m; |
723 | vco = updrate * m; |
724 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
724 | if (vco >= limit->vco.min && vco < limit->vco.max) { |
725 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
725 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; |
726 | absppm = (ppm > 0) ? ppm : (-ppm); |
726 | absppm = (ppm > 0) ? ppm : (-ppm); |
727 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
727 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { |
728 | bestppm = 0; |
728 | bestppm = 0; |
729 | flag = 1; |
729 | flag = 1; |
730 | } |
730 | } |
731 | if (absppm < bestppm - 10) { |
731 | if (absppm < bestppm - 10) { |
732 | bestppm = absppm; |
732 | bestppm = absppm; |
733 | flag = 1; |
733 | flag = 1; |
734 | } |
734 | } |
735 | if (flag) { |
735 | if (flag) { |
736 | bestn = n; |
736 | bestn = n; |
737 | bestm1 = m1; |
737 | bestm1 = m1; |
738 | bestm2 = m2; |
738 | bestm2 = m2; |
739 | bestp1 = p1; |
739 | bestp1 = p1; |
740 | bestp2 = p2; |
740 | bestp2 = p2; |
741 | flag = 0; |
741 | flag = 0; |
742 | } |
742 | } |
743 | } |
743 | } |
744 | } |
744 | } |
745 | } |
745 | } |
746 | } |
746 | } |
747 | } |
747 | } |
748 | best_clock->n = bestn; |
748 | best_clock->n = bestn; |
749 | best_clock->m1 = bestm1; |
749 | best_clock->m1 = bestm1; |
750 | best_clock->m2 = bestm2; |
750 | best_clock->m2 = bestm2; |
751 | best_clock->p1 = bestp1; |
751 | best_clock->p1 = bestp1; |
752 | best_clock->p2 = bestp2; |
752 | best_clock->p2 = bestp2; |
753 | 753 | ||
754 | return true; |
754 | return true; |
755 | } |
755 | } |
756 | 756 | ||
757 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
757 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
758 | enum pipe pipe) |
758 | enum pipe pipe) |
759 | { |
759 | { |
760 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
760 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
762 | 762 | ||
763 | return intel_crtc->config.cpu_transcoder; |
763 | return intel_crtc->config.cpu_transcoder; |
764 | } |
764 | } |
765 | 765 | ||
766 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
766 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
767 | { |
767 | { |
768 | struct drm_i915_private *dev_priv = dev->dev_private; |
768 | struct drm_i915_private *dev_priv = dev->dev_private; |
769 | u32 frame, frame_reg = PIPEFRAME(pipe); |
769 | u32 frame, frame_reg = PIPEFRAME(pipe); |
770 | 770 | ||
771 | frame = I915_READ(frame_reg); |
771 | frame = I915_READ(frame_reg); |
772 | 772 | ||
773 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
773 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
774 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
774 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
775 | } |
775 | } |
776 | 776 | ||
777 | /** |
777 | /** |
778 | * intel_wait_for_vblank - wait for vblank on a given pipe |
778 | * intel_wait_for_vblank - wait for vblank on a given pipe |
779 | * @dev: drm device |
779 | * @dev: drm device |
780 | * @pipe: pipe to wait for |
780 | * @pipe: pipe to wait for |
781 | * |
781 | * |
782 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
782 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
783 | * mode setting code. |
783 | * mode setting code. |
784 | */ |
784 | */ |
785 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
785 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
786 | { |
786 | { |
787 | struct drm_i915_private *dev_priv = dev->dev_private; |
787 | struct drm_i915_private *dev_priv = dev->dev_private; |
788 | int pipestat_reg = PIPESTAT(pipe); |
788 | int pipestat_reg = PIPESTAT(pipe); |
789 | 789 | ||
790 | if (INTEL_INFO(dev)->gen >= 5) { |
790 | if (INTEL_INFO(dev)->gen >= 5) { |
791 | ironlake_wait_for_vblank(dev, pipe); |
791 | ironlake_wait_for_vblank(dev, pipe); |
792 | return; |
792 | return; |
793 | } |
793 | } |
794 | 794 | ||
795 | /* Clear existing vblank status. Note this will clear any other |
795 | /* Clear existing vblank status. Note this will clear any other |
796 | * sticky status fields as well. |
796 | * sticky status fields as well. |
797 | * |
797 | * |
798 | * This races with i915_driver_irq_handler() with the result |
798 | * This races with i915_driver_irq_handler() with the result |
799 | * that either function could miss a vblank event. Here it is not |
799 | * that either function could miss a vblank event. Here it is not |
800 | * fatal, as we will either wait upon the next vblank interrupt or |
800 | * fatal, as we will either wait upon the next vblank interrupt or |
801 | * timeout. Generally speaking intel_wait_for_vblank() is only |
801 | * timeout. Generally speaking intel_wait_for_vblank() is only |
802 | * called during modeset at which time the GPU should be idle and |
802 | * called during modeset at which time the GPU should be idle and |
803 | * should *not* be performing page flips and thus not waiting on |
803 | * should *not* be performing page flips and thus not waiting on |
804 | * vblanks... |
804 | * vblanks... |
805 | * Currently, the result of us stealing a vblank from the irq |
805 | * Currently, the result of us stealing a vblank from the irq |
806 | * handler is that a single frame will be skipped during swapbuffers. |
806 | * handler is that a single frame will be skipped during swapbuffers. |
807 | */ |
807 | */ |
808 | I915_WRITE(pipestat_reg, |
808 | I915_WRITE(pipestat_reg, |
809 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
809 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
810 | 810 | ||
811 | /* Wait for vblank interrupt bit to set */ |
811 | /* Wait for vblank interrupt bit to set */ |
812 | if (wait_for(I915_READ(pipestat_reg) & |
812 | if (wait_for(I915_READ(pipestat_reg) & |
813 | PIPE_VBLANK_INTERRUPT_STATUS, |
813 | PIPE_VBLANK_INTERRUPT_STATUS, |
814 | 50)) |
814 | 50)) |
815 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
815 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
816 | } |
816 | } |
817 | 817 | ||
818 | /* |
818 | /* |
819 | * intel_wait_for_pipe_off - wait for pipe to turn off |
819 | * intel_wait_for_pipe_off - wait for pipe to turn off |
820 | * @dev: drm device |
820 | * @dev: drm device |
821 | * @pipe: pipe to wait for |
821 | * @pipe: pipe to wait for |
822 | * |
822 | * |
823 | * After disabling a pipe, we can't wait for vblank in the usual way, |
823 | * After disabling a pipe, we can't wait for vblank in the usual way, |
824 | * spinning on the vblank interrupt status bit, since we won't actually |
824 | * spinning on the vblank interrupt status bit, since we won't actually |
825 | * see an interrupt when the pipe is disabled. |
825 | * see an interrupt when the pipe is disabled. |
826 | * |
826 | * |
827 | * On Gen4 and above: |
827 | * On Gen4 and above: |
828 | * wait for the pipe register state bit to turn off |
828 | * wait for the pipe register state bit to turn off |
829 | * |
829 | * |
830 | * Otherwise: |
830 | * Otherwise: |
831 | * wait for the display line value to settle (it usually |
831 | * wait for the display line value to settle (it usually |
832 | * ends up stopping at the start of the next frame). |
832 | * ends up stopping at the start of the next frame). |
833 | * |
833 | * |
834 | */ |
834 | */ |
835 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
835 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
836 | { |
836 | { |
837 | struct drm_i915_private *dev_priv = dev->dev_private; |
837 | struct drm_i915_private *dev_priv = dev->dev_private; |
838 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
838 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
839 | pipe); |
839 | pipe); |
840 | 840 | ||
841 | if (INTEL_INFO(dev)->gen >= 4) { |
841 | if (INTEL_INFO(dev)->gen >= 4) { |
842 | int reg = PIPECONF(cpu_transcoder); |
842 | int reg = PIPECONF(cpu_transcoder); |
843 | 843 | ||
844 | /* Wait for the Pipe State to go off */ |
844 | /* Wait for the Pipe State to go off */ |
845 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
845 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
846 | 100)) |
846 | 100)) |
847 | WARN(1, "pipe_off wait timed out\n"); |
847 | WARN(1, "pipe_off wait timed out\n"); |
848 | } else { |
848 | } else { |
849 | u32 last_line, line_mask; |
849 | u32 last_line, line_mask; |
850 | int reg = PIPEDSL(pipe); |
850 | int reg = PIPEDSL(pipe); |
851 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
851 | unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100); |
852 | 852 | ||
853 | if (IS_GEN2(dev)) |
853 | if (IS_GEN2(dev)) |
854 | line_mask = DSL_LINEMASK_GEN2; |
854 | line_mask = DSL_LINEMASK_GEN2; |
855 | else |
855 | else |
856 | line_mask = DSL_LINEMASK_GEN3; |
856 | line_mask = DSL_LINEMASK_GEN3; |
857 | 857 | ||
858 | /* Wait for the display line to settle */ |
858 | /* Wait for the display line to settle */ |
859 | do { |
859 | do { |
860 | last_line = I915_READ(reg) & line_mask; |
860 | last_line = I915_READ(reg) & line_mask; |
861 | mdelay(5); |
861 | mdelay(5); |
862 | } while (((I915_READ(reg) & line_mask) != last_line) && |
862 | } while (((I915_READ(reg) & line_mask) != last_line) && |
863 | time_after(timeout, GetTimerTicks())); |
863 | time_after(timeout, GetTimerTicks())); |
864 | if (time_after(GetTimerTicks(), timeout)) |
864 | if (time_after(GetTimerTicks(), timeout)) |
865 | WARN(1, "pipe_off wait timed out\n"); |
865 | WARN(1, "pipe_off wait timed out\n"); |
866 | } |
866 | } |
867 | } |
867 | } |
868 | 868 | ||
869 | /* |
869 | /* |
870 | * ibx_digital_port_connected - is the specified port connected? |
870 | * ibx_digital_port_connected - is the specified port connected? |
871 | * @dev_priv: i915 private structure |
871 | * @dev_priv: i915 private structure |
872 | * @port: the port to test |
872 | * @port: the port to test |
873 | * |
873 | * |
874 | * Returns true if @port is connected, false otherwise. |
874 | * Returns true if @port is connected, false otherwise. |
875 | */ |
875 | */ |
876 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
876 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
877 | struct intel_digital_port *port) |
877 | struct intel_digital_port *port) |
878 | { |
878 | { |
879 | u32 bit; |
879 | u32 bit; |
880 | 880 | ||
881 | if (HAS_PCH_IBX(dev_priv->dev)) { |
881 | if (HAS_PCH_IBX(dev_priv->dev)) { |
882 | switch(port->port) { |
882 | switch(port->port) { |
883 | case PORT_B: |
883 | case PORT_B: |
884 | bit = SDE_PORTB_HOTPLUG; |
884 | bit = SDE_PORTB_HOTPLUG; |
885 | break; |
885 | break; |
886 | case PORT_C: |
886 | case PORT_C: |
887 | bit = SDE_PORTC_HOTPLUG; |
887 | bit = SDE_PORTC_HOTPLUG; |
888 | break; |
888 | break; |
889 | case PORT_D: |
889 | case PORT_D: |
890 | bit = SDE_PORTD_HOTPLUG; |
890 | bit = SDE_PORTD_HOTPLUG; |
891 | break; |
891 | break; |
892 | default: |
892 | default: |
893 | return true; |
893 | return true; |
894 | } |
894 | } |
895 | } else { |
895 | } else { |
896 | switch(port->port) { |
896 | switch(port->port) { |
897 | case PORT_B: |
897 | case PORT_B: |
898 | bit = SDE_PORTB_HOTPLUG_CPT; |
898 | bit = SDE_PORTB_HOTPLUG_CPT; |
899 | break; |
899 | break; |
900 | case PORT_C: |
900 | case PORT_C: |
901 | bit = SDE_PORTC_HOTPLUG_CPT; |
901 | bit = SDE_PORTC_HOTPLUG_CPT; |
902 | break; |
902 | break; |
903 | case PORT_D: |
903 | case PORT_D: |
904 | bit = SDE_PORTD_HOTPLUG_CPT; |
904 | bit = SDE_PORTD_HOTPLUG_CPT; |
905 | break; |
905 | break; |
906 | default: |
906 | default: |
907 | return true; |
907 | return true; |
908 | } |
908 | } |
909 | } |
909 | } |
910 | 910 | ||
911 | return I915_READ(SDEISR) & bit; |
911 | return I915_READ(SDEISR) & bit; |
912 | } |
912 | } |
913 | 913 | ||
914 | static const char *state_string(bool enabled) |
914 | static const char *state_string(bool enabled) |
915 | { |
915 | { |
916 | return enabled ? "on" : "off"; |
916 | return enabled ? "on" : "off"; |
917 | } |
917 | } |
918 | 918 | ||
919 | /* Only for pre-ILK configs */ |
919 | /* Only for pre-ILK configs */ |
920 | void assert_pll(struct drm_i915_private *dev_priv, |
920 | void assert_pll(struct drm_i915_private *dev_priv, |
921 | enum pipe pipe, bool state) |
921 | enum pipe pipe, bool state) |
922 | { |
922 | { |
923 | int reg; |
923 | int reg; |
924 | u32 val; |
924 | u32 val; |
925 | bool cur_state; |
925 | bool cur_state; |
926 | 926 | ||
927 | reg = DPLL(pipe); |
927 | reg = DPLL(pipe); |
928 | val = I915_READ(reg); |
928 | val = I915_READ(reg); |
929 | cur_state = !!(val & DPLL_VCO_ENABLE); |
929 | cur_state = !!(val & DPLL_VCO_ENABLE); |
930 | WARN(cur_state != state, |
930 | WARN(cur_state != state, |
931 | "PLL state assertion failure (expected %s, current %s)\n", |
931 | "PLL state assertion failure (expected %s, current %s)\n", |
932 | state_string(state), state_string(cur_state)); |
932 | state_string(state), state_string(cur_state)); |
933 | } |
933 | } |
934 | 934 | ||
935 | struct intel_shared_dpll * |
935 | struct intel_shared_dpll * |
936 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
936 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
937 | { |
937 | { |
938 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
938 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
939 | 939 | ||
940 | if (crtc->config.shared_dpll < 0) |
940 | if (crtc->config.shared_dpll < 0) |
941 | return NULL; |
941 | return NULL; |
942 | 942 | ||
943 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
943 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
944 | } |
944 | } |
945 | 945 | ||
946 | /* For ILK+ */ |
946 | /* For ILK+ */ |
947 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
947 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
948 | struct intel_shared_dpll *pll, |
948 | struct intel_shared_dpll *pll, |
949 | bool state) |
949 | bool state) |
950 | { |
950 | { |
951 | bool cur_state; |
951 | bool cur_state; |
952 | struct intel_dpll_hw_state hw_state; |
952 | struct intel_dpll_hw_state hw_state; |
953 | 953 | ||
954 | if (HAS_PCH_LPT(dev_priv->dev)) { |
954 | if (HAS_PCH_LPT(dev_priv->dev)) { |
955 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
955 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
956 | return; |
956 | return; |
957 | } |
957 | } |
958 | 958 | ||
959 | if (WARN (!pll, |
959 | if (WARN (!pll, |
960 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
960 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
961 | return; |
961 | return; |
962 | 962 | ||
963 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
963 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
964 | WARN(cur_state != state, |
964 | WARN(cur_state != state, |
965 | "%s assertion failure (expected %s, current %s)\n", |
965 | "%s assertion failure (expected %s, current %s)\n", |
966 | pll->name, state_string(state), state_string(cur_state)); |
966 | pll->name, state_string(state), state_string(cur_state)); |
967 | } |
967 | } |
968 | 968 | ||
969 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
969 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
970 | enum pipe pipe, bool state) |
970 | enum pipe pipe, bool state) |
971 | { |
971 | { |
972 | int reg; |
972 | int reg; |
973 | u32 val; |
973 | u32 val; |
974 | bool cur_state; |
974 | bool cur_state; |
975 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
975 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
976 | pipe); |
976 | pipe); |
977 | 977 | ||
978 | if (HAS_DDI(dev_priv->dev)) { |
978 | if (HAS_DDI(dev_priv->dev)) { |
979 | /* DDI does not have a specific FDI_TX register */ |
979 | /* DDI does not have a specific FDI_TX register */ |
980 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
980 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
981 | val = I915_READ(reg); |
981 | val = I915_READ(reg); |
982 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
982 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
983 | } else { |
983 | } else { |
984 | reg = FDI_TX_CTL(pipe); |
984 | reg = FDI_TX_CTL(pipe); |
985 | val = I915_READ(reg); |
985 | val = I915_READ(reg); |
986 | cur_state = !!(val & FDI_TX_ENABLE); |
986 | cur_state = !!(val & FDI_TX_ENABLE); |
987 | } |
987 | } |
988 | WARN(cur_state != state, |
988 | WARN(cur_state != state, |
989 | "FDI TX state assertion failure (expected %s, current %s)\n", |
989 | "FDI TX state assertion failure (expected %s, current %s)\n", |
990 | state_string(state), state_string(cur_state)); |
990 | state_string(state), state_string(cur_state)); |
991 | } |
991 | } |
992 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
992 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
993 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
993 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
994 | 994 | ||
995 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
995 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
996 | enum pipe pipe, bool state) |
996 | enum pipe pipe, bool state) |
997 | { |
997 | { |
998 | int reg; |
998 | int reg; |
999 | u32 val; |
999 | u32 val; |
1000 | bool cur_state; |
1000 | bool cur_state; |
1001 | 1001 | ||
1002 | reg = FDI_RX_CTL(pipe); |
1002 | reg = FDI_RX_CTL(pipe); |
1003 | val = I915_READ(reg); |
1003 | val = I915_READ(reg); |
1004 | cur_state = !!(val & FDI_RX_ENABLE); |
1004 | cur_state = !!(val & FDI_RX_ENABLE); |
1005 | WARN(cur_state != state, |
1005 | WARN(cur_state != state, |
1006 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1006 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1007 | state_string(state), state_string(cur_state)); |
1007 | state_string(state), state_string(cur_state)); |
1008 | } |
1008 | } |
1009 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1009 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1010 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1010 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1011 | 1011 | ||
1012 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1012 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1013 | enum pipe pipe) |
1013 | enum pipe pipe) |
1014 | { |
1014 | { |
1015 | int reg; |
1015 | int reg; |
1016 | u32 val; |
1016 | u32 val; |
1017 | 1017 | ||
1018 | /* ILK FDI PLL is always enabled */ |
1018 | /* ILK FDI PLL is always enabled */ |
1019 | if (dev_priv->info->gen == 5) |
1019 | if (dev_priv->info->gen == 5) |
1020 | return; |
1020 | return; |
1021 | 1021 | ||
1022 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1022 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1023 | if (HAS_DDI(dev_priv->dev)) |
1023 | if (HAS_DDI(dev_priv->dev)) |
1024 | return; |
1024 | return; |
1025 | 1025 | ||
1026 | reg = FDI_TX_CTL(pipe); |
1026 | reg = FDI_TX_CTL(pipe); |
1027 | val = I915_READ(reg); |
1027 | val = I915_READ(reg); |
1028 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1028 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
1029 | } |
1029 | } |
1030 | 1030 | ||
1031 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1031 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1032 | enum pipe pipe, bool state) |
1032 | enum pipe pipe, bool state) |
1033 | { |
1033 | { |
1034 | int reg; |
1034 | int reg; |
1035 | u32 val; |
1035 | u32 val; |
1036 | bool cur_state; |
1036 | bool cur_state; |
1037 | 1037 | ||
1038 | reg = FDI_RX_CTL(pipe); |
1038 | reg = FDI_RX_CTL(pipe); |
1039 | val = I915_READ(reg); |
1039 | val = I915_READ(reg); |
1040 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1040 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1041 | WARN(cur_state != state, |
1041 | WARN(cur_state != state, |
1042 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1042 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1043 | state_string(state), state_string(cur_state)); |
1043 | state_string(state), state_string(cur_state)); |
1044 | } |
1044 | } |
1045 | 1045 | ||
1046 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1046 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1047 | enum pipe pipe) |
1047 | enum pipe pipe) |
1048 | { |
1048 | { |
1049 | int pp_reg, lvds_reg; |
1049 | int pp_reg, lvds_reg; |
1050 | u32 val; |
1050 | u32 val; |
1051 | enum pipe panel_pipe = PIPE_A; |
1051 | enum pipe panel_pipe = PIPE_A; |
1052 | bool locked = true; |
1052 | bool locked = true; |
1053 | 1053 | ||
1054 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1054 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1055 | pp_reg = PCH_PP_CONTROL; |
1055 | pp_reg = PCH_PP_CONTROL; |
1056 | lvds_reg = PCH_LVDS; |
1056 | lvds_reg = PCH_LVDS; |
1057 | } else { |
1057 | } else { |
1058 | pp_reg = PP_CONTROL; |
1058 | pp_reg = PP_CONTROL; |
1059 | lvds_reg = LVDS; |
1059 | lvds_reg = LVDS; |
1060 | } |
1060 | } |
1061 | 1061 | ||
1062 | val = I915_READ(pp_reg); |
1062 | val = I915_READ(pp_reg); |
1063 | if (!(val & PANEL_POWER_ON) || |
1063 | if (!(val & PANEL_POWER_ON) || |
1064 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1064 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1065 | locked = false; |
1065 | locked = false; |
1066 | 1066 | ||
1067 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1067 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1068 | panel_pipe = PIPE_B; |
1068 | panel_pipe = PIPE_B; |
1069 | 1069 | ||
1070 | WARN(panel_pipe == pipe && locked, |
1070 | WARN(panel_pipe == pipe && locked, |
1071 | "panel assertion failure, pipe %c regs locked\n", |
1071 | "panel assertion failure, pipe %c regs locked\n", |
1072 | pipe_name(pipe)); |
1072 | pipe_name(pipe)); |
1073 | } |
1073 | } |
1074 | 1074 | ||
1075 | void assert_pipe(struct drm_i915_private *dev_priv, |
1075 | void assert_pipe(struct drm_i915_private *dev_priv, |
1076 | enum pipe pipe, bool state) |
1076 | enum pipe pipe, bool state) |
1077 | { |
1077 | { |
1078 | int reg; |
1078 | int reg; |
1079 | u32 val; |
1079 | u32 val; |
1080 | bool cur_state; |
1080 | bool cur_state; |
1081 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1081 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1082 | pipe); |
1082 | pipe); |
1083 | 1083 | ||
1084 | /* if we need the pipe A quirk it must be always on */ |
1084 | /* if we need the pipe A quirk it must be always on */ |
1085 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1085 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1086 | state = true; |
1086 | state = true; |
1087 | 1087 | ||
1088 | if (!intel_display_power_enabled(dev_priv->dev, |
1088 | if (!intel_display_power_enabled(dev_priv->dev, |
1089 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1089 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1090 | cur_state = false; |
1090 | cur_state = false; |
1091 | } else { |
1091 | } else { |
1092 | reg = PIPECONF(cpu_transcoder); |
1092 | reg = PIPECONF(cpu_transcoder); |
1093 | val = I915_READ(reg); |
1093 | val = I915_READ(reg); |
1094 | cur_state = !!(val & PIPECONF_ENABLE); |
1094 | cur_state = !!(val & PIPECONF_ENABLE); |
1095 | } |
1095 | } |
1096 | 1096 | ||
1097 | WARN(cur_state != state, |
1097 | WARN(cur_state != state, |
1098 | "pipe %c assertion failure (expected %s, current %s)\n", |
1098 | "pipe %c assertion failure (expected %s, current %s)\n", |
1099 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1099 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1100 | } |
1100 | } |
1101 | 1101 | ||
1102 | static void assert_plane(struct drm_i915_private *dev_priv, |
1102 | static void assert_plane(struct drm_i915_private *dev_priv, |
1103 | enum plane plane, bool state) |
1103 | enum plane plane, bool state) |
1104 | { |
1104 | { |
1105 | int reg; |
1105 | int reg; |
1106 | u32 val; |
1106 | u32 val; |
1107 | bool cur_state; |
1107 | bool cur_state; |
1108 | 1108 | ||
1109 | reg = DSPCNTR(plane); |
1109 | reg = DSPCNTR(plane); |
1110 | val = I915_READ(reg); |
1110 | val = I915_READ(reg); |
1111 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1111 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1112 | WARN(cur_state != state, |
1112 | WARN(cur_state != state, |
1113 | "plane %c assertion failure (expected %s, current %s)\n", |
1113 | "plane %c assertion failure (expected %s, current %s)\n", |
1114 | plane_name(plane), state_string(state), state_string(cur_state)); |
1114 | plane_name(plane), state_string(state), state_string(cur_state)); |
1115 | } |
1115 | } |
1116 | 1116 | ||
1117 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1117 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1118 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1118 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1119 | 1119 | ||
1120 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1120 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1121 | enum pipe pipe) |
1121 | enum pipe pipe) |
1122 | { |
1122 | { |
1123 | struct drm_device *dev = dev_priv->dev; |
1123 | struct drm_device *dev = dev_priv->dev; |
1124 | int reg, i; |
1124 | int reg, i; |
1125 | u32 val; |
1125 | u32 val; |
1126 | int cur_pipe; |
1126 | int cur_pipe; |
1127 | 1127 | ||
1128 | /* Primary planes are fixed to pipes on gen4+ */ |
1128 | /* Primary planes are fixed to pipes on gen4+ */ |
1129 | if (INTEL_INFO(dev)->gen >= 4) { |
1129 | if (INTEL_INFO(dev)->gen >= 4) { |
1130 | reg = DSPCNTR(pipe); |
1130 | reg = DSPCNTR(pipe); |
1131 | val = I915_READ(reg); |
1131 | val = I915_READ(reg); |
1132 | WARN((val & DISPLAY_PLANE_ENABLE), |
1132 | WARN((val & DISPLAY_PLANE_ENABLE), |
1133 | "plane %c assertion failure, should be disabled but not\n", |
1133 | "plane %c assertion failure, should be disabled but not\n", |
1134 | plane_name(pipe)); |
1134 | plane_name(pipe)); |
1135 | return; |
1135 | return; |
1136 | } |
1136 | } |
1137 | 1137 | ||
1138 | /* Need to check both planes against the pipe */ |
1138 | /* Need to check both planes against the pipe */ |
1139 | for_each_pipe(i) { |
1139 | for_each_pipe(i) { |
1140 | reg = DSPCNTR(i); |
1140 | reg = DSPCNTR(i); |
1141 | val = I915_READ(reg); |
1141 | val = I915_READ(reg); |
1142 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1142 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1143 | DISPPLANE_SEL_PIPE_SHIFT; |
1143 | DISPPLANE_SEL_PIPE_SHIFT; |
1144 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1144 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1145 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1145 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1146 | plane_name(i), pipe_name(pipe)); |
1146 | plane_name(i), pipe_name(pipe)); |
1147 | } |
1147 | } |
1148 | } |
1148 | } |
1149 | 1149 | ||
1150 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1150 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1151 | enum pipe pipe) |
1151 | enum pipe pipe) |
1152 | { |
1152 | { |
1153 | struct drm_device *dev = dev_priv->dev; |
1153 | struct drm_device *dev = dev_priv->dev; |
1154 | int reg, i; |
1154 | int reg, i; |
1155 | u32 val; |
1155 | u32 val; |
1156 | 1156 | ||
1157 | if (IS_VALLEYVIEW(dev)) { |
1157 | if (IS_VALLEYVIEW(dev)) { |
1158 | for (i = 0; i < dev_priv->num_plane; i++) { |
1158 | for (i = 0; i < dev_priv->num_plane; i++) { |
1159 | reg = SPCNTR(pipe, i); |
1159 | reg = SPCNTR(pipe, i); |
1160 | val = I915_READ(reg); |
1160 | val = I915_READ(reg); |
1161 | WARN((val & SP_ENABLE), |
1161 | WARN((val & SP_ENABLE), |
1162 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1162 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1163 | sprite_name(pipe, i), pipe_name(pipe)); |
1163 | sprite_name(pipe, i), pipe_name(pipe)); |
1164 | } |
1164 | } |
1165 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1165 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1166 | reg = SPRCTL(pipe); |
1166 | reg = SPRCTL(pipe); |
1167 | val = I915_READ(reg); |
1167 | val = I915_READ(reg); |
1168 | WARN((val & SPRITE_ENABLE), |
1168 | WARN((val & SPRITE_ENABLE), |
1169 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1169 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1170 | plane_name(pipe), pipe_name(pipe)); |
1170 | plane_name(pipe), pipe_name(pipe)); |
1171 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1171 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1172 | reg = DVSCNTR(pipe); |
1172 | reg = DVSCNTR(pipe); |
1173 | val = I915_READ(reg); |
1173 | val = I915_READ(reg); |
1174 | WARN((val & DVS_ENABLE), |
1174 | WARN((val & DVS_ENABLE), |
1175 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1175 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1176 | plane_name(pipe), pipe_name(pipe)); |
1176 | plane_name(pipe), pipe_name(pipe)); |
1177 | } |
1177 | } |
1178 | } |
1178 | } |
1179 | 1179 | ||
1180 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1180 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1181 | { |
1181 | { |
1182 | u32 val; |
1182 | u32 val; |
1183 | bool enabled; |
1183 | bool enabled; |
1184 | 1184 | ||
1185 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1185 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1186 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
1186 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); |
1187 | return; |
1187 | return; |
1188 | } |
1188 | } |
1189 | 1189 | ||
1190 | val = I915_READ(PCH_DREF_CONTROL); |
1190 | val = I915_READ(PCH_DREF_CONTROL); |
1191 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1191 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1192 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1192 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1193 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1193 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
1194 | } |
1194 | } |
1195 | 1195 | ||
1196 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1196 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1197 | enum pipe pipe) |
1197 | enum pipe pipe) |
1198 | { |
1198 | { |
1199 | int reg; |
1199 | int reg; |
1200 | u32 val; |
1200 | u32 val; |
1201 | bool enabled; |
1201 | bool enabled; |
1202 | 1202 | ||
1203 | reg = PCH_TRANSCONF(pipe); |
1203 | reg = PCH_TRANSCONF(pipe); |
1204 | val = I915_READ(reg); |
1204 | val = I915_READ(reg); |
1205 | enabled = !!(val & TRANS_ENABLE); |
1205 | enabled = !!(val & TRANS_ENABLE); |
1206 | WARN(enabled, |
1206 | WARN(enabled, |
1207 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1207 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1208 | pipe_name(pipe)); |
1208 | pipe_name(pipe)); |
1209 | } |
1209 | } |
1210 | 1210 | ||
1211 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1211 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1212 | enum pipe pipe, u32 port_sel, u32 val) |
1212 | enum pipe pipe, u32 port_sel, u32 val) |
1213 | { |
1213 | { |
1214 | if ((val & DP_PORT_EN) == 0) |
1214 | if ((val & DP_PORT_EN) == 0) |
1215 | return false; |
1215 | return false; |
1216 | 1216 | ||
1217 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1217 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1218 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1218 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1219 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1219 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1220 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1220 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1221 | return false; |
1221 | return false; |
1222 | } else { |
1222 | } else { |
1223 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1223 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1224 | return false; |
1224 | return false; |
1225 | } |
1225 | } |
1226 | return true; |
1226 | return true; |
1227 | } |
1227 | } |
1228 | 1228 | ||
1229 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1229 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1230 | enum pipe pipe, u32 val) |
1230 | enum pipe pipe, u32 val) |
1231 | { |
1231 | { |
1232 | if ((val & SDVO_ENABLE) == 0) |
1232 | if ((val & SDVO_ENABLE) == 0) |
1233 | return false; |
1233 | return false; |
1234 | 1234 | ||
1235 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1235 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1236 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1236 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1237 | return false; |
1237 | return false; |
1238 | } else { |
1238 | } else { |
1239 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1239 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1240 | return false; |
1240 | return false; |
1241 | } |
1241 | } |
1242 | return true; |
1242 | return true; |
1243 | } |
1243 | } |
1244 | 1244 | ||
1245 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1245 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe, u32 val) |
1246 | enum pipe pipe, u32 val) |
1247 | { |
1247 | { |
1248 | if ((val & LVDS_PORT_EN) == 0) |
1248 | if ((val & LVDS_PORT_EN) == 0) |
1249 | return false; |
1249 | return false; |
1250 | 1250 | ||
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1252 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1252 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1253 | return false; |
1253 | return false; |
1254 | } else { |
1254 | } else { |
1255 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1255 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1256 | return false; |
1256 | return false; |
1257 | } |
1257 | } |
1258 | return true; |
1258 | return true; |
1259 | } |
1259 | } |
1260 | 1260 | ||
1261 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1261 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1262 | enum pipe pipe, u32 val) |
1262 | enum pipe pipe, u32 val) |
1263 | { |
1263 | { |
1264 | if ((val & ADPA_DAC_ENABLE) == 0) |
1264 | if ((val & ADPA_DAC_ENABLE) == 0) |
1265 | return false; |
1265 | return false; |
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1267 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1267 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1268 | return false; |
1268 | return false; |
1269 | } else { |
1269 | } else { |
1270 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1270 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1271 | return false; |
1271 | return false; |
1272 | } |
1272 | } |
1273 | return true; |
1273 | return true; |
1274 | } |
1274 | } |
1275 | 1275 | ||
1276 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1276 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1277 | enum pipe pipe, int reg, u32 port_sel) |
1277 | enum pipe pipe, int reg, u32 port_sel) |
1278 | { |
1278 | { |
1279 | u32 val = I915_READ(reg); |
1279 | u32 val = I915_READ(reg); |
1280 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1280 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1281 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1281 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1282 | reg, pipe_name(pipe)); |
1282 | reg, pipe_name(pipe)); |
1283 | 1283 | ||
1284 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1284 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1285 | && (val & DP_PIPEB_SELECT), |
1285 | && (val & DP_PIPEB_SELECT), |
1286 | "IBX PCH dp port still using transcoder B\n"); |
1286 | "IBX PCH dp port still using transcoder B\n"); |
1287 | } |
1287 | } |
1288 | 1288 | ||
1289 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1289 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1290 | enum pipe pipe, int reg) |
1290 | enum pipe pipe, int reg) |
1291 | { |
1291 | { |
1292 | u32 val = I915_READ(reg); |
1292 | u32 val = I915_READ(reg); |
1293 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1293 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1294 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1294 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1295 | reg, pipe_name(pipe)); |
1295 | reg, pipe_name(pipe)); |
1296 | 1296 | ||
1297 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
1297 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
1298 | && (val & SDVO_PIPE_B_SELECT), |
1298 | && (val & SDVO_PIPE_B_SELECT), |
1299 | "IBX PCH hdmi port still using transcoder B\n"); |
1299 | "IBX PCH hdmi port still using transcoder B\n"); |
1300 | } |
1300 | } |
1301 | 1301 | ||
1302 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1302 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1303 | enum pipe pipe) |
1303 | enum pipe pipe) |
1304 | { |
1304 | { |
1305 | int reg; |
1305 | int reg; |
1306 | u32 val; |
1306 | u32 val; |
1307 | 1307 | ||
1308 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1308 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1309 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1309 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1310 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1310 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1311 | 1311 | ||
1312 | reg = PCH_ADPA; |
1312 | reg = PCH_ADPA; |
1313 | val = I915_READ(reg); |
1313 | val = I915_READ(reg); |
1314 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1314 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1315 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1315 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
1316 | pipe_name(pipe)); |
1316 | pipe_name(pipe)); |
1317 | 1317 | ||
1318 | reg = PCH_LVDS; |
1318 | reg = PCH_LVDS; |
1319 | val = I915_READ(reg); |
1319 | val = I915_READ(reg); |
1320 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1320 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1321 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1321 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
1322 | pipe_name(pipe)); |
1322 | pipe_name(pipe)); |
1323 | 1323 | ||
1324 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1324 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1325 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1325 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1326 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1326 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1327 | } |
1327 | } |
1328 | 1328 | ||
1329 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1329 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1330 | { |
1330 | { |
1331 | struct drm_device *dev = crtc->base.dev; |
1331 | struct drm_device *dev = crtc->base.dev; |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
1333 | int reg = DPLL(crtc->pipe); |
1333 | int reg = DPLL(crtc->pipe); |
1334 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1334 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1335 | 1335 | ||
1336 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1336 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1337 | 1337 | ||
1338 | /* No really, not for ILK+ */ |
1338 | /* No really, not for ILK+ */ |
1339 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1339 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1340 | 1340 | ||
1341 | /* PLL is protected by panel, make sure we can write it */ |
1341 | /* PLL is protected by panel, make sure we can write it */ |
1342 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1342 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1343 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1343 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1344 | 1344 | ||
1345 | I915_WRITE(reg, dpll); |
1345 | I915_WRITE(reg, dpll); |
1346 | POSTING_READ(reg); |
1346 | POSTING_READ(reg); |
1347 | udelay(150); |
1347 | udelay(150); |
1348 | 1348 | ||
1349 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1349 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1350 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
1350 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
1351 | 1351 | ||
1352 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
1352 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
1353 | POSTING_READ(DPLL_MD(crtc->pipe)); |
1353 | POSTING_READ(DPLL_MD(crtc->pipe)); |
1354 | 1354 | ||
1355 | /* We do this three times for luck */ |
1355 | /* We do this three times for luck */ |
1356 | I915_WRITE(reg, dpll); |
1356 | I915_WRITE(reg, dpll); |
1357 | POSTING_READ(reg); |
1357 | POSTING_READ(reg); |
1358 | udelay(150); /* wait for warmup */ |
1358 | udelay(150); /* wait for warmup */ |
1359 | I915_WRITE(reg, dpll); |
1359 | I915_WRITE(reg, dpll); |
1360 | POSTING_READ(reg); |
1360 | POSTING_READ(reg); |
1361 | udelay(150); /* wait for warmup */ |
1361 | udelay(150); /* wait for warmup */ |
1362 | I915_WRITE(reg, dpll); |
1362 | I915_WRITE(reg, dpll); |
1363 | POSTING_READ(reg); |
1363 | POSTING_READ(reg); |
1364 | udelay(150); /* wait for warmup */ |
1364 | udelay(150); /* wait for warmup */ |
1365 | } |
1365 | } |
1366 | 1366 | ||
1367 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1367 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1368 | { |
1368 | { |
1369 | struct drm_device *dev = crtc->base.dev; |
1369 | struct drm_device *dev = crtc->base.dev; |
1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
1371 | int reg = DPLL(crtc->pipe); |
1371 | int reg = DPLL(crtc->pipe); |
1372 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1372 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1373 | 1373 | ||
1374 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1374 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1375 | 1375 | ||
1376 | /* No really, not for ILK+ */ |
1376 | /* No really, not for ILK+ */ |
1377 | BUG_ON(dev_priv->info->gen >= 5); |
1377 | BUG_ON(dev_priv->info->gen >= 5); |
1378 | 1378 | ||
1379 | /* PLL is protected by panel, make sure we can write it */ |
1379 | /* PLL is protected by panel, make sure we can write it */ |
1380 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1380 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1381 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1381 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1382 | 1382 | ||
1383 | I915_WRITE(reg, dpll); |
1383 | I915_WRITE(reg, dpll); |
1384 | 1384 | ||
1385 | /* Wait for the clocks to stabilize. */ |
1385 | /* Wait for the clocks to stabilize. */ |
1386 | POSTING_READ(reg); |
1386 | POSTING_READ(reg); |
1387 | udelay(150); |
1387 | udelay(150); |
1388 | 1388 | ||
1389 | if (INTEL_INFO(dev)->gen >= 4) { |
1389 | if (INTEL_INFO(dev)->gen >= 4) { |
1390 | I915_WRITE(DPLL_MD(crtc->pipe), |
1390 | I915_WRITE(DPLL_MD(crtc->pipe), |
1391 | crtc->config.dpll_hw_state.dpll_md); |
1391 | crtc->config.dpll_hw_state.dpll_md); |
1392 | } else { |
1392 | } else { |
1393 | /* The pixel multiplier can only be updated once the |
1393 | /* The pixel multiplier can only be updated once the |
1394 | * DPLL is enabled and the clocks are stable. |
1394 | * DPLL is enabled and the clocks are stable. |
1395 | * |
1395 | * |
1396 | * So write it again. |
1396 | * So write it again. |
1397 | */ |
1397 | */ |
1398 | I915_WRITE(reg, dpll); |
1398 | I915_WRITE(reg, dpll); |
1399 | } |
1399 | } |
1400 | 1400 | ||
1401 | /* We do this three times for luck */ |
1401 | /* We do this three times for luck */ |
1402 | I915_WRITE(reg, dpll); |
1402 | I915_WRITE(reg, dpll); |
1403 | POSTING_READ(reg); |
1403 | POSTING_READ(reg); |
1404 | udelay(150); /* wait for warmup */ |
1404 | udelay(150); /* wait for warmup */ |
1405 | I915_WRITE(reg, dpll); |
1405 | I915_WRITE(reg, dpll); |
1406 | POSTING_READ(reg); |
1406 | POSTING_READ(reg); |
1407 | udelay(150); /* wait for warmup */ |
1407 | udelay(150); /* wait for warmup */ |
1408 | I915_WRITE(reg, dpll); |
1408 | I915_WRITE(reg, dpll); |
1409 | POSTING_READ(reg); |
1409 | POSTING_READ(reg); |
1410 | udelay(150); /* wait for warmup */ |
1410 | udelay(150); /* wait for warmup */ |
1411 | } |
1411 | } |
1412 | 1412 | ||
1413 | /** |
1413 | /** |
1414 | * i9xx_disable_pll - disable a PLL |
1414 | * i9xx_disable_pll - disable a PLL |
1415 | * @dev_priv: i915 private structure |
1415 | * @dev_priv: i915 private structure |
1416 | * @pipe: pipe PLL to disable |
1416 | * @pipe: pipe PLL to disable |
1417 | * |
1417 | * |
1418 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1418 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1419 | * |
1419 | * |
1420 | * Note! This is for pre-ILK only. |
1420 | * Note! This is for pre-ILK only. |
1421 | */ |
1421 | */ |
1422 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1422 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1423 | { |
1423 | { |
1424 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1424 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1425 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1425 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1426 | return; |
1426 | return; |
1427 | 1427 | ||
1428 | /* Make sure the pipe isn't still relying on us */ |
1428 | /* Make sure the pipe isn't still relying on us */ |
1429 | assert_pipe_disabled(dev_priv, pipe); |
1429 | assert_pipe_disabled(dev_priv, pipe); |
1430 | 1430 | ||
1431 | I915_WRITE(DPLL(pipe), 0); |
1431 | I915_WRITE(DPLL(pipe), 0); |
1432 | POSTING_READ(DPLL(pipe)); |
1432 | POSTING_READ(DPLL(pipe)); |
1433 | } |
1433 | } |
1434 | 1434 | ||
1435 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1435 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1436 | { |
1436 | { |
1437 | u32 port_mask; |
1437 | u32 port_mask; |
1438 | 1438 | ||
1439 | if (!port) |
1439 | if (!port) |
1440 | port_mask = DPLL_PORTB_READY_MASK; |
1440 | port_mask = DPLL_PORTB_READY_MASK; |
1441 | else |
1441 | else |
1442 | port_mask = DPLL_PORTC_READY_MASK; |
1442 | port_mask = DPLL_PORTC_READY_MASK; |
1443 | 1443 | ||
1444 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1444 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1445 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
1445 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
1446 | 'B' + port, I915_READ(DPLL(0))); |
1446 | 'B' + port, I915_READ(DPLL(0))); |
1447 | } |
1447 | } |
1448 | 1448 | ||
1449 | /** |
1449 | /** |
1450 | * ironlake_enable_shared_dpll - enable PCH PLL |
1450 | * ironlake_enable_shared_dpll - enable PCH PLL |
1451 | * @dev_priv: i915 private structure |
1451 | * @dev_priv: i915 private structure |
1452 | * @pipe: pipe PLL to enable |
1452 | * @pipe: pipe PLL to enable |
1453 | * |
1453 | * |
1454 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1454 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1455 | * drives the transcoder clock. |
1455 | * drives the transcoder clock. |
1456 | */ |
1456 | */ |
1457 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
1457 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
1458 | { |
1458 | { |
1459 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1459 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1460 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1460 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1461 | 1461 | ||
1462 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1462 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1463 | BUG_ON(dev_priv->info->gen < 5); |
1463 | BUG_ON(dev_priv->info->gen < 5); |
1464 | if (WARN_ON(pll == NULL)) |
1464 | if (WARN_ON(pll == NULL)) |
1465 | return; |
1465 | return; |
1466 | 1466 | ||
1467 | if (WARN_ON(pll->refcount == 0)) |
1467 | if (WARN_ON(pll->refcount == 0)) |
1468 | return; |
1468 | return; |
1469 | 1469 | ||
1470 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1470 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1471 | pll->name, pll->active, pll->on, |
1471 | pll->name, pll->active, pll->on, |
1472 | crtc->base.base.id); |
1472 | crtc->base.base.id); |
1473 | 1473 | ||
1474 | if (pll->active++) { |
1474 | if (pll->active++) { |
1475 | WARN_ON(!pll->on); |
1475 | WARN_ON(!pll->on); |
1476 | assert_shared_dpll_enabled(dev_priv, pll); |
1476 | assert_shared_dpll_enabled(dev_priv, pll); |
1477 | return; |
1477 | return; |
1478 | } |
1478 | } |
1479 | WARN_ON(pll->on); |
1479 | WARN_ON(pll->on); |
1480 | 1480 | ||
1481 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1481 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
1482 | pll->enable(dev_priv, pll); |
1482 | pll->enable(dev_priv, pll); |
1483 | pll->on = true; |
1483 | pll->on = true; |
1484 | } |
1484 | } |
1485 | 1485 | ||
1486 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
1486 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
1487 | { |
1487 | { |
1488 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1488 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1489 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1489 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1490 | 1490 | ||
1491 | /* PCH only available on ILK+ */ |
1491 | /* PCH only available on ILK+ */ |
1492 | BUG_ON(dev_priv->info->gen < 5); |
1492 | BUG_ON(dev_priv->info->gen < 5); |
1493 | if (WARN_ON(pll == NULL)) |
1493 | if (WARN_ON(pll == NULL)) |
1494 | return; |
1494 | return; |
1495 | 1495 | ||
1496 | if (WARN_ON(pll->refcount == 0)) |
1496 | if (WARN_ON(pll->refcount == 0)) |
1497 | return; |
1497 | return; |
1498 | 1498 | ||
1499 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1499 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1500 | pll->name, pll->active, pll->on, |
1500 | pll->name, pll->active, pll->on, |
1501 | crtc->base.base.id); |
1501 | crtc->base.base.id); |
1502 | 1502 | ||
1503 | if (WARN_ON(pll->active == 0)) { |
1503 | if (WARN_ON(pll->active == 0)) { |
1504 | assert_shared_dpll_disabled(dev_priv, pll); |
1504 | assert_shared_dpll_disabled(dev_priv, pll); |
1505 | return; |
1505 | return; |
1506 | } |
1506 | } |
1507 | 1507 | ||
1508 | assert_shared_dpll_enabled(dev_priv, pll); |
1508 | assert_shared_dpll_enabled(dev_priv, pll); |
1509 | WARN_ON(!pll->on); |
1509 | WARN_ON(!pll->on); |
1510 | if (--pll->active) |
1510 | if (--pll->active) |
1511 | return; |
1511 | return; |
1512 | 1512 | ||
1513 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1513 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
1514 | pll->disable(dev_priv, pll); |
1514 | pll->disable(dev_priv, pll); |
1515 | pll->on = false; |
1515 | pll->on = false; |
1516 | } |
1516 | } |
1517 | 1517 | ||
1518 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1518 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1519 | enum pipe pipe) |
1519 | enum pipe pipe) |
1520 | { |
1520 | { |
1521 | struct drm_device *dev = dev_priv->dev; |
1521 | struct drm_device *dev = dev_priv->dev; |
1522 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1522 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1524 | uint32_t reg, val, pipeconf_val; |
1524 | uint32_t reg, val, pipeconf_val; |
1525 | 1525 | ||
1526 | /* PCH only available on ILK+ */ |
1526 | /* PCH only available on ILK+ */ |
1527 | BUG_ON(dev_priv->info->gen < 5); |
1527 | BUG_ON(dev_priv->info->gen < 5); |
1528 | 1528 | ||
1529 | /* Make sure PCH DPLL is enabled */ |
1529 | /* Make sure PCH DPLL is enabled */ |
1530 | assert_shared_dpll_enabled(dev_priv, |
1530 | assert_shared_dpll_enabled(dev_priv, |
1531 | intel_crtc_to_shared_dpll(intel_crtc)); |
1531 | intel_crtc_to_shared_dpll(intel_crtc)); |
1532 | 1532 | ||
1533 | /* FDI must be feeding us bits for PCH ports */ |
1533 | /* FDI must be feeding us bits for PCH ports */ |
1534 | assert_fdi_tx_enabled(dev_priv, pipe); |
1534 | assert_fdi_tx_enabled(dev_priv, pipe); |
1535 | assert_fdi_rx_enabled(dev_priv, pipe); |
1535 | assert_fdi_rx_enabled(dev_priv, pipe); |
1536 | 1536 | ||
1537 | if (HAS_PCH_CPT(dev)) { |
1537 | if (HAS_PCH_CPT(dev)) { |
1538 | /* Workaround: Set the timing override bit before enabling the |
1538 | /* Workaround: Set the timing override bit before enabling the |
1539 | * pch transcoder. */ |
1539 | * pch transcoder. */ |
1540 | reg = TRANS_CHICKEN2(pipe); |
1540 | reg = TRANS_CHICKEN2(pipe); |
1541 | val = I915_READ(reg); |
1541 | val = I915_READ(reg); |
1542 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1542 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1543 | I915_WRITE(reg, val); |
1543 | I915_WRITE(reg, val); |
1544 | } |
1544 | } |
1545 | 1545 | ||
1546 | reg = PCH_TRANSCONF(pipe); |
1546 | reg = PCH_TRANSCONF(pipe); |
1547 | val = I915_READ(reg); |
1547 | val = I915_READ(reg); |
1548 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1548 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1549 | 1549 | ||
1550 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1550 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1551 | /* |
1551 | /* |
1552 | * make the BPC in transcoder be consistent with |
1552 | * make the BPC in transcoder be consistent with |
1553 | * that in pipeconf reg. |
1553 | * that in pipeconf reg. |
1554 | */ |
1554 | */ |
1555 | val &= ~PIPECONF_BPC_MASK; |
1555 | val &= ~PIPECONF_BPC_MASK; |
1556 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
1556 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
1557 | } |
1557 | } |
1558 | 1558 | ||
1559 | val &= ~TRANS_INTERLACE_MASK; |
1559 | val &= ~TRANS_INTERLACE_MASK; |
1560 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1560 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1561 | if (HAS_PCH_IBX(dev_priv->dev) && |
1561 | if (HAS_PCH_IBX(dev_priv->dev) && |
1562 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1562 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1563 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1563 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1564 | else |
1564 | else |
1565 | val |= TRANS_INTERLACED; |
1565 | val |= TRANS_INTERLACED; |
1566 | else |
1566 | else |
1567 | val |= TRANS_PROGRESSIVE; |
1567 | val |= TRANS_PROGRESSIVE; |
1568 | 1568 | ||
1569 | I915_WRITE(reg, val | TRANS_ENABLE); |
1569 | I915_WRITE(reg, val | TRANS_ENABLE); |
1570 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1570 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1571 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
1571 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
1572 | } |
1572 | } |
1573 | 1573 | ||
1574 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1574 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1575 | enum transcoder cpu_transcoder) |
1575 | enum transcoder cpu_transcoder) |
1576 | { |
1576 | { |
1577 | u32 val, pipeconf_val; |
1577 | u32 val, pipeconf_val; |
1578 | 1578 | ||
1579 | /* PCH only available on ILK+ */ |
1579 | /* PCH only available on ILK+ */ |
1580 | BUG_ON(dev_priv->info->gen < 5); |
1580 | BUG_ON(dev_priv->info->gen < 5); |
1581 | 1581 | ||
1582 | /* FDI must be feeding us bits for PCH ports */ |
1582 | /* FDI must be feeding us bits for PCH ports */ |
1583 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
1583 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
1584 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1584 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1585 | 1585 | ||
1586 | /* Workaround: set timing override bit. */ |
1586 | /* Workaround: set timing override bit. */ |
1587 | val = I915_READ(_TRANSA_CHICKEN2); |
1587 | val = I915_READ(_TRANSA_CHICKEN2); |
1588 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1588 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1589 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1589 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1590 | 1590 | ||
1591 | val = TRANS_ENABLE; |
1591 | val = TRANS_ENABLE; |
1592 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1592 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1593 | 1593 | ||
1594 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1594 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1595 | PIPECONF_INTERLACED_ILK) |
1595 | PIPECONF_INTERLACED_ILK) |
1596 | val |= TRANS_INTERLACED; |
1596 | val |= TRANS_INTERLACED; |
1597 | else |
1597 | else |
1598 | val |= TRANS_PROGRESSIVE; |
1598 | val |= TRANS_PROGRESSIVE; |
1599 | 1599 | ||
1600 | I915_WRITE(LPT_TRANSCONF, val); |
1600 | I915_WRITE(LPT_TRANSCONF, val); |
1601 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
1601 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
1602 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
1602 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
1603 | } |
1603 | } |
1604 | 1604 | ||
1605 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1605 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1606 | enum pipe pipe) |
1606 | enum pipe pipe) |
1607 | { |
1607 | { |
1608 | struct drm_device *dev = dev_priv->dev; |
1608 | struct drm_device *dev = dev_priv->dev; |
1609 | uint32_t reg, val; |
1609 | uint32_t reg, val; |
1610 | 1610 | ||
1611 | /* FDI relies on the transcoder */ |
1611 | /* FDI relies on the transcoder */ |
1612 | assert_fdi_tx_disabled(dev_priv, pipe); |
1612 | assert_fdi_tx_disabled(dev_priv, pipe); |
1613 | assert_fdi_rx_disabled(dev_priv, pipe); |
1613 | assert_fdi_rx_disabled(dev_priv, pipe); |
1614 | 1614 | ||
1615 | /* Ports must be off as well */ |
1615 | /* Ports must be off as well */ |
1616 | assert_pch_ports_disabled(dev_priv, pipe); |
1616 | assert_pch_ports_disabled(dev_priv, pipe); |
1617 | 1617 | ||
1618 | reg = PCH_TRANSCONF(pipe); |
1618 | reg = PCH_TRANSCONF(pipe); |
1619 | val = I915_READ(reg); |
1619 | val = I915_READ(reg); |
1620 | val &= ~TRANS_ENABLE; |
1620 | val &= ~TRANS_ENABLE; |
1621 | I915_WRITE(reg, val); |
1621 | I915_WRITE(reg, val); |
1622 | /* wait for PCH transcoder off, transcoder state */ |
1622 | /* wait for PCH transcoder off, transcoder state */ |
1623 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1623 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1624 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
1624 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
1625 | 1625 | ||
1626 | if (!HAS_PCH_IBX(dev)) { |
1626 | if (!HAS_PCH_IBX(dev)) { |
1627 | /* Workaround: Clear the timing override chicken bit again. */ |
1627 | /* Workaround: Clear the timing override chicken bit again. */ |
1628 | reg = TRANS_CHICKEN2(pipe); |
1628 | reg = TRANS_CHICKEN2(pipe); |
1629 | val = I915_READ(reg); |
1629 | val = I915_READ(reg); |
1630 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1630 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1631 | I915_WRITE(reg, val); |
1631 | I915_WRITE(reg, val); |
1632 | } |
1632 | } |
1633 | } |
1633 | } |
1634 | 1634 | ||
1635 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1635 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1636 | { |
1636 | { |
1637 | u32 val; |
1637 | u32 val; |
1638 | 1638 | ||
1639 | val = I915_READ(LPT_TRANSCONF); |
1639 | val = I915_READ(LPT_TRANSCONF); |
1640 | val &= ~TRANS_ENABLE; |
1640 | val &= ~TRANS_ENABLE; |
1641 | I915_WRITE(LPT_TRANSCONF, val); |
1641 | I915_WRITE(LPT_TRANSCONF, val); |
1642 | /* wait for PCH transcoder off, transcoder state */ |
1642 | /* wait for PCH transcoder off, transcoder state */ |
1643 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1643 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1644 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
1644 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
1645 | 1645 | ||
1646 | /* Workaround: clear timing override bit. */ |
1646 | /* Workaround: clear timing override bit. */ |
1647 | val = I915_READ(_TRANSA_CHICKEN2); |
1647 | val = I915_READ(_TRANSA_CHICKEN2); |
1648 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1648 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1649 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1649 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1650 | } |
1650 | } |
1651 | 1651 | ||
1652 | /** |
1652 | /** |
1653 | * intel_enable_pipe - enable a pipe, asserting requirements |
1653 | * intel_enable_pipe - enable a pipe, asserting requirements |
1654 | * @dev_priv: i915 private structure |
1654 | * @dev_priv: i915 private structure |
1655 | * @pipe: pipe to enable |
1655 | * @pipe: pipe to enable |
1656 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
1656 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
1657 | * |
1657 | * |
1658 | * Enable @pipe, making sure that various hardware specific requirements |
1658 | * Enable @pipe, making sure that various hardware specific requirements |
1659 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1659 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1660 | * |
1660 | * |
1661 | * @pipe should be %PIPE_A or %PIPE_B. |
1661 | * @pipe should be %PIPE_A or %PIPE_B. |
1662 | * |
1662 | * |
1663 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1663 | * Will wait until the pipe is actually running (i.e. first vblank) before |
1664 | * returning. |
1664 | * returning. |
1665 | */ |
1665 | */ |
1666 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1666 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1667 | bool pch_port) |
1667 | bool pch_port) |
1668 | { |
1668 | { |
1669 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1669 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1670 | pipe); |
1670 | pipe); |
1671 | enum pipe pch_transcoder; |
1671 | enum pipe pch_transcoder; |
1672 | int reg; |
1672 | int reg; |
1673 | u32 val; |
1673 | u32 val; |
1674 | 1674 | ||
1675 | assert_planes_disabled(dev_priv, pipe); |
1675 | assert_planes_disabled(dev_priv, pipe); |
1676 | assert_sprites_disabled(dev_priv, pipe); |
1676 | assert_sprites_disabled(dev_priv, pipe); |
1677 | 1677 | ||
1678 | if (HAS_PCH_LPT(dev_priv->dev)) |
1678 | if (HAS_PCH_LPT(dev_priv->dev)) |
1679 | pch_transcoder = TRANSCODER_A; |
1679 | pch_transcoder = TRANSCODER_A; |
1680 | else |
1680 | else |
1681 | pch_transcoder = pipe; |
1681 | pch_transcoder = pipe; |
1682 | 1682 | ||
1683 | /* |
1683 | /* |
1684 | * A pipe without a PLL won't actually be able to drive bits from |
1684 | * A pipe without a PLL won't actually be able to drive bits from |
1685 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1685 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1686 | * need the check. |
1686 | * need the check. |
1687 | */ |
1687 | */ |
1688 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1688 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1689 | assert_pll_enabled(dev_priv, pipe); |
1689 | assert_pll_enabled(dev_priv, pipe); |
1690 | else { |
1690 | else { |
1691 | if (pch_port) { |
1691 | if (pch_port) { |
1692 | /* if driving the PCH, we need FDI enabled */ |
1692 | /* if driving the PCH, we need FDI enabled */ |
1693 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1693 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1694 | assert_fdi_tx_pll_enabled(dev_priv, |
1694 | assert_fdi_tx_pll_enabled(dev_priv, |
1695 | (enum pipe) cpu_transcoder); |
1695 | (enum pipe) cpu_transcoder); |
1696 | } |
1696 | } |
1697 | /* FIXME: assert CPU port conditions for SNB+ */ |
1697 | /* FIXME: assert CPU port conditions for SNB+ */ |
1698 | } |
1698 | } |
1699 | 1699 | ||
1700 | reg = PIPECONF(cpu_transcoder); |
1700 | reg = PIPECONF(cpu_transcoder); |
1701 | val = I915_READ(reg); |
1701 | val = I915_READ(reg); |
1702 | if (val & PIPECONF_ENABLE) |
1702 | if (val & PIPECONF_ENABLE) |
1703 | return; |
1703 | return; |
1704 | 1704 | ||
1705 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1705 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1706 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1706 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1707 | } |
1707 | } |
1708 | 1708 | ||
1709 | /** |
1709 | /** |
1710 | * intel_disable_pipe - disable a pipe, asserting requirements |
1710 | * intel_disable_pipe - disable a pipe, asserting requirements |
1711 | * @dev_priv: i915 private structure |
1711 | * @dev_priv: i915 private structure |
1712 | * @pipe: pipe to disable |
1712 | * @pipe: pipe to disable |
1713 | * |
1713 | * |
1714 | * Disable @pipe, making sure that various hardware specific requirements |
1714 | * Disable @pipe, making sure that various hardware specific requirements |
1715 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1715 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1716 | * |
1716 | * |
1717 | * @pipe should be %PIPE_A or %PIPE_B. |
1717 | * @pipe should be %PIPE_A or %PIPE_B. |
1718 | * |
1718 | * |
1719 | * Will wait until the pipe has shut down before returning. |
1719 | * Will wait until the pipe has shut down before returning. |
1720 | */ |
1720 | */ |
1721 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1721 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1722 | enum pipe pipe) |
1722 | enum pipe pipe) |
1723 | { |
1723 | { |
1724 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1724 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1725 | pipe); |
1725 | pipe); |
1726 | int reg; |
1726 | int reg; |
1727 | u32 val; |
1727 | u32 val; |
1728 | 1728 | ||
1729 | /* |
1729 | /* |
1730 | * Make sure planes won't keep trying to pump pixels to us, |
1730 | * Make sure planes won't keep trying to pump pixels to us, |
1731 | * or we might hang the display. |
1731 | * or we might hang the display. |
1732 | */ |
1732 | */ |
1733 | assert_planes_disabled(dev_priv, pipe); |
1733 | assert_planes_disabled(dev_priv, pipe); |
1734 | assert_sprites_disabled(dev_priv, pipe); |
1734 | assert_sprites_disabled(dev_priv, pipe); |
1735 | 1735 | ||
1736 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1736 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1737 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1737 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1738 | return; |
1738 | return; |
1739 | 1739 | ||
1740 | reg = PIPECONF(cpu_transcoder); |
1740 | reg = PIPECONF(cpu_transcoder); |
1741 | val = I915_READ(reg); |
1741 | val = I915_READ(reg); |
1742 | if ((val & PIPECONF_ENABLE) == 0) |
1742 | if ((val & PIPECONF_ENABLE) == 0) |
1743 | return; |
1743 | return; |
1744 | 1744 | ||
1745 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1745 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1746 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1746 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1747 | } |
1747 | } |
1748 | 1748 | ||
1749 | /* |
1749 | /* |
1750 | * Plane regs are double buffered, going from enabled->disabled needs a |
1750 | * Plane regs are double buffered, going from enabled->disabled needs a |
1751 | * trigger in order to latch. The display address reg provides this. |
1751 | * trigger in order to latch. The display address reg provides this. |
1752 | */ |
1752 | */ |
1753 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
1753 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
1754 | enum plane plane) |
1754 | enum plane plane) |
1755 | { |
1755 | { |
1756 | if (dev_priv->info->gen >= 4) |
1756 | if (dev_priv->info->gen >= 4) |
1757 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
1757 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
1758 | else |
1758 | else |
1759 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1759 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
1760 | } |
1760 | } |
1761 | 1761 | ||
1762 | /** |
1762 | /** |
1763 | * intel_enable_plane - enable a display plane on a given pipe |
1763 | * intel_enable_plane - enable a display plane on a given pipe |
1764 | * @dev_priv: i915 private structure |
1764 | * @dev_priv: i915 private structure |
1765 | * @plane: plane to enable |
1765 | * @plane: plane to enable |
1766 | * @pipe: pipe being fed |
1766 | * @pipe: pipe being fed |
1767 | * |
1767 | * |
1768 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1768 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1769 | */ |
1769 | */ |
1770 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
1770 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
1771 | enum plane plane, enum pipe pipe) |
1771 | enum plane plane, enum pipe pipe) |
1772 | { |
1772 | { |
1773 | int reg; |
1773 | int reg; |
1774 | u32 val; |
1774 | u32 val; |
1775 | 1775 | ||
1776 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1776 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1777 | assert_pipe_enabled(dev_priv, pipe); |
1777 | assert_pipe_enabled(dev_priv, pipe); |
1778 | 1778 | ||
1779 | reg = DSPCNTR(plane); |
1779 | reg = DSPCNTR(plane); |
1780 | val = I915_READ(reg); |
1780 | val = I915_READ(reg); |
1781 | if (val & DISPLAY_PLANE_ENABLE) |
1781 | if (val & DISPLAY_PLANE_ENABLE) |
1782 | return; |
1782 | return; |
1783 | 1783 | ||
1784 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1784 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1785 | intel_flush_display_plane(dev_priv, plane); |
1785 | intel_flush_display_plane(dev_priv, plane); |
1786 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1786 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1787 | } |
1787 | } |
1788 | 1788 | ||
1789 | /** |
1789 | /** |
1790 | * intel_disable_plane - disable a display plane |
1790 | * intel_disable_plane - disable a display plane |
1791 | * @dev_priv: i915 private structure |
1791 | * @dev_priv: i915 private structure |
1792 | * @plane: plane to disable |
1792 | * @plane: plane to disable |
1793 | * @pipe: pipe consuming the data |
1793 | * @pipe: pipe consuming the data |
1794 | * |
1794 | * |
1795 | * Disable @plane; should be an independent operation. |
1795 | * Disable @plane; should be an independent operation. |
1796 | */ |
1796 | */ |
1797 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
1797 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
1798 | enum plane plane, enum pipe pipe) |
1798 | enum plane plane, enum pipe pipe) |
1799 | { |
1799 | { |
1800 | int reg; |
1800 | int reg; |
1801 | u32 val; |
1801 | u32 val; |
1802 | 1802 | ||
1803 | reg = DSPCNTR(plane); |
1803 | reg = DSPCNTR(plane); |
1804 | val = I915_READ(reg); |
1804 | val = I915_READ(reg); |
1805 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1805 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1806 | return; |
1806 | return; |
1807 | 1807 | ||
1808 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1808 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1809 | intel_flush_display_plane(dev_priv, plane); |
1809 | intel_flush_display_plane(dev_priv, plane); |
1810 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1810 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1811 | } |
1811 | } |
1812 | 1812 | ||
1813 | static bool need_vtd_wa(struct drm_device *dev) |
1813 | static bool need_vtd_wa(struct drm_device *dev) |
1814 | { |
1814 | { |
1815 | #ifdef CONFIG_INTEL_IOMMU |
1815 | #ifdef CONFIG_INTEL_IOMMU |
1816 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
1816 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
1817 | return true; |
1817 | return true; |
1818 | #endif |
1818 | #endif |
1819 | return false; |
1819 | return false; |
1820 | } |
1820 | } |
1821 | 1821 | ||
1822 | int |
1822 | int |
1823 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1823 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1824 | struct drm_i915_gem_object *obj, |
1824 | struct drm_i915_gem_object *obj, |
1825 | struct intel_ring_buffer *pipelined) |
1825 | struct intel_ring_buffer *pipelined) |
1826 | { |
1826 | { |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
1828 | u32 alignment; |
1828 | u32 alignment; |
1829 | int ret; |
1829 | int ret; |
- | 1830 | ||
- | 1831 | ENTER(); |
|
1830 | 1832 | ||
1831 | switch (obj->tiling_mode) { |
1833 | switch (obj->tiling_mode) { |
1832 | case I915_TILING_NONE: |
1834 | case I915_TILING_NONE: |
1833 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1835 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1834 | alignment = 128 * 1024; |
1836 | alignment = 128 * 1024; |
1835 | else if (INTEL_INFO(dev)->gen >= 4) |
1837 | else if (INTEL_INFO(dev)->gen >= 4) |
1836 | alignment = 4 * 1024; |
1838 | alignment = 4 * 1024; |
1837 | else |
1839 | else |
1838 | alignment = 64 * 1024; |
1840 | alignment = 64 * 1024; |
1839 | break; |
1841 | break; |
1840 | case I915_TILING_X: |
1842 | case I915_TILING_X: |
1841 | /* pin() will align the object as required by fence */ |
1843 | /* pin() will align the object as required by fence */ |
1842 | alignment = 0; |
1844 | alignment = 0; |
1843 | break; |
1845 | break; |
1844 | case I915_TILING_Y: |
1846 | case I915_TILING_Y: |
1845 | /* Despite that we check this in framebuffer_init userspace can |
1847 | /* Despite that we check this in framebuffer_init userspace can |
1846 | * screw us over and change the tiling after the fact. Only |
1848 | * screw us over and change the tiling after the fact. Only |
1847 | * pinned buffers can't change their tiling. */ |
1849 | * pinned buffers can't change their tiling. */ |
1848 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); |
1850 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); |
1849 | return -EINVAL; |
1851 | return -EINVAL; |
1850 | default: |
1852 | default: |
1851 | BUG(); |
1853 | BUG(); |
1852 | } |
1854 | } |
1853 | 1855 | ||
1854 | /* Note that the w/a also requires 64 PTE of padding following the |
1856 | /* Note that the w/a also requires 64 PTE of padding following the |
1855 | * bo. We currently fill all unused PTE with the shadow page and so |
1857 | * bo. We currently fill all unused PTE with the shadow page and so |
1856 | * we should always have valid PTE following the scanout preventing |
1858 | * we should always have valid PTE following the scanout preventing |
1857 | * the VT-d warning. |
1859 | * the VT-d warning. |
1858 | */ |
1860 | */ |
1859 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
1861 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
1860 | alignment = 256 * 1024; |
1862 | alignment = 256 * 1024; |
1861 | 1863 | ||
1862 | dev_priv->mm.interruptible = false; |
1864 | dev_priv->mm.interruptible = false; |
1863 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
1865 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
1864 | if (ret) |
1866 | if (ret) |
1865 | goto err_interruptible; |
1867 | goto err_interruptible; |
1866 | 1868 | ||
1867 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1869 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1868 | * fence, whereas 965+ only requires a fence if using |
1870 | * fence, whereas 965+ only requires a fence if using |
1869 | * framebuffer compression. For simplicity, we always install |
1871 | * framebuffer compression. For simplicity, we always install |
1870 | * a fence as the cost is not that onerous. |
1872 | * a fence as the cost is not that onerous. |
1871 | */ |
1873 | */ |
1872 | ret = i915_gem_object_get_fence(obj); |
1874 | ret = i915_gem_object_get_fence(obj); |
1873 | if (ret) |
1875 | if (ret) |
1874 | goto err_unpin; |
1876 | goto err_unpin; |
1875 | 1877 | ||
1876 | i915_gem_object_pin_fence(obj); |
1878 | i915_gem_object_pin_fence(obj); |
1877 | 1879 | ||
1878 | dev_priv->mm.interruptible = true; |
1880 | dev_priv->mm.interruptible = true; |
- | 1881 | ||
- | 1882 | LEAVE(); |
|
- | 1883 | ||
1879 | return 0; |
1884 | return 0; |
1880 | 1885 | ||
1881 | err_unpin: |
1886 | err_unpin: |
1882 | i915_gem_object_unpin_from_display_plane(obj); |
1887 | i915_gem_object_unpin_from_display_plane(obj); |
1883 | err_interruptible: |
1888 | err_interruptible: |
1884 | dev_priv->mm.interruptible = true; |
1889 | dev_priv->mm.interruptible = true; |
1885 | return ret; |
1890 | return ret; |
1886 | } |
1891 | } |
1887 | 1892 | ||
1888 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1893 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1889 | { |
1894 | { |
1890 | // i915_gem_object_unpin_fence(obj); |
1895 | // i915_gem_object_unpin_fence(obj); |
1891 | // i915_gem_object_unpin(obj); |
1896 | // i915_gem_object_unpin(obj); |
1892 | } |
1897 | } |
1893 | 1898 | ||
1894 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1899 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1895 | * is assumed to be a power-of-two. */ |
1900 | * is assumed to be a power-of-two. */ |
1896 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1901 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1897 | unsigned int tiling_mode, |
1902 | unsigned int tiling_mode, |
1898 | unsigned int cpp, |
1903 | unsigned int cpp, |
1899 | unsigned int pitch) |
1904 | unsigned int pitch) |
1900 | { |
1905 | { |
1901 | if (tiling_mode != I915_TILING_NONE) { |
1906 | if (tiling_mode != I915_TILING_NONE) { |
1902 | unsigned int tile_rows, tiles; |
1907 | unsigned int tile_rows, tiles; |
1903 | 1908 | ||
1904 | tile_rows = *y / 8; |
1909 | tile_rows = *y / 8; |
1905 | *y %= 8; |
1910 | *y %= 8; |
1906 | 1911 | ||
1907 | tiles = *x / (512/cpp); |
1912 | tiles = *x / (512/cpp); |
1908 | *x %= 512/cpp; |
1913 | *x %= 512/cpp; |
1909 | 1914 | ||
1910 | return tile_rows * pitch * 8 + tiles * 4096; |
1915 | return tile_rows * pitch * 8 + tiles * 4096; |
1911 | } else { |
1916 | } else { |
1912 | unsigned int offset; |
1917 | unsigned int offset; |
1913 | 1918 | ||
1914 | offset = *y * pitch + *x * cpp; |
1919 | offset = *y * pitch + *x * cpp; |
1915 | *y = 0; |
1920 | *y = 0; |
1916 | *x = (offset & 4095) / cpp; |
1921 | *x = (offset & 4095) / cpp; |
1917 | return offset & -4096; |
1922 | return offset & -4096; |
1918 | } |
1923 | } |
1919 | } |
1924 | } |
1920 | 1925 | ||
1921 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1926 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1922 | int x, int y) |
1927 | int x, int y) |
1923 | { |
1928 | { |
1924 | struct drm_device *dev = crtc->dev; |
1929 | struct drm_device *dev = crtc->dev; |
1925 | struct drm_i915_private *dev_priv = dev->dev_private; |
1930 | struct drm_i915_private *dev_priv = dev->dev_private; |
1926 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1931 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1927 | struct intel_framebuffer *intel_fb; |
1932 | struct intel_framebuffer *intel_fb; |
1928 | struct drm_i915_gem_object *obj; |
1933 | struct drm_i915_gem_object *obj; |
1929 | int plane = intel_crtc->plane; |
1934 | int plane = intel_crtc->plane; |
1930 | unsigned long linear_offset; |
1935 | unsigned long linear_offset; |
1931 | u32 dspcntr; |
1936 | u32 dspcntr; |
1932 | u32 reg; |
1937 | u32 reg; |
1933 | 1938 | ||
1934 | switch (plane) { |
1939 | switch (plane) { |
1935 | case 0: |
1940 | case 0: |
1936 | case 1: |
1941 | case 1: |
1937 | break; |
1942 | break; |
1938 | default: |
1943 | default: |
1939 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
1944 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
1940 | return -EINVAL; |
1945 | return -EINVAL; |
1941 | } |
1946 | } |
1942 | 1947 | ||
1943 | intel_fb = to_intel_framebuffer(fb); |
1948 | intel_fb = to_intel_framebuffer(fb); |
1944 | obj = intel_fb->obj; |
1949 | obj = intel_fb->obj; |
1945 | 1950 | ||
1946 | reg = DSPCNTR(plane); |
1951 | reg = DSPCNTR(plane); |
1947 | dspcntr = I915_READ(reg); |
1952 | dspcntr = I915_READ(reg); |
1948 | /* Mask out pixel format bits in case we change it */ |
1953 | /* Mask out pixel format bits in case we change it */ |
1949 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
1954 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
1950 | switch (fb->pixel_format) { |
1955 | switch (fb->pixel_format) { |
1951 | case DRM_FORMAT_C8: |
1956 | case DRM_FORMAT_C8: |
1952 | dspcntr |= DISPPLANE_8BPP; |
1957 | dspcntr |= DISPPLANE_8BPP; |
1953 | break; |
1958 | break; |
1954 | case DRM_FORMAT_XRGB1555: |
1959 | case DRM_FORMAT_XRGB1555: |
1955 | case DRM_FORMAT_ARGB1555: |
1960 | case DRM_FORMAT_ARGB1555: |
1956 | dspcntr |= DISPPLANE_BGRX555; |
1961 | dspcntr |= DISPPLANE_BGRX555; |
1957 | break; |
1962 | break; |
1958 | case DRM_FORMAT_RGB565: |
1963 | case DRM_FORMAT_RGB565: |
1959 | dspcntr |= DISPPLANE_BGRX565; |
1964 | dspcntr |= DISPPLANE_BGRX565; |
1960 | break; |
1965 | break; |
1961 | case DRM_FORMAT_XRGB8888: |
1966 | case DRM_FORMAT_XRGB8888: |
1962 | case DRM_FORMAT_ARGB8888: |
1967 | case DRM_FORMAT_ARGB8888: |
1963 | dspcntr |= DISPPLANE_BGRX888; |
1968 | dspcntr |= DISPPLANE_BGRX888; |
1964 | break; |
1969 | break; |
1965 | case DRM_FORMAT_XBGR8888: |
1970 | case DRM_FORMAT_XBGR8888: |
1966 | case DRM_FORMAT_ABGR8888: |
1971 | case DRM_FORMAT_ABGR8888: |
1967 | dspcntr |= DISPPLANE_RGBX888; |
1972 | dspcntr |= DISPPLANE_RGBX888; |
1968 | break; |
1973 | break; |
1969 | case DRM_FORMAT_XRGB2101010: |
1974 | case DRM_FORMAT_XRGB2101010: |
1970 | case DRM_FORMAT_ARGB2101010: |
1975 | case DRM_FORMAT_ARGB2101010: |
1971 | dspcntr |= DISPPLANE_BGRX101010; |
1976 | dspcntr |= DISPPLANE_BGRX101010; |
1972 | break; |
1977 | break; |
1973 | case DRM_FORMAT_XBGR2101010: |
1978 | case DRM_FORMAT_XBGR2101010: |
1974 | case DRM_FORMAT_ABGR2101010: |
1979 | case DRM_FORMAT_ABGR2101010: |
1975 | dspcntr |= DISPPLANE_RGBX101010; |
1980 | dspcntr |= DISPPLANE_RGBX101010; |
1976 | break; |
1981 | break; |
1977 | default: |
1982 | default: |
1978 | BUG(); |
1983 | BUG(); |
1979 | } |
1984 | } |
1980 | 1985 | ||
1981 | if (INTEL_INFO(dev)->gen >= 4) { |
1986 | if (INTEL_INFO(dev)->gen >= 4) { |
1982 | if (obj->tiling_mode != I915_TILING_NONE) |
1987 | if (obj->tiling_mode != I915_TILING_NONE) |
1983 | dspcntr |= DISPPLANE_TILED; |
1988 | dspcntr |= DISPPLANE_TILED; |
1984 | else |
1989 | else |
1985 | dspcntr &= ~DISPPLANE_TILED; |
1990 | dspcntr &= ~DISPPLANE_TILED; |
1986 | } |
1991 | } |
1987 | 1992 | ||
1988 | if (IS_G4X(dev)) |
1993 | if (IS_G4X(dev)) |
1989 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
1994 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
1990 | 1995 | ||
1991 | I915_WRITE(reg, dspcntr); |
1996 | I915_WRITE(reg, dspcntr); |
1992 | 1997 | ||
1993 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
1998 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
1994 | 1999 | ||
1995 | if (INTEL_INFO(dev)->gen >= 4) { |
2000 | if (INTEL_INFO(dev)->gen >= 4) { |
1996 | intel_crtc->dspaddr_offset = |
2001 | intel_crtc->dspaddr_offset = |
1997 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2002 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
1998 | fb->bits_per_pixel / 8, |
2003 | fb->bits_per_pixel / 8, |
1999 | fb->pitches[0]); |
2004 | fb->pitches[0]); |
2000 | linear_offset -= intel_crtc->dspaddr_offset; |
2005 | linear_offset -= intel_crtc->dspaddr_offset; |
2001 | } else { |
2006 | } else { |
2002 | intel_crtc->dspaddr_offset = linear_offset; |
2007 | intel_crtc->dspaddr_offset = linear_offset; |
2003 | } |
2008 | } |
2004 | 2009 | ||
2005 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2010 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2006 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2011 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2007 | fb->pitches[0]); |
2012 | fb->pitches[0]); |
2008 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2013 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2009 | if (INTEL_INFO(dev)->gen >= 4) { |
2014 | if (INTEL_INFO(dev)->gen >= 4) { |
2010 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2015 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2011 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2016 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2012 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2017 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2013 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2018 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2014 | } else |
2019 | } else |
2015 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2020 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2016 | POSTING_READ(reg); |
2021 | POSTING_READ(reg); |
2017 | 2022 | ||
2018 | return 0; |
2023 | return 0; |
2019 | } |
2024 | } |
2020 | 2025 | ||
2021 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2026 | static int ironlake_update_plane(struct drm_crtc *crtc, |
2022 | struct drm_framebuffer *fb, int x, int y) |
2027 | struct drm_framebuffer *fb, int x, int y) |
2023 | { |
2028 | { |
2024 | struct drm_device *dev = crtc->dev; |
2029 | struct drm_device *dev = crtc->dev; |
2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
2030 | struct drm_i915_private *dev_priv = dev->dev_private; |
2026 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2027 | struct intel_framebuffer *intel_fb; |
2032 | struct intel_framebuffer *intel_fb; |
2028 | struct drm_i915_gem_object *obj; |
2033 | struct drm_i915_gem_object *obj; |
2029 | int plane = intel_crtc->plane; |
2034 | int plane = intel_crtc->plane; |
2030 | unsigned long linear_offset; |
2035 | unsigned long linear_offset; |
2031 | u32 dspcntr; |
2036 | u32 dspcntr; |
2032 | u32 reg; |
2037 | u32 reg; |
2033 | 2038 | ||
2034 | switch (plane) { |
2039 | switch (plane) { |
2035 | case 0: |
2040 | case 0: |
2036 | case 1: |
2041 | case 1: |
2037 | case 2: |
2042 | case 2: |
2038 | break; |
2043 | break; |
2039 | default: |
2044 | default: |
2040 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
2045 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
2041 | return -EINVAL; |
2046 | return -EINVAL; |
2042 | } |
2047 | } |
2043 | 2048 | ||
2044 | intel_fb = to_intel_framebuffer(fb); |
2049 | intel_fb = to_intel_framebuffer(fb); |
2045 | obj = intel_fb->obj; |
2050 | obj = intel_fb->obj; |
2046 | 2051 | ||
2047 | reg = DSPCNTR(plane); |
2052 | reg = DSPCNTR(plane); |
2048 | dspcntr = I915_READ(reg); |
2053 | dspcntr = I915_READ(reg); |
2049 | /* Mask out pixel format bits in case we change it */ |
2054 | /* Mask out pixel format bits in case we change it */ |
2050 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2055 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2051 | switch (fb->pixel_format) { |
2056 | switch (fb->pixel_format) { |
2052 | case DRM_FORMAT_C8: |
2057 | case DRM_FORMAT_C8: |
2053 | dspcntr |= DISPPLANE_8BPP; |
2058 | dspcntr |= DISPPLANE_8BPP; |
2054 | break; |
2059 | break; |
2055 | case DRM_FORMAT_RGB565: |
2060 | case DRM_FORMAT_RGB565: |
2056 | dspcntr |= DISPPLANE_BGRX565; |
2061 | dspcntr |= DISPPLANE_BGRX565; |
2057 | break; |
2062 | break; |
2058 | case DRM_FORMAT_XRGB8888: |
2063 | case DRM_FORMAT_XRGB8888: |
2059 | case DRM_FORMAT_ARGB8888: |
2064 | case DRM_FORMAT_ARGB8888: |
2060 | dspcntr |= DISPPLANE_BGRX888; |
2065 | dspcntr |= DISPPLANE_BGRX888; |
2061 | break; |
2066 | break; |
2062 | case DRM_FORMAT_XBGR8888: |
2067 | case DRM_FORMAT_XBGR8888: |
2063 | case DRM_FORMAT_ABGR8888: |
2068 | case DRM_FORMAT_ABGR8888: |
2064 | dspcntr |= DISPPLANE_RGBX888; |
2069 | dspcntr |= DISPPLANE_RGBX888; |
2065 | break; |
2070 | break; |
2066 | case DRM_FORMAT_XRGB2101010: |
2071 | case DRM_FORMAT_XRGB2101010: |
2067 | case DRM_FORMAT_ARGB2101010: |
2072 | case DRM_FORMAT_ARGB2101010: |
2068 | dspcntr |= DISPPLANE_BGRX101010; |
2073 | dspcntr |= DISPPLANE_BGRX101010; |
2069 | break; |
2074 | break; |
2070 | case DRM_FORMAT_XBGR2101010: |
2075 | case DRM_FORMAT_XBGR2101010: |
2071 | case DRM_FORMAT_ABGR2101010: |
2076 | case DRM_FORMAT_ABGR2101010: |
2072 | dspcntr |= DISPPLANE_RGBX101010; |
2077 | dspcntr |= DISPPLANE_RGBX101010; |
2073 | break; |
2078 | break; |
2074 | default: |
2079 | default: |
2075 | BUG(); |
2080 | BUG(); |
2076 | } |
2081 | } |
2077 | 2082 | ||
2078 | if (obj->tiling_mode != I915_TILING_NONE) |
2083 | if (obj->tiling_mode != I915_TILING_NONE) |
2079 | dspcntr |= DISPPLANE_TILED; |
2084 | dspcntr |= DISPPLANE_TILED; |
2080 | else |
2085 | else |
2081 | dspcntr &= ~DISPPLANE_TILED; |
2086 | dspcntr &= ~DISPPLANE_TILED; |
2082 | 2087 | ||
2083 | if (IS_HASWELL(dev)) |
2088 | if (IS_HASWELL(dev)) |
2084 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2089 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2085 | else |
2090 | else |
2086 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2091 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2087 | 2092 | ||
2088 | I915_WRITE(reg, dspcntr); |
2093 | I915_WRITE(reg, dspcntr); |
2089 | 2094 | ||
2090 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2095 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2091 | intel_crtc->dspaddr_offset = |
2096 | intel_crtc->dspaddr_offset = |
2092 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2097 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2093 | fb->bits_per_pixel / 8, |
2098 | fb->bits_per_pixel / 8, |
2094 | fb->pitches[0]); |
2099 | fb->pitches[0]); |
2095 | linear_offset -= intel_crtc->dspaddr_offset; |
2100 | linear_offset -= intel_crtc->dspaddr_offset; |
2096 | 2101 | ||
2097 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2102 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2098 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2103 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2099 | fb->pitches[0]); |
2104 | fb->pitches[0]); |
2100 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2105 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2101 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2106 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2102 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2107 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2103 | if (IS_HASWELL(dev)) { |
2108 | if (IS_HASWELL(dev)) { |
2104 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2109 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2105 | } else { |
2110 | } else { |
2106 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2111 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2107 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2112 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2108 | } |
2113 | } |
2109 | POSTING_READ(reg); |
2114 | POSTING_READ(reg); |
2110 | 2115 | ||
2111 | return 0; |
2116 | return 0; |
2112 | } |
2117 | } |
2113 | 2118 | ||
2114 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2119 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2115 | static int |
2120 | static int |
2116 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2121 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2117 | int x, int y, enum mode_set_atomic state) |
2122 | int x, int y, enum mode_set_atomic state) |
2118 | { |
2123 | { |
2119 | struct drm_device *dev = crtc->dev; |
2124 | struct drm_device *dev = crtc->dev; |
2120 | struct drm_i915_private *dev_priv = dev->dev_private; |
2125 | struct drm_i915_private *dev_priv = dev->dev_private; |
2121 | 2126 | ||
2122 | if (dev_priv->display.disable_fbc) |
2127 | if (dev_priv->display.disable_fbc) |
2123 | dev_priv->display.disable_fbc(dev); |
2128 | dev_priv->display.disable_fbc(dev); |
2124 | intel_increase_pllclock(crtc); |
2129 | intel_increase_pllclock(crtc); |
2125 | 2130 | ||
2126 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2131 | return dev_priv->display.update_plane(crtc, fb, x, y); |
2127 | } |
2132 | } |
2128 | 2133 | ||
2129 | #if 0 |
2134 | #if 0 |
2130 | void intel_display_handle_reset(struct drm_device *dev) |
2135 | void intel_display_handle_reset(struct drm_device *dev) |
2131 | { |
2136 | { |
2132 | struct drm_i915_private *dev_priv = dev->dev_private; |
2137 | struct drm_i915_private *dev_priv = dev->dev_private; |
2133 | struct drm_crtc *crtc; |
2138 | struct drm_crtc *crtc; |
2134 | 2139 | ||
2135 | /* |
2140 | /* |
2136 | * Flips in the rings have been nuked by the reset, |
2141 | * Flips in the rings have been nuked by the reset, |
2137 | * so complete all pending flips so that user space |
2142 | * so complete all pending flips so that user space |
2138 | * will get its events and not get stuck. |
2143 | * will get its events and not get stuck. |
2139 | * |
2144 | * |
2140 | * Also update the base address of all primary |
2145 | * Also update the base address of all primary |
2141 | * planes to the the last fb to make sure we're |
2146 | * planes to the the last fb to make sure we're |
2142 | * showing the correct fb after a reset. |
2147 | * showing the correct fb after a reset. |
2143 | * |
2148 | * |
2144 | * Need to make two loops over the crtcs so that we |
2149 | * Need to make two loops over the crtcs so that we |
2145 | * don't try to grab a crtc mutex before the |
2150 | * don't try to grab a crtc mutex before the |
2146 | * pending_flip_queue really got woken up. |
2151 | * pending_flip_queue really got woken up. |
2147 | */ |
2152 | */ |
2148 | 2153 | ||
2149 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2154 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2150 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2151 | enum plane plane = intel_crtc->plane; |
2156 | enum plane plane = intel_crtc->plane; |
2152 | 2157 | ||
2153 | intel_prepare_page_flip(dev, plane); |
2158 | intel_prepare_page_flip(dev, plane); |
2154 | intel_finish_page_flip_plane(dev, plane); |
2159 | intel_finish_page_flip_plane(dev, plane); |
2155 | } |
2160 | } |
2156 | 2161 | ||
2157 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2162 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2159 | 2164 | ||
2160 | mutex_lock(&crtc->mutex); |
2165 | mutex_lock(&crtc->mutex); |
2161 | if (intel_crtc->active) |
2166 | if (intel_crtc->active) |
2162 | dev_priv->display.update_plane(crtc, crtc->fb, |
2167 | dev_priv->display.update_plane(crtc, crtc->fb, |
2163 | crtc->x, crtc->y); |
2168 | crtc->x, crtc->y); |
2164 | mutex_unlock(&crtc->mutex); |
2169 | mutex_unlock(&crtc->mutex); |
2165 | } |
2170 | } |
2166 | } |
2171 | } |
2167 | 2172 | ||
2168 | static int |
2173 | static int |
2169 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2174 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2170 | { |
2175 | { |
2171 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2176 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2172 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2177 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2173 | bool was_interruptible = dev_priv->mm.interruptible; |
2178 | bool was_interruptible = dev_priv->mm.interruptible; |
2174 | int ret; |
2179 | int ret; |
2175 | 2180 | ||
2176 | /* Big Hammer, we also need to ensure that any pending |
2181 | /* Big Hammer, we also need to ensure that any pending |
2177 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2182 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2178 | * current scanout is retired before unpinning the old |
2183 | * current scanout is retired before unpinning the old |
2179 | * framebuffer. |
2184 | * framebuffer. |
2180 | * |
2185 | * |
2181 | * This should only fail upon a hung GPU, in which case we |
2186 | * This should only fail upon a hung GPU, in which case we |
2182 | * can safely continue. |
2187 | * can safely continue. |
2183 | */ |
2188 | */ |
2184 | dev_priv->mm.interruptible = false; |
2189 | dev_priv->mm.interruptible = false; |
2185 | ret = i915_gem_object_finish_gpu(obj); |
2190 | ret = i915_gem_object_finish_gpu(obj); |
2186 | dev_priv->mm.interruptible = was_interruptible; |
2191 | dev_priv->mm.interruptible = was_interruptible; |
2187 | 2192 | ||
2188 | return ret; |
2193 | return ret; |
2189 | } |
2194 | } |
2190 | 2195 | ||
2191 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2196 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2192 | { |
2197 | { |
2193 | struct drm_device *dev = crtc->dev; |
2198 | struct drm_device *dev = crtc->dev; |
2194 | struct drm_i915_master_private *master_priv; |
2199 | struct drm_i915_master_private *master_priv; |
2195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2196 | 2201 | ||
2197 | if (!dev->primary->master) |
2202 | if (!dev->primary->master) |
2198 | return; |
2203 | return; |
2199 | 2204 | ||
2200 | master_priv = dev->primary->master->driver_priv; |
2205 | master_priv = dev->primary->master->driver_priv; |
2201 | if (!master_priv->sarea_priv) |
2206 | if (!master_priv->sarea_priv) |
2202 | return; |
2207 | return; |
2203 | 2208 | ||
2204 | switch (intel_crtc->pipe) { |
2209 | switch (intel_crtc->pipe) { |
2205 | case 0: |
2210 | case 0: |
2206 | master_priv->sarea_priv->pipeA_x = x; |
2211 | master_priv->sarea_priv->pipeA_x = x; |
2207 | master_priv->sarea_priv->pipeA_y = y; |
2212 | master_priv->sarea_priv->pipeA_y = y; |
2208 | break; |
2213 | break; |
2209 | case 1: |
2214 | case 1: |
2210 | master_priv->sarea_priv->pipeB_x = x; |
2215 | master_priv->sarea_priv->pipeB_x = x; |
2211 | master_priv->sarea_priv->pipeB_y = y; |
2216 | master_priv->sarea_priv->pipeB_y = y; |
2212 | break; |
2217 | break; |
2213 | default: |
2218 | default: |
2214 | break; |
2219 | break; |
2215 | } |
2220 | } |
2216 | } |
2221 | } |
2217 | #endif |
2222 | #endif |
2218 | 2223 | ||
2219 | static int |
2224 | static int |
2220 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2225 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2221 | struct drm_framebuffer *fb) |
2226 | struct drm_framebuffer *fb) |
2222 | { |
2227 | { |
2223 | struct drm_device *dev = crtc->dev; |
2228 | struct drm_device *dev = crtc->dev; |
2224 | struct drm_i915_private *dev_priv = dev->dev_private; |
2229 | struct drm_i915_private *dev_priv = dev->dev_private; |
2225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2226 | struct drm_framebuffer *old_fb; |
2231 | struct drm_framebuffer *old_fb; |
2227 | int ret; |
2232 | int ret; |
2228 | 2233 | ||
2229 | /* no fb bound */ |
2234 | /* no fb bound */ |
2230 | if (!fb) { |
2235 | if (!fb) { |
2231 | DRM_ERROR("No FB bound\n"); |
2236 | DRM_ERROR("No FB bound\n"); |
2232 | return 0; |
2237 | return 0; |
2233 | } |
2238 | } |
2234 | 2239 | ||
2235 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
2240 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
2236 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2241 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2237 | plane_name(intel_crtc->plane), |
2242 | plane_name(intel_crtc->plane), |
2238 | INTEL_INFO(dev)->num_pipes); |
2243 | INTEL_INFO(dev)->num_pipes); |
2239 | return -EINVAL; |
2244 | return -EINVAL; |
2240 | } |
2245 | } |
2241 | 2246 | ||
2242 | mutex_lock(&dev->struct_mutex); |
2247 | mutex_lock(&dev->struct_mutex); |
2243 | // ret = intel_pin_and_fence_fb_obj(dev, |
2248 | ret = intel_pin_and_fence_fb_obj(dev, |
2244 | // to_intel_framebuffer(fb)->obj, |
2249 | to_intel_framebuffer(fb)->obj, |
2245 | // NULL); |
2250 | NULL); |
2246 | // if (ret != 0) { |
2251 | if (ret != 0) { |
2247 | // mutex_unlock(&dev->struct_mutex); |
2252 | mutex_unlock(&dev->struct_mutex); |
2248 | // DRM_ERROR("pin & fence failed\n"); |
2253 | DRM_ERROR("pin & fence failed\n"); |
2249 | // return ret; |
2254 | return ret; |
2250 | // } |
2255 | } |
- | 2256 | ||
- | 2257 | /* Update pipe size and adjust fitter if needed */ |
|
- | 2258 | if (i915_fastboot) { |
|
- | 2259 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
|
- | 2260 | ((crtc->mode.hdisplay - 1) << 16) | |
|
- | 2261 | (crtc->mode.vdisplay - 1)); |
|
- | 2262 | if (!intel_crtc->config.pch_pfit.enabled && |
|
- | 2263 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
|
- | 2264 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
|
- | 2265 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
|
- | 2266 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
|
- | 2267 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
|
- | 2268 | } |
|
2251 | 2269 | } |
|
2252 | 2270 | ||
2253 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2271 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2254 | if (ret) { |
2272 | if (ret) { |
2255 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2273 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2256 | mutex_unlock(&dev->struct_mutex); |
2274 | mutex_unlock(&dev->struct_mutex); |
2257 | DRM_ERROR("failed to update base address\n"); |
2275 | DRM_ERROR("failed to update base address\n"); |
2258 | return ret; |
2276 | return ret; |
2259 | } |
2277 | } |
2260 | 2278 | ||
2261 | old_fb = crtc->fb; |
2279 | old_fb = crtc->fb; |
2262 | crtc->fb = fb; |
2280 | crtc->fb = fb; |
2263 | crtc->x = x; |
2281 | crtc->x = x; |
2264 | crtc->y = y; |
2282 | crtc->y = y; |
2265 | 2283 | ||
2266 | if (old_fb) { |
2284 | if (old_fb) { |
2267 | if (intel_crtc->active && old_fb != fb) |
2285 | if (intel_crtc->active && old_fb != fb) |
2268 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2286 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2269 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2287 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2270 | } |
2288 | } |
2271 | 2289 | ||
2272 | intel_update_fbc(dev); |
2290 | intel_update_fbc(dev); |
2273 | intel_edp_psr_update(dev); |
2291 | intel_edp_psr_update(dev); |
2274 | mutex_unlock(&dev->struct_mutex); |
2292 | mutex_unlock(&dev->struct_mutex); |
2275 | 2293 | ||
2276 | return 0; |
2294 | return 0; |
2277 | } |
2295 | } |
2278 | 2296 | ||
2279 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2297 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2280 | { |
2298 | { |
2281 | struct drm_device *dev = crtc->dev; |
2299 | struct drm_device *dev = crtc->dev; |
2282 | struct drm_i915_private *dev_priv = dev->dev_private; |
2300 | struct drm_i915_private *dev_priv = dev->dev_private; |
2283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2301 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2284 | int pipe = intel_crtc->pipe; |
2302 | int pipe = intel_crtc->pipe; |
2285 | u32 reg, temp; |
2303 | u32 reg, temp; |
2286 | 2304 | ||
2287 | /* enable normal train */ |
2305 | /* enable normal train */ |
2288 | reg = FDI_TX_CTL(pipe); |
2306 | reg = FDI_TX_CTL(pipe); |
2289 | temp = I915_READ(reg); |
2307 | temp = I915_READ(reg); |
2290 | if (IS_IVYBRIDGE(dev)) { |
2308 | if (IS_IVYBRIDGE(dev)) { |
2291 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2309 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2292 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2310 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2293 | } else { |
2311 | } else { |
2294 | temp &= ~FDI_LINK_TRAIN_NONE; |
2312 | temp &= ~FDI_LINK_TRAIN_NONE; |
2295 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2313 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2296 | } |
2314 | } |
2297 | I915_WRITE(reg, temp); |
2315 | I915_WRITE(reg, temp); |
2298 | 2316 | ||
2299 | reg = FDI_RX_CTL(pipe); |
2317 | reg = FDI_RX_CTL(pipe); |
2300 | temp = I915_READ(reg); |
2318 | temp = I915_READ(reg); |
2301 | if (HAS_PCH_CPT(dev)) { |
2319 | if (HAS_PCH_CPT(dev)) { |
2302 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2320 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2303 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2321 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2304 | } else { |
2322 | } else { |
2305 | temp &= ~FDI_LINK_TRAIN_NONE; |
2323 | temp &= ~FDI_LINK_TRAIN_NONE; |
2306 | temp |= FDI_LINK_TRAIN_NONE; |
2324 | temp |= FDI_LINK_TRAIN_NONE; |
2307 | } |
2325 | } |
2308 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2326 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2309 | 2327 | ||
2310 | /* wait one idle pattern time */ |
2328 | /* wait one idle pattern time */ |
2311 | POSTING_READ(reg); |
2329 | POSTING_READ(reg); |
2312 | udelay(1000); |
2330 | udelay(1000); |
2313 | 2331 | ||
2314 | /* IVB wants error correction enabled */ |
2332 | /* IVB wants error correction enabled */ |
2315 | if (IS_IVYBRIDGE(dev)) |
2333 | if (IS_IVYBRIDGE(dev)) |
2316 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2334 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2317 | FDI_FE_ERRC_ENABLE); |
2335 | FDI_FE_ERRC_ENABLE); |
2318 | } |
2336 | } |
2319 | 2337 | ||
2320 | static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) |
2338 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
2321 | { |
2339 | { |
- | 2340 | return crtc->base.enabled && crtc->active && |
|
2322 | return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder; |
2341 | crtc->config.has_pch_encoder; |
2323 | } |
2342 | } |
2324 | 2343 | ||
2325 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2344 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2326 | { |
2345 | { |
2327 | struct drm_i915_private *dev_priv = dev->dev_private; |
2346 | struct drm_i915_private *dev_priv = dev->dev_private; |
2328 | struct intel_crtc *pipe_B_crtc = |
2347 | struct intel_crtc *pipe_B_crtc = |
2329 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
2348 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
2330 | struct intel_crtc *pipe_C_crtc = |
2349 | struct intel_crtc *pipe_C_crtc = |
2331 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
2350 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
2332 | uint32_t temp; |
2351 | uint32_t temp; |
2333 | 2352 | ||
2334 | /* |
2353 | /* |
2335 | * When everything is off disable fdi C so that we could enable fdi B |
2354 | * When everything is off disable fdi C so that we could enable fdi B |
2336 | * with all lanes. Note that we don't care about enabled pipes without |
2355 | * with all lanes. Note that we don't care about enabled pipes without |
2337 | * an enabled pch encoder. |
2356 | * an enabled pch encoder. |
2338 | */ |
2357 | */ |
2339 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
2358 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
2340 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
2359 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
2341 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2360 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2342 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2361 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2343 | 2362 | ||
2344 | temp = I915_READ(SOUTH_CHICKEN1); |
2363 | temp = I915_READ(SOUTH_CHICKEN1); |
2345 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
2364 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
2346 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
2365 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
2347 | I915_WRITE(SOUTH_CHICKEN1, temp); |
2366 | I915_WRITE(SOUTH_CHICKEN1, temp); |
2348 | } |
2367 | } |
2349 | } |
2368 | } |
2350 | 2369 | ||
2351 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2370 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2352 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2371 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2353 | { |
2372 | { |
2354 | struct drm_device *dev = crtc->dev; |
2373 | struct drm_device *dev = crtc->dev; |
2355 | struct drm_i915_private *dev_priv = dev->dev_private; |
2374 | struct drm_i915_private *dev_priv = dev->dev_private; |
2356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2375 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2357 | int pipe = intel_crtc->pipe; |
2376 | int pipe = intel_crtc->pipe; |
2358 | int plane = intel_crtc->plane; |
2377 | int plane = intel_crtc->plane; |
2359 | u32 reg, temp, tries; |
2378 | u32 reg, temp, tries; |
2360 | 2379 | ||
2361 | /* FDI needs bits from pipe & plane first */ |
2380 | /* FDI needs bits from pipe & plane first */ |
2362 | assert_pipe_enabled(dev_priv, pipe); |
2381 | assert_pipe_enabled(dev_priv, pipe); |
2363 | assert_plane_enabled(dev_priv, plane); |
2382 | assert_plane_enabled(dev_priv, plane); |
2364 | 2383 | ||
2365 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2384 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2366 | for train result */ |
2385 | for train result */ |
2367 | reg = FDI_RX_IMR(pipe); |
2386 | reg = FDI_RX_IMR(pipe); |
2368 | temp = I915_READ(reg); |
2387 | temp = I915_READ(reg); |
2369 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2388 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2370 | temp &= ~FDI_RX_BIT_LOCK; |
2389 | temp &= ~FDI_RX_BIT_LOCK; |
2371 | I915_WRITE(reg, temp); |
2390 | I915_WRITE(reg, temp); |
2372 | I915_READ(reg); |
2391 | I915_READ(reg); |
2373 | udelay(150); |
2392 | udelay(150); |
2374 | 2393 | ||
2375 | /* enable CPU FDI TX and PCH FDI RX */ |
2394 | /* enable CPU FDI TX and PCH FDI RX */ |
2376 | reg = FDI_TX_CTL(pipe); |
2395 | reg = FDI_TX_CTL(pipe); |
2377 | temp = I915_READ(reg); |
2396 | temp = I915_READ(reg); |
2378 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2397 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2379 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2398 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2380 | temp &= ~FDI_LINK_TRAIN_NONE; |
2399 | temp &= ~FDI_LINK_TRAIN_NONE; |
2381 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2400 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2382 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2401 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2383 | 2402 | ||
2384 | reg = FDI_RX_CTL(pipe); |
2403 | reg = FDI_RX_CTL(pipe); |
2385 | temp = I915_READ(reg); |
2404 | temp = I915_READ(reg); |
2386 | temp &= ~FDI_LINK_TRAIN_NONE; |
2405 | temp &= ~FDI_LINK_TRAIN_NONE; |
2387 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2406 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2388 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2407 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2389 | 2408 | ||
2390 | POSTING_READ(reg); |
2409 | POSTING_READ(reg); |
2391 | udelay(150); |
2410 | udelay(150); |
2392 | 2411 | ||
2393 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2412 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2394 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2413 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2395 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2414 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2396 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2415 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2397 | 2416 | ||
2398 | reg = FDI_RX_IIR(pipe); |
2417 | reg = FDI_RX_IIR(pipe); |
2399 | for (tries = 0; tries < 5; tries++) { |
2418 | for (tries = 0; tries < 5; tries++) { |
2400 | temp = I915_READ(reg); |
2419 | temp = I915_READ(reg); |
2401 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2420 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2402 | 2421 | ||
2403 | if ((temp & FDI_RX_BIT_LOCK)) { |
2422 | if ((temp & FDI_RX_BIT_LOCK)) { |
2404 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2423 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2405 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2424 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2406 | break; |
2425 | break; |
2407 | } |
2426 | } |
2408 | } |
2427 | } |
2409 | if (tries == 5) |
2428 | if (tries == 5) |
2410 | DRM_ERROR("FDI train 1 fail!\n"); |
2429 | DRM_ERROR("FDI train 1 fail!\n"); |
2411 | 2430 | ||
2412 | /* Train 2 */ |
2431 | /* Train 2 */ |
2413 | reg = FDI_TX_CTL(pipe); |
2432 | reg = FDI_TX_CTL(pipe); |
2414 | temp = I915_READ(reg); |
2433 | temp = I915_READ(reg); |
2415 | temp &= ~FDI_LINK_TRAIN_NONE; |
2434 | temp &= ~FDI_LINK_TRAIN_NONE; |
2416 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2435 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2417 | I915_WRITE(reg, temp); |
2436 | I915_WRITE(reg, temp); |
2418 | 2437 | ||
2419 | reg = FDI_RX_CTL(pipe); |
2438 | reg = FDI_RX_CTL(pipe); |
2420 | temp = I915_READ(reg); |
2439 | temp = I915_READ(reg); |
2421 | temp &= ~FDI_LINK_TRAIN_NONE; |
2440 | temp &= ~FDI_LINK_TRAIN_NONE; |
2422 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2441 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2423 | I915_WRITE(reg, temp); |
2442 | I915_WRITE(reg, temp); |
2424 | 2443 | ||
2425 | POSTING_READ(reg); |
2444 | POSTING_READ(reg); |
2426 | udelay(150); |
2445 | udelay(150); |
2427 | 2446 | ||
2428 | reg = FDI_RX_IIR(pipe); |
2447 | reg = FDI_RX_IIR(pipe); |
2429 | for (tries = 0; tries < 5; tries++) { |
2448 | for (tries = 0; tries < 5; tries++) { |
2430 | temp = I915_READ(reg); |
2449 | temp = I915_READ(reg); |
2431 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2450 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2432 | 2451 | ||
2433 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2452 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2434 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2453 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2435 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2454 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2436 | break; |
2455 | break; |
2437 | } |
2456 | } |
2438 | } |
2457 | } |
2439 | if (tries == 5) |
2458 | if (tries == 5) |
2440 | DRM_ERROR("FDI train 2 fail!\n"); |
2459 | DRM_ERROR("FDI train 2 fail!\n"); |
2441 | 2460 | ||
2442 | DRM_DEBUG_KMS("FDI train done\n"); |
2461 | DRM_DEBUG_KMS("FDI train done\n"); |
2443 | 2462 | ||
2444 | } |
2463 | } |
2445 | 2464 | ||
2446 | static const int snb_b_fdi_train_param[] = { |
2465 | static const int snb_b_fdi_train_param[] = { |
2447 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2466 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2448 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2467 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2449 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2468 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2450 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2469 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2451 | }; |
2470 | }; |
2452 | 2471 | ||
2453 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2472 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2454 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2473 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2455 | { |
2474 | { |
2456 | struct drm_device *dev = crtc->dev; |
2475 | struct drm_device *dev = crtc->dev; |
2457 | struct drm_i915_private *dev_priv = dev->dev_private; |
2476 | struct drm_i915_private *dev_priv = dev->dev_private; |
2458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2477 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2459 | int pipe = intel_crtc->pipe; |
2478 | int pipe = intel_crtc->pipe; |
2460 | u32 reg, temp, i, retry; |
2479 | u32 reg, temp, i, retry; |
2461 | 2480 | ||
2462 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2481 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2463 | for train result */ |
2482 | for train result */ |
2464 | reg = FDI_RX_IMR(pipe); |
2483 | reg = FDI_RX_IMR(pipe); |
2465 | temp = I915_READ(reg); |
2484 | temp = I915_READ(reg); |
2466 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2485 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2467 | temp &= ~FDI_RX_BIT_LOCK; |
2486 | temp &= ~FDI_RX_BIT_LOCK; |
2468 | I915_WRITE(reg, temp); |
2487 | I915_WRITE(reg, temp); |
2469 | 2488 | ||
2470 | POSTING_READ(reg); |
2489 | POSTING_READ(reg); |
2471 | udelay(150); |
2490 | udelay(150); |
2472 | 2491 | ||
2473 | /* enable CPU FDI TX and PCH FDI RX */ |
2492 | /* enable CPU FDI TX and PCH FDI RX */ |
2474 | reg = FDI_TX_CTL(pipe); |
2493 | reg = FDI_TX_CTL(pipe); |
2475 | temp = I915_READ(reg); |
2494 | temp = I915_READ(reg); |
2476 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2495 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2477 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2496 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2478 | temp &= ~FDI_LINK_TRAIN_NONE; |
2497 | temp &= ~FDI_LINK_TRAIN_NONE; |
2479 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2498 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2480 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2499 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2481 | /* SNB-B */ |
2500 | /* SNB-B */ |
2482 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2501 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2483 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2502 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2484 | 2503 | ||
2485 | I915_WRITE(FDI_RX_MISC(pipe), |
2504 | I915_WRITE(FDI_RX_MISC(pipe), |
2486 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2505 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2487 | 2506 | ||
2488 | reg = FDI_RX_CTL(pipe); |
2507 | reg = FDI_RX_CTL(pipe); |
2489 | temp = I915_READ(reg); |
2508 | temp = I915_READ(reg); |
2490 | if (HAS_PCH_CPT(dev)) { |
2509 | if (HAS_PCH_CPT(dev)) { |
2491 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2510 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2492 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2511 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2493 | } else { |
2512 | } else { |
2494 | temp &= ~FDI_LINK_TRAIN_NONE; |
2513 | temp &= ~FDI_LINK_TRAIN_NONE; |
2495 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2514 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2496 | } |
2515 | } |
2497 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2516 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2498 | 2517 | ||
2499 | POSTING_READ(reg); |
2518 | POSTING_READ(reg); |
2500 | udelay(150); |
2519 | udelay(150); |
2501 | 2520 | ||
2502 | for (i = 0; i < 4; i++) { |
2521 | for (i = 0; i < 4; i++) { |
2503 | reg = FDI_TX_CTL(pipe); |
2522 | reg = FDI_TX_CTL(pipe); |
2504 | temp = I915_READ(reg); |
2523 | temp = I915_READ(reg); |
2505 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2524 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2506 | temp |= snb_b_fdi_train_param[i]; |
2525 | temp |= snb_b_fdi_train_param[i]; |
2507 | I915_WRITE(reg, temp); |
2526 | I915_WRITE(reg, temp); |
2508 | 2527 | ||
2509 | POSTING_READ(reg); |
2528 | POSTING_READ(reg); |
2510 | udelay(500); |
2529 | udelay(500); |
2511 | 2530 | ||
2512 | for (retry = 0; retry < 5; retry++) { |
2531 | for (retry = 0; retry < 5; retry++) { |
2513 | reg = FDI_RX_IIR(pipe); |
2532 | reg = FDI_RX_IIR(pipe); |
2514 | temp = I915_READ(reg); |
2533 | temp = I915_READ(reg); |
2515 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2534 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2516 | if (temp & FDI_RX_BIT_LOCK) { |
2535 | if (temp & FDI_RX_BIT_LOCK) { |
2517 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2536 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2518 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2537 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2519 | break; |
2538 | break; |
2520 | } |
2539 | } |
2521 | udelay(50); |
2540 | udelay(50); |
2522 | } |
2541 | } |
2523 | if (retry < 5) |
2542 | if (retry < 5) |
2524 | break; |
2543 | break; |
2525 | } |
2544 | } |
2526 | if (i == 4) |
2545 | if (i == 4) |
2527 | DRM_ERROR("FDI train 1 fail!\n"); |
2546 | DRM_ERROR("FDI train 1 fail!\n"); |
2528 | 2547 | ||
2529 | /* Train 2 */ |
2548 | /* Train 2 */ |
2530 | reg = FDI_TX_CTL(pipe); |
2549 | reg = FDI_TX_CTL(pipe); |
2531 | temp = I915_READ(reg); |
2550 | temp = I915_READ(reg); |
2532 | temp &= ~FDI_LINK_TRAIN_NONE; |
2551 | temp &= ~FDI_LINK_TRAIN_NONE; |
2533 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2552 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2534 | if (IS_GEN6(dev)) { |
2553 | if (IS_GEN6(dev)) { |
2535 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2554 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2536 | /* SNB-B */ |
2555 | /* SNB-B */ |
2537 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2556 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2538 | } |
2557 | } |
2539 | I915_WRITE(reg, temp); |
2558 | I915_WRITE(reg, temp); |
2540 | 2559 | ||
2541 | reg = FDI_RX_CTL(pipe); |
2560 | reg = FDI_RX_CTL(pipe); |
2542 | temp = I915_READ(reg); |
2561 | temp = I915_READ(reg); |
2543 | if (HAS_PCH_CPT(dev)) { |
2562 | if (HAS_PCH_CPT(dev)) { |
2544 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2563 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2545 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2564 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2546 | } else { |
2565 | } else { |
2547 | temp &= ~FDI_LINK_TRAIN_NONE; |
2566 | temp &= ~FDI_LINK_TRAIN_NONE; |
2548 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2567 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2549 | } |
2568 | } |
2550 | I915_WRITE(reg, temp); |
2569 | I915_WRITE(reg, temp); |
2551 | 2570 | ||
2552 | POSTING_READ(reg); |
2571 | POSTING_READ(reg); |
2553 | udelay(150); |
2572 | udelay(150); |
2554 | 2573 | ||
2555 | for (i = 0; i < 4; i++) { |
2574 | for (i = 0; i < 4; i++) { |
2556 | reg = FDI_TX_CTL(pipe); |
2575 | reg = FDI_TX_CTL(pipe); |
2557 | temp = I915_READ(reg); |
2576 | temp = I915_READ(reg); |
2558 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2577 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2559 | temp |= snb_b_fdi_train_param[i]; |
2578 | temp |= snb_b_fdi_train_param[i]; |
2560 | I915_WRITE(reg, temp); |
2579 | I915_WRITE(reg, temp); |
2561 | 2580 | ||
2562 | POSTING_READ(reg); |
2581 | POSTING_READ(reg); |
2563 | udelay(500); |
2582 | udelay(500); |
2564 | 2583 | ||
2565 | for (retry = 0; retry < 5; retry++) { |
2584 | for (retry = 0; retry < 5; retry++) { |
2566 | reg = FDI_RX_IIR(pipe); |
2585 | reg = FDI_RX_IIR(pipe); |
2567 | temp = I915_READ(reg); |
2586 | temp = I915_READ(reg); |
2568 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2587 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2569 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2588 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2570 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2589 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2571 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2590 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2572 | break; |
2591 | break; |
2573 | } |
2592 | } |
2574 | udelay(50); |
2593 | udelay(50); |
2575 | } |
2594 | } |
2576 | if (retry < 5) |
2595 | if (retry < 5) |
2577 | break; |
2596 | break; |
2578 | } |
2597 | } |
2579 | if (i == 4) |
2598 | if (i == 4) |
2580 | DRM_ERROR("FDI train 2 fail!\n"); |
2599 | DRM_ERROR("FDI train 2 fail!\n"); |
2581 | 2600 | ||
2582 | DRM_DEBUG_KMS("FDI train done.\n"); |
2601 | DRM_DEBUG_KMS("FDI train done.\n"); |
2583 | } |
2602 | } |
2584 | 2603 | ||
2585 | /* Manual link training for Ivy Bridge A0 parts */ |
2604 | /* Manual link training for Ivy Bridge A0 parts */ |
2586 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2605 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2587 | { |
2606 | { |
2588 | struct drm_device *dev = crtc->dev; |
2607 | struct drm_device *dev = crtc->dev; |
2589 | struct drm_i915_private *dev_priv = dev->dev_private; |
2608 | struct drm_i915_private *dev_priv = dev->dev_private; |
2590 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2609 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2591 | int pipe = intel_crtc->pipe; |
2610 | int pipe = intel_crtc->pipe; |
2592 | u32 reg, temp, i, j; |
2611 | u32 reg, temp, i, j; |
2593 | 2612 | ||
2594 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2613 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2595 | for train result */ |
2614 | for train result */ |
2596 | reg = FDI_RX_IMR(pipe); |
2615 | reg = FDI_RX_IMR(pipe); |
2597 | temp = I915_READ(reg); |
2616 | temp = I915_READ(reg); |
2598 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2617 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2599 | temp &= ~FDI_RX_BIT_LOCK; |
2618 | temp &= ~FDI_RX_BIT_LOCK; |
2600 | I915_WRITE(reg, temp); |
2619 | I915_WRITE(reg, temp); |
2601 | 2620 | ||
2602 | POSTING_READ(reg); |
2621 | POSTING_READ(reg); |
2603 | udelay(150); |
2622 | udelay(150); |
2604 | 2623 | ||
2605 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2624 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2606 | I915_READ(FDI_RX_IIR(pipe))); |
2625 | I915_READ(FDI_RX_IIR(pipe))); |
2607 | 2626 | ||
2608 | /* Try each vswing and preemphasis setting twice before moving on */ |
2627 | /* Try each vswing and preemphasis setting twice before moving on */ |
2609 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
2628 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
2610 | /* disable first in case we need to retry */ |
2629 | /* disable first in case we need to retry */ |
2611 | reg = FDI_TX_CTL(pipe); |
2630 | reg = FDI_TX_CTL(pipe); |
2612 | temp = I915_READ(reg); |
2631 | temp = I915_READ(reg); |
2613 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2632 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2614 | temp &= ~FDI_TX_ENABLE; |
2633 | temp &= ~FDI_TX_ENABLE; |
2615 | I915_WRITE(reg, temp); |
2634 | I915_WRITE(reg, temp); |
2616 | 2635 | ||
2617 | reg = FDI_RX_CTL(pipe); |
2636 | reg = FDI_RX_CTL(pipe); |
2618 | temp = I915_READ(reg); |
2637 | temp = I915_READ(reg); |
2619 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2638 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2620 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2639 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2621 | temp &= ~FDI_RX_ENABLE; |
2640 | temp &= ~FDI_RX_ENABLE; |
2622 | I915_WRITE(reg, temp); |
2641 | I915_WRITE(reg, temp); |
2623 | 2642 | ||
2624 | /* enable CPU FDI TX and PCH FDI RX */ |
2643 | /* enable CPU FDI TX and PCH FDI RX */ |
2625 | reg = FDI_TX_CTL(pipe); |
2644 | reg = FDI_TX_CTL(pipe); |
2626 | temp = I915_READ(reg); |
2645 | temp = I915_READ(reg); |
2627 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2646 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2628 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2647 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2629 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2648 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2630 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2649 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2631 | temp |= snb_b_fdi_train_param[j/2]; |
2650 | temp |= snb_b_fdi_train_param[j/2]; |
2632 | temp |= FDI_COMPOSITE_SYNC; |
2651 | temp |= FDI_COMPOSITE_SYNC; |
2633 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2652 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2634 | 2653 | ||
2635 | I915_WRITE(FDI_RX_MISC(pipe), |
2654 | I915_WRITE(FDI_RX_MISC(pipe), |
2636 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2655 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2637 | 2656 | ||
2638 | reg = FDI_RX_CTL(pipe); |
2657 | reg = FDI_RX_CTL(pipe); |
2639 | temp = I915_READ(reg); |
2658 | temp = I915_READ(reg); |
2640 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2659 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2641 | temp |= FDI_COMPOSITE_SYNC; |
2660 | temp |= FDI_COMPOSITE_SYNC; |
2642 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2661 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2643 | 2662 | ||
2644 | POSTING_READ(reg); |
2663 | POSTING_READ(reg); |
2645 | udelay(1); /* should be 0.5us */ |
2664 | udelay(1); /* should be 0.5us */ |
2646 | 2665 | ||
2647 | for (i = 0; i < 4; i++) { |
2666 | for (i = 0; i < 4; i++) { |
2648 | reg = FDI_RX_IIR(pipe); |
2667 | reg = FDI_RX_IIR(pipe); |
2649 | temp = I915_READ(reg); |
2668 | temp = I915_READ(reg); |
2650 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2669 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2651 | 2670 | ||
2652 | if (temp & FDI_RX_BIT_LOCK || |
2671 | if (temp & FDI_RX_BIT_LOCK || |
2653 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2672 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2654 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2673 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2655 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
2674 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
2656 | i); |
2675 | i); |
2657 | break; |
2676 | break; |
2658 | } |
2677 | } |
2659 | udelay(1); /* should be 0.5us */ |
2678 | udelay(1); /* should be 0.5us */ |
2660 | } |
2679 | } |
2661 | if (i == 4) { |
2680 | if (i == 4) { |
2662 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
2681 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
2663 | continue; |
2682 | continue; |
2664 | } |
2683 | } |
2665 | 2684 | ||
2666 | /* Train 2 */ |
2685 | /* Train 2 */ |
2667 | reg = FDI_TX_CTL(pipe); |
2686 | reg = FDI_TX_CTL(pipe); |
2668 | temp = I915_READ(reg); |
2687 | temp = I915_READ(reg); |
2669 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2688 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2670 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2689 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2671 | I915_WRITE(reg, temp); |
2690 | I915_WRITE(reg, temp); |
2672 | 2691 | ||
2673 | reg = FDI_RX_CTL(pipe); |
2692 | reg = FDI_RX_CTL(pipe); |
2674 | temp = I915_READ(reg); |
2693 | temp = I915_READ(reg); |
2675 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2694 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2676 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2695 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2677 | I915_WRITE(reg, temp); |
2696 | I915_WRITE(reg, temp); |
2678 | 2697 | ||
2679 | POSTING_READ(reg); |
2698 | POSTING_READ(reg); |
2680 | udelay(2); /* should be 1.5us */ |
2699 | udelay(2); /* should be 1.5us */ |
2681 | 2700 | ||
2682 | for (i = 0; i < 4; i++) { |
2701 | for (i = 0; i < 4; i++) { |
2683 | reg = FDI_RX_IIR(pipe); |
2702 | reg = FDI_RX_IIR(pipe); |
2684 | temp = I915_READ(reg); |
2703 | temp = I915_READ(reg); |
2685 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2704 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2686 | 2705 | ||
2687 | if (temp & FDI_RX_SYMBOL_LOCK || |
2706 | if (temp & FDI_RX_SYMBOL_LOCK || |
2688 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
2707 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
2689 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2708 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2690 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
2709 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
2691 | i); |
2710 | i); |
2692 | goto train_done; |
2711 | goto train_done; |
2693 | } |
2712 | } |
2694 | udelay(2); /* should be 1.5us */ |
2713 | udelay(2); /* should be 1.5us */ |
2695 | } |
2714 | } |
2696 | if (i == 4) |
2715 | if (i == 4) |
2697 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
2716 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
2698 | } |
2717 | } |
2699 | 2718 | ||
2700 | train_done: |
2719 | train_done: |
2701 | DRM_DEBUG_KMS("FDI train done.\n"); |
2720 | DRM_DEBUG_KMS("FDI train done.\n"); |
2702 | } |
2721 | } |
2703 | 2722 | ||
2704 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2723 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2705 | { |
2724 | { |
2706 | struct drm_device *dev = intel_crtc->base.dev; |
2725 | struct drm_device *dev = intel_crtc->base.dev; |
2707 | struct drm_i915_private *dev_priv = dev->dev_private; |
2726 | struct drm_i915_private *dev_priv = dev->dev_private; |
2708 | int pipe = intel_crtc->pipe; |
2727 | int pipe = intel_crtc->pipe; |
2709 | u32 reg, temp; |
2728 | u32 reg, temp; |
2710 | 2729 | ||
2711 | 2730 | ||
2712 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2731 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2713 | reg = FDI_RX_CTL(pipe); |
2732 | reg = FDI_RX_CTL(pipe); |
2714 | temp = I915_READ(reg); |
2733 | temp = I915_READ(reg); |
2715 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2734 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2716 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2735 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2717 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2736 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2718 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2737 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2719 | 2738 | ||
2720 | POSTING_READ(reg); |
2739 | POSTING_READ(reg); |
2721 | udelay(200); |
2740 | udelay(200); |
2722 | 2741 | ||
2723 | /* Switch from Rawclk to PCDclk */ |
2742 | /* Switch from Rawclk to PCDclk */ |
2724 | temp = I915_READ(reg); |
2743 | temp = I915_READ(reg); |
2725 | I915_WRITE(reg, temp | FDI_PCDCLK); |
2744 | I915_WRITE(reg, temp | FDI_PCDCLK); |
2726 | 2745 | ||
2727 | POSTING_READ(reg); |
2746 | POSTING_READ(reg); |
2728 | udelay(200); |
2747 | udelay(200); |
2729 | 2748 | ||
2730 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2749 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2731 | reg = FDI_TX_CTL(pipe); |
2750 | reg = FDI_TX_CTL(pipe); |
2732 | temp = I915_READ(reg); |
2751 | temp = I915_READ(reg); |
2733 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
2752 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
2734 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2753 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2735 | 2754 | ||
2736 | POSTING_READ(reg); |
2755 | POSTING_READ(reg); |
2737 | udelay(100); |
2756 | udelay(100); |
2738 | } |
2757 | } |
2739 | } |
2758 | } |
2740 | 2759 | ||
2741 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2760 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2742 | { |
2761 | { |
2743 | struct drm_device *dev = intel_crtc->base.dev; |
2762 | struct drm_device *dev = intel_crtc->base.dev; |
2744 | struct drm_i915_private *dev_priv = dev->dev_private; |
2763 | struct drm_i915_private *dev_priv = dev->dev_private; |
2745 | int pipe = intel_crtc->pipe; |
2764 | int pipe = intel_crtc->pipe; |
2746 | u32 reg, temp; |
2765 | u32 reg, temp; |
2747 | 2766 | ||
2748 | /* Switch from PCDclk to Rawclk */ |
2767 | /* Switch from PCDclk to Rawclk */ |
2749 | reg = FDI_RX_CTL(pipe); |
2768 | reg = FDI_RX_CTL(pipe); |
2750 | temp = I915_READ(reg); |
2769 | temp = I915_READ(reg); |
2751 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
2770 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
2752 | 2771 | ||
2753 | /* Disable CPU FDI TX PLL */ |
2772 | /* Disable CPU FDI TX PLL */ |
2754 | reg = FDI_TX_CTL(pipe); |
2773 | reg = FDI_TX_CTL(pipe); |
2755 | temp = I915_READ(reg); |
2774 | temp = I915_READ(reg); |
2756 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
2775 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
2757 | 2776 | ||
2758 | POSTING_READ(reg); |
2777 | POSTING_READ(reg); |
2759 | udelay(100); |
2778 | udelay(100); |
2760 | 2779 | ||
2761 | reg = FDI_RX_CTL(pipe); |
2780 | reg = FDI_RX_CTL(pipe); |
2762 | temp = I915_READ(reg); |
2781 | temp = I915_READ(reg); |
2763 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
2782 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
2764 | 2783 | ||
2765 | /* Wait for the clocks to turn off. */ |
2784 | /* Wait for the clocks to turn off. */ |
2766 | POSTING_READ(reg); |
2785 | POSTING_READ(reg); |
2767 | udelay(100); |
2786 | udelay(100); |
2768 | } |
2787 | } |
2769 | 2788 | ||
2770 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2789 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2771 | { |
2790 | { |
2772 | struct drm_device *dev = crtc->dev; |
2791 | struct drm_device *dev = crtc->dev; |
2773 | struct drm_i915_private *dev_priv = dev->dev_private; |
2792 | struct drm_i915_private *dev_priv = dev->dev_private; |
2774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2775 | int pipe = intel_crtc->pipe; |
2794 | int pipe = intel_crtc->pipe; |
2776 | u32 reg, temp; |
2795 | u32 reg, temp; |
2777 | 2796 | ||
2778 | /* disable CPU FDI tx and PCH FDI rx */ |
2797 | /* disable CPU FDI tx and PCH FDI rx */ |
2779 | reg = FDI_TX_CTL(pipe); |
2798 | reg = FDI_TX_CTL(pipe); |
2780 | temp = I915_READ(reg); |
2799 | temp = I915_READ(reg); |
2781 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
2800 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
2782 | POSTING_READ(reg); |
2801 | POSTING_READ(reg); |
2783 | 2802 | ||
2784 | reg = FDI_RX_CTL(pipe); |
2803 | reg = FDI_RX_CTL(pipe); |
2785 | temp = I915_READ(reg); |
2804 | temp = I915_READ(reg); |
2786 | temp &= ~(0x7 << 16); |
2805 | temp &= ~(0x7 << 16); |
2787 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2806 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2788 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2807 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2789 | 2808 | ||
2790 | POSTING_READ(reg); |
2809 | POSTING_READ(reg); |
2791 | udelay(100); |
2810 | udelay(100); |
2792 | 2811 | ||
2793 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2812 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2794 | if (HAS_PCH_IBX(dev)) { |
2813 | if (HAS_PCH_IBX(dev)) { |
2795 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2814 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2796 | } |
2815 | } |
2797 | 2816 | ||
2798 | /* still set train pattern 1 */ |
2817 | /* still set train pattern 1 */ |
2799 | reg = FDI_TX_CTL(pipe); |
2818 | reg = FDI_TX_CTL(pipe); |
2800 | temp = I915_READ(reg); |
2819 | temp = I915_READ(reg); |
2801 | temp &= ~FDI_LINK_TRAIN_NONE; |
2820 | temp &= ~FDI_LINK_TRAIN_NONE; |
2802 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2821 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2803 | I915_WRITE(reg, temp); |
2822 | I915_WRITE(reg, temp); |
2804 | 2823 | ||
2805 | reg = FDI_RX_CTL(pipe); |
2824 | reg = FDI_RX_CTL(pipe); |
2806 | temp = I915_READ(reg); |
2825 | temp = I915_READ(reg); |
2807 | if (HAS_PCH_CPT(dev)) { |
2826 | if (HAS_PCH_CPT(dev)) { |
2808 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2827 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2809 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2828 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2810 | } else { |
2829 | } else { |
2811 | temp &= ~FDI_LINK_TRAIN_NONE; |
2830 | temp &= ~FDI_LINK_TRAIN_NONE; |
2812 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2831 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2813 | } |
2832 | } |
2814 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2833 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2815 | temp &= ~(0x07 << 16); |
2834 | temp &= ~(0x07 << 16); |
2816 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2835 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
2817 | I915_WRITE(reg, temp); |
2836 | I915_WRITE(reg, temp); |
2818 | 2837 | ||
2819 | POSTING_READ(reg); |
2838 | POSTING_READ(reg); |
2820 | udelay(100); |
2839 | udelay(100); |
2821 | } |
2840 | } |
2822 | 2841 | ||
2823 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2842 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2824 | { |
2843 | { |
2825 | struct drm_device *dev = crtc->dev; |
2844 | struct drm_device *dev = crtc->dev; |
2826 | struct drm_i915_private *dev_priv = dev->dev_private; |
2845 | struct drm_i915_private *dev_priv = dev->dev_private; |
2827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2828 | unsigned long flags; |
2847 | unsigned long flags; |
2829 | bool pending; |
2848 | bool pending; |
2830 | 2849 | ||
2831 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2850 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2832 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
2851 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
2833 | return false; |
2852 | return false; |
2834 | 2853 | ||
2835 | spin_lock_irqsave(&dev->event_lock, flags); |
2854 | spin_lock_irqsave(&dev->event_lock, flags); |
2836 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2855 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2837 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2856 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2838 | 2857 | ||
2839 | return pending; |
2858 | return pending; |
2840 | } |
2859 | } |
2841 | 2860 | ||
2842 | #if 0 |
2861 | #if 0 |
2843 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2862 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2844 | { |
2863 | { |
2845 | struct drm_device *dev = crtc->dev; |
2864 | struct drm_device *dev = crtc->dev; |
2846 | struct drm_i915_private *dev_priv = dev->dev_private; |
2865 | struct drm_i915_private *dev_priv = dev->dev_private; |
2847 | 2866 | ||
2848 | if (crtc->fb == NULL) |
2867 | if (crtc->fb == NULL) |
2849 | return; |
2868 | return; |
2850 | 2869 | ||
2851 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2870 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2852 | 2871 | ||
2853 | wait_event(dev_priv->pending_flip_queue, |
2872 | wait_event(dev_priv->pending_flip_queue, |
2854 | !intel_crtc_has_pending_flip(crtc)); |
2873 | !intel_crtc_has_pending_flip(crtc)); |
2855 | 2874 | ||
2856 | mutex_lock(&dev->struct_mutex); |
2875 | mutex_lock(&dev->struct_mutex); |
2857 | intel_finish_fb(crtc->fb); |
2876 | intel_finish_fb(crtc->fb); |
2858 | mutex_unlock(&dev->struct_mutex); |
2877 | mutex_unlock(&dev->struct_mutex); |
2859 | } |
2878 | } |
2860 | #endif |
2879 | #endif |
2861 | 2880 | ||
2862 | /* Program iCLKIP clock to the desired frequency */ |
2881 | /* Program iCLKIP clock to the desired frequency */ |
2863 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
2882 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
2864 | { |
2883 | { |
2865 | struct drm_device *dev = crtc->dev; |
2884 | struct drm_device *dev = crtc->dev; |
2866 | struct drm_i915_private *dev_priv = dev->dev_private; |
2885 | struct drm_i915_private *dev_priv = dev->dev_private; |
2867 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2886 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2868 | u32 temp; |
2887 | u32 temp; |
2869 | 2888 | ||
2870 | mutex_lock(&dev_priv->dpio_lock); |
2889 | mutex_lock(&dev_priv->dpio_lock); |
2871 | 2890 | ||
2872 | /* It is necessary to ungate the pixclk gate prior to programming |
2891 | /* It is necessary to ungate the pixclk gate prior to programming |
2873 | * the divisors, and gate it back when it is done. |
2892 | * the divisors, and gate it back when it is done. |
2874 | */ |
2893 | */ |
2875 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
2894 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
2876 | 2895 | ||
2877 | /* Disable SSCCTL */ |
2896 | /* Disable SSCCTL */ |
2878 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
2897 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
2879 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2898 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2880 | SBI_SSCCTL_DISABLE, |
2899 | SBI_SSCCTL_DISABLE, |
2881 | SBI_ICLK); |
2900 | SBI_ICLK); |
2882 | 2901 | ||
2883 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
2902 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
2884 | if (crtc->mode.clock == 20000) { |
2903 | if (crtc->mode.clock == 20000) { |
2885 | auxdiv = 1; |
2904 | auxdiv = 1; |
2886 | divsel = 0x41; |
2905 | divsel = 0x41; |
2887 | phaseinc = 0x20; |
2906 | phaseinc = 0x20; |
2888 | } else { |
2907 | } else { |
2889 | /* The iCLK virtual clock root frequency is in MHz, |
2908 | /* The iCLK virtual clock root frequency is in MHz, |
2890 | * but the crtc->mode.clock in in KHz. To get the divisors, |
2909 | * but the crtc->mode.clock in in KHz. To get the divisors, |
2891 | * it is necessary to divide one by another, so we |
2910 | * it is necessary to divide one by another, so we |
2892 | * convert the virtual clock precision to KHz here for higher |
2911 | * convert the virtual clock precision to KHz here for higher |
2893 | * precision. |
2912 | * precision. |
2894 | */ |
2913 | */ |
2895 | u32 iclk_virtual_root_freq = 172800 * 1000; |
2914 | u32 iclk_virtual_root_freq = 172800 * 1000; |
2896 | u32 iclk_pi_range = 64; |
2915 | u32 iclk_pi_range = 64; |
2897 | u32 desired_divisor, msb_divisor_value, pi_value; |
2916 | u32 desired_divisor, msb_divisor_value, pi_value; |
2898 | 2917 | ||
2899 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
2918 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); |
2900 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2919 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2901 | pi_value = desired_divisor % iclk_pi_range; |
2920 | pi_value = desired_divisor % iclk_pi_range; |
2902 | 2921 | ||
2903 | auxdiv = 0; |
2922 | auxdiv = 0; |
2904 | divsel = msb_divisor_value - 2; |
2923 | divsel = msb_divisor_value - 2; |
2905 | phaseinc = pi_value; |
2924 | phaseinc = pi_value; |
2906 | } |
2925 | } |
2907 | 2926 | ||
2908 | /* This should not happen with any sane values */ |
2927 | /* This should not happen with any sane values */ |
2909 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
2928 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
2910 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
2929 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
2911 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
2930 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
2912 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
2931 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
2913 | 2932 | ||
2914 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
2933 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
2915 | crtc->mode.clock, |
2934 | crtc->mode.clock, |
2916 | auxdiv, |
2935 | auxdiv, |
2917 | divsel, |
2936 | divsel, |
2918 | phasedir, |
2937 | phasedir, |
2919 | phaseinc); |
2938 | phaseinc); |
2920 | 2939 | ||
2921 | /* Program SSCDIVINTPHASE6 */ |
2940 | /* Program SSCDIVINTPHASE6 */ |
2922 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
2941 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
2923 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2942 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2924 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
2943 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
2925 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
2944 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
2926 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
2945 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
2927 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
2946 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
2928 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
2947 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
2929 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
2948 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
2930 | 2949 | ||
2931 | /* Program SSCAUXDIV */ |
2950 | /* Program SSCAUXDIV */ |
2932 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
2951 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
2933 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2952 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2934 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
2953 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
2935 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
2954 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
2936 | 2955 | ||
2937 | /* Enable modulator and associated divider */ |
2956 | /* Enable modulator and associated divider */ |
2938 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
2957 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
2939 | temp &= ~SBI_SSCCTL_DISABLE; |
2958 | temp &= ~SBI_SSCCTL_DISABLE; |
2940 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
2959 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
2941 | 2960 | ||
2942 | /* Wait for initialization time */ |
2961 | /* Wait for initialization time */ |
2943 | udelay(24); |
2962 | udelay(24); |
2944 | 2963 | ||
2945 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
2964 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
2946 | 2965 | ||
2947 | mutex_unlock(&dev_priv->dpio_lock); |
2966 | mutex_unlock(&dev_priv->dpio_lock); |
2948 | } |
2967 | } |
2949 | 2968 | ||
2950 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
2969 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
2951 | enum pipe pch_transcoder) |
2970 | enum pipe pch_transcoder) |
2952 | { |
2971 | { |
2953 | struct drm_device *dev = crtc->base.dev; |
2972 | struct drm_device *dev = crtc->base.dev; |
2954 | struct drm_i915_private *dev_priv = dev->dev_private; |
2973 | struct drm_i915_private *dev_priv = dev->dev_private; |
2955 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
2974 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
2956 | 2975 | ||
2957 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
2976 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
2958 | I915_READ(HTOTAL(cpu_transcoder))); |
2977 | I915_READ(HTOTAL(cpu_transcoder))); |
2959 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
2978 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
2960 | I915_READ(HBLANK(cpu_transcoder))); |
2979 | I915_READ(HBLANK(cpu_transcoder))); |
2961 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
2980 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
2962 | I915_READ(HSYNC(cpu_transcoder))); |
2981 | I915_READ(HSYNC(cpu_transcoder))); |
2963 | 2982 | ||
2964 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
2983 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
2965 | I915_READ(VTOTAL(cpu_transcoder))); |
2984 | I915_READ(VTOTAL(cpu_transcoder))); |
2966 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
2985 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
2967 | I915_READ(VBLANK(cpu_transcoder))); |
2986 | I915_READ(VBLANK(cpu_transcoder))); |
2968 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
2987 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
2969 | I915_READ(VSYNC(cpu_transcoder))); |
2988 | I915_READ(VSYNC(cpu_transcoder))); |
2970 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
2989 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
2971 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
2990 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
2972 | } |
2991 | } |
- | 2992 | ||
- | 2993 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
|
- | 2994 | { |
|
- | 2995 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2996 | uint32_t temp; |
|
- | 2997 | ||
- | 2998 | temp = I915_READ(SOUTH_CHICKEN1); |
|
- | 2999 | if (temp & FDI_BC_BIFURCATION_SELECT) |
|
- | 3000 | return; |
|
- | 3001 | ||
- | 3002 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
|
- | 3003 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
|
- | 3004 | ||
- | 3005 | temp |= FDI_BC_BIFURCATION_SELECT; |
|
- | 3006 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
|
- | 3007 | I915_WRITE(SOUTH_CHICKEN1, temp); |
|
- | 3008 | POSTING_READ(SOUTH_CHICKEN1); |
|
- | 3009 | } |
|
- | 3010 | ||
- | 3011 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
|
- | 3012 | { |
|
- | 3013 | struct drm_device *dev = intel_crtc->base.dev; |
|
- | 3014 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3015 | ||
- | 3016 | switch (intel_crtc->pipe) { |
|
- | 3017 | case PIPE_A: |
|
- | 3018 | break; |
|
- | 3019 | case PIPE_B: |
|
- | 3020 | if (intel_crtc->config.fdi_lanes > 2) |
|
- | 3021 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
|
- | 3022 | else |
|
- | 3023 | cpt_enable_fdi_bc_bifurcation(dev); |
|
- | 3024 | ||
- | 3025 | break; |
|
- | 3026 | case PIPE_C: |
|
- | 3027 | cpt_enable_fdi_bc_bifurcation(dev); |
|
- | 3028 | ||
- | 3029 | break; |
|
- | 3030 | default: |
|
- | 3031 | BUG(); |
|
- | 3032 | } |
|
- | 3033 | } |
|
2973 | 3034 | ||
2974 | /* |
3035 | /* |
2975 | * Enable PCH resources required for PCH ports: |
3036 | * Enable PCH resources required for PCH ports: |
2976 | * - PCH PLLs |
3037 | * - PCH PLLs |
2977 | * - FDI training & RX/TX |
3038 | * - FDI training & RX/TX |
2978 | * - update transcoder timings |
3039 | * - update transcoder timings |
2979 | * - DP transcoding bits |
3040 | * - DP transcoding bits |
2980 | * - transcoder |
3041 | * - transcoder |
2981 | */ |
3042 | */ |
2982 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
3043 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
2983 | { |
3044 | { |
2984 | struct drm_device *dev = crtc->dev; |
3045 | struct drm_device *dev = crtc->dev; |
2985 | struct drm_i915_private *dev_priv = dev->dev_private; |
3046 | struct drm_i915_private *dev_priv = dev->dev_private; |
2986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2987 | int pipe = intel_crtc->pipe; |
3048 | int pipe = intel_crtc->pipe; |
2988 | u32 reg, temp; |
3049 | u32 reg, temp; |
2989 | 3050 | ||
2990 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3051 | assert_pch_transcoder_disabled(dev_priv, pipe); |
- | 3052 | ||
- | 3053 | if (IS_IVYBRIDGE(dev)) |
|
- | 3054 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
|
2991 | 3055 | ||
2992 | /* Write the TU size bits before fdi link training, so that error |
3056 | /* Write the TU size bits before fdi link training, so that error |
2993 | * detection works. */ |
3057 | * detection works. */ |
2994 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
3058 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2995 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
3059 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
2996 | 3060 | ||
2997 | /* For PCH output, training FDI link */ |
3061 | /* For PCH output, training FDI link */ |
2998 | dev_priv->display.fdi_link_train(crtc); |
3062 | dev_priv->display.fdi_link_train(crtc); |
2999 | 3063 | ||
3000 | /* We need to program the right clock selection before writing the pixel |
3064 | /* We need to program the right clock selection before writing the pixel |
3001 | * mutliplier into the DPLL. */ |
3065 | * mutliplier into the DPLL. */ |
3002 | if (HAS_PCH_CPT(dev)) { |
3066 | if (HAS_PCH_CPT(dev)) { |
3003 | u32 sel; |
3067 | u32 sel; |
3004 | 3068 | ||
3005 | temp = I915_READ(PCH_DPLL_SEL); |
3069 | temp = I915_READ(PCH_DPLL_SEL); |
3006 | temp |= TRANS_DPLL_ENABLE(pipe); |
3070 | temp |= TRANS_DPLL_ENABLE(pipe); |
3007 | sel = TRANS_DPLLB_SEL(pipe); |
3071 | sel = TRANS_DPLLB_SEL(pipe); |
3008 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
3072 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
3009 | temp |= sel; |
3073 | temp |= sel; |
3010 | else |
3074 | else |
3011 | temp &= ~sel; |
3075 | temp &= ~sel; |
3012 | I915_WRITE(PCH_DPLL_SEL, temp); |
3076 | I915_WRITE(PCH_DPLL_SEL, temp); |
3013 | } |
3077 | } |
3014 | 3078 | ||
3015 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3079 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3016 | * transcoder, and we actually should do this to not upset any PCH |
3080 | * transcoder, and we actually should do this to not upset any PCH |
3017 | * transcoder that already use the clock when we share it. |
3081 | * transcoder that already use the clock when we share it. |
3018 | * |
3082 | * |
3019 | * Note that enable_shared_dpll tries to do the right thing, but |
3083 | * Note that enable_shared_dpll tries to do the right thing, but |
3020 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3084 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3021 | * the right LVDS enable sequence. */ |
3085 | * the right LVDS enable sequence. */ |
3022 | ironlake_enable_shared_dpll(intel_crtc); |
3086 | ironlake_enable_shared_dpll(intel_crtc); |
3023 | 3087 | ||
3024 | /* set transcoder timing, panel must allow it */ |
3088 | /* set transcoder timing, panel must allow it */ |
3025 | assert_panel_unlocked(dev_priv, pipe); |
3089 | assert_panel_unlocked(dev_priv, pipe); |
3026 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
3090 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
3027 | 3091 | ||
3028 | intel_fdi_normal_train(crtc); |
3092 | intel_fdi_normal_train(crtc); |
3029 | 3093 | ||
3030 | /* For PCH DP, enable TRANS_DP_CTL */ |
3094 | /* For PCH DP, enable TRANS_DP_CTL */ |
3031 | if (HAS_PCH_CPT(dev) && |
3095 | if (HAS_PCH_CPT(dev) && |
3032 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3096 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3033 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3097 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3034 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
3098 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
3035 | reg = TRANS_DP_CTL(pipe); |
3099 | reg = TRANS_DP_CTL(pipe); |
3036 | temp = I915_READ(reg); |
3100 | temp = I915_READ(reg); |
3037 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3101 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3038 | TRANS_DP_SYNC_MASK | |
3102 | TRANS_DP_SYNC_MASK | |
3039 | TRANS_DP_BPC_MASK); |
3103 | TRANS_DP_BPC_MASK); |
3040 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3104 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3041 | TRANS_DP_ENH_FRAMING); |
3105 | TRANS_DP_ENH_FRAMING); |
3042 | temp |= bpc << 9; /* same format but at 11:9 */ |
3106 | temp |= bpc << 9; /* same format but at 11:9 */ |
3043 | 3107 | ||
3044 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3108 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3045 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3109 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3046 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3110 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3047 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3111 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3048 | 3112 | ||
3049 | switch (intel_trans_dp_port_sel(crtc)) { |
3113 | switch (intel_trans_dp_port_sel(crtc)) { |
3050 | case PCH_DP_B: |
3114 | case PCH_DP_B: |
3051 | temp |= TRANS_DP_PORT_SEL_B; |
3115 | temp |= TRANS_DP_PORT_SEL_B; |
3052 | break; |
3116 | break; |
3053 | case PCH_DP_C: |
3117 | case PCH_DP_C: |
3054 | temp |= TRANS_DP_PORT_SEL_C; |
3118 | temp |= TRANS_DP_PORT_SEL_C; |
3055 | break; |
3119 | break; |
3056 | case PCH_DP_D: |
3120 | case PCH_DP_D: |
3057 | temp |= TRANS_DP_PORT_SEL_D; |
3121 | temp |= TRANS_DP_PORT_SEL_D; |
3058 | break; |
3122 | break; |
3059 | default: |
3123 | default: |
3060 | BUG(); |
3124 | BUG(); |
3061 | } |
3125 | } |
3062 | 3126 | ||
3063 | I915_WRITE(reg, temp); |
3127 | I915_WRITE(reg, temp); |
3064 | } |
3128 | } |
3065 | 3129 | ||
3066 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
3130 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
3067 | } |
3131 | } |
3068 | 3132 | ||
3069 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3133 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3070 | { |
3134 | { |
3071 | struct drm_device *dev = crtc->dev; |
3135 | struct drm_device *dev = crtc->dev; |
3072 | struct drm_i915_private *dev_priv = dev->dev_private; |
3136 | struct drm_i915_private *dev_priv = dev->dev_private; |
3073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3137 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3074 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3138 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3075 | 3139 | ||
3076 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3140 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3077 | 3141 | ||
3078 | lpt_program_iclkip(crtc); |
3142 | lpt_program_iclkip(crtc); |
3079 | 3143 | ||
3080 | /* Set transcoder timing. */ |
3144 | /* Set transcoder timing. */ |
3081 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3145 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3082 | 3146 | ||
3083 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3147 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3084 | } |
3148 | } |
3085 | 3149 | ||
3086 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3150 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3087 | { |
3151 | { |
3088 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3152 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3089 | 3153 | ||
3090 | if (pll == NULL) |
3154 | if (pll == NULL) |
3091 | return; |
3155 | return; |
3092 | 3156 | ||
3093 | if (pll->refcount == 0) { |
3157 | if (pll->refcount == 0) { |
3094 | WARN(1, "bad %s refcount\n", pll->name); |
3158 | WARN(1, "bad %s refcount\n", pll->name); |
3095 | return; |
3159 | return; |
3096 | } |
3160 | } |
3097 | 3161 | ||
3098 | if (--pll->refcount == 0) { |
3162 | if (--pll->refcount == 0) { |
3099 | WARN_ON(pll->on); |
3163 | WARN_ON(pll->on); |
3100 | WARN_ON(pll->active); |
3164 | WARN_ON(pll->active); |
3101 | } |
3165 | } |
3102 | 3166 | ||
3103 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3167 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3104 | } |
3168 | } |
3105 | 3169 | ||
3106 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3170 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3107 | { |
3171 | { |
3108 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3172 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3109 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3173 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3110 | enum intel_dpll_id i; |
3174 | enum intel_dpll_id i; |
3111 | 3175 | ||
3112 | if (pll) { |
3176 | if (pll) { |
3113 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3177 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3114 | crtc->base.base.id, pll->name); |
3178 | crtc->base.base.id, pll->name); |
3115 | intel_put_shared_dpll(crtc); |
3179 | intel_put_shared_dpll(crtc); |
3116 | } |
3180 | } |
3117 | 3181 | ||
3118 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3182 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3119 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3183 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3120 | i = (enum intel_dpll_id) crtc->pipe; |
3184 | i = (enum intel_dpll_id) crtc->pipe; |
3121 | pll = &dev_priv->shared_dplls[i]; |
3185 | pll = &dev_priv->shared_dplls[i]; |
3122 | 3186 | ||
3123 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3187 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3124 | crtc->base.base.id, pll->name); |
3188 | crtc->base.base.id, pll->name); |
3125 | 3189 | ||
3126 | goto found; |
3190 | goto found; |
3127 | } |
3191 | } |
3128 | 3192 | ||
3129 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3193 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3130 | pll = &dev_priv->shared_dplls[i]; |
3194 | pll = &dev_priv->shared_dplls[i]; |
3131 | 3195 | ||
3132 | /* Only want to check enabled timings first */ |
3196 | /* Only want to check enabled timings first */ |
3133 | if (pll->refcount == 0) |
3197 | if (pll->refcount == 0) |
3134 | continue; |
3198 | continue; |
3135 | 3199 | ||
3136 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3200 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3137 | sizeof(pll->hw_state)) == 0) { |
3201 | sizeof(pll->hw_state)) == 0) { |
3138 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
3202 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
3139 | crtc->base.base.id, |
3203 | crtc->base.base.id, |
3140 | pll->name, pll->refcount, pll->active); |
3204 | pll->name, pll->refcount, pll->active); |
3141 | 3205 | ||
3142 | goto found; |
3206 | goto found; |
3143 | } |
3207 | } |
3144 | } |
3208 | } |
3145 | 3209 | ||
3146 | /* Ok no matching timings, maybe there's a free one? */ |
3210 | /* Ok no matching timings, maybe there's a free one? */ |
3147 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3211 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3148 | pll = &dev_priv->shared_dplls[i]; |
3212 | pll = &dev_priv->shared_dplls[i]; |
3149 | if (pll->refcount == 0) { |
3213 | if (pll->refcount == 0) { |
3150 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3214 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3151 | crtc->base.base.id, pll->name); |
3215 | crtc->base.base.id, pll->name); |
3152 | goto found; |
3216 | goto found; |
3153 | } |
3217 | } |
3154 | } |
3218 | } |
3155 | 3219 | ||
3156 | return NULL; |
3220 | return NULL; |
3157 | 3221 | ||
3158 | found: |
3222 | found: |
3159 | crtc->config.shared_dpll = i; |
3223 | crtc->config.shared_dpll = i; |
3160 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3224 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3161 | pipe_name(crtc->pipe)); |
3225 | pipe_name(crtc->pipe)); |
3162 | 3226 | ||
3163 | if (pll->active == 0) { |
3227 | if (pll->active == 0) { |
3164 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3228 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3165 | sizeof(pll->hw_state)); |
3229 | sizeof(pll->hw_state)); |
3166 | 3230 | ||
3167 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
3231 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
3168 | WARN_ON(pll->on); |
3232 | WARN_ON(pll->on); |
3169 | assert_shared_dpll_disabled(dev_priv, pll); |
3233 | assert_shared_dpll_disabled(dev_priv, pll); |
3170 | 3234 | ||
3171 | pll->mode_set(dev_priv, pll); |
3235 | pll->mode_set(dev_priv, pll); |
3172 | } |
3236 | } |
3173 | pll->refcount++; |
3237 | pll->refcount++; |
3174 | 3238 | ||
3175 | return pll; |
3239 | return pll; |
3176 | } |
3240 | } |
3177 | 3241 | ||
3178 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
3242 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
3179 | { |
3243 | { |
3180 | struct drm_i915_private *dev_priv = dev->dev_private; |
3244 | struct drm_i915_private *dev_priv = dev->dev_private; |
3181 | int dslreg = PIPEDSL(pipe); |
3245 | int dslreg = PIPEDSL(pipe); |
3182 | u32 temp; |
3246 | u32 temp; |
3183 | 3247 | ||
3184 | temp = I915_READ(dslreg); |
3248 | temp = I915_READ(dslreg); |
3185 | udelay(500); |
3249 | udelay(500); |
3186 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3250 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3187 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3251 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3188 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
3252 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
3189 | } |
3253 | } |
3190 | } |
3254 | } |
3191 | 3255 | ||
3192 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3256 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3193 | { |
3257 | { |
3194 | struct drm_device *dev = crtc->base.dev; |
3258 | struct drm_device *dev = crtc->base.dev; |
3195 | struct drm_i915_private *dev_priv = dev->dev_private; |
3259 | struct drm_i915_private *dev_priv = dev->dev_private; |
3196 | int pipe = crtc->pipe; |
3260 | int pipe = crtc->pipe; |
3197 | 3261 | ||
3198 | if (crtc->config.pch_pfit.enabled) { |
3262 | if (crtc->config.pch_pfit.enabled) { |
3199 | /* Force use of hard-coded filter coefficients |
3263 | /* Force use of hard-coded filter coefficients |
3200 | * as some pre-programmed values are broken, |
3264 | * as some pre-programmed values are broken, |
3201 | * e.g. x201. |
3265 | * e.g. x201. |
3202 | */ |
3266 | */ |
3203 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
3267 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
3204 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3268 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3205 | PF_PIPE_SEL_IVB(pipe)); |
3269 | PF_PIPE_SEL_IVB(pipe)); |
3206 | else |
3270 | else |
3207 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3271 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3208 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
3272 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
3209 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
3273 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
3210 | } |
3274 | } |
3211 | } |
3275 | } |
3212 | 3276 | ||
3213 | static void intel_enable_planes(struct drm_crtc *crtc) |
3277 | static void intel_enable_planes(struct drm_crtc *crtc) |
3214 | { |
3278 | { |
3215 | struct drm_device *dev = crtc->dev; |
3279 | struct drm_device *dev = crtc->dev; |
3216 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3280 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3217 | struct intel_plane *intel_plane; |
3281 | struct intel_plane *intel_plane; |
3218 | 3282 | ||
3219 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3283 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3220 | if (intel_plane->pipe == pipe) |
3284 | if (intel_plane->pipe == pipe) |
3221 | intel_plane_restore(&intel_plane->base); |
3285 | intel_plane_restore(&intel_plane->base); |
3222 | } |
3286 | } |
3223 | 3287 | ||
3224 | static void intel_disable_planes(struct drm_crtc *crtc) |
3288 | static void intel_disable_planes(struct drm_crtc *crtc) |
3225 | { |
3289 | { |
3226 | struct drm_device *dev = crtc->dev; |
3290 | struct drm_device *dev = crtc->dev; |
3227 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3291 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
3228 | struct intel_plane *intel_plane; |
3292 | struct intel_plane *intel_plane; |
3229 | 3293 | ||
3230 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3294 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
3231 | if (intel_plane->pipe == pipe) |
3295 | if (intel_plane->pipe == pipe) |
3232 | intel_plane_disable(&intel_plane->base); |
3296 | intel_plane_disable(&intel_plane->base); |
3233 | } |
3297 | } |
3234 | 3298 | ||
3235 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3299 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3236 | { |
3300 | { |
3237 | struct drm_device *dev = crtc->dev; |
3301 | struct drm_device *dev = crtc->dev; |
3238 | struct drm_i915_private *dev_priv = dev->dev_private; |
3302 | struct drm_i915_private *dev_priv = dev->dev_private; |
3239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3303 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3240 | struct intel_encoder *encoder; |
3304 | struct intel_encoder *encoder; |
3241 | int pipe = intel_crtc->pipe; |
3305 | int pipe = intel_crtc->pipe; |
3242 | int plane = intel_crtc->plane; |
3306 | int plane = intel_crtc->plane; |
3243 | 3307 | ||
3244 | WARN_ON(!crtc->enabled); |
3308 | WARN_ON(!crtc->enabled); |
3245 | 3309 | ||
3246 | if (intel_crtc->active) |
3310 | if (intel_crtc->active) |
3247 | return; |
3311 | return; |
3248 | 3312 | ||
3249 | intel_crtc->active = true; |
3313 | intel_crtc->active = true; |
3250 | 3314 | ||
3251 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3315 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3252 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3316 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3253 | 3317 | ||
3254 | intel_update_watermarks(dev); |
3318 | intel_update_watermarks(dev); |
3255 | 3319 | ||
3256 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3320 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3257 | if (encoder->pre_enable) |
3321 | if (encoder->pre_enable) |
3258 | encoder->pre_enable(encoder); |
3322 | encoder->pre_enable(encoder); |
3259 | 3323 | ||
3260 | if (intel_crtc->config.has_pch_encoder) { |
3324 | if (intel_crtc->config.has_pch_encoder) { |
3261 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3325 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3262 | * cpu pipes, hence this is separate from all the other fdi/pch |
3326 | * cpu pipes, hence this is separate from all the other fdi/pch |
3263 | * enabling. */ |
3327 | * enabling. */ |
3264 | ironlake_fdi_pll_enable(intel_crtc); |
3328 | ironlake_fdi_pll_enable(intel_crtc); |
3265 | } else { |
3329 | } else { |
3266 | assert_fdi_tx_disabled(dev_priv, pipe); |
3330 | assert_fdi_tx_disabled(dev_priv, pipe); |
3267 | assert_fdi_rx_disabled(dev_priv, pipe); |
3331 | assert_fdi_rx_disabled(dev_priv, pipe); |
3268 | } |
3332 | } |
3269 | 3333 | ||
3270 | ironlake_pfit_enable(intel_crtc); |
3334 | ironlake_pfit_enable(intel_crtc); |
3271 | 3335 | ||
3272 | /* |
3336 | /* |
3273 | * On ILK+ LUT must be loaded before the pipe is running but with |
3337 | * On ILK+ LUT must be loaded before the pipe is running but with |
3274 | * clocks enabled |
3338 | * clocks enabled |
3275 | */ |
3339 | */ |
3276 | intel_crtc_load_lut(crtc); |
3340 | intel_crtc_load_lut(crtc); |
3277 | 3341 | ||
3278 | intel_enable_pipe(dev_priv, pipe, |
3342 | intel_enable_pipe(dev_priv, pipe, |
3279 | intel_crtc->config.has_pch_encoder); |
3343 | intel_crtc->config.has_pch_encoder); |
3280 | intel_enable_plane(dev_priv, plane, pipe); |
3344 | intel_enable_plane(dev_priv, plane, pipe); |
3281 | intel_enable_planes(crtc); |
3345 | intel_enable_planes(crtc); |
3282 | // intel_crtc_update_cursor(crtc, true); |
3346 | // intel_crtc_update_cursor(crtc, true); |
3283 | 3347 | ||
3284 | if (intel_crtc->config.has_pch_encoder) |
3348 | if (intel_crtc->config.has_pch_encoder) |
3285 | ironlake_pch_enable(crtc); |
3349 | ironlake_pch_enable(crtc); |
3286 | 3350 | ||
3287 | mutex_lock(&dev->struct_mutex); |
3351 | mutex_lock(&dev->struct_mutex); |
3288 | intel_update_fbc(dev); |
3352 | intel_update_fbc(dev); |
3289 | mutex_unlock(&dev->struct_mutex); |
3353 | mutex_unlock(&dev->struct_mutex); |
3290 | 3354 | ||
3291 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3355 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3292 | encoder->enable(encoder); |
3356 | encoder->enable(encoder); |
3293 | 3357 | ||
3294 | if (HAS_PCH_CPT(dev)) |
3358 | if (HAS_PCH_CPT(dev)) |
3295 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3359 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3296 | 3360 | ||
3297 | /* |
3361 | /* |
3298 | * There seems to be a race in PCH platform hw (at least on some |
3362 | * There seems to be a race in PCH platform hw (at least on some |
3299 | * outputs) where an enabled pipe still completes any pageflip right |
3363 | * outputs) where an enabled pipe still completes any pageflip right |
3300 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3364 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3301 | * as the first vblank happend, everything works as expected. Hence just |
3365 | * as the first vblank happend, everything works as expected. Hence just |
3302 | * wait for one vblank before returning to avoid strange things |
3366 | * wait for one vblank before returning to avoid strange things |
3303 | * happening. |
3367 | * happening. |
3304 | */ |
3368 | */ |
3305 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3369 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3306 | } |
3370 | } |
3307 | 3371 | ||
3308 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3372 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3309 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3373 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3310 | { |
3374 | { |
3311 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3375 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3312 | } |
3376 | } |
3313 | 3377 | ||
3314 | static void hsw_enable_ips(struct intel_crtc *crtc) |
3378 | static void hsw_enable_ips(struct intel_crtc *crtc) |
3315 | { |
3379 | { |
3316 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3380 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3317 | 3381 | ||
3318 | if (!crtc->config.ips_enabled) |
3382 | if (!crtc->config.ips_enabled) |
3319 | return; |
3383 | return; |
3320 | 3384 | ||
3321 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
3385 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
3322 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3386 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3323 | * only after intel_enable_plane. And intel_enable_plane already waits |
3387 | * only after intel_enable_plane. And intel_enable_plane already waits |
3324 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3388 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3325 | assert_plane_enabled(dev_priv, crtc->plane); |
3389 | assert_plane_enabled(dev_priv, crtc->plane); |
3326 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3390 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3327 | } |
3391 | } |
3328 | 3392 | ||
3329 | static void hsw_disable_ips(struct intel_crtc *crtc) |
3393 | static void hsw_disable_ips(struct intel_crtc *crtc) |
3330 | { |
3394 | { |
3331 | struct drm_device *dev = crtc->base.dev; |
3395 | struct drm_device *dev = crtc->base.dev; |
3332 | struct drm_i915_private *dev_priv = dev->dev_private; |
3396 | struct drm_i915_private *dev_priv = dev->dev_private; |
3333 | 3397 | ||
3334 | if (!crtc->config.ips_enabled) |
3398 | if (!crtc->config.ips_enabled) |
3335 | return; |
3399 | return; |
3336 | 3400 | ||
3337 | assert_plane_enabled(dev_priv, crtc->plane); |
3401 | assert_plane_enabled(dev_priv, crtc->plane); |
3338 | I915_WRITE(IPS_CTL, 0); |
3402 | I915_WRITE(IPS_CTL, 0); |
3339 | 3403 | ||
3340 | /* We need to wait for a vblank before we can disable the plane. */ |
3404 | /* We need to wait for a vblank before we can disable the plane. */ |
3341 | intel_wait_for_vblank(dev, crtc->pipe); |
3405 | intel_wait_for_vblank(dev, crtc->pipe); |
3342 | } |
3406 | } |
3343 | 3407 | ||
3344 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3408 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3345 | { |
3409 | { |
3346 | struct drm_device *dev = crtc->dev; |
3410 | struct drm_device *dev = crtc->dev; |
3347 | struct drm_i915_private *dev_priv = dev->dev_private; |
3411 | struct drm_i915_private *dev_priv = dev->dev_private; |
3348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3412 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3349 | struct intel_encoder *encoder; |
3413 | struct intel_encoder *encoder; |
3350 | int pipe = intel_crtc->pipe; |
3414 | int pipe = intel_crtc->pipe; |
3351 | int plane = intel_crtc->plane; |
3415 | int plane = intel_crtc->plane; |
3352 | 3416 | ||
3353 | WARN_ON(!crtc->enabled); |
3417 | WARN_ON(!crtc->enabled); |
3354 | 3418 | ||
3355 | if (intel_crtc->active) |
3419 | if (intel_crtc->active) |
3356 | return; |
3420 | return; |
3357 | 3421 | ||
3358 | intel_crtc->active = true; |
3422 | intel_crtc->active = true; |
3359 | 3423 | ||
3360 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3424 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3361 | if (intel_crtc->config.has_pch_encoder) |
3425 | if (intel_crtc->config.has_pch_encoder) |
3362 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3426 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3363 | 3427 | ||
3364 | intel_update_watermarks(dev); |
3428 | intel_update_watermarks(dev); |
3365 | 3429 | ||
3366 | if (intel_crtc->config.has_pch_encoder) |
3430 | if (intel_crtc->config.has_pch_encoder) |
3367 | dev_priv->display.fdi_link_train(crtc); |
3431 | dev_priv->display.fdi_link_train(crtc); |
3368 | 3432 | ||
3369 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3433 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3370 | if (encoder->pre_enable) |
3434 | if (encoder->pre_enable) |
3371 | encoder->pre_enable(encoder); |
3435 | encoder->pre_enable(encoder); |
3372 | 3436 | ||
3373 | intel_ddi_enable_pipe_clock(intel_crtc); |
3437 | intel_ddi_enable_pipe_clock(intel_crtc); |
3374 | 3438 | ||
3375 | ironlake_pfit_enable(intel_crtc); |
3439 | ironlake_pfit_enable(intel_crtc); |
3376 | 3440 | ||
3377 | /* |
3441 | /* |
3378 | * On ILK+ LUT must be loaded before the pipe is running but with |
3442 | * On ILK+ LUT must be loaded before the pipe is running but with |
3379 | * clocks enabled |
3443 | * clocks enabled |
3380 | */ |
3444 | */ |
3381 | intel_crtc_load_lut(crtc); |
3445 | intel_crtc_load_lut(crtc); |
3382 | 3446 | ||
3383 | intel_ddi_set_pipe_settings(crtc); |
3447 | intel_ddi_set_pipe_settings(crtc); |
3384 | intel_ddi_enable_transcoder_func(crtc); |
3448 | intel_ddi_enable_transcoder_func(crtc); |
3385 | 3449 | ||
3386 | intel_enable_pipe(dev_priv, pipe, |
3450 | intel_enable_pipe(dev_priv, pipe, |
3387 | intel_crtc->config.has_pch_encoder); |
3451 | intel_crtc->config.has_pch_encoder); |
3388 | intel_enable_plane(dev_priv, plane, pipe); |
3452 | intel_enable_plane(dev_priv, plane, pipe); |
3389 | intel_enable_planes(crtc); |
3453 | intel_enable_planes(crtc); |
3390 | // intel_crtc_update_cursor(crtc, true); |
3454 | // intel_crtc_update_cursor(crtc, true); |
3391 | 3455 | ||
3392 | hsw_enable_ips(intel_crtc); |
3456 | hsw_enable_ips(intel_crtc); |
3393 | 3457 | ||
3394 | if (intel_crtc->config.has_pch_encoder) |
3458 | if (intel_crtc->config.has_pch_encoder) |
3395 | lpt_pch_enable(crtc); |
3459 | lpt_pch_enable(crtc); |
3396 | 3460 | ||
3397 | mutex_lock(&dev->struct_mutex); |
3461 | mutex_lock(&dev->struct_mutex); |
3398 | intel_update_fbc(dev); |
3462 | intel_update_fbc(dev); |
3399 | mutex_unlock(&dev->struct_mutex); |
3463 | mutex_unlock(&dev->struct_mutex); |
3400 | 3464 | ||
3401 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3465 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3402 | encoder->enable(encoder); |
3466 | encoder->enable(encoder); |
3403 | 3467 | ||
3404 | /* |
3468 | /* |
3405 | * There seems to be a race in PCH platform hw (at least on some |
3469 | * There seems to be a race in PCH platform hw (at least on some |
3406 | * outputs) where an enabled pipe still completes any pageflip right |
3470 | * outputs) where an enabled pipe still completes any pageflip right |
3407 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3471 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3408 | * as the first vblank happend, everything works as expected. Hence just |
3472 | * as the first vblank happend, everything works as expected. Hence just |
3409 | * wait for one vblank before returning to avoid strange things |
3473 | * wait for one vblank before returning to avoid strange things |
3410 | * happening. |
3474 | * happening. |
3411 | */ |
3475 | */ |
3412 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3476 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3413 | } |
3477 | } |
3414 | 3478 | ||
3415 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3479 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3416 | { |
3480 | { |
3417 | struct drm_device *dev = crtc->base.dev; |
3481 | struct drm_device *dev = crtc->base.dev; |
3418 | struct drm_i915_private *dev_priv = dev->dev_private; |
3482 | struct drm_i915_private *dev_priv = dev->dev_private; |
3419 | int pipe = crtc->pipe; |
3483 | int pipe = crtc->pipe; |
3420 | 3484 | ||
3421 | /* To avoid upsetting the power well on haswell only disable the pfit if |
3485 | /* To avoid upsetting the power well on haswell only disable the pfit if |
3422 | * it's in use. The hw state code will make sure we get this right. */ |
3486 | * it's in use. The hw state code will make sure we get this right. */ |
3423 | if (crtc->config.pch_pfit.enabled) { |
3487 | if (crtc->config.pch_pfit.enabled) { |
3424 | I915_WRITE(PF_CTL(pipe), 0); |
3488 | I915_WRITE(PF_CTL(pipe), 0); |
3425 | I915_WRITE(PF_WIN_POS(pipe), 0); |
3489 | I915_WRITE(PF_WIN_POS(pipe), 0); |
3426 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3490 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3427 | } |
3491 | } |
3428 | } |
3492 | } |
3429 | 3493 | ||
3430 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3494 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3431 | { |
3495 | { |
3432 | struct drm_device *dev = crtc->dev; |
3496 | struct drm_device *dev = crtc->dev; |
3433 | struct drm_i915_private *dev_priv = dev->dev_private; |
3497 | struct drm_i915_private *dev_priv = dev->dev_private; |
3434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3435 | struct intel_encoder *encoder; |
3499 | struct intel_encoder *encoder; |
3436 | int pipe = intel_crtc->pipe; |
3500 | int pipe = intel_crtc->pipe; |
3437 | int plane = intel_crtc->plane; |
3501 | int plane = intel_crtc->plane; |
3438 | u32 reg, temp; |
3502 | u32 reg, temp; |
3439 | 3503 | ||
3440 | 3504 | ||
3441 | if (!intel_crtc->active) |
3505 | if (!intel_crtc->active) |
3442 | return; |
3506 | return; |
3443 | 3507 | ||
3444 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3508 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3445 | encoder->disable(encoder); |
3509 | encoder->disable(encoder); |
3446 | 3510 | ||
3447 | // intel_crtc_wait_for_pending_flips(crtc); |
3511 | // intel_crtc_wait_for_pending_flips(crtc); |
3448 | // drm_vblank_off(dev, pipe); |
3512 | // drm_vblank_off(dev, pipe); |
3449 | 3513 | ||
3450 | if (dev_priv->fbc.plane == plane) |
3514 | if (dev_priv->fbc.plane == plane) |
3451 | intel_disable_fbc(dev); |
3515 | intel_disable_fbc(dev); |
3452 | 3516 | ||
3453 | // intel_crtc_update_cursor(crtc, false); |
3517 | // intel_crtc_update_cursor(crtc, false); |
3454 | intel_disable_planes(crtc); |
3518 | intel_disable_planes(crtc); |
3455 | intel_disable_plane(dev_priv, plane, pipe); |
3519 | intel_disable_plane(dev_priv, plane, pipe); |
3456 | 3520 | ||
3457 | if (intel_crtc->config.has_pch_encoder) |
3521 | if (intel_crtc->config.has_pch_encoder) |
3458 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
3522 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
3459 | 3523 | ||
3460 | intel_disable_pipe(dev_priv, pipe); |
3524 | intel_disable_pipe(dev_priv, pipe); |
3461 | 3525 | ||
3462 | ironlake_pfit_disable(intel_crtc); |
3526 | ironlake_pfit_disable(intel_crtc); |
3463 | 3527 | ||
3464 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3528 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3465 | if (encoder->post_disable) |
3529 | if (encoder->post_disable) |
3466 | encoder->post_disable(encoder); |
3530 | encoder->post_disable(encoder); |
3467 | 3531 | ||
3468 | if (intel_crtc->config.has_pch_encoder) { |
3532 | if (intel_crtc->config.has_pch_encoder) { |
3469 | ironlake_fdi_disable(crtc); |
3533 | ironlake_fdi_disable(crtc); |
3470 | 3534 | ||
3471 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3535 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3472 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3536 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3473 | 3537 | ||
3474 | if (HAS_PCH_CPT(dev)) { |
3538 | if (HAS_PCH_CPT(dev)) { |
3475 | /* disable TRANS_DP_CTL */ |
3539 | /* disable TRANS_DP_CTL */ |
3476 | reg = TRANS_DP_CTL(pipe); |
3540 | reg = TRANS_DP_CTL(pipe); |
3477 | temp = I915_READ(reg); |
3541 | temp = I915_READ(reg); |
3478 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
3542 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
3479 | TRANS_DP_PORT_SEL_MASK); |
3543 | TRANS_DP_PORT_SEL_MASK); |
3480 | temp |= TRANS_DP_PORT_SEL_NONE; |
3544 | temp |= TRANS_DP_PORT_SEL_NONE; |
3481 | I915_WRITE(reg, temp); |
3545 | I915_WRITE(reg, temp); |
3482 | 3546 | ||
3483 | /* disable DPLL_SEL */ |
3547 | /* disable DPLL_SEL */ |
3484 | temp = I915_READ(PCH_DPLL_SEL); |
3548 | temp = I915_READ(PCH_DPLL_SEL); |
3485 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
3549 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
3486 | I915_WRITE(PCH_DPLL_SEL, temp); |
3550 | I915_WRITE(PCH_DPLL_SEL, temp); |
3487 | } |
3551 | } |
3488 | 3552 | ||
3489 | /* disable PCH DPLL */ |
3553 | /* disable PCH DPLL */ |
3490 | intel_disable_shared_dpll(intel_crtc); |
3554 | intel_disable_shared_dpll(intel_crtc); |
3491 | 3555 | ||
3492 | ironlake_fdi_pll_disable(intel_crtc); |
3556 | ironlake_fdi_pll_disable(intel_crtc); |
3493 | } |
3557 | } |
3494 | 3558 | ||
3495 | intel_crtc->active = false; |
3559 | intel_crtc->active = false; |
3496 | intel_update_watermarks(dev); |
3560 | intel_update_watermarks(dev); |
3497 | 3561 | ||
3498 | mutex_lock(&dev->struct_mutex); |
3562 | mutex_lock(&dev->struct_mutex); |
3499 | intel_update_fbc(dev); |
3563 | intel_update_fbc(dev); |
3500 | mutex_unlock(&dev->struct_mutex); |
3564 | mutex_unlock(&dev->struct_mutex); |
3501 | } |
3565 | } |
3502 | 3566 | ||
3503 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
3567 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
3504 | { |
3568 | { |
3505 | struct drm_device *dev = crtc->dev; |
3569 | struct drm_device *dev = crtc->dev; |
3506 | struct drm_i915_private *dev_priv = dev->dev_private; |
3570 | struct drm_i915_private *dev_priv = dev->dev_private; |
3507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3571 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3508 | struct intel_encoder *encoder; |
3572 | struct intel_encoder *encoder; |
3509 | int pipe = intel_crtc->pipe; |
3573 | int pipe = intel_crtc->pipe; |
3510 | int plane = intel_crtc->plane; |
3574 | int plane = intel_crtc->plane; |
3511 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3575 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3512 | 3576 | ||
3513 | if (!intel_crtc->active) |
3577 | if (!intel_crtc->active) |
3514 | return; |
3578 | return; |
3515 | 3579 | ||
3516 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3580 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3517 | encoder->disable(encoder); |
3581 | encoder->disable(encoder); |
3518 | 3582 | ||
3519 | 3583 | ||
3520 | /* FBC must be disabled before disabling the plane on HSW. */ |
3584 | /* FBC must be disabled before disabling the plane on HSW. */ |
3521 | if (dev_priv->fbc.plane == plane) |
3585 | if (dev_priv->fbc.plane == plane) |
3522 | intel_disable_fbc(dev); |
3586 | intel_disable_fbc(dev); |
3523 | 3587 | ||
3524 | hsw_disable_ips(intel_crtc); |
3588 | hsw_disable_ips(intel_crtc); |
3525 | 3589 | ||
3526 | // intel_crtc_update_cursor(crtc, false); |
3590 | // intel_crtc_update_cursor(crtc, false); |
3527 | intel_disable_planes(crtc); |
3591 | intel_disable_planes(crtc); |
3528 | intel_disable_plane(dev_priv, plane, pipe); |
3592 | intel_disable_plane(dev_priv, plane, pipe); |
3529 | 3593 | ||
3530 | if (intel_crtc->config.has_pch_encoder) |
3594 | if (intel_crtc->config.has_pch_encoder) |
3531 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
3595 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
3532 | intel_disable_pipe(dev_priv, pipe); |
3596 | intel_disable_pipe(dev_priv, pipe); |
3533 | 3597 | ||
3534 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
3598 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
3535 | 3599 | ||
3536 | ironlake_pfit_disable(intel_crtc); |
3600 | ironlake_pfit_disable(intel_crtc); |
3537 | 3601 | ||
3538 | intel_ddi_disable_pipe_clock(intel_crtc); |
3602 | intel_ddi_disable_pipe_clock(intel_crtc); |
3539 | 3603 | ||
3540 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3604 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3541 | if (encoder->post_disable) |
3605 | if (encoder->post_disable) |
3542 | encoder->post_disable(encoder); |
3606 | encoder->post_disable(encoder); |
3543 | 3607 | ||
3544 | if (intel_crtc->config.has_pch_encoder) { |
3608 | if (intel_crtc->config.has_pch_encoder) { |
3545 | lpt_disable_pch_transcoder(dev_priv); |
3609 | lpt_disable_pch_transcoder(dev_priv); |
3546 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3610 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3547 | intel_ddi_fdi_disable(crtc); |
3611 | intel_ddi_fdi_disable(crtc); |
3548 | } |
3612 | } |
3549 | 3613 | ||
3550 | intel_crtc->active = false; |
3614 | intel_crtc->active = false; |
3551 | intel_update_watermarks(dev); |
3615 | intel_update_watermarks(dev); |
3552 | 3616 | ||
3553 | mutex_lock(&dev->struct_mutex); |
3617 | mutex_lock(&dev->struct_mutex); |
3554 | intel_update_fbc(dev); |
3618 | intel_update_fbc(dev); |
3555 | mutex_unlock(&dev->struct_mutex); |
3619 | mutex_unlock(&dev->struct_mutex); |
3556 | } |
3620 | } |
3557 | 3621 | ||
3558 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3622 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3559 | { |
3623 | { |
3560 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3561 | intel_put_shared_dpll(intel_crtc); |
3625 | intel_put_shared_dpll(intel_crtc); |
3562 | } |
3626 | } |
3563 | 3627 | ||
3564 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3628 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3565 | { |
3629 | { |
3566 | intel_ddi_put_crtc_pll(crtc); |
3630 | intel_ddi_put_crtc_pll(crtc); |
3567 | } |
3631 | } |
3568 | 3632 | ||
3569 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3633 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3570 | { |
3634 | { |
3571 | if (!enable && intel_crtc->overlay) { |
3635 | if (!enable && intel_crtc->overlay) { |
3572 | struct drm_device *dev = intel_crtc->base.dev; |
3636 | struct drm_device *dev = intel_crtc->base.dev; |
3573 | struct drm_i915_private *dev_priv = dev->dev_private; |
3637 | struct drm_i915_private *dev_priv = dev->dev_private; |
3574 | 3638 | ||
3575 | mutex_lock(&dev->struct_mutex); |
3639 | mutex_lock(&dev->struct_mutex); |
3576 | dev_priv->mm.interruptible = false; |
3640 | dev_priv->mm.interruptible = false; |
3577 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
3641 | // (void) intel_overlay_switch_off(intel_crtc->overlay); |
3578 | dev_priv->mm.interruptible = true; |
3642 | dev_priv->mm.interruptible = true; |
3579 | mutex_unlock(&dev->struct_mutex); |
3643 | mutex_unlock(&dev->struct_mutex); |
3580 | } |
3644 | } |
3581 | 3645 | ||
3582 | /* Let userspace switch the overlay on again. In most cases userspace |
3646 | /* Let userspace switch the overlay on again. In most cases userspace |
3583 | * has to recompute where to put it anyway. |
3647 | * has to recompute where to put it anyway. |
3584 | */ |
3648 | */ |
3585 | } |
3649 | } |
3586 | 3650 | ||
3587 | /** |
3651 | /** |
3588 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
3652 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
3589 | * cursor plane briefly if not already running after enabling the display |
3653 | * cursor plane briefly if not already running after enabling the display |
3590 | * plane. |
3654 | * plane. |
3591 | * This workaround avoids occasional blank screens when self refresh is |
3655 | * This workaround avoids occasional blank screens when self refresh is |
3592 | * enabled. |
3656 | * enabled. |
3593 | */ |
3657 | */ |
3594 | static void |
3658 | static void |
3595 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
3659 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
3596 | { |
3660 | { |
3597 | u32 cntl = I915_READ(CURCNTR(pipe)); |
3661 | u32 cntl = I915_READ(CURCNTR(pipe)); |
3598 | 3662 | ||
3599 | if ((cntl & CURSOR_MODE) == 0) { |
3663 | if ((cntl & CURSOR_MODE) == 0) { |
3600 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
3664 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
3601 | 3665 | ||
3602 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
3666 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
3603 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
3667 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
3604 | intel_wait_for_vblank(dev_priv->dev, pipe); |
3668 | intel_wait_for_vblank(dev_priv->dev, pipe); |
3605 | I915_WRITE(CURCNTR(pipe), cntl); |
3669 | I915_WRITE(CURCNTR(pipe), cntl); |
3606 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
3670 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
3607 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
3671 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
3608 | } |
3672 | } |
3609 | } |
3673 | } |
3610 | 3674 | ||
3611 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3675 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3612 | { |
3676 | { |
3613 | struct drm_device *dev = crtc->base.dev; |
3677 | struct drm_device *dev = crtc->base.dev; |
3614 | struct drm_i915_private *dev_priv = dev->dev_private; |
3678 | struct drm_i915_private *dev_priv = dev->dev_private; |
3615 | struct intel_crtc_config *pipe_config = &crtc->config; |
3679 | struct intel_crtc_config *pipe_config = &crtc->config; |
3616 | 3680 | ||
3617 | if (!crtc->config.gmch_pfit.control) |
3681 | if (!crtc->config.gmch_pfit.control) |
3618 | return; |
3682 | return; |
3619 | 3683 | ||
3620 | /* |
3684 | /* |
3621 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3685 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3622 | * according to register description and PRM. |
3686 | * according to register description and PRM. |
3623 | */ |
3687 | */ |
3624 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3688 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3625 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3689 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3626 | 3690 | ||
3627 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3691 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3628 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
3692 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
3629 | 3693 | ||
3630 | /* Border color in case we don't scale up to the full screen. Black by |
3694 | /* Border color in case we don't scale up to the full screen. Black by |
3631 | * default, change to something else for debugging. */ |
3695 | * default, change to something else for debugging. */ |
3632 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3696 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3633 | } |
3697 | } |
3634 | 3698 | ||
3635 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3699 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3636 | { |
3700 | { |
3637 | struct drm_device *dev = crtc->dev; |
3701 | struct drm_device *dev = crtc->dev; |
3638 | struct drm_i915_private *dev_priv = dev->dev_private; |
3702 | struct drm_i915_private *dev_priv = dev->dev_private; |
3639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3640 | struct intel_encoder *encoder; |
3704 | struct intel_encoder *encoder; |
3641 | int pipe = intel_crtc->pipe; |
3705 | int pipe = intel_crtc->pipe; |
3642 | int plane = intel_crtc->plane; |
3706 | int plane = intel_crtc->plane; |
3643 | 3707 | ||
3644 | WARN_ON(!crtc->enabled); |
3708 | WARN_ON(!crtc->enabled); |
3645 | 3709 | ||
3646 | if (intel_crtc->active) |
3710 | if (intel_crtc->active) |
3647 | return; |
3711 | return; |
3648 | 3712 | ||
3649 | intel_crtc->active = true; |
3713 | intel_crtc->active = true; |
3650 | intel_update_watermarks(dev); |
3714 | intel_update_watermarks(dev); |
3651 | 3715 | ||
3652 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3716 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3653 | if (encoder->pre_pll_enable) |
3717 | if (encoder->pre_pll_enable) |
3654 | encoder->pre_pll_enable(encoder); |
3718 | encoder->pre_pll_enable(encoder); |
3655 | 3719 | ||
3656 | vlv_enable_pll(intel_crtc); |
3720 | vlv_enable_pll(intel_crtc); |
3657 | 3721 | ||
3658 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3722 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3659 | if (encoder->pre_enable) |
3723 | if (encoder->pre_enable) |
3660 | encoder->pre_enable(encoder); |
3724 | encoder->pre_enable(encoder); |
3661 | 3725 | ||
3662 | i9xx_pfit_enable(intel_crtc); |
3726 | i9xx_pfit_enable(intel_crtc); |
3663 | 3727 | ||
3664 | intel_crtc_load_lut(crtc); |
3728 | intel_crtc_load_lut(crtc); |
3665 | 3729 | ||
3666 | intel_enable_pipe(dev_priv, pipe, false); |
3730 | intel_enable_pipe(dev_priv, pipe, false); |
3667 | intel_enable_plane(dev_priv, plane, pipe); |
3731 | intel_enable_plane(dev_priv, plane, pipe); |
3668 | intel_enable_planes(crtc); |
3732 | intel_enable_planes(crtc); |
3669 | // intel_crtc_update_cursor(crtc, true); |
3733 | // intel_crtc_update_cursor(crtc, true); |
3670 | 3734 | ||
3671 | intel_update_fbc(dev); |
3735 | intel_update_fbc(dev); |
3672 | 3736 | ||
3673 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3737 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3674 | encoder->enable(encoder); |
3738 | encoder->enable(encoder); |
3675 | } |
3739 | } |
3676 | 3740 | ||
3677 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
3741 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
3678 | { |
3742 | { |
3679 | struct drm_device *dev = crtc->dev; |
3743 | struct drm_device *dev = crtc->dev; |
3680 | struct drm_i915_private *dev_priv = dev->dev_private; |
3744 | struct drm_i915_private *dev_priv = dev->dev_private; |
3681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3745 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3682 | struct intel_encoder *encoder; |
3746 | struct intel_encoder *encoder; |
3683 | int pipe = intel_crtc->pipe; |
3747 | int pipe = intel_crtc->pipe; |
3684 | int plane = intel_crtc->plane; |
3748 | int plane = intel_crtc->plane; |
3685 | 3749 | ||
3686 | WARN_ON(!crtc->enabled); |
3750 | WARN_ON(!crtc->enabled); |
3687 | 3751 | ||
3688 | if (intel_crtc->active) |
3752 | if (intel_crtc->active) |
3689 | return; |
3753 | return; |
3690 | 3754 | ||
3691 | intel_crtc->active = true; |
3755 | intel_crtc->active = true; |
3692 | intel_update_watermarks(dev); |
3756 | intel_update_watermarks(dev); |
3693 | 3757 | ||
3694 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3758 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3695 | if (encoder->pre_enable) |
3759 | if (encoder->pre_enable) |
3696 | encoder->pre_enable(encoder); |
3760 | encoder->pre_enable(encoder); |
3697 | 3761 | ||
3698 | i9xx_enable_pll(intel_crtc); |
3762 | i9xx_enable_pll(intel_crtc); |
3699 | 3763 | ||
3700 | i9xx_pfit_enable(intel_crtc); |
3764 | i9xx_pfit_enable(intel_crtc); |
3701 | 3765 | ||
3702 | intel_crtc_load_lut(crtc); |
3766 | intel_crtc_load_lut(crtc); |
3703 | 3767 | ||
3704 | intel_enable_pipe(dev_priv, pipe, false); |
3768 | intel_enable_pipe(dev_priv, pipe, false); |
3705 | intel_enable_plane(dev_priv, plane, pipe); |
3769 | intel_enable_plane(dev_priv, plane, pipe); |
3706 | intel_enable_planes(crtc); |
3770 | intel_enable_planes(crtc); |
3707 | /* The fixup needs to happen before cursor is enabled */ |
3771 | /* The fixup needs to happen before cursor is enabled */ |
3708 | if (IS_G4X(dev)) |
3772 | if (IS_G4X(dev)) |
3709 | g4x_fixup_plane(dev_priv, pipe); |
3773 | g4x_fixup_plane(dev_priv, pipe); |
3710 | // intel_crtc_update_cursor(crtc, true); |
3774 | // intel_crtc_update_cursor(crtc, true); |
3711 | 3775 | ||
3712 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3776 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3713 | intel_crtc_dpms_overlay(intel_crtc, true); |
3777 | intel_crtc_dpms_overlay(intel_crtc, true); |
3714 | 3778 | ||
3715 | intel_update_fbc(dev); |
3779 | intel_update_fbc(dev); |
3716 | 3780 | ||
3717 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3781 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3718 | encoder->enable(encoder); |
3782 | encoder->enable(encoder); |
3719 | } |
3783 | } |
3720 | 3784 | ||
3721 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3785 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3722 | { |
3786 | { |
3723 | struct drm_device *dev = crtc->base.dev; |
3787 | struct drm_device *dev = crtc->base.dev; |
3724 | struct drm_i915_private *dev_priv = dev->dev_private; |
3788 | struct drm_i915_private *dev_priv = dev->dev_private; |
3725 | 3789 | ||
3726 | if (!crtc->config.gmch_pfit.control) |
3790 | if (!crtc->config.gmch_pfit.control) |
3727 | return; |
3791 | return; |
3728 | 3792 | ||
3729 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3793 | assert_pipe_disabled(dev_priv, crtc->pipe); |
3730 | 3794 | ||
3731 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3795 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3732 | I915_READ(PFIT_CONTROL)); |
3796 | I915_READ(PFIT_CONTROL)); |
3733 | I915_WRITE(PFIT_CONTROL, 0); |
3797 | I915_WRITE(PFIT_CONTROL, 0); |
3734 | } |
3798 | } |
3735 | 3799 | ||
3736 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3800 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3737 | { |
3801 | { |
3738 | struct drm_device *dev = crtc->dev; |
3802 | struct drm_device *dev = crtc->dev; |
3739 | struct drm_i915_private *dev_priv = dev->dev_private; |
3803 | struct drm_i915_private *dev_priv = dev->dev_private; |
3740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3804 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3741 | struct intel_encoder *encoder; |
3805 | struct intel_encoder *encoder; |
3742 | int pipe = intel_crtc->pipe; |
3806 | int pipe = intel_crtc->pipe; |
3743 | int plane = intel_crtc->plane; |
3807 | int plane = intel_crtc->plane; |
3744 | 3808 | ||
3745 | if (!intel_crtc->active) |
3809 | if (!intel_crtc->active) |
3746 | return; |
3810 | return; |
3747 | 3811 | ||
3748 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3812 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3749 | encoder->disable(encoder); |
3813 | encoder->disable(encoder); |
3750 | 3814 | ||
3751 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3815 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
3752 | // intel_crtc_wait_for_pending_flips(crtc); |
3816 | // intel_crtc_wait_for_pending_flips(crtc); |
3753 | // drm_vblank_off(dev, pipe); |
3817 | // drm_vblank_off(dev, pipe); |
3754 | 3818 | ||
3755 | if (dev_priv->fbc.plane == plane) |
3819 | if (dev_priv->fbc.plane == plane) |
3756 | intel_disable_fbc(dev); |
3820 | intel_disable_fbc(dev); |
3757 | 3821 | ||
3758 | intel_crtc_dpms_overlay(intel_crtc, false); |
3822 | intel_crtc_dpms_overlay(intel_crtc, false); |
3759 | // intel_crtc_update_cursor(crtc, false); |
3823 | // intel_crtc_update_cursor(crtc, false); |
3760 | intel_disable_planes(crtc); |
3824 | intel_disable_planes(crtc); |
3761 | intel_disable_plane(dev_priv, plane, pipe); |
3825 | intel_disable_plane(dev_priv, plane, pipe); |
3762 | 3826 | ||
3763 | intel_disable_pipe(dev_priv, pipe); |
3827 | intel_disable_pipe(dev_priv, pipe); |
3764 | 3828 | ||
3765 | i9xx_pfit_disable(intel_crtc); |
3829 | i9xx_pfit_disable(intel_crtc); |
3766 | 3830 | ||
3767 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3831 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3768 | if (encoder->post_disable) |
3832 | if (encoder->post_disable) |
3769 | encoder->post_disable(encoder); |
3833 | encoder->post_disable(encoder); |
3770 | 3834 | ||
3771 | i9xx_disable_pll(dev_priv, pipe); |
3835 | i9xx_disable_pll(dev_priv, pipe); |
3772 | 3836 | ||
3773 | intel_crtc->active = false; |
3837 | intel_crtc->active = false; |
3774 | intel_update_fbc(dev); |
3838 | intel_update_fbc(dev); |
3775 | intel_update_watermarks(dev); |
3839 | intel_update_watermarks(dev); |
3776 | } |
3840 | } |
3777 | 3841 | ||
3778 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3842 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3779 | { |
3843 | { |
3780 | } |
3844 | } |
3781 | 3845 | ||
3782 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3846 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3783 | bool enabled) |
3847 | bool enabled) |
3784 | { |
3848 | { |
3785 | struct drm_device *dev = crtc->dev; |
3849 | struct drm_device *dev = crtc->dev; |
3786 | struct drm_i915_master_private *master_priv; |
3850 | struct drm_i915_master_private *master_priv; |
3787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3788 | int pipe = intel_crtc->pipe; |
3852 | int pipe = intel_crtc->pipe; |
3789 | 3853 | ||
3790 | 3854 | ||
3791 | #if 0 |
3855 | #if 0 |
3792 | if (!dev->primary->master) |
3856 | if (!dev->primary->master) |
3793 | return; |
3857 | return; |
3794 | 3858 | ||
3795 | master_priv = dev->primary->master->driver_priv; |
3859 | master_priv = dev->primary->master->driver_priv; |
3796 | if (!master_priv->sarea_priv) |
3860 | if (!master_priv->sarea_priv) |
3797 | return; |
3861 | return; |
3798 | 3862 | ||
3799 | switch (pipe) { |
3863 | switch (pipe) { |
3800 | case 0: |
3864 | case 0: |
3801 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
3865 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
3802 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
3866 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
3803 | break; |
3867 | break; |
3804 | case 1: |
3868 | case 1: |
3805 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
3869 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
3806 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
3870 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
3807 | break; |
3871 | break; |
3808 | default: |
3872 | default: |
3809 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
3873 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
3810 | break; |
3874 | break; |
3811 | } |
3875 | } |
3812 | #endif |
3876 | #endif |
3813 | 3877 | ||
3814 | } |
3878 | } |
3815 | 3879 | ||
3816 | /** |
3880 | /** |
3817 | * Sets the power management mode of the pipe and plane. |
3881 | * Sets the power management mode of the pipe and plane. |
3818 | */ |
3882 | */ |
3819 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
3883 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
3820 | { |
3884 | { |
3821 | struct drm_device *dev = crtc->dev; |
3885 | struct drm_device *dev = crtc->dev; |
3822 | struct drm_i915_private *dev_priv = dev->dev_private; |
3886 | struct drm_i915_private *dev_priv = dev->dev_private; |
3823 | struct intel_encoder *intel_encoder; |
3887 | struct intel_encoder *intel_encoder; |
3824 | bool enable = false; |
3888 | bool enable = false; |
3825 | 3889 | ||
3826 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
3890 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
3827 | enable |= intel_encoder->connectors_active; |
3891 | enable |= intel_encoder->connectors_active; |
3828 | 3892 | ||
3829 | if (enable) |
3893 | if (enable) |
3830 | dev_priv->display.crtc_enable(crtc); |
3894 | dev_priv->display.crtc_enable(crtc); |
3831 | else |
3895 | else |
3832 | dev_priv->display.crtc_disable(crtc); |
3896 | dev_priv->display.crtc_disable(crtc); |
3833 | 3897 | ||
3834 | intel_crtc_update_sarea(crtc, enable); |
3898 | intel_crtc_update_sarea(crtc, enable); |
3835 | } |
3899 | } |
3836 | 3900 | ||
3837 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3901 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3838 | { |
3902 | { |
3839 | struct drm_device *dev = crtc->dev; |
3903 | struct drm_device *dev = crtc->dev; |
3840 | struct drm_connector *connector; |
3904 | struct drm_connector *connector; |
3841 | struct drm_i915_private *dev_priv = dev->dev_private; |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; |
3842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3906 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3843 | 3907 | ||
3844 | /* crtc should still be enabled when we disable it. */ |
3908 | /* crtc should still be enabled when we disable it. */ |
3845 | WARN_ON(!crtc->enabled); |
3909 | WARN_ON(!crtc->enabled); |
3846 | 3910 | ||
3847 | dev_priv->display.crtc_disable(crtc); |
3911 | dev_priv->display.crtc_disable(crtc); |
3848 | intel_crtc->eld_vld = false; |
3912 | intel_crtc->eld_vld = false; |
3849 | intel_crtc_update_sarea(crtc, false); |
3913 | intel_crtc_update_sarea(crtc, false); |
3850 | dev_priv->display.off(crtc); |
3914 | dev_priv->display.off(crtc); |
3851 | 3915 | ||
3852 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3916 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3853 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3917 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3854 | 3918 | ||
3855 | // if (crtc->fb) { |
3919 | if (crtc->fb) { |
3856 | // mutex_lock(&dev->struct_mutex); |
3920 | mutex_lock(&dev->struct_mutex); |
3857 | // intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3921 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3858 | // mutex_unlock(&dev->struct_mutex); |
3922 | mutex_unlock(&dev->struct_mutex); |
3859 | // crtc->fb = NULL; |
3923 | crtc->fb = NULL; |
3860 | // } |
3924 | } |
3861 | 3925 | ||
3862 | /* Update computed state. */ |
3926 | /* Update computed state. */ |
3863 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
3927 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
3864 | if (!connector->encoder || !connector->encoder->crtc) |
3928 | if (!connector->encoder || !connector->encoder->crtc) |
3865 | continue; |
3929 | continue; |
3866 | 3930 | ||
3867 | if (connector->encoder->crtc != crtc) |
3931 | if (connector->encoder->crtc != crtc) |
3868 | continue; |
3932 | continue; |
3869 | 3933 | ||
3870 | connector->dpms = DRM_MODE_DPMS_OFF; |
3934 | connector->dpms = DRM_MODE_DPMS_OFF; |
3871 | to_intel_encoder(connector->encoder)->connectors_active = false; |
3935 | to_intel_encoder(connector->encoder)->connectors_active = false; |
3872 | } |
3936 | } |
3873 | } |
3937 | } |
3874 | 3938 | ||
3875 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3939 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3876 | { |
3940 | { |
3877 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3941 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
3878 | 3942 | ||
3879 | drm_encoder_cleanup(encoder); |
3943 | drm_encoder_cleanup(encoder); |
3880 | kfree(intel_encoder); |
3944 | kfree(intel_encoder); |
3881 | } |
3945 | } |
3882 | 3946 | ||
3883 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
3947 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
3884 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3948 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3885 | * state of the entire output pipe. */ |
3949 | * state of the entire output pipe. */ |
3886 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
3950 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
3887 | { |
3951 | { |
3888 | if (mode == DRM_MODE_DPMS_ON) { |
3952 | if (mode == DRM_MODE_DPMS_ON) { |
3889 | encoder->connectors_active = true; |
3953 | encoder->connectors_active = true; |
3890 | 3954 | ||
3891 | intel_crtc_update_dpms(encoder->base.crtc); |
3955 | intel_crtc_update_dpms(encoder->base.crtc); |
3892 | } else { |
3956 | } else { |
3893 | encoder->connectors_active = false; |
3957 | encoder->connectors_active = false; |
3894 | 3958 | ||
3895 | intel_crtc_update_dpms(encoder->base.crtc); |
3959 | intel_crtc_update_dpms(encoder->base.crtc); |
3896 | } |
3960 | } |
3897 | } |
3961 | } |
3898 | 3962 | ||
3899 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3963 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3900 | * internal consistency). */ |
3964 | * internal consistency). */ |
3901 | static void intel_connector_check_state(struct intel_connector *connector) |
3965 | static void intel_connector_check_state(struct intel_connector *connector) |
3902 | { |
3966 | { |
3903 | if (connector->get_hw_state(connector)) { |
3967 | if (connector->get_hw_state(connector)) { |
3904 | struct intel_encoder *encoder = connector->encoder; |
3968 | struct intel_encoder *encoder = connector->encoder; |
3905 | struct drm_crtc *crtc; |
3969 | struct drm_crtc *crtc; |
3906 | bool encoder_enabled; |
3970 | bool encoder_enabled; |
3907 | enum pipe pipe; |
3971 | enum pipe pipe; |
3908 | 3972 | ||
3909 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3973 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3910 | connector->base.base.id, |
3974 | connector->base.base.id, |
3911 | drm_get_connector_name(&connector->base)); |
3975 | drm_get_connector_name(&connector->base)); |
3912 | 3976 | ||
3913 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
3977 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
3914 | "wrong connector dpms state\n"); |
3978 | "wrong connector dpms state\n"); |
3915 | WARN(connector->base.encoder != &encoder->base, |
3979 | WARN(connector->base.encoder != &encoder->base, |
3916 | "active connector not linked to encoder\n"); |
3980 | "active connector not linked to encoder\n"); |
3917 | WARN(!encoder->connectors_active, |
3981 | WARN(!encoder->connectors_active, |
3918 | "encoder->connectors_active not set\n"); |
3982 | "encoder->connectors_active not set\n"); |
3919 | 3983 | ||
3920 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
3984 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
3921 | WARN(!encoder_enabled, "encoder not enabled\n"); |
3985 | WARN(!encoder_enabled, "encoder not enabled\n"); |
3922 | if (WARN_ON(!encoder->base.crtc)) |
3986 | if (WARN_ON(!encoder->base.crtc)) |
3923 | return; |
3987 | return; |
3924 | 3988 | ||
3925 | crtc = encoder->base.crtc; |
3989 | crtc = encoder->base.crtc; |
3926 | 3990 | ||
3927 | WARN(!crtc->enabled, "crtc not enabled\n"); |
3991 | WARN(!crtc->enabled, "crtc not enabled\n"); |
3928 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
3992 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
3929 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
3993 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
3930 | "encoder active on the wrong pipe\n"); |
3994 | "encoder active on the wrong pipe\n"); |
3931 | } |
3995 | } |
3932 | } |
3996 | } |
3933 | 3997 | ||
3934 | /* Even simpler default implementation, if there's really no special case to |
3998 | /* Even simpler default implementation, if there's really no special case to |
3935 | * consider. */ |
3999 | * consider. */ |
3936 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
4000 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
3937 | { |
4001 | { |
3938 | /* All the simple cases only support two dpms states. */ |
4002 | /* All the simple cases only support two dpms states. */ |
3939 | if (mode != DRM_MODE_DPMS_ON) |
4003 | if (mode != DRM_MODE_DPMS_ON) |
3940 | mode = DRM_MODE_DPMS_OFF; |
4004 | mode = DRM_MODE_DPMS_OFF; |
3941 | 4005 | ||
3942 | if (mode == connector->dpms) |
4006 | if (mode == connector->dpms) |
3943 | return; |
4007 | return; |
3944 | 4008 | ||
3945 | connector->dpms = mode; |
4009 | connector->dpms = mode; |
3946 | 4010 | ||
3947 | /* Only need to change hw state when actually enabled */ |
4011 | /* Only need to change hw state when actually enabled */ |
3948 | if (connector->encoder) |
4012 | if (connector->encoder) |
3949 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
4013 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
3950 | 4014 | ||
3951 | intel_modeset_check_state(connector->dev); |
4015 | intel_modeset_check_state(connector->dev); |
3952 | } |
4016 | } |
3953 | 4017 | ||
3954 | /* Simple connector->get_hw_state implementation for encoders that support only |
4018 | /* Simple connector->get_hw_state implementation for encoders that support only |
3955 | * one connector and no cloning and hence the encoder state determines the state |
4019 | * one connector and no cloning and hence the encoder state determines the state |
3956 | * of the connector. */ |
4020 | * of the connector. */ |
3957 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
4021 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
3958 | { |
4022 | { |
3959 | enum pipe pipe = 0; |
4023 | enum pipe pipe = 0; |
3960 | struct intel_encoder *encoder = connector->encoder; |
4024 | struct intel_encoder *encoder = connector->encoder; |
3961 | 4025 | ||
3962 | return encoder->get_hw_state(encoder, &pipe); |
4026 | return encoder->get_hw_state(encoder, &pipe); |
3963 | } |
4027 | } |
3964 | 4028 | ||
3965 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4029 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
3966 | struct intel_crtc_config *pipe_config) |
4030 | struct intel_crtc_config *pipe_config) |
3967 | { |
4031 | { |
3968 | struct drm_i915_private *dev_priv = dev->dev_private; |
4032 | struct drm_i915_private *dev_priv = dev->dev_private; |
3969 | struct intel_crtc *pipe_B_crtc = |
4033 | struct intel_crtc *pipe_B_crtc = |
3970 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
4034 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
3971 | 4035 | ||
3972 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
4036 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
3973 | pipe_name(pipe), pipe_config->fdi_lanes); |
4037 | pipe_name(pipe), pipe_config->fdi_lanes); |
3974 | if (pipe_config->fdi_lanes > 4) { |
4038 | if (pipe_config->fdi_lanes > 4) { |
3975 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
4039 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
3976 | pipe_name(pipe), pipe_config->fdi_lanes); |
4040 | pipe_name(pipe), pipe_config->fdi_lanes); |
3977 | return false; |
4041 | return false; |
3978 | } |
4042 | } |
3979 | 4043 | ||
3980 | if (IS_HASWELL(dev)) { |
4044 | if (IS_HASWELL(dev)) { |
3981 | if (pipe_config->fdi_lanes > 2) { |
4045 | if (pipe_config->fdi_lanes > 2) { |
3982 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
4046 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
3983 | pipe_config->fdi_lanes); |
4047 | pipe_config->fdi_lanes); |
3984 | return false; |
4048 | return false; |
3985 | } else { |
4049 | } else { |
3986 | return true; |
4050 | return true; |
3987 | } |
4051 | } |
3988 | } |
4052 | } |
3989 | 4053 | ||
3990 | if (INTEL_INFO(dev)->num_pipes == 2) |
4054 | if (INTEL_INFO(dev)->num_pipes == 2) |
3991 | return true; |
4055 | return true; |
3992 | 4056 | ||
3993 | /* Ivybridge 3 pipe is really complicated */ |
4057 | /* Ivybridge 3 pipe is really complicated */ |
3994 | switch (pipe) { |
4058 | switch (pipe) { |
3995 | case PIPE_A: |
4059 | case PIPE_A: |
3996 | return true; |
4060 | return true; |
3997 | case PIPE_B: |
4061 | case PIPE_B: |
3998 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
4062 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
3999 | pipe_config->fdi_lanes > 2) { |
4063 | pipe_config->fdi_lanes > 2) { |
4000 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4064 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4001 | pipe_name(pipe), pipe_config->fdi_lanes); |
4065 | pipe_name(pipe), pipe_config->fdi_lanes); |
4002 | return false; |
4066 | return false; |
4003 | } |
4067 | } |
4004 | return true; |
4068 | return true; |
4005 | case PIPE_C: |
4069 | case PIPE_C: |
4006 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
4070 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
4007 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4071 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4008 | if (pipe_config->fdi_lanes > 2) { |
4072 | if (pipe_config->fdi_lanes > 2) { |
4009 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4073 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
4010 | pipe_name(pipe), pipe_config->fdi_lanes); |
4074 | pipe_name(pipe), pipe_config->fdi_lanes); |
4011 | return false; |
4075 | return false; |
4012 | } |
4076 | } |
4013 | } else { |
4077 | } else { |
4014 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
4078 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
4015 | return false; |
4079 | return false; |
4016 | } |
4080 | } |
4017 | return true; |
4081 | return true; |
4018 | default: |
4082 | default: |
4019 | BUG(); |
4083 | BUG(); |
4020 | } |
4084 | } |
4021 | } |
4085 | } |
4022 | 4086 | ||
4023 | #define RETRY 1 |
4087 | #define RETRY 1 |
4024 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
4088 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
4025 | struct intel_crtc_config *pipe_config) |
4089 | struct intel_crtc_config *pipe_config) |
4026 | { |
4090 | { |
4027 | struct drm_device *dev = intel_crtc->base.dev; |
4091 | struct drm_device *dev = intel_crtc->base.dev; |
4028 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4092 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4029 | int lane, link_bw, fdi_dotclock; |
4093 | int lane, link_bw, fdi_dotclock; |
4030 | bool setup_ok, needs_recompute = false; |
4094 | bool setup_ok, needs_recompute = false; |
4031 | 4095 | ||
4032 | retry: |
4096 | retry: |
4033 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4097 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4034 | * each output octet as 10 bits. The actual frequency |
4098 | * each output octet as 10 bits. The actual frequency |
4035 | * is stored as a divider into a 100MHz clock, and the |
4099 | * is stored as a divider into a 100MHz clock, and the |
4036 | * mode pixel clock is stored in units of 1KHz. |
4100 | * mode pixel clock is stored in units of 1KHz. |
4037 | * Hence the bw of each lane in terms of the mode signal |
4101 | * Hence the bw of each lane in terms of the mode signal |
4038 | * is: |
4102 | * is: |
4039 | */ |
4103 | */ |
4040 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4104 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4041 | 4105 | ||
4042 | fdi_dotclock = adjusted_mode->clock; |
4106 | fdi_dotclock = adjusted_mode->clock; |
4043 | fdi_dotclock /= pipe_config->pixel_multiplier; |
4107 | fdi_dotclock /= pipe_config->pixel_multiplier; |
4044 | 4108 | ||
4045 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
4109 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
4046 | pipe_config->pipe_bpp); |
4110 | pipe_config->pipe_bpp); |
4047 | 4111 | ||
4048 | pipe_config->fdi_lanes = lane; |
4112 | pipe_config->fdi_lanes = lane; |
4049 | 4113 | ||
4050 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
4114 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
4051 | link_bw, &pipe_config->fdi_m_n); |
4115 | link_bw, &pipe_config->fdi_m_n); |
4052 | 4116 | ||
4053 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4117 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4054 | intel_crtc->pipe, pipe_config); |
4118 | intel_crtc->pipe, pipe_config); |
4055 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
4119 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
4056 | pipe_config->pipe_bpp -= 2*3; |
4120 | pipe_config->pipe_bpp -= 2*3; |
4057 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
4121 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
4058 | pipe_config->pipe_bpp); |
4122 | pipe_config->pipe_bpp); |
4059 | needs_recompute = true; |
4123 | needs_recompute = true; |
4060 | pipe_config->bw_constrained = true; |
4124 | pipe_config->bw_constrained = true; |
4061 | 4125 | ||
4062 | goto retry; |
4126 | goto retry; |
4063 | } |
4127 | } |
4064 | 4128 | ||
4065 | if (needs_recompute) |
4129 | if (needs_recompute) |
4066 | return RETRY; |
4130 | return RETRY; |
4067 | 4131 | ||
4068 | return setup_ok ? 0 : -EINVAL; |
4132 | return setup_ok ? 0 : -EINVAL; |
4069 | } |
4133 | } |
4070 | 4134 | ||
4071 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4135 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4072 | struct intel_crtc_config *pipe_config) |
4136 | struct intel_crtc_config *pipe_config) |
4073 | { |
4137 | { |
4074 | pipe_config->ips_enabled = i915_enable_ips && |
4138 | pipe_config->ips_enabled = i915_enable_ips && |
4075 | hsw_crtc_supports_ips(crtc) && |
4139 | hsw_crtc_supports_ips(crtc) && |
4076 | pipe_config->pipe_bpp <= 24; |
4140 | pipe_config->pipe_bpp <= 24; |
4077 | } |
4141 | } |
4078 | 4142 | ||
4079 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
4143 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
4080 | struct intel_crtc_config *pipe_config) |
4144 | struct intel_crtc_config *pipe_config) |
4081 | { |
4145 | { |
4082 | struct drm_device *dev = crtc->base.dev; |
4146 | struct drm_device *dev = crtc->base.dev; |
4083 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4147 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4084 | 4148 | ||
4085 | if (HAS_PCH_SPLIT(dev)) { |
4149 | if (HAS_PCH_SPLIT(dev)) { |
4086 | /* FDI link clock is fixed at 2.7G */ |
4150 | /* FDI link clock is fixed at 2.7G */ |
4087 | if (pipe_config->requested_mode.clock * 3 |
4151 | if (pipe_config->requested_mode.clock * 3 |
4088 | > IRONLAKE_FDI_FREQ * 4) |
4152 | > IRONLAKE_FDI_FREQ * 4) |
4089 | return -EINVAL; |
4153 | return -EINVAL; |
4090 | } |
4154 | } |
4091 | 4155 | ||
4092 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4156 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4093 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4157 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4094 | */ |
4158 | */ |
4095 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
4159 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
4096 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
4160 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
4097 | return -EINVAL; |
4161 | return -EINVAL; |
4098 | 4162 | ||
4099 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
4163 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
4100 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
4164 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
4101 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
4165 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
4102 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4166 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4103 | * for lvds. */ |
4167 | * for lvds. */ |
4104 | pipe_config->pipe_bpp = 8*3; |
4168 | pipe_config->pipe_bpp = 8*3; |
4105 | } |
4169 | } |
4106 | 4170 | ||
4107 | if (HAS_IPS(dev)) |
4171 | if (HAS_IPS(dev)) |
4108 | hsw_compute_ips_config(crtc, pipe_config); |
4172 | hsw_compute_ips_config(crtc, pipe_config); |
4109 | 4173 | ||
4110 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
4174 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
4111 | * clock survives for now. */ |
4175 | * clock survives for now. */ |
4112 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
4176 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
4113 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
4177 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
4114 | 4178 | ||
4115 | if (pipe_config->has_pch_encoder) |
4179 | if (pipe_config->has_pch_encoder) |
4116 | return ironlake_fdi_compute_config(crtc, pipe_config); |
4180 | return ironlake_fdi_compute_config(crtc, pipe_config); |
4117 | 4181 | ||
4118 | return 0; |
4182 | return 0; |
4119 | } |
4183 | } |
4120 | 4184 | ||
4121 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4185 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4122 | { |
4186 | { |
4123 | return 400000; /* FIXME */ |
4187 | return 400000; /* FIXME */ |
4124 | } |
4188 | } |
4125 | 4189 | ||
4126 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4190 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4127 | { |
4191 | { |
4128 | return 400000; |
4192 | return 400000; |
4129 | } |
4193 | } |
4130 | 4194 | ||
4131 | static int i915_get_display_clock_speed(struct drm_device *dev) |
4195 | static int i915_get_display_clock_speed(struct drm_device *dev) |
4132 | { |
4196 | { |
4133 | return 333000; |
4197 | return 333000; |
4134 | } |
4198 | } |
4135 | 4199 | ||
4136 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4200 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4137 | { |
4201 | { |
4138 | return 200000; |
4202 | return 200000; |
4139 | } |
4203 | } |
4140 | 4204 | ||
4141 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4205 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4142 | { |
4206 | { |
4143 | u16 gcfgc = 0; |
4207 | u16 gcfgc = 0; |
4144 | 4208 | ||
4145 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4209 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4146 | 4210 | ||
4147 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4211 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4148 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
4212 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
4149 | return 267000; |
4213 | return 267000; |
4150 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
4214 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
4151 | return 333000; |
4215 | return 333000; |
4152 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
4216 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
4153 | return 444000; |
4217 | return 444000; |
4154 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
4218 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
4155 | return 200000; |
4219 | return 200000; |
4156 | default: |
4220 | default: |
4157 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
4221 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
4158 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
4222 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
4159 | return 133000; |
4223 | return 133000; |
4160 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
4224 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
4161 | return 167000; |
4225 | return 167000; |
4162 | } |
4226 | } |
4163 | } |
4227 | } |
4164 | 4228 | ||
4165 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4229 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4166 | { |
4230 | { |
4167 | u16 gcfgc = 0; |
4231 | u16 gcfgc = 0; |
4168 | 4232 | ||
4169 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4233 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4170 | 4234 | ||
4171 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
4235 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
4172 | return 133000; |
4236 | return 133000; |
4173 | else { |
4237 | else { |
4174 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4238 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4175 | case GC_DISPLAY_CLOCK_333_MHZ: |
4239 | case GC_DISPLAY_CLOCK_333_MHZ: |
4176 | return 333000; |
4240 | return 333000; |
4177 | default: |
4241 | default: |
4178 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
4242 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
4179 | return 190000; |
4243 | return 190000; |
4180 | } |
4244 | } |
4181 | } |
4245 | } |
4182 | } |
4246 | } |
4183 | 4247 | ||
4184 | static int i865_get_display_clock_speed(struct drm_device *dev) |
4248 | static int i865_get_display_clock_speed(struct drm_device *dev) |
4185 | { |
4249 | { |
4186 | return 266000; |
4250 | return 266000; |
4187 | } |
4251 | } |
4188 | 4252 | ||
4189 | static int i855_get_display_clock_speed(struct drm_device *dev) |
4253 | static int i855_get_display_clock_speed(struct drm_device *dev) |
4190 | { |
4254 | { |
4191 | u16 hpllcc = 0; |
4255 | u16 hpllcc = 0; |
4192 | /* Assume that the hardware is in the high speed state. This |
4256 | /* Assume that the hardware is in the high speed state. This |
4193 | * should be the default. |
4257 | * should be the default. |
4194 | */ |
4258 | */ |
4195 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
4259 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
4196 | case GC_CLOCK_133_200: |
4260 | case GC_CLOCK_133_200: |
4197 | case GC_CLOCK_100_200: |
4261 | case GC_CLOCK_100_200: |
4198 | return 200000; |
4262 | return 200000; |
4199 | case GC_CLOCK_166_250: |
4263 | case GC_CLOCK_166_250: |
4200 | return 250000; |
4264 | return 250000; |
4201 | case GC_CLOCK_100_133: |
4265 | case GC_CLOCK_100_133: |
4202 | return 133000; |
4266 | return 133000; |
4203 | } |
4267 | } |
4204 | 4268 | ||
4205 | /* Shouldn't happen */ |
4269 | /* Shouldn't happen */ |
4206 | return 0; |
4270 | return 0; |
4207 | } |
4271 | } |
4208 | 4272 | ||
4209 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4273 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4210 | { |
4274 | { |
4211 | return 133000; |
4275 | return 133000; |
4212 | } |
4276 | } |
4213 | 4277 | ||
4214 | static void |
4278 | static void |
4215 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
4279 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
4216 | { |
4280 | { |
4217 | while (*num > DATA_LINK_M_N_MASK || |
4281 | while (*num > DATA_LINK_M_N_MASK || |
4218 | *den > DATA_LINK_M_N_MASK) { |
4282 | *den > DATA_LINK_M_N_MASK) { |
4219 | *num >>= 1; |
4283 | *num >>= 1; |
4220 | *den >>= 1; |
4284 | *den >>= 1; |
4221 | } |
4285 | } |
4222 | } |
4286 | } |
4223 | 4287 | ||
4224 | static void compute_m_n(unsigned int m, unsigned int n, |
4288 | static void compute_m_n(unsigned int m, unsigned int n, |
4225 | uint32_t *ret_m, uint32_t *ret_n) |
4289 | uint32_t *ret_m, uint32_t *ret_n) |
4226 | { |
4290 | { |
4227 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
4291 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
4228 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
4292 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
4229 | intel_reduce_m_n_ratio(ret_m, ret_n); |
4293 | intel_reduce_m_n_ratio(ret_m, ret_n); |
4230 | } |
4294 | } |
4231 | 4295 | ||
4232 | void |
4296 | void |
4233 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
4297 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
4234 | int pixel_clock, int link_clock, |
4298 | int pixel_clock, int link_clock, |
4235 | struct intel_link_m_n *m_n) |
4299 | struct intel_link_m_n *m_n) |
4236 | { |
4300 | { |
4237 | m_n->tu = 64; |
4301 | m_n->tu = 64; |
4238 | 4302 | ||
4239 | compute_m_n(bits_per_pixel * pixel_clock, |
4303 | compute_m_n(bits_per_pixel * pixel_clock, |
4240 | link_clock * nlanes * 8, |
4304 | link_clock * nlanes * 8, |
4241 | &m_n->gmch_m, &m_n->gmch_n); |
4305 | &m_n->gmch_m, &m_n->gmch_n); |
4242 | 4306 | ||
4243 | compute_m_n(pixel_clock, link_clock, |
4307 | compute_m_n(pixel_clock, link_clock, |
4244 | &m_n->link_m, &m_n->link_n); |
4308 | &m_n->link_m, &m_n->link_n); |
4245 | } |
4309 | } |
4246 | 4310 | ||
4247 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4311 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4248 | { |
4312 | { |
4249 | if (i915_panel_use_ssc >= 0) |
4313 | if (i915_panel_use_ssc >= 0) |
4250 | return i915_panel_use_ssc != 0; |
4314 | return i915_panel_use_ssc != 0; |
4251 | return dev_priv->vbt.lvds_use_ssc |
4315 | return dev_priv->vbt.lvds_use_ssc |
4252 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4316 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
4253 | } |
4317 | } |
4254 | 4318 | ||
4255 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4319 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4256 | { |
4320 | { |
4257 | struct drm_device *dev = crtc->dev; |
4321 | struct drm_device *dev = crtc->dev; |
4258 | struct drm_i915_private *dev_priv = dev->dev_private; |
4322 | struct drm_i915_private *dev_priv = dev->dev_private; |
4259 | int refclk = 27000; /* for DP & HDMI */ |
4323 | int refclk = 27000; /* for DP & HDMI */ |
4260 | 4324 | ||
4261 | return 100000; /* only one validated so far */ |
4325 | return 100000; /* only one validated so far */ |
4262 | 4326 | ||
4263 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
4327 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
4264 | refclk = 96000; |
4328 | refclk = 96000; |
4265 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
4329 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
4266 | if (intel_panel_use_ssc(dev_priv)) |
4330 | if (intel_panel_use_ssc(dev_priv)) |
4267 | refclk = 100000; |
4331 | refclk = 100000; |
4268 | else |
4332 | else |
4269 | refclk = 96000; |
4333 | refclk = 96000; |
4270 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
4334 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
4271 | refclk = 100000; |
4335 | refclk = 100000; |
4272 | } |
4336 | } |
4273 | 4337 | ||
4274 | return refclk; |
4338 | return refclk; |
4275 | } |
4339 | } |
4276 | 4340 | ||
4277 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4341 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4278 | { |
4342 | { |
4279 | struct drm_device *dev = crtc->dev; |
4343 | struct drm_device *dev = crtc->dev; |
4280 | struct drm_i915_private *dev_priv = dev->dev_private; |
4344 | struct drm_i915_private *dev_priv = dev->dev_private; |
4281 | int refclk; |
4345 | int refclk; |
4282 | 4346 | ||
4283 | if (IS_VALLEYVIEW(dev)) { |
4347 | if (IS_VALLEYVIEW(dev)) { |
4284 | refclk = vlv_get_refclk(crtc); |
4348 | refclk = vlv_get_refclk(crtc); |
4285 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4349 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
4286 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4350 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4287 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
4351 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
4288 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4352 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4289 | refclk / 1000); |
4353 | refclk / 1000); |
4290 | } else if (!IS_GEN2(dev)) { |
4354 | } else if (!IS_GEN2(dev)) { |
4291 | refclk = 96000; |
4355 | refclk = 96000; |
4292 | } else { |
4356 | } else { |
4293 | refclk = 48000; |
4357 | refclk = 48000; |
4294 | } |
4358 | } |
4295 | 4359 | ||
4296 | return refclk; |
4360 | return refclk; |
4297 | } |
4361 | } |
4298 | 4362 | ||
4299 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
4363 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
4300 | { |
4364 | { |
4301 | return (1 << dpll->n) << 16 | dpll->m2; |
4365 | return (1 << dpll->n) << 16 | dpll->m2; |
4302 | } |
4366 | } |
4303 | 4367 | ||
4304 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4368 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4305 | { |
4369 | { |
4306 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
4370 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
4307 | } |
4371 | } |
4308 | 4372 | ||
4309 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
4373 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
4310 | intel_clock_t *reduced_clock) |
4374 | intel_clock_t *reduced_clock) |
4311 | { |
4375 | { |
4312 | struct drm_device *dev = crtc->base.dev; |
4376 | struct drm_device *dev = crtc->base.dev; |
4313 | struct drm_i915_private *dev_priv = dev->dev_private; |
4377 | struct drm_i915_private *dev_priv = dev->dev_private; |
4314 | int pipe = crtc->pipe; |
4378 | int pipe = crtc->pipe; |
4315 | u32 fp, fp2 = 0; |
4379 | u32 fp, fp2 = 0; |
4316 | 4380 | ||
4317 | if (IS_PINEVIEW(dev)) { |
4381 | if (IS_PINEVIEW(dev)) { |
4318 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
4382 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
4319 | if (reduced_clock) |
4383 | if (reduced_clock) |
4320 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
4384 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
4321 | } else { |
4385 | } else { |
4322 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
4386 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
4323 | if (reduced_clock) |
4387 | if (reduced_clock) |
4324 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
4388 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
4325 | } |
4389 | } |
4326 | 4390 | ||
4327 | I915_WRITE(FP0(pipe), fp); |
4391 | I915_WRITE(FP0(pipe), fp); |
4328 | crtc->config.dpll_hw_state.fp0 = fp; |
4392 | crtc->config.dpll_hw_state.fp0 = fp; |
4329 | 4393 | ||
4330 | crtc->lowfreq_avail = false; |
4394 | crtc->lowfreq_avail = false; |
4331 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4395 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4332 | reduced_clock && i915_powersave) { |
4396 | reduced_clock && i915_powersave) { |
4333 | I915_WRITE(FP1(pipe), fp2); |
4397 | I915_WRITE(FP1(pipe), fp2); |
4334 | crtc->config.dpll_hw_state.fp1 = fp2; |
4398 | crtc->config.dpll_hw_state.fp1 = fp2; |
4335 | crtc->lowfreq_avail = true; |
4399 | crtc->lowfreq_avail = true; |
4336 | } else { |
4400 | } else { |
4337 | I915_WRITE(FP1(pipe), fp); |
4401 | I915_WRITE(FP1(pipe), fp); |
4338 | crtc->config.dpll_hw_state.fp1 = fp; |
4402 | crtc->config.dpll_hw_state.fp1 = fp; |
4339 | } |
4403 | } |
4340 | } |
4404 | } |
4341 | 4405 | ||
4342 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4406 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4343 | { |
4407 | { |
4344 | u32 reg_val; |
4408 | u32 reg_val; |
4345 | 4409 | ||
4346 | /* |
4410 | /* |
4347 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
4411 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
4348 | * and set it to a reasonable value instead. |
4412 | * and set it to a reasonable value instead. |
4349 | */ |
4413 | */ |
4350 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4414 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4351 | reg_val &= 0xffffff00; |
4415 | reg_val &= 0xffffff00; |
4352 | reg_val |= 0x00000030; |
4416 | reg_val |= 0x00000030; |
4353 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4417 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4354 | 4418 | ||
4355 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4419 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4356 | reg_val &= 0x8cffffff; |
4420 | reg_val &= 0x8cffffff; |
4357 | reg_val = 0x8c000000; |
4421 | reg_val = 0x8c000000; |
4358 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4422 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4359 | 4423 | ||
4360 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4424 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
4361 | reg_val &= 0xffffff00; |
4425 | reg_val &= 0xffffff00; |
4362 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4426 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
4363 | 4427 | ||
4364 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4428 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
4365 | reg_val &= 0x00ffffff; |
4429 | reg_val &= 0x00ffffff; |
4366 | reg_val |= 0xb0000000; |
4430 | reg_val |= 0xb0000000; |
4367 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4431 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
4368 | } |
4432 | } |
4369 | 4433 | ||
4370 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4434 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4371 | struct intel_link_m_n *m_n) |
4435 | struct intel_link_m_n *m_n) |
4372 | { |
4436 | { |
4373 | struct drm_device *dev = crtc->base.dev; |
4437 | struct drm_device *dev = crtc->base.dev; |
4374 | struct drm_i915_private *dev_priv = dev->dev_private; |
4438 | struct drm_i915_private *dev_priv = dev->dev_private; |
4375 | int pipe = crtc->pipe; |
4439 | int pipe = crtc->pipe; |
4376 | 4440 | ||
4377 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4441 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4378 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
4442 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
4379 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
4443 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
4380 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
4444 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
4381 | } |
4445 | } |
4382 | 4446 | ||
4383 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
4447 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
4384 | struct intel_link_m_n *m_n) |
4448 | struct intel_link_m_n *m_n) |
4385 | { |
4449 | { |
4386 | struct drm_device *dev = crtc->base.dev; |
4450 | struct drm_device *dev = crtc->base.dev; |
4387 | struct drm_i915_private *dev_priv = dev->dev_private; |
4451 | struct drm_i915_private *dev_priv = dev->dev_private; |
4388 | int pipe = crtc->pipe; |
4452 | int pipe = crtc->pipe; |
4389 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
4453 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
4390 | 4454 | ||
4391 | if (INTEL_INFO(dev)->gen >= 5) { |
4455 | if (INTEL_INFO(dev)->gen >= 5) { |
4392 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4456 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4393 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
4457 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
4394 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
4458 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
4395 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
4459 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
4396 | } else { |
4460 | } else { |
4397 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4461 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4398 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
4462 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
4399 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
4463 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
4400 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
4464 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
4401 | } |
4465 | } |
4402 | } |
4466 | } |
4403 | 4467 | ||
4404 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4468 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4405 | { |
4469 | { |
4406 | if (crtc->config.has_pch_encoder) |
4470 | if (crtc->config.has_pch_encoder) |
4407 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4471 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4408 | else |
4472 | else |
4409 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4473 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
4410 | } |
4474 | } |
4411 | 4475 | ||
4412 | static void vlv_update_pll(struct intel_crtc *crtc) |
4476 | static void vlv_update_pll(struct intel_crtc *crtc) |
4413 | { |
4477 | { |
4414 | struct drm_device *dev = crtc->base.dev; |
4478 | struct drm_device *dev = crtc->base.dev; |
4415 | struct drm_i915_private *dev_priv = dev->dev_private; |
4479 | struct drm_i915_private *dev_priv = dev->dev_private; |
4416 | int pipe = crtc->pipe; |
4480 | int pipe = crtc->pipe; |
4417 | u32 dpll, mdiv; |
4481 | u32 dpll, mdiv; |
4418 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4482 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
4419 | u32 coreclk, reg_val, dpll_md; |
4483 | u32 coreclk, reg_val, dpll_md; |
4420 | 4484 | ||
4421 | mutex_lock(&dev_priv->dpio_lock); |
4485 | mutex_lock(&dev_priv->dpio_lock); |
4422 | 4486 | ||
4423 | bestn = crtc->config.dpll.n; |
4487 | bestn = crtc->config.dpll.n; |
4424 | bestm1 = crtc->config.dpll.m1; |
4488 | bestm1 = crtc->config.dpll.m1; |
4425 | bestm2 = crtc->config.dpll.m2; |
4489 | bestm2 = crtc->config.dpll.m2; |
4426 | bestp1 = crtc->config.dpll.p1; |
4490 | bestp1 = crtc->config.dpll.p1; |
4427 | bestp2 = crtc->config.dpll.p2; |
4491 | bestp2 = crtc->config.dpll.p2; |
4428 | 4492 | ||
4429 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4493 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4430 | 4494 | ||
4431 | /* PLL B needs special handling */ |
4495 | /* PLL B needs special handling */ |
4432 | if (pipe) |
4496 | if (pipe) |
4433 | vlv_pllb_recal_opamp(dev_priv); |
4497 | vlv_pllb_recal_opamp(dev_priv); |
4434 | 4498 | ||
4435 | /* Set up Tx target for periodic Rcomp update */ |
4499 | /* Set up Tx target for periodic Rcomp update */ |
4436 | vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); |
4500 | vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); |
4437 | 4501 | ||
4438 | /* Disable target IRef on PLL */ |
4502 | /* Disable target IRef on PLL */ |
4439 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); |
4503 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); |
4440 | reg_val &= 0x00ffffff; |
4504 | reg_val &= 0x00ffffff; |
4441 | vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); |
4505 | vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); |
4442 | 4506 | ||
4443 | /* Disable fast lock */ |
4507 | /* Disable fast lock */ |
4444 | vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610); |
4508 | vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610); |
4445 | 4509 | ||
4446 | /* Set idtafcrecal before PLL is enabled */ |
4510 | /* Set idtafcrecal before PLL is enabled */ |
4447 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4511 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4448 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
4512 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
4449 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
4513 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
4450 | mdiv |= (1 << DPIO_K_SHIFT); |
4514 | mdiv |= (1 << DPIO_K_SHIFT); |
4451 | 4515 | ||
4452 | /* |
4516 | /* |
4453 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
4517 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
4454 | * but we don't support that). |
4518 | * but we don't support that). |
4455 | * Note: don't use the DAC post divider as it seems unstable. |
4519 | * Note: don't use the DAC post divider as it seems unstable. |
4456 | */ |
4520 | */ |
4457 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
4521 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
4458 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4522 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4459 | 4523 | ||
4460 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4524 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4461 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4525 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4462 | 4526 | ||
4463 | /* Set HBR and RBR LPF coefficients */ |
4527 | /* Set HBR and RBR LPF coefficients */ |
4464 | if (crtc->config.port_clock == 162000 || |
4528 | if (crtc->config.port_clock == 162000 || |
4465 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
4529 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
4466 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4530 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4467 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4531 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4468 | 0x009f0003); |
4532 | 0x009f0003); |
4469 | else |
4533 | else |
4470 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4534 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
4471 | 0x00d0000f); |
4535 | 0x00d0000f); |
4472 | 4536 | ||
4473 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4537 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
4474 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4538 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
4475 | /* Use SSC source */ |
4539 | /* Use SSC source */ |
4476 | if (!pipe) |
4540 | if (!pipe) |
4477 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4541 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4478 | 0x0df40000); |
4542 | 0x0df40000); |
4479 | else |
4543 | else |
4480 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4544 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4481 | 0x0df70000); |
4545 | 0x0df70000); |
4482 | } else { /* HDMI or VGA */ |
4546 | } else { /* HDMI or VGA */ |
4483 | /* Use bend source */ |
4547 | /* Use bend source */ |
4484 | if (!pipe) |
4548 | if (!pipe) |
4485 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4549 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4486 | 0x0df70000); |
4550 | 0x0df70000); |
4487 | else |
4551 | else |
4488 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4552 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
4489 | 0x0df40000); |
4553 | 0x0df40000); |
4490 | } |
4554 | } |
4491 | 4555 | ||
4492 | coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
4556 | coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
4493 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4557 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4494 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
4558 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
4495 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
4559 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
4496 | coreclk |= 0x01000000; |
4560 | coreclk |= 0x01000000; |
4497 | vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); |
4561 | vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); |
4498 | 4562 | ||
4499 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
4563 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
4500 | 4564 | ||
4501 | /* Enable DPIO clock input */ |
4565 | /* Enable DPIO clock input */ |
4502 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
4566 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
4503 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
4567 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
4504 | if (pipe) |
4568 | if (pipe) |
4505 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
4569 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
4506 | 4570 | ||
4507 | dpll |= DPLL_VCO_ENABLE; |
4571 | dpll |= DPLL_VCO_ENABLE; |
4508 | crtc->config.dpll_hw_state.dpll = dpll; |
4572 | crtc->config.dpll_hw_state.dpll = dpll; |
4509 | 4573 | ||
4510 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4574 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4511 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4575 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4512 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4576 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4513 | 4577 | ||
4514 | if (crtc->config.has_dp_encoder) |
4578 | if (crtc->config.has_dp_encoder) |
4515 | intel_dp_set_m_n(crtc); |
4579 | intel_dp_set_m_n(crtc); |
4516 | 4580 | ||
4517 | mutex_unlock(&dev_priv->dpio_lock); |
4581 | mutex_unlock(&dev_priv->dpio_lock); |
4518 | } |
4582 | } |
4519 | 4583 | ||
4520 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4584 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4521 | intel_clock_t *reduced_clock, |
4585 | intel_clock_t *reduced_clock, |
4522 | int num_connectors) |
4586 | int num_connectors) |
4523 | { |
4587 | { |
4524 | struct drm_device *dev = crtc->base.dev; |
4588 | struct drm_device *dev = crtc->base.dev; |
4525 | struct drm_i915_private *dev_priv = dev->dev_private; |
4589 | struct drm_i915_private *dev_priv = dev->dev_private; |
4526 | u32 dpll; |
4590 | u32 dpll; |
4527 | bool is_sdvo; |
4591 | bool is_sdvo; |
4528 | struct dpll *clock = &crtc->config.dpll; |
4592 | struct dpll *clock = &crtc->config.dpll; |
4529 | 4593 | ||
4530 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4594 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4531 | 4595 | ||
4532 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4596 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4533 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
4597 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
4534 | 4598 | ||
4535 | dpll = DPLL_VGA_MODE_DIS; |
4599 | dpll = DPLL_VGA_MODE_DIS; |
4536 | 4600 | ||
4537 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
4601 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
4538 | dpll |= DPLLB_MODE_LVDS; |
4602 | dpll |= DPLLB_MODE_LVDS; |
4539 | else |
4603 | else |
4540 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4604 | dpll |= DPLLB_MODE_DAC_SERIAL; |
4541 | 4605 | ||
4542 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
4606 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
4543 | dpll |= (crtc->config.pixel_multiplier - 1) |
4607 | dpll |= (crtc->config.pixel_multiplier - 1) |
4544 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
4608 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
4545 | } |
4609 | } |
4546 | 4610 | ||
4547 | if (is_sdvo) |
4611 | if (is_sdvo) |
4548 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4612 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4549 | 4613 | ||
4550 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4614 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4551 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4615 | dpll |= DPLL_SDVO_HIGH_SPEED; |
4552 | 4616 | ||
4553 | /* compute bitmask from p1 value */ |
4617 | /* compute bitmask from p1 value */ |
4554 | if (IS_PINEVIEW(dev)) |
4618 | if (IS_PINEVIEW(dev)) |
4555 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
4619 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
4556 | else { |
4620 | else { |
4557 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4621 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4558 | if (IS_G4X(dev) && reduced_clock) |
4622 | if (IS_G4X(dev) && reduced_clock) |
4559 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4623 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
4560 | } |
4624 | } |
4561 | switch (clock->p2) { |
4625 | switch (clock->p2) { |
4562 | case 5: |
4626 | case 5: |
4563 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4627 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
4564 | break; |
4628 | break; |
4565 | case 7: |
4629 | case 7: |
4566 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4630 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
4567 | break; |
4631 | break; |
4568 | case 10: |
4632 | case 10: |
4569 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4633 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
4570 | break; |
4634 | break; |
4571 | case 14: |
4635 | case 14: |
4572 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4636 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
4573 | break; |
4637 | break; |
4574 | } |
4638 | } |
4575 | if (INTEL_INFO(dev)->gen >= 4) |
4639 | if (INTEL_INFO(dev)->gen >= 4) |
4576 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4640 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4577 | 4641 | ||
4578 | if (crtc->config.sdvo_tv_clock) |
4642 | if (crtc->config.sdvo_tv_clock) |
4579 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4643 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
4580 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4644 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4581 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4645 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4582 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4646 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4583 | else |
4647 | else |
4584 | dpll |= PLL_REF_INPUT_DREFCLK; |
4648 | dpll |= PLL_REF_INPUT_DREFCLK; |
4585 | 4649 | ||
4586 | dpll |= DPLL_VCO_ENABLE; |
4650 | dpll |= DPLL_VCO_ENABLE; |
4587 | crtc->config.dpll_hw_state.dpll = dpll; |
4651 | crtc->config.dpll_hw_state.dpll = dpll; |
4588 | 4652 | ||
4589 | if (INTEL_INFO(dev)->gen >= 4) { |
4653 | if (INTEL_INFO(dev)->gen >= 4) { |
4590 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
4654 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
4591 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4655 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
4592 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4656 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4593 | } |
4657 | } |
4594 | 4658 | ||
4595 | if (crtc->config.has_dp_encoder) |
4659 | if (crtc->config.has_dp_encoder) |
4596 | intel_dp_set_m_n(crtc); |
4660 | intel_dp_set_m_n(crtc); |
4597 | } |
4661 | } |
4598 | 4662 | ||
4599 | static void i8xx_update_pll(struct intel_crtc *crtc, |
4663 | static void i8xx_update_pll(struct intel_crtc *crtc, |
4600 | intel_clock_t *reduced_clock, |
4664 | intel_clock_t *reduced_clock, |
4601 | int num_connectors) |
4665 | int num_connectors) |
4602 | { |
4666 | { |
4603 | struct drm_device *dev = crtc->base.dev; |
4667 | struct drm_device *dev = crtc->base.dev; |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; |
4668 | struct drm_i915_private *dev_priv = dev->dev_private; |
4605 | u32 dpll; |
4669 | u32 dpll; |
4606 | struct dpll *clock = &crtc->config.dpll; |
4670 | struct dpll *clock = &crtc->config.dpll; |
4607 | 4671 | ||
4608 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4672 | i9xx_update_pll_dividers(crtc, reduced_clock); |
4609 | 4673 | ||
4610 | dpll = DPLL_VGA_MODE_DIS; |
4674 | dpll = DPLL_VGA_MODE_DIS; |
4611 | 4675 | ||
4612 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
4676 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
4613 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4677 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4614 | } else { |
4678 | } else { |
4615 | if (clock->p1 == 2) |
4679 | if (clock->p1 == 2) |
4616 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
4680 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
4617 | else |
4681 | else |
4618 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4682 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4619 | if (clock->p2 == 4) |
4683 | if (clock->p2 == 4) |
4620 | dpll |= PLL_P2_DIVIDE_BY_4; |
4684 | dpll |= PLL_P2_DIVIDE_BY_4; |
4621 | } |
4685 | } |
4622 | 4686 | ||
4623 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4687 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4624 | dpll |= DPLL_DVO_2X_MODE; |
4688 | dpll |= DPLL_DVO_2X_MODE; |
4625 | 4689 | ||
4626 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4690 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4627 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4691 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4628 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4692 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
4629 | else |
4693 | else |
4630 | dpll |= PLL_REF_INPUT_DREFCLK; |
4694 | dpll |= PLL_REF_INPUT_DREFCLK; |
4631 | 4695 | ||
4632 | dpll |= DPLL_VCO_ENABLE; |
4696 | dpll |= DPLL_VCO_ENABLE; |
4633 | crtc->config.dpll_hw_state.dpll = dpll; |
4697 | crtc->config.dpll_hw_state.dpll = dpll; |
4634 | } |
4698 | } |
4635 | 4699 | ||
4636 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
4700 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
4637 | { |
4701 | { |
4638 | struct drm_device *dev = intel_crtc->base.dev; |
4702 | struct drm_device *dev = intel_crtc->base.dev; |
4639 | struct drm_i915_private *dev_priv = dev->dev_private; |
4703 | struct drm_i915_private *dev_priv = dev->dev_private; |
4640 | enum pipe pipe = intel_crtc->pipe; |
4704 | enum pipe pipe = intel_crtc->pipe; |
4641 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4705 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4642 | struct drm_display_mode *adjusted_mode = |
4706 | struct drm_display_mode *adjusted_mode = |
4643 | &intel_crtc->config.adjusted_mode; |
4707 | &intel_crtc->config.adjusted_mode; |
4644 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4708 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4645 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4709 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4646 | 4710 | ||
4647 | /* We need to be careful not to changed the adjusted mode, for otherwise |
4711 | /* We need to be careful not to changed the adjusted mode, for otherwise |
4648 | * the hw state checker will get angry at the mismatch. */ |
4712 | * the hw state checker will get angry at the mismatch. */ |
4649 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
4713 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
4650 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
4714 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
4651 | 4715 | ||
4652 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4716 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4653 | /* the chip adds 2 halflines automatically */ |
4717 | /* the chip adds 2 halflines automatically */ |
4654 | crtc_vtotal -= 1; |
4718 | crtc_vtotal -= 1; |
4655 | crtc_vblank_end -= 1; |
4719 | crtc_vblank_end -= 1; |
4656 | vsyncshift = adjusted_mode->crtc_hsync_start |
4720 | vsyncshift = adjusted_mode->crtc_hsync_start |
4657 | - adjusted_mode->crtc_htotal / 2; |
4721 | - adjusted_mode->crtc_htotal / 2; |
4658 | } else { |
4722 | } else { |
4659 | vsyncshift = 0; |
4723 | vsyncshift = 0; |
4660 | } |
4724 | } |
4661 | 4725 | ||
4662 | if (INTEL_INFO(dev)->gen > 3) |
4726 | if (INTEL_INFO(dev)->gen > 3) |
4663 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
4727 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
4664 | 4728 | ||
4665 | I915_WRITE(HTOTAL(cpu_transcoder), |
4729 | I915_WRITE(HTOTAL(cpu_transcoder), |
4666 | (adjusted_mode->crtc_hdisplay - 1) | |
4730 | (adjusted_mode->crtc_hdisplay - 1) | |
4667 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
4731 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
4668 | I915_WRITE(HBLANK(cpu_transcoder), |
4732 | I915_WRITE(HBLANK(cpu_transcoder), |
4669 | (adjusted_mode->crtc_hblank_start - 1) | |
4733 | (adjusted_mode->crtc_hblank_start - 1) | |
4670 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
4734 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
4671 | I915_WRITE(HSYNC(cpu_transcoder), |
4735 | I915_WRITE(HSYNC(cpu_transcoder), |
4672 | (adjusted_mode->crtc_hsync_start - 1) | |
4736 | (adjusted_mode->crtc_hsync_start - 1) | |
4673 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
4737 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
4674 | 4738 | ||
4675 | I915_WRITE(VTOTAL(cpu_transcoder), |
4739 | I915_WRITE(VTOTAL(cpu_transcoder), |
4676 | (adjusted_mode->crtc_vdisplay - 1) | |
4740 | (adjusted_mode->crtc_vdisplay - 1) | |
4677 | ((crtc_vtotal - 1) << 16)); |
4741 | ((crtc_vtotal - 1) << 16)); |
4678 | I915_WRITE(VBLANK(cpu_transcoder), |
4742 | I915_WRITE(VBLANK(cpu_transcoder), |
4679 | (adjusted_mode->crtc_vblank_start - 1) | |
4743 | (adjusted_mode->crtc_vblank_start - 1) | |
4680 | ((crtc_vblank_end - 1) << 16)); |
4744 | ((crtc_vblank_end - 1) << 16)); |
4681 | I915_WRITE(VSYNC(cpu_transcoder), |
4745 | I915_WRITE(VSYNC(cpu_transcoder), |
4682 | (adjusted_mode->crtc_vsync_start - 1) | |
4746 | (adjusted_mode->crtc_vsync_start - 1) | |
4683 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
4747 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
4684 | 4748 | ||
4685 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4749 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4686 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
4750 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
4687 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
4751 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
4688 | * bits. */ |
4752 | * bits. */ |
4689 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
4753 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
4690 | (pipe == PIPE_B || pipe == PIPE_C)) |
4754 | (pipe == PIPE_B || pipe == PIPE_C)) |
4691 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
4755 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
4692 | 4756 | ||
4693 | /* pipesrc controls the size that is scaled from, which should |
4757 | /* pipesrc controls the size that is scaled from, which should |
4694 | * always be the user's requested size. |
4758 | * always be the user's requested size. |
4695 | */ |
4759 | */ |
4696 | I915_WRITE(PIPESRC(pipe), |
4760 | I915_WRITE(PIPESRC(pipe), |
4697 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
4761 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
4698 | } |
4762 | } |
4699 | 4763 | ||
4700 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4764 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4701 | struct intel_crtc_config *pipe_config) |
4765 | struct intel_crtc_config *pipe_config) |
4702 | { |
4766 | { |
4703 | struct drm_device *dev = crtc->base.dev; |
4767 | struct drm_device *dev = crtc->base.dev; |
4704 | struct drm_i915_private *dev_priv = dev->dev_private; |
4768 | struct drm_i915_private *dev_priv = dev->dev_private; |
4705 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
4769 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
4706 | uint32_t tmp; |
4770 | uint32_t tmp; |
4707 | 4771 | ||
4708 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
4772 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
4709 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
4773 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
4710 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
4774 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
4711 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
4775 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
4712 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
4776 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
4713 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
4777 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
4714 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
4778 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
4715 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
4779 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
4716 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
4780 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
4717 | 4781 | ||
4718 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
4782 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
4719 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
4783 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
4720 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
4784 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
4721 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
4785 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
4722 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
4786 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
4723 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
4787 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
4724 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
4788 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
4725 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
4789 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
4726 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
4790 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
4727 | 4791 | ||
4728 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
4792 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
4729 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
4793 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
4730 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
4794 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
4731 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
4795 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
4732 | } |
4796 | } |
4733 | 4797 | ||
4734 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
4798 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
4735 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; |
4799 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; |
4736 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; |
4800 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; |
4737 | } |
4801 | } |
4738 | 4802 | ||
4739 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
4803 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
4740 | struct intel_crtc_config *pipe_config) |
4804 | struct intel_crtc_config *pipe_config) |
4741 | { |
4805 | { |
4742 | struct drm_crtc *crtc = &intel_crtc->base; |
4806 | struct drm_crtc *crtc = &intel_crtc->base; |
4743 | 4807 | ||
4744 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
4808 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
4745 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; |
4809 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; |
4746 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
4810 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
4747 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
4811 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
4748 | 4812 | ||
4749 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
4813 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
4750 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
4814 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
4751 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
4815 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
4752 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
4816 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
4753 | 4817 | ||
4754 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
4818 | crtc->mode.flags = pipe_config->adjusted_mode.flags; |
4755 | 4819 | ||
4756 | crtc->mode.clock = pipe_config->adjusted_mode.clock; |
4820 | crtc->mode.clock = pipe_config->adjusted_mode.clock; |
4757 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
4821 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
4758 | } |
4822 | } |
4759 | 4823 | ||
4760 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4824 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4761 | { |
4825 | { |
4762 | struct drm_device *dev = intel_crtc->base.dev; |
4826 | struct drm_device *dev = intel_crtc->base.dev; |
4763 | struct drm_i915_private *dev_priv = dev->dev_private; |
4827 | struct drm_i915_private *dev_priv = dev->dev_private; |
4764 | uint32_t pipeconf; |
4828 | uint32_t pipeconf; |
4765 | 4829 | ||
4766 | pipeconf = 0; |
4830 | pipeconf = 0; |
4767 | 4831 | ||
4768 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4832 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4769 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
4833 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
4770 | pipeconf |= PIPECONF_ENABLE; |
4834 | pipeconf |= PIPECONF_ENABLE; |
4771 | 4835 | ||
4772 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
4836 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
4773 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4837 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4774 | * core speed. |
4838 | * core speed. |
4775 | * |
4839 | * |
4776 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
4840 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
4777 | * pipe == 0 check? |
4841 | * pipe == 0 check? |
4778 | */ |
4842 | */ |
4779 | if (intel_crtc->config.requested_mode.clock > |
4843 | if (intel_crtc->config.requested_mode.clock > |
4780 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
4844 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
4781 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
4845 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
4782 | } |
4846 | } |
4783 | 4847 | ||
4784 | /* only g4x and later have fancy bpc/dither controls */ |
4848 | /* only g4x and later have fancy bpc/dither controls */ |
4785 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
4849 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
4786 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
4850 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
4787 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
4851 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
4788 | pipeconf |= PIPECONF_DITHER_EN | |
4852 | pipeconf |= PIPECONF_DITHER_EN | |
4789 | PIPECONF_DITHER_TYPE_SP; |
4853 | PIPECONF_DITHER_TYPE_SP; |
4790 | 4854 | ||
4791 | switch (intel_crtc->config.pipe_bpp) { |
4855 | switch (intel_crtc->config.pipe_bpp) { |
4792 | case 18: |
4856 | case 18: |
4793 | pipeconf |= PIPECONF_6BPC; |
4857 | pipeconf |= PIPECONF_6BPC; |
4794 | break; |
4858 | break; |
4795 | case 24: |
4859 | case 24: |
4796 | pipeconf |= PIPECONF_8BPC; |
4860 | pipeconf |= PIPECONF_8BPC; |
4797 | break; |
4861 | break; |
4798 | case 30: |
4862 | case 30: |
4799 | pipeconf |= PIPECONF_10BPC; |
4863 | pipeconf |= PIPECONF_10BPC; |
4800 | break; |
4864 | break; |
4801 | default: |
4865 | default: |
4802 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
4866 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
4803 | BUG(); |
4867 | BUG(); |
4804 | } |
4868 | } |
4805 | } |
4869 | } |
4806 | 4870 | ||
4807 | if (HAS_PIPE_CXSR(dev)) { |
4871 | if (HAS_PIPE_CXSR(dev)) { |
4808 | if (intel_crtc->lowfreq_avail) { |
4872 | if (intel_crtc->lowfreq_avail) { |
4809 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
4873 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
4810 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4874 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4811 | } else { |
4875 | } else { |
4812 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
4876 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
4813 | } |
4877 | } |
4814 | } |
4878 | } |
4815 | 4879 | ||
4816 | if (!IS_GEN2(dev) && |
4880 | if (!IS_GEN2(dev) && |
4817 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
4881 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
4818 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4882 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4819 | else |
4883 | else |
4820 | pipeconf |= PIPECONF_PROGRESSIVE; |
4884 | pipeconf |= PIPECONF_PROGRESSIVE; |
4821 | 4885 | ||
4822 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
4886 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
4823 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
4887 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
4824 | 4888 | ||
4825 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4889 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4826 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
4890 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
4827 | } |
4891 | } |
4828 | 4892 | ||
4829 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4893 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4830 | int x, int y, |
4894 | int x, int y, |
4831 | struct drm_framebuffer *fb) |
4895 | struct drm_framebuffer *fb) |
4832 | { |
4896 | { |
4833 | struct drm_device *dev = crtc->dev; |
4897 | struct drm_device *dev = crtc->dev; |
4834 | struct drm_i915_private *dev_priv = dev->dev_private; |
4898 | struct drm_i915_private *dev_priv = dev->dev_private; |
4835 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4836 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4900 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
4837 | int pipe = intel_crtc->pipe; |
4901 | int pipe = intel_crtc->pipe; |
4838 | int plane = intel_crtc->plane; |
4902 | int plane = intel_crtc->plane; |
4839 | int refclk, num_connectors = 0; |
4903 | int refclk, num_connectors = 0; |
4840 | intel_clock_t clock, reduced_clock; |
4904 | intel_clock_t clock, reduced_clock; |
4841 | u32 dspcntr; |
4905 | u32 dspcntr; |
4842 | bool ok, has_reduced_clock = false; |
4906 | bool ok, has_reduced_clock = false; |
4843 | bool is_lvds = false; |
4907 | bool is_lvds = false; |
4844 | struct intel_encoder *encoder; |
4908 | struct intel_encoder *encoder; |
4845 | const intel_limit_t *limit; |
4909 | const intel_limit_t *limit; |
4846 | int ret; |
4910 | int ret; |
4847 | 4911 | ||
4848 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4912 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4849 | switch (encoder->type) { |
4913 | switch (encoder->type) { |
4850 | case INTEL_OUTPUT_LVDS: |
4914 | case INTEL_OUTPUT_LVDS: |
4851 | is_lvds = true; |
4915 | is_lvds = true; |
4852 | break; |
4916 | break; |
4853 | } |
4917 | } |
4854 | 4918 | ||
4855 | num_connectors++; |
4919 | num_connectors++; |
4856 | } |
4920 | } |
4857 | 4921 | ||
4858 | refclk = i9xx_get_refclk(crtc, num_connectors); |
4922 | refclk = i9xx_get_refclk(crtc, num_connectors); |
4859 | 4923 | ||
4860 | /* |
4924 | /* |
4861 | * Returns a set of divisors for the desired target clock with the given |
4925 | * Returns a set of divisors for the desired target clock with the given |
4862 | * refclk, or FALSE. The returned values represent the clock equation: |
4926 | * refclk, or FALSE. The returned values represent the clock equation: |
4863 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4927 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
4864 | */ |
4928 | */ |
4865 | limit = intel_limit(crtc, refclk); |
4929 | limit = intel_limit(crtc, refclk); |
4866 | ok = dev_priv->display.find_dpll(limit, crtc, |
4930 | ok = dev_priv->display.find_dpll(limit, crtc, |
4867 | intel_crtc->config.port_clock, |
4931 | intel_crtc->config.port_clock, |
4868 | refclk, NULL, &clock); |
4932 | refclk, NULL, &clock); |
4869 | if (!ok && !intel_crtc->config.clock_set) { |
4933 | if (!ok && !intel_crtc->config.clock_set) { |
4870 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4934 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
4871 | return -EINVAL; |
4935 | return -EINVAL; |
4872 | } |
4936 | } |
4873 | 4937 | ||
4874 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4938 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4875 | /* |
4939 | /* |
4876 | * Ensure we match the reduced clock's P to the target clock. |
4940 | * Ensure we match the reduced clock's P to the target clock. |
4877 | * If the clocks don't match, we can't switch the display clock |
4941 | * If the clocks don't match, we can't switch the display clock |
4878 | * by using the FP0/FP1. In such case we will disable the LVDS |
4942 | * by using the FP0/FP1. In such case we will disable the LVDS |
4879 | * downclock feature. |
4943 | * downclock feature. |
4880 | */ |
4944 | */ |
4881 | has_reduced_clock = |
4945 | has_reduced_clock = |
4882 | dev_priv->display.find_dpll(limit, crtc, |
4946 | dev_priv->display.find_dpll(limit, crtc, |
4883 | dev_priv->lvds_downclock, |
4947 | dev_priv->lvds_downclock, |
4884 | refclk, &clock, |
4948 | refclk, &clock, |
4885 | &reduced_clock); |
4949 | &reduced_clock); |
4886 | } |
4950 | } |
4887 | /* Compat-code for transition, will disappear. */ |
4951 | /* Compat-code for transition, will disappear. */ |
4888 | if (!intel_crtc->config.clock_set) { |
4952 | if (!intel_crtc->config.clock_set) { |
4889 | intel_crtc->config.dpll.n = clock.n; |
4953 | intel_crtc->config.dpll.n = clock.n; |
4890 | intel_crtc->config.dpll.m1 = clock.m1; |
4954 | intel_crtc->config.dpll.m1 = clock.m1; |
4891 | intel_crtc->config.dpll.m2 = clock.m2; |
4955 | intel_crtc->config.dpll.m2 = clock.m2; |
4892 | intel_crtc->config.dpll.p1 = clock.p1; |
4956 | intel_crtc->config.dpll.p1 = clock.p1; |
4893 | intel_crtc->config.dpll.p2 = clock.p2; |
4957 | intel_crtc->config.dpll.p2 = clock.p2; |
4894 | } |
4958 | } |
4895 | 4959 | ||
4896 | if (IS_GEN2(dev)) |
4960 | if (IS_GEN2(dev)) |
4897 | i8xx_update_pll(intel_crtc, |
4961 | i8xx_update_pll(intel_crtc, |
4898 | has_reduced_clock ? &reduced_clock : NULL, |
4962 | has_reduced_clock ? &reduced_clock : NULL, |
4899 | num_connectors); |
4963 | num_connectors); |
4900 | else if (IS_VALLEYVIEW(dev)) |
4964 | else if (IS_VALLEYVIEW(dev)) |
4901 | vlv_update_pll(intel_crtc); |
4965 | vlv_update_pll(intel_crtc); |
4902 | else |
4966 | else |
4903 | i9xx_update_pll(intel_crtc, |
4967 | i9xx_update_pll(intel_crtc, |
4904 | has_reduced_clock ? &reduced_clock : NULL, |
4968 | has_reduced_clock ? &reduced_clock : NULL, |
4905 | num_connectors); |
4969 | num_connectors); |
4906 | 4970 | ||
4907 | /* Set up the display plane register */ |
4971 | /* Set up the display plane register */ |
4908 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
4972 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
4909 | 4973 | ||
4910 | if (!IS_VALLEYVIEW(dev)) { |
4974 | if (!IS_VALLEYVIEW(dev)) { |
4911 | if (pipe == 0) |
4975 | if (pipe == 0) |
4912 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
4976 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
4913 | else |
4977 | else |
4914 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
4978 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
4915 | } |
4979 | } |
4916 | 4980 | ||
4917 | intel_set_pipe_timings(intel_crtc); |
4981 | intel_set_pipe_timings(intel_crtc); |
4918 | 4982 | ||
4919 | /* pipesrc and dspsize control the size that is scaled from, |
4983 | /* pipesrc and dspsize control the size that is scaled from, |
4920 | * which should always be the user's requested size. |
4984 | * which should always be the user's requested size. |
4921 | */ |
4985 | */ |
4922 | I915_WRITE(DSPSIZE(plane), |
4986 | I915_WRITE(DSPSIZE(plane), |
4923 | ((mode->vdisplay - 1) << 16) | |
4987 | ((mode->vdisplay - 1) << 16) | |
4924 | (mode->hdisplay - 1)); |
4988 | (mode->hdisplay - 1)); |
4925 | I915_WRITE(DSPPOS(plane), 0); |
4989 | I915_WRITE(DSPPOS(plane), 0); |
4926 | 4990 | ||
4927 | i9xx_set_pipeconf(intel_crtc); |
4991 | i9xx_set_pipeconf(intel_crtc); |
4928 | 4992 | ||
4929 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4993 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4930 | POSTING_READ(DSPCNTR(plane)); |
4994 | POSTING_READ(DSPCNTR(plane)); |
4931 | 4995 | ||
4932 | ret = intel_pipe_set_base(crtc, x, y, fb); |
4996 | ret = intel_pipe_set_base(crtc, x, y, fb); |
4933 | 4997 | ||
4934 | intel_update_watermarks(dev); |
4998 | intel_update_watermarks(dev); |
4935 | 4999 | ||
4936 | return ret; |
5000 | return ret; |
4937 | } |
5001 | } |
4938 | 5002 | ||
4939 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5003 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
4940 | struct intel_crtc_config *pipe_config) |
5004 | struct intel_crtc_config *pipe_config) |
4941 | { |
5005 | { |
4942 | struct drm_device *dev = crtc->base.dev; |
5006 | struct drm_device *dev = crtc->base.dev; |
4943 | struct drm_i915_private *dev_priv = dev->dev_private; |
5007 | struct drm_i915_private *dev_priv = dev->dev_private; |
4944 | uint32_t tmp; |
5008 | uint32_t tmp; |
4945 | 5009 | ||
4946 | tmp = I915_READ(PFIT_CONTROL); |
5010 | tmp = I915_READ(PFIT_CONTROL); |
4947 | if (!(tmp & PFIT_ENABLE)) |
5011 | if (!(tmp & PFIT_ENABLE)) |
4948 | return; |
5012 | return; |
4949 | 5013 | ||
4950 | /* Check whether the pfit is attached to our pipe. */ |
5014 | /* Check whether the pfit is attached to our pipe. */ |
4951 | if (INTEL_INFO(dev)->gen < 4) { |
5015 | if (INTEL_INFO(dev)->gen < 4) { |
4952 | if (crtc->pipe != PIPE_B) |
5016 | if (crtc->pipe != PIPE_B) |
4953 | return; |
5017 | return; |
4954 | } else { |
5018 | } else { |
4955 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
5019 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
4956 | return; |
5020 | return; |
4957 | } |
5021 | } |
4958 | 5022 | ||
4959 | pipe_config->gmch_pfit.control = tmp; |
5023 | pipe_config->gmch_pfit.control = tmp; |
4960 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5024 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
4961 | if (INTEL_INFO(dev)->gen < 5) |
5025 | if (INTEL_INFO(dev)->gen < 5) |
4962 | pipe_config->gmch_pfit.lvds_border_bits = |
5026 | pipe_config->gmch_pfit.lvds_border_bits = |
4963 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
5027 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
4964 | } |
5028 | } |
4965 | 5029 | ||
4966 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5030 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
4967 | struct intel_crtc_config *pipe_config) |
5031 | struct intel_crtc_config *pipe_config) |
4968 | { |
5032 | { |
4969 | struct drm_device *dev = crtc->base.dev; |
5033 | struct drm_device *dev = crtc->base.dev; |
4970 | struct drm_i915_private *dev_priv = dev->dev_private; |
5034 | struct drm_i915_private *dev_priv = dev->dev_private; |
4971 | uint32_t tmp; |
5035 | uint32_t tmp; |
4972 | 5036 | ||
4973 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5037 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
4974 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5038 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
4975 | 5039 | ||
4976 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5040 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
4977 | if (!(tmp & PIPECONF_ENABLE)) |
5041 | if (!(tmp & PIPECONF_ENABLE)) |
4978 | return false; |
5042 | return false; |
- | 5043 | ||
- | 5044 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
|
- | 5045 | switch (tmp & PIPECONF_BPC_MASK) { |
|
- | 5046 | case PIPECONF_6BPC: |
|
- | 5047 | pipe_config->pipe_bpp = 18; |
|
- | 5048 | break; |
|
- | 5049 | case PIPECONF_8BPC: |
|
- | 5050 | pipe_config->pipe_bpp = 24; |
|
- | 5051 | break; |
|
- | 5052 | case PIPECONF_10BPC: |
|
- | 5053 | pipe_config->pipe_bpp = 30; |
|
- | 5054 | break; |
|
- | 5055 | default: |
|
- | 5056 | break; |
|
- | 5057 | } |
|
- | 5058 | } |
|
4979 | 5059 | ||
4980 | intel_get_pipe_timings(crtc, pipe_config); |
5060 | intel_get_pipe_timings(crtc, pipe_config); |
4981 | 5061 | ||
4982 | i9xx_get_pfit_config(crtc, pipe_config); |
5062 | i9xx_get_pfit_config(crtc, pipe_config); |
4983 | 5063 | ||
4984 | if (INTEL_INFO(dev)->gen >= 4) { |
5064 | if (INTEL_INFO(dev)->gen >= 4) { |
4985 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
5065 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
4986 | pipe_config->pixel_multiplier = |
5066 | pipe_config->pixel_multiplier = |
4987 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
5067 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
4988 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
5068 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
4989 | pipe_config->dpll_hw_state.dpll_md = tmp; |
5069 | pipe_config->dpll_hw_state.dpll_md = tmp; |
4990 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5070 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
4991 | tmp = I915_READ(DPLL(crtc->pipe)); |
5071 | tmp = I915_READ(DPLL(crtc->pipe)); |
4992 | pipe_config->pixel_multiplier = |
5072 | pipe_config->pixel_multiplier = |
4993 | ((tmp & SDVO_MULTIPLIER_MASK) |
5073 | ((tmp & SDVO_MULTIPLIER_MASK) |
4994 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
5074 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
4995 | } else { |
5075 | } else { |
4996 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
5076 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
4997 | * port and will be fixed up in the encoder->get_config |
5077 | * port and will be fixed up in the encoder->get_config |
4998 | * function. */ |
5078 | * function. */ |
4999 | pipe_config->pixel_multiplier = 1; |
5079 | pipe_config->pixel_multiplier = 1; |
5000 | } |
5080 | } |
5001 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5081 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5002 | if (!IS_VALLEYVIEW(dev)) { |
5082 | if (!IS_VALLEYVIEW(dev)) { |
5003 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
5083 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
5004 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
5084 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
5005 | } else { |
5085 | } else { |
5006 | /* Mask out read-only status bits. */ |
5086 | /* Mask out read-only status bits. */ |
5007 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5087 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5008 | DPLL_PORTC_READY_MASK | |
5088 | DPLL_PORTC_READY_MASK | |
5009 | DPLL_PORTB_READY_MASK); |
5089 | DPLL_PORTB_READY_MASK); |
5010 | } |
5090 | } |
5011 | 5091 | ||
5012 | return true; |
5092 | return true; |
5013 | } |
5093 | } |
5014 | 5094 | ||
5015 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
5095 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
5016 | { |
5096 | { |
5017 | struct drm_i915_private *dev_priv = dev->dev_private; |
5097 | struct drm_i915_private *dev_priv = dev->dev_private; |
5018 | struct drm_mode_config *mode_config = &dev->mode_config; |
5098 | struct drm_mode_config *mode_config = &dev->mode_config; |
5019 | struct intel_encoder *encoder; |
5099 | struct intel_encoder *encoder; |
5020 | u32 val, final; |
5100 | u32 val, final; |
5021 | bool has_lvds = false; |
5101 | bool has_lvds = false; |
5022 | bool has_cpu_edp = false; |
5102 | bool has_cpu_edp = false; |
5023 | bool has_panel = false; |
5103 | bool has_panel = false; |
5024 | bool has_ck505 = false; |
5104 | bool has_ck505 = false; |
5025 | bool can_ssc = false; |
5105 | bool can_ssc = false; |
5026 | 5106 | ||
5027 | /* We need to take the global config into account */ |
5107 | /* We need to take the global config into account */ |
5028 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5108 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5029 | base.head) { |
5109 | base.head) { |
5030 | switch (encoder->type) { |
5110 | switch (encoder->type) { |
5031 | case INTEL_OUTPUT_LVDS: |
5111 | case INTEL_OUTPUT_LVDS: |
5032 | has_panel = true; |
5112 | has_panel = true; |
5033 | has_lvds = true; |
5113 | has_lvds = true; |
5034 | break; |
5114 | break; |
5035 | case INTEL_OUTPUT_EDP: |
5115 | case INTEL_OUTPUT_EDP: |
5036 | has_panel = true; |
5116 | has_panel = true; |
5037 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
5117 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
5038 | has_cpu_edp = true; |
5118 | has_cpu_edp = true; |
5039 | break; |
5119 | break; |
5040 | } |
5120 | } |
5041 | } |
5121 | } |
5042 | 5122 | ||
5043 | if (HAS_PCH_IBX(dev)) { |
5123 | if (HAS_PCH_IBX(dev)) { |
5044 | has_ck505 = dev_priv->vbt.display_clock_mode; |
5124 | has_ck505 = dev_priv->vbt.display_clock_mode; |
5045 | can_ssc = has_ck505; |
5125 | can_ssc = has_ck505; |
5046 | } else { |
5126 | } else { |
5047 | has_ck505 = false; |
5127 | has_ck505 = false; |
5048 | can_ssc = true; |
5128 | can_ssc = true; |
5049 | } |
5129 | } |
5050 | 5130 | ||
5051 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5131 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5052 | has_panel, has_lvds, has_ck505); |
5132 | has_panel, has_lvds, has_ck505); |
5053 | 5133 | ||
5054 | /* Ironlake: try to setup display ref clock before DPLL |
5134 | /* Ironlake: try to setup display ref clock before DPLL |
5055 | * enabling. This is only under driver's control after |
5135 | * enabling. This is only under driver's control after |
5056 | * PCH B stepping, previous chipset stepping should be |
5136 | * PCH B stepping, previous chipset stepping should be |
5057 | * ignoring this setting. |
5137 | * ignoring this setting. |
5058 | */ |
5138 | */ |
5059 | val = I915_READ(PCH_DREF_CONTROL); |
5139 | val = I915_READ(PCH_DREF_CONTROL); |
5060 | 5140 | ||
5061 | /* As we must carefully and slowly disable/enable each source in turn, |
5141 | /* As we must carefully and slowly disable/enable each source in turn, |
5062 | * compute the final state we want first and check if we need to |
5142 | * compute the final state we want first and check if we need to |
5063 | * make any changes at all. |
5143 | * make any changes at all. |
5064 | */ |
5144 | */ |
5065 | final = val; |
5145 | final = val; |
5066 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
5146 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
5067 | if (has_ck505) |
5147 | if (has_ck505) |
5068 | final |= DREF_NONSPREAD_CK505_ENABLE; |
5148 | final |= DREF_NONSPREAD_CK505_ENABLE; |
5069 | else |
5149 | else |
5070 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
5150 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
5071 | 5151 | ||
5072 | final &= ~DREF_SSC_SOURCE_MASK; |
5152 | final &= ~DREF_SSC_SOURCE_MASK; |
5073 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5153 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5074 | final &= ~DREF_SSC1_ENABLE; |
5154 | final &= ~DREF_SSC1_ENABLE; |
5075 | 5155 | ||
5076 | if (has_panel) { |
5156 | if (has_panel) { |
5077 | final |= DREF_SSC_SOURCE_ENABLE; |
5157 | final |= DREF_SSC_SOURCE_ENABLE; |
5078 | 5158 | ||
5079 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5159 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5080 | final |= DREF_SSC1_ENABLE; |
5160 | final |= DREF_SSC1_ENABLE; |
5081 | 5161 | ||
5082 | if (has_cpu_edp) { |
5162 | if (has_cpu_edp) { |
5083 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5163 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5084 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5164 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5085 | else |
5165 | else |
5086 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5166 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5087 | } else |
5167 | } else |
5088 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5168 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5089 | } else { |
5169 | } else { |
5090 | final |= DREF_SSC_SOURCE_DISABLE; |
5170 | final |= DREF_SSC_SOURCE_DISABLE; |
5091 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5171 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5092 | } |
5172 | } |
5093 | 5173 | ||
5094 | if (final == val) |
5174 | if (final == val) |
5095 | return; |
5175 | return; |
5096 | 5176 | ||
5097 | /* Always enable nonspread source */ |
5177 | /* Always enable nonspread source */ |
5098 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
5178 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
5099 | 5179 | ||
5100 | if (has_ck505) |
5180 | if (has_ck505) |
5101 | val |= DREF_NONSPREAD_CK505_ENABLE; |
5181 | val |= DREF_NONSPREAD_CK505_ENABLE; |
5102 | else |
5182 | else |
5103 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
5183 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
5104 | 5184 | ||
5105 | if (has_panel) { |
5185 | if (has_panel) { |
5106 | val &= ~DREF_SSC_SOURCE_MASK; |
5186 | val &= ~DREF_SSC_SOURCE_MASK; |
5107 | val |= DREF_SSC_SOURCE_ENABLE; |
5187 | val |= DREF_SSC_SOURCE_ENABLE; |
5108 | 5188 | ||
5109 | /* SSC must be turned on before enabling the CPU output */ |
5189 | /* SSC must be turned on before enabling the CPU output */ |
5110 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5190 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5111 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
5191 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
5112 | val |= DREF_SSC1_ENABLE; |
5192 | val |= DREF_SSC1_ENABLE; |
5113 | } else |
5193 | } else |
5114 | val &= ~DREF_SSC1_ENABLE; |
5194 | val &= ~DREF_SSC1_ENABLE; |
5115 | 5195 | ||
5116 | /* Get SSC going before enabling the outputs */ |
5196 | /* Get SSC going before enabling the outputs */ |
5117 | I915_WRITE(PCH_DREF_CONTROL, val); |
5197 | I915_WRITE(PCH_DREF_CONTROL, val); |
5118 | POSTING_READ(PCH_DREF_CONTROL); |
5198 | POSTING_READ(PCH_DREF_CONTROL); |
5119 | udelay(200); |
5199 | udelay(200); |
5120 | 5200 | ||
5121 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5201 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5122 | 5202 | ||
5123 | /* Enable CPU source on CPU attached eDP */ |
5203 | /* Enable CPU source on CPU attached eDP */ |
5124 | if (has_cpu_edp) { |
5204 | if (has_cpu_edp) { |
5125 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5205 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
5126 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
5206 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
5127 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5207 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5128 | } |
5208 | } |
5129 | else |
5209 | else |
5130 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5210 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5131 | } else |
5211 | } else |
5132 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5212 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5133 | 5213 | ||
5134 | I915_WRITE(PCH_DREF_CONTROL, val); |
5214 | I915_WRITE(PCH_DREF_CONTROL, val); |
5135 | POSTING_READ(PCH_DREF_CONTROL); |
5215 | POSTING_READ(PCH_DREF_CONTROL); |
5136 | udelay(200); |
5216 | udelay(200); |
5137 | } else { |
5217 | } else { |
5138 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
5218 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
5139 | 5219 | ||
5140 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5220 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5141 | 5221 | ||
5142 | /* Turn off CPU output */ |
5222 | /* Turn off CPU output */ |
5143 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5223 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5144 | 5224 | ||
5145 | I915_WRITE(PCH_DREF_CONTROL, val); |
5225 | I915_WRITE(PCH_DREF_CONTROL, val); |
5146 | POSTING_READ(PCH_DREF_CONTROL); |
5226 | POSTING_READ(PCH_DREF_CONTROL); |
5147 | udelay(200); |
5227 | udelay(200); |
5148 | 5228 | ||
5149 | /* Turn off the SSC source */ |
5229 | /* Turn off the SSC source */ |
5150 | val &= ~DREF_SSC_SOURCE_MASK; |
5230 | val &= ~DREF_SSC_SOURCE_MASK; |
5151 | val |= DREF_SSC_SOURCE_DISABLE; |
5231 | val |= DREF_SSC_SOURCE_DISABLE; |
5152 | 5232 | ||
5153 | /* Turn off SSC1 */ |
5233 | /* Turn off SSC1 */ |
5154 | val &= ~DREF_SSC1_ENABLE; |
5234 | val &= ~DREF_SSC1_ENABLE; |
5155 | 5235 | ||
5156 | I915_WRITE(PCH_DREF_CONTROL, val); |
5236 | I915_WRITE(PCH_DREF_CONTROL, val); |
5157 | POSTING_READ(PCH_DREF_CONTROL); |
5237 | POSTING_READ(PCH_DREF_CONTROL); |
5158 | udelay(200); |
5238 | udelay(200); |
5159 | } |
5239 | } |
5160 | 5240 | ||
5161 | BUG_ON(val != final); |
5241 | BUG_ON(val != final); |
5162 | } |
5242 | } |
5163 | 5243 | ||
5164 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
5244 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
5165 | { |
5245 | { |
5166 | uint32_t tmp; |
5246 | uint32_t tmp; |
5167 | 5247 | ||
5168 | tmp = I915_READ(SOUTH_CHICKEN2); |
5248 | tmp = I915_READ(SOUTH_CHICKEN2); |
5169 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
5249 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
5170 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5250 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5171 | 5251 | ||
5172 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5252 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5173 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
5253 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
5174 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
5254 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
5175 | 5255 | ||
5176 | tmp = I915_READ(SOUTH_CHICKEN2); |
5256 | tmp = I915_READ(SOUTH_CHICKEN2); |
5177 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
5257 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
5178 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5258 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
5179 | 5259 | ||
5180 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5260 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5181 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
5261 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
5182 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
5262 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
5183 | } |
5263 | } |
5184 | 5264 | ||
5185 | /* WaMPhyProgramming:hsw */ |
5265 | /* WaMPhyProgramming:hsw */ |
5186 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
5266 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
5187 | { |
5267 | { |
5188 | uint32_t tmp; |
5268 | uint32_t tmp; |
5189 | 5269 | ||
5190 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
5270 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
5191 | tmp &= ~(0xFF << 24); |
5271 | tmp &= ~(0xFF << 24); |
5192 | tmp |= (0x12 << 24); |
5272 | tmp |= (0x12 << 24); |
5193 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
5273 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
5194 | 5274 | ||
5195 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5275 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5196 | tmp |= (1 << 11); |
5276 | tmp |= (1 << 11); |
5197 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
5277 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
5198 | 5278 | ||
5199 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
5279 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
5200 | tmp |= (1 << 11); |
5280 | tmp |= (1 << 11); |
5201 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
5281 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
5202 | 5282 | ||
5203 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5283 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5204 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5284 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5205 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
5285 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
5206 | 5286 | ||
5207 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
5287 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
5208 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5288 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
5209 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
5289 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
5210 | 5290 | ||
5211 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5291 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5212 | tmp &= ~(7 << 13); |
5292 | tmp &= ~(7 << 13); |
5213 | tmp |= (5 << 13); |
5293 | tmp |= (5 << 13); |
5214 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
5294 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
5215 | 5295 | ||
5216 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5296 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5217 | tmp &= ~(7 << 13); |
5297 | tmp &= ~(7 << 13); |
5218 | tmp |= (5 << 13); |
5298 | tmp |= (5 << 13); |
5219 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
5299 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
5220 | 5300 | ||
5221 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
5301 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
5222 | tmp &= ~0xFF; |
5302 | tmp &= ~0xFF; |
5223 | tmp |= 0x1C; |
5303 | tmp |= 0x1C; |
5224 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
5304 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
5225 | 5305 | ||
5226 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
5306 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
5227 | tmp &= ~0xFF; |
5307 | tmp &= ~0xFF; |
5228 | tmp |= 0x1C; |
5308 | tmp |= 0x1C; |
5229 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
5309 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
5230 | 5310 | ||
5231 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
5311 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
5232 | tmp &= ~(0xFF << 16); |
5312 | tmp &= ~(0xFF << 16); |
5233 | tmp |= (0x1C << 16); |
5313 | tmp |= (0x1C << 16); |
5234 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
5314 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
5235 | 5315 | ||
5236 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
5316 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
5237 | tmp &= ~(0xFF << 16); |
5317 | tmp &= ~(0xFF << 16); |
5238 | tmp |= (0x1C << 16); |
5318 | tmp |= (0x1C << 16); |
5239 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
5319 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
5240 | 5320 | ||
5241 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5321 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5242 | tmp |= (1 << 27); |
5322 | tmp |= (1 << 27); |
5243 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
5323 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
5244 | 5324 | ||
5245 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5325 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5246 | tmp |= (1 << 27); |
5326 | tmp |= (1 << 27); |
5247 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
5327 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
5248 | 5328 | ||
5249 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5329 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5250 | tmp &= ~(0xF << 28); |
5330 | tmp &= ~(0xF << 28); |
5251 | tmp |= (4 << 28); |
5331 | tmp |= (4 << 28); |
5252 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
5332 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
5253 | 5333 | ||
5254 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5334 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5255 | tmp &= ~(0xF << 28); |
5335 | tmp &= ~(0xF << 28); |
5256 | tmp |= (4 << 28); |
5336 | tmp |= (4 << 28); |
5257 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
5337 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
5258 | } |
5338 | } |
5259 | 5339 | ||
5260 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5340 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5261 | * Programming" based on the parameters passed: |
5341 | * Programming" based on the parameters passed: |
5262 | * - Sequence to enable CLKOUT_DP |
5342 | * - Sequence to enable CLKOUT_DP |
5263 | * - Sequence to enable CLKOUT_DP without spread |
5343 | * - Sequence to enable CLKOUT_DP without spread |
5264 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
5344 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
5265 | */ |
5345 | */ |
5266 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
5346 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
5267 | bool with_fdi) |
5347 | bool with_fdi) |
5268 | { |
5348 | { |
5269 | struct drm_i915_private *dev_priv = dev->dev_private; |
5349 | struct drm_i915_private *dev_priv = dev->dev_private; |
5270 | uint32_t reg, tmp; |
5350 | uint32_t reg, tmp; |
5271 | 5351 | ||
5272 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
5352 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
5273 | with_spread = true; |
5353 | with_spread = true; |
5274 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
5354 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
5275 | with_fdi, "LP PCH doesn't have FDI\n")) |
5355 | with_fdi, "LP PCH doesn't have FDI\n")) |
5276 | with_fdi = false; |
5356 | with_fdi = false; |
5277 | 5357 | ||
5278 | mutex_lock(&dev_priv->dpio_lock); |
5358 | mutex_lock(&dev_priv->dpio_lock); |
5279 | 5359 | ||
5280 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5360 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5281 | tmp &= ~SBI_SSCCTL_DISABLE; |
5361 | tmp &= ~SBI_SSCCTL_DISABLE; |
5282 | tmp |= SBI_SSCCTL_PATHALT; |
5362 | tmp |= SBI_SSCCTL_PATHALT; |
5283 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5363 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5284 | 5364 | ||
5285 | udelay(24); |
5365 | udelay(24); |
5286 | 5366 | ||
5287 | if (with_spread) { |
5367 | if (with_spread) { |
5288 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5368 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5289 | tmp &= ~SBI_SSCCTL_PATHALT; |
5369 | tmp &= ~SBI_SSCCTL_PATHALT; |
5290 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5370 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5291 | 5371 | ||
5292 | if (with_fdi) { |
5372 | if (with_fdi) { |
5293 | lpt_reset_fdi_mphy(dev_priv); |
5373 | lpt_reset_fdi_mphy(dev_priv); |
5294 | lpt_program_fdi_mphy(dev_priv); |
5374 | lpt_program_fdi_mphy(dev_priv); |
5295 | } |
5375 | } |
5296 | } |
5376 | } |
5297 | 5377 | ||
5298 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5378 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5299 | SBI_GEN0 : SBI_DBUFF0; |
5379 | SBI_GEN0 : SBI_DBUFF0; |
5300 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5380 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5301 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5381 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5302 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5382 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5303 | 5383 | ||
5304 | mutex_unlock(&dev_priv->dpio_lock); |
5384 | mutex_unlock(&dev_priv->dpio_lock); |
5305 | } |
5385 | } |
5306 | 5386 | ||
5307 | /* Sequence to disable CLKOUT_DP */ |
5387 | /* Sequence to disable CLKOUT_DP */ |
5308 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
5388 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
5309 | { |
5389 | { |
5310 | struct drm_i915_private *dev_priv = dev->dev_private; |
5390 | struct drm_i915_private *dev_priv = dev->dev_private; |
5311 | uint32_t reg, tmp; |
5391 | uint32_t reg, tmp; |
5312 | 5392 | ||
5313 | mutex_lock(&dev_priv->dpio_lock); |
5393 | mutex_lock(&dev_priv->dpio_lock); |
5314 | 5394 | ||
5315 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5395 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5316 | SBI_GEN0 : SBI_DBUFF0; |
5396 | SBI_GEN0 : SBI_DBUFF0; |
5317 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5397 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
5318 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5398 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
5319 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5399 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
5320 | 5400 | ||
5321 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5401 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
5322 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
5402 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
5323 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
5403 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
5324 | tmp |= SBI_SSCCTL_PATHALT; |
5404 | tmp |= SBI_SSCCTL_PATHALT; |
5325 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5405 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5326 | udelay(32); |
5406 | udelay(32); |
5327 | } |
5407 | } |
5328 | tmp |= SBI_SSCCTL_DISABLE; |
5408 | tmp |= SBI_SSCCTL_DISABLE; |
5329 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5409 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
5330 | } |
5410 | } |
5331 | 5411 | ||
5332 | mutex_unlock(&dev_priv->dpio_lock); |
5412 | mutex_unlock(&dev_priv->dpio_lock); |
5333 | } |
5413 | } |
5334 | 5414 | ||
5335 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5415 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5336 | { |
5416 | { |
5337 | struct drm_mode_config *mode_config = &dev->mode_config; |
5417 | struct drm_mode_config *mode_config = &dev->mode_config; |
5338 | struct intel_encoder *encoder; |
5418 | struct intel_encoder *encoder; |
5339 | bool has_vga = false; |
5419 | bool has_vga = false; |
5340 | 5420 | ||
5341 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5421 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5342 | switch (encoder->type) { |
5422 | switch (encoder->type) { |
5343 | case INTEL_OUTPUT_ANALOG: |
5423 | case INTEL_OUTPUT_ANALOG: |
5344 | has_vga = true; |
5424 | has_vga = true; |
5345 | break; |
5425 | break; |
5346 | } |
5426 | } |
5347 | } |
5427 | } |
5348 | 5428 | ||
5349 | if (has_vga) |
5429 | if (has_vga) |
5350 | lpt_enable_clkout_dp(dev, true, true); |
5430 | lpt_enable_clkout_dp(dev, true, true); |
5351 | else |
5431 | else |
5352 | lpt_disable_clkout_dp(dev); |
5432 | lpt_disable_clkout_dp(dev); |
5353 | } |
5433 | } |
5354 | 5434 | ||
5355 | /* |
5435 | /* |
5356 | * Initialize reference clocks when the driver loads |
5436 | * Initialize reference clocks when the driver loads |
5357 | */ |
5437 | */ |
5358 | void intel_init_pch_refclk(struct drm_device *dev) |
5438 | void intel_init_pch_refclk(struct drm_device *dev) |
5359 | { |
5439 | { |
5360 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
5440 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
5361 | ironlake_init_pch_refclk(dev); |
5441 | ironlake_init_pch_refclk(dev); |
5362 | else if (HAS_PCH_LPT(dev)) |
5442 | else if (HAS_PCH_LPT(dev)) |
5363 | lpt_init_pch_refclk(dev); |
5443 | lpt_init_pch_refclk(dev); |
5364 | } |
5444 | } |
5365 | 5445 | ||
5366 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5446 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5367 | { |
5447 | { |
5368 | struct drm_device *dev = crtc->dev; |
5448 | struct drm_device *dev = crtc->dev; |
5369 | struct drm_i915_private *dev_priv = dev->dev_private; |
5449 | struct drm_i915_private *dev_priv = dev->dev_private; |
5370 | struct intel_encoder *encoder; |
5450 | struct intel_encoder *encoder; |
5371 | int num_connectors = 0; |
5451 | int num_connectors = 0; |
5372 | bool is_lvds = false; |
5452 | bool is_lvds = false; |
5373 | 5453 | ||
5374 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5454 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5375 | switch (encoder->type) { |
5455 | switch (encoder->type) { |
5376 | case INTEL_OUTPUT_LVDS: |
5456 | case INTEL_OUTPUT_LVDS: |
5377 | is_lvds = true; |
5457 | is_lvds = true; |
5378 | break; |
5458 | break; |
5379 | } |
5459 | } |
5380 | num_connectors++; |
5460 | num_connectors++; |
5381 | } |
5461 | } |
5382 | 5462 | ||
5383 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5463 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5384 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5464 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5385 | dev_priv->vbt.lvds_ssc_freq); |
5465 | dev_priv->vbt.lvds_ssc_freq); |
5386 | return dev_priv->vbt.lvds_ssc_freq * 1000; |
5466 | return dev_priv->vbt.lvds_ssc_freq * 1000; |
5387 | } |
5467 | } |
5388 | 5468 | ||
5389 | return 120000; |
5469 | return 120000; |
5390 | } |
5470 | } |
5391 | 5471 | ||
5392 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
5472 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
5393 | { |
5473 | { |
5394 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5474 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5396 | int pipe = intel_crtc->pipe; |
5476 | int pipe = intel_crtc->pipe; |
5397 | uint32_t val; |
5477 | uint32_t val; |
5398 | 5478 | ||
5399 | val = 0; |
5479 | val = 0; |
5400 | 5480 | ||
5401 | switch (intel_crtc->config.pipe_bpp) { |
5481 | switch (intel_crtc->config.pipe_bpp) { |
5402 | case 18: |
5482 | case 18: |
5403 | val |= PIPECONF_6BPC; |
5483 | val |= PIPECONF_6BPC; |
5404 | break; |
5484 | break; |
5405 | case 24: |
5485 | case 24: |
5406 | val |= PIPECONF_8BPC; |
5486 | val |= PIPECONF_8BPC; |
5407 | break; |
5487 | break; |
5408 | case 30: |
5488 | case 30: |
5409 | val |= PIPECONF_10BPC; |
5489 | val |= PIPECONF_10BPC; |
5410 | break; |
5490 | break; |
5411 | case 36: |
5491 | case 36: |
5412 | val |= PIPECONF_12BPC; |
5492 | val |= PIPECONF_12BPC; |
5413 | break; |
5493 | break; |
5414 | default: |
5494 | default: |
5415 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5495 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5416 | BUG(); |
5496 | BUG(); |
5417 | } |
5497 | } |
5418 | 5498 | ||
5419 | if (intel_crtc->config.dither) |
5499 | if (intel_crtc->config.dither) |
5420 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5500 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5421 | 5501 | ||
5422 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5502 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5423 | val |= PIPECONF_INTERLACED_ILK; |
5503 | val |= PIPECONF_INTERLACED_ILK; |
5424 | else |
5504 | else |
5425 | val |= PIPECONF_PROGRESSIVE; |
5505 | val |= PIPECONF_PROGRESSIVE; |
5426 | 5506 | ||
5427 | if (intel_crtc->config.limited_color_range) |
5507 | if (intel_crtc->config.limited_color_range) |
5428 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5508 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5429 | 5509 | ||
5430 | I915_WRITE(PIPECONF(pipe), val); |
5510 | I915_WRITE(PIPECONF(pipe), val); |
5431 | POSTING_READ(PIPECONF(pipe)); |
5511 | POSTING_READ(PIPECONF(pipe)); |
5432 | } |
5512 | } |
5433 | 5513 | ||
5434 | /* |
5514 | /* |
5435 | * Set up the pipe CSC unit. |
5515 | * Set up the pipe CSC unit. |
5436 | * |
5516 | * |
5437 | * Currently only full range RGB to limited range RGB conversion |
5517 | * Currently only full range RGB to limited range RGB conversion |
5438 | * is supported, but eventually this should handle various |
5518 | * is supported, but eventually this should handle various |
5439 | * RGB<->YCbCr scenarios as well. |
5519 | * RGB<->YCbCr scenarios as well. |
5440 | */ |
5520 | */ |
5441 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
5521 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
5442 | { |
5522 | { |
5443 | struct drm_device *dev = crtc->dev; |
5523 | struct drm_device *dev = crtc->dev; |
5444 | struct drm_i915_private *dev_priv = dev->dev_private; |
5524 | struct drm_i915_private *dev_priv = dev->dev_private; |
5445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5525 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5446 | int pipe = intel_crtc->pipe; |
5526 | int pipe = intel_crtc->pipe; |
5447 | uint16_t coeff = 0x7800; /* 1.0 */ |
5527 | uint16_t coeff = 0x7800; /* 1.0 */ |
5448 | 5528 | ||
5449 | /* |
5529 | /* |
5450 | * TODO: Check what kind of values actually come out of the pipe |
5530 | * TODO: Check what kind of values actually come out of the pipe |
5451 | * with these coeff/postoff values and adjust to get the best |
5531 | * with these coeff/postoff values and adjust to get the best |
5452 | * accuracy. Perhaps we even need to take the bpc value into |
5532 | * accuracy. Perhaps we even need to take the bpc value into |
5453 | * consideration. |
5533 | * consideration. |
5454 | */ |
5534 | */ |
5455 | 5535 | ||
5456 | if (intel_crtc->config.limited_color_range) |
5536 | if (intel_crtc->config.limited_color_range) |
5457 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5537 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5458 | 5538 | ||
5459 | /* |
5539 | /* |
5460 | * GY/GU and RY/RU should be the other way around according |
5540 | * GY/GU and RY/RU should be the other way around according |
5461 | * to BSpec, but reality doesn't agree. Just set them up in |
5541 | * to BSpec, but reality doesn't agree. Just set them up in |
5462 | * a way that results in the correct picture. |
5542 | * a way that results in the correct picture. |
5463 | */ |
5543 | */ |
5464 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
5544 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
5465 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
5545 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
5466 | 5546 | ||
5467 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
5547 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
5468 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
5548 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
5469 | 5549 | ||
5470 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
5550 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
5471 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
5551 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
5472 | 5552 | ||
5473 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
5553 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
5474 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
5554 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
5475 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
5555 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
5476 | 5556 | ||
5477 | if (INTEL_INFO(dev)->gen > 6) { |
5557 | if (INTEL_INFO(dev)->gen > 6) { |
5478 | uint16_t postoff = 0; |
5558 | uint16_t postoff = 0; |
5479 | 5559 | ||
5480 | if (intel_crtc->config.limited_color_range) |
5560 | if (intel_crtc->config.limited_color_range) |
5481 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5561 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5482 | 5562 | ||
5483 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
5563 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
5484 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
5564 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
5485 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
5565 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
5486 | 5566 | ||
5487 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
5567 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
5488 | } else { |
5568 | } else { |
5489 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
5569 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
5490 | 5570 | ||
5491 | if (intel_crtc->config.limited_color_range) |
5571 | if (intel_crtc->config.limited_color_range) |
5492 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5572 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5493 | 5573 | ||
5494 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
5574 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
5495 | } |
5575 | } |
5496 | } |
5576 | } |
5497 | 5577 | ||
5498 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
5578 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
5499 | { |
5579 | { |
5500 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5580 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5502 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5582 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5503 | uint32_t val; |
5583 | uint32_t val; |
5504 | 5584 | ||
5505 | val = 0; |
5585 | val = 0; |
5506 | 5586 | ||
5507 | if (intel_crtc->config.dither) |
5587 | if (intel_crtc->config.dither) |
5508 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5588 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5509 | 5589 | ||
5510 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5590 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
5511 | val |= PIPECONF_INTERLACED_ILK; |
5591 | val |= PIPECONF_INTERLACED_ILK; |
5512 | else |
5592 | else |
5513 | val |= PIPECONF_PROGRESSIVE; |
5593 | val |= PIPECONF_PROGRESSIVE; |
5514 | 5594 | ||
5515 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5595 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5516 | POSTING_READ(PIPECONF(cpu_transcoder)); |
5596 | POSTING_READ(PIPECONF(cpu_transcoder)); |
5517 | 5597 | ||
5518 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
5598 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
5519 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
5599 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
5520 | } |
5600 | } |
5521 | 5601 | ||
5522 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5602 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5523 | intel_clock_t *clock, |
5603 | intel_clock_t *clock, |
5524 | bool *has_reduced_clock, |
5604 | bool *has_reduced_clock, |
5525 | intel_clock_t *reduced_clock) |
5605 | intel_clock_t *reduced_clock) |
5526 | { |
5606 | { |
5527 | struct drm_device *dev = crtc->dev; |
5607 | struct drm_device *dev = crtc->dev; |
5528 | struct drm_i915_private *dev_priv = dev->dev_private; |
5608 | struct drm_i915_private *dev_priv = dev->dev_private; |
5529 | struct intel_encoder *intel_encoder; |
5609 | struct intel_encoder *intel_encoder; |
5530 | int refclk; |
5610 | int refclk; |
5531 | const intel_limit_t *limit; |
5611 | const intel_limit_t *limit; |
5532 | bool ret, is_lvds = false; |
5612 | bool ret, is_lvds = false; |
5533 | 5613 | ||
5534 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5614 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5535 | switch (intel_encoder->type) { |
5615 | switch (intel_encoder->type) { |
5536 | case INTEL_OUTPUT_LVDS: |
5616 | case INTEL_OUTPUT_LVDS: |
5537 | is_lvds = true; |
5617 | is_lvds = true; |
5538 | break; |
5618 | break; |
5539 | } |
5619 | } |
5540 | } |
5620 | } |
5541 | 5621 | ||
5542 | refclk = ironlake_get_refclk(crtc); |
5622 | refclk = ironlake_get_refclk(crtc); |
5543 | 5623 | ||
5544 | /* |
5624 | /* |
5545 | * Returns a set of divisors for the desired target clock with the given |
5625 | * Returns a set of divisors for the desired target clock with the given |
5546 | * refclk, or FALSE. The returned values represent the clock equation: |
5626 | * refclk, or FALSE. The returned values represent the clock equation: |
5547 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
5627 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
5548 | */ |
5628 | */ |
5549 | limit = intel_limit(crtc, refclk); |
5629 | limit = intel_limit(crtc, refclk); |
5550 | ret = dev_priv->display.find_dpll(limit, crtc, |
5630 | ret = dev_priv->display.find_dpll(limit, crtc, |
5551 | to_intel_crtc(crtc)->config.port_clock, |
5631 | to_intel_crtc(crtc)->config.port_clock, |
5552 | refclk, NULL, clock); |
5632 | refclk, NULL, clock); |
5553 | if (!ret) |
5633 | if (!ret) |
5554 | return false; |
5634 | return false; |
5555 | 5635 | ||
5556 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5636 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5557 | /* |
5637 | /* |
5558 | * Ensure we match the reduced clock's P to the target clock. |
5638 | * Ensure we match the reduced clock's P to the target clock. |
5559 | * If the clocks don't match, we can't switch the display clock |
5639 | * If the clocks don't match, we can't switch the display clock |
5560 | * by using the FP0/FP1. In such case we will disable the LVDS |
5640 | * by using the FP0/FP1. In such case we will disable the LVDS |
5561 | * downclock feature. |
5641 | * downclock feature. |
5562 | */ |
5642 | */ |
5563 | *has_reduced_clock = |
5643 | *has_reduced_clock = |
5564 | dev_priv->display.find_dpll(limit, crtc, |
5644 | dev_priv->display.find_dpll(limit, crtc, |
5565 | dev_priv->lvds_downclock, |
5645 | dev_priv->lvds_downclock, |
5566 | refclk, clock, |
5646 | refclk, clock, |
5567 | reduced_clock); |
5647 | reduced_clock); |
5568 | } |
5648 | } |
5569 | 5649 | ||
5570 | return true; |
5650 | return true; |
5571 | } |
5651 | } |
5572 | - | ||
5573 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
- | |
5574 | { |
- | |
5575 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
5576 | uint32_t temp; |
- | |
5577 | - | ||
5578 | temp = I915_READ(SOUTH_CHICKEN1); |
- | |
5579 | if (temp & FDI_BC_BIFURCATION_SELECT) |
- | |
5580 | return; |
- | |
5581 | - | ||
5582 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
- | |
5583 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
- | |
5584 | - | ||
5585 | temp |= FDI_BC_BIFURCATION_SELECT; |
- | |
5586 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
- | |
5587 | I915_WRITE(SOUTH_CHICKEN1, temp); |
- | |
5588 | POSTING_READ(SOUTH_CHICKEN1); |
- | |
5589 | } |
- | |
5590 | - | ||
5591 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
- | |
5592 | { |
- | |
5593 | struct drm_device *dev = intel_crtc->base.dev; |
- | |
5594 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
5595 | - | ||
5596 | switch (intel_crtc->pipe) { |
- | |
5597 | case PIPE_A: |
- | |
5598 | break; |
- | |
5599 | case PIPE_B: |
- | |
5600 | if (intel_crtc->config.fdi_lanes > 2) |
- | |
5601 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
- | |
5602 | else |
- | |
5603 | cpt_enable_fdi_bc_bifurcation(dev); |
- | |
5604 | - | ||
5605 | break; |
- | |
5606 | case PIPE_C: |
- | |
5607 | cpt_enable_fdi_bc_bifurcation(dev); |
- | |
5608 | - | ||
5609 | break; |
- | |
5610 | default: |
- | |
5611 | BUG(); |
- | |
5612 | } |
- | |
5613 | } |
- | |
5614 | 5652 | ||
5615 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5653 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5616 | { |
5654 | { |
5617 | /* |
5655 | /* |
5618 | * Account for spread spectrum to avoid |
5656 | * Account for spread spectrum to avoid |
5619 | * oversubscribing the link. Max center spread |
5657 | * oversubscribing the link. Max center spread |
5620 | * is 2.5%; use 5% for safety's sake. |
5658 | * is 2.5%; use 5% for safety's sake. |
5621 | */ |
5659 | */ |
5622 | u32 bps = target_clock * bpp * 21 / 20; |
5660 | u32 bps = target_clock * bpp * 21 / 20; |
5623 | return bps / (link_bw * 8) + 1; |
5661 | return bps / (link_bw * 8) + 1; |
5624 | } |
5662 | } |
5625 | 5663 | ||
5626 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
5664 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
5627 | { |
5665 | { |
5628 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
5666 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
5629 | } |
5667 | } |
5630 | 5668 | ||
5631 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
5669 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
5632 | u32 *fp, |
5670 | u32 *fp, |
5633 | intel_clock_t *reduced_clock, u32 *fp2) |
5671 | intel_clock_t *reduced_clock, u32 *fp2) |
5634 | { |
5672 | { |
5635 | struct drm_crtc *crtc = &intel_crtc->base; |
5673 | struct drm_crtc *crtc = &intel_crtc->base; |
5636 | struct drm_device *dev = crtc->dev; |
5674 | struct drm_device *dev = crtc->dev; |
5637 | struct drm_i915_private *dev_priv = dev->dev_private; |
5675 | struct drm_i915_private *dev_priv = dev->dev_private; |
5638 | struct intel_encoder *intel_encoder; |
5676 | struct intel_encoder *intel_encoder; |
5639 | uint32_t dpll; |
5677 | uint32_t dpll; |
5640 | int factor, num_connectors = 0; |
5678 | int factor, num_connectors = 0; |
5641 | bool is_lvds = false, is_sdvo = false; |
5679 | bool is_lvds = false, is_sdvo = false; |
5642 | 5680 | ||
5643 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5681 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5644 | switch (intel_encoder->type) { |
5682 | switch (intel_encoder->type) { |
5645 | case INTEL_OUTPUT_LVDS: |
5683 | case INTEL_OUTPUT_LVDS: |
5646 | is_lvds = true; |
5684 | is_lvds = true; |
5647 | break; |
5685 | break; |
5648 | case INTEL_OUTPUT_SDVO: |
5686 | case INTEL_OUTPUT_SDVO: |
5649 | case INTEL_OUTPUT_HDMI: |
5687 | case INTEL_OUTPUT_HDMI: |
5650 | is_sdvo = true; |
5688 | is_sdvo = true; |
5651 | break; |
5689 | break; |
5652 | } |
5690 | } |
5653 | 5691 | ||
5654 | num_connectors++; |
5692 | num_connectors++; |
5655 | } |
5693 | } |
5656 | 5694 | ||
5657 | /* Enable autotuning of the PLL clock (if permissible) */ |
5695 | /* Enable autotuning of the PLL clock (if permissible) */ |
5658 | factor = 21; |
5696 | factor = 21; |
5659 | if (is_lvds) { |
5697 | if (is_lvds) { |
5660 | if ((intel_panel_use_ssc(dev_priv) && |
5698 | if ((intel_panel_use_ssc(dev_priv) && |
5661 | dev_priv->vbt.lvds_ssc_freq == 100) || |
5699 | dev_priv->vbt.lvds_ssc_freq == 100) || |
5662 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
5700 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
5663 | factor = 25; |
5701 | factor = 25; |
5664 | } else if (intel_crtc->config.sdvo_tv_clock) |
5702 | } else if (intel_crtc->config.sdvo_tv_clock) |
5665 | factor = 20; |
5703 | factor = 20; |
5666 | 5704 | ||
5667 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
5705 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
5668 | *fp |= FP_CB_TUNE; |
5706 | *fp |= FP_CB_TUNE; |
5669 | 5707 | ||
5670 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5708 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5671 | *fp2 |= FP_CB_TUNE; |
5709 | *fp2 |= FP_CB_TUNE; |
5672 | 5710 | ||
5673 | dpll = 0; |
5711 | dpll = 0; |
5674 | 5712 | ||
5675 | if (is_lvds) |
5713 | if (is_lvds) |
5676 | dpll |= DPLLB_MODE_LVDS; |
5714 | dpll |= DPLLB_MODE_LVDS; |
5677 | else |
5715 | else |
5678 | dpll |= DPLLB_MODE_DAC_SERIAL; |
5716 | dpll |= DPLLB_MODE_DAC_SERIAL; |
5679 | 5717 | ||
5680 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5718 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5681 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
5719 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
5682 | 5720 | ||
5683 | if (is_sdvo) |
5721 | if (is_sdvo) |
5684 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5722 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5685 | if (intel_crtc->config.has_dp_encoder) |
5723 | if (intel_crtc->config.has_dp_encoder) |
5686 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5724 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5687 | 5725 | ||
5688 | /* compute bitmask from p1 value */ |
5726 | /* compute bitmask from p1 value */ |
5689 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5727 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5690 | /* also FPA1 */ |
5728 | /* also FPA1 */ |
5691 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
5729 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
5692 | 5730 | ||
5693 | switch (intel_crtc->config.dpll.p2) { |
5731 | switch (intel_crtc->config.dpll.p2) { |
5694 | case 5: |
5732 | case 5: |
5695 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
5733 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
5696 | break; |
5734 | break; |
5697 | case 7: |
5735 | case 7: |
5698 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
5736 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
5699 | break; |
5737 | break; |
5700 | case 10: |
5738 | case 10: |
5701 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
5739 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
5702 | break; |
5740 | break; |
5703 | case 14: |
5741 | case 14: |
5704 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
5742 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
5705 | break; |
5743 | break; |
5706 | } |
5744 | } |
5707 | 5745 | ||
5708 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5746 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5709 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5747 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5710 | else |
5748 | else |
5711 | dpll |= PLL_REF_INPUT_DREFCLK; |
5749 | dpll |= PLL_REF_INPUT_DREFCLK; |
5712 | 5750 | ||
5713 | return dpll | DPLL_VCO_ENABLE; |
5751 | return dpll | DPLL_VCO_ENABLE; |
5714 | } |
5752 | } |
5715 | 5753 | ||
5716 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5754 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5717 | int x, int y, |
5755 | int x, int y, |
5718 | struct drm_framebuffer *fb) |
5756 | struct drm_framebuffer *fb) |
5719 | { |
5757 | { |
5720 | struct drm_device *dev = crtc->dev; |
5758 | struct drm_device *dev = crtc->dev; |
5721 | struct drm_i915_private *dev_priv = dev->dev_private; |
5759 | struct drm_i915_private *dev_priv = dev->dev_private; |
5722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5723 | int pipe = intel_crtc->pipe; |
5761 | int pipe = intel_crtc->pipe; |
5724 | int plane = intel_crtc->plane; |
5762 | int plane = intel_crtc->plane; |
5725 | int num_connectors = 0; |
5763 | int num_connectors = 0; |
5726 | intel_clock_t clock, reduced_clock; |
5764 | intel_clock_t clock, reduced_clock; |
5727 | u32 dpll = 0, fp = 0, fp2 = 0; |
5765 | u32 dpll = 0, fp = 0, fp2 = 0; |
5728 | bool ok, has_reduced_clock = false; |
5766 | bool ok, has_reduced_clock = false; |
5729 | bool is_lvds = false; |
5767 | bool is_lvds = false; |
5730 | struct intel_encoder *encoder; |
5768 | struct intel_encoder *encoder; |
5731 | struct intel_shared_dpll *pll; |
5769 | struct intel_shared_dpll *pll; |
5732 | int ret; |
5770 | int ret; |
5733 | 5771 | ||
5734 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5772 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5735 | switch (encoder->type) { |
5773 | switch (encoder->type) { |
5736 | case INTEL_OUTPUT_LVDS: |
5774 | case INTEL_OUTPUT_LVDS: |
5737 | is_lvds = true; |
5775 | is_lvds = true; |
5738 | break; |
5776 | break; |
5739 | } |
5777 | } |
5740 | 5778 | ||
5741 | num_connectors++; |
5779 | num_connectors++; |
5742 | } |
5780 | } |
5743 | 5781 | ||
5744 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5782 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5745 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
5783 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
5746 | 5784 | ||
5747 | ok = ironlake_compute_clocks(crtc, &clock, |
5785 | ok = ironlake_compute_clocks(crtc, &clock, |
5748 | &has_reduced_clock, &reduced_clock); |
5786 | &has_reduced_clock, &reduced_clock); |
5749 | if (!ok && !intel_crtc->config.clock_set) { |
5787 | if (!ok && !intel_crtc->config.clock_set) { |
5750 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5788 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5751 | return -EINVAL; |
5789 | return -EINVAL; |
5752 | } |
5790 | } |
5753 | /* Compat-code for transition, will disappear. */ |
5791 | /* Compat-code for transition, will disappear. */ |
5754 | if (!intel_crtc->config.clock_set) { |
5792 | if (!intel_crtc->config.clock_set) { |
5755 | intel_crtc->config.dpll.n = clock.n; |
5793 | intel_crtc->config.dpll.n = clock.n; |
5756 | intel_crtc->config.dpll.m1 = clock.m1; |
5794 | intel_crtc->config.dpll.m1 = clock.m1; |
5757 | intel_crtc->config.dpll.m2 = clock.m2; |
5795 | intel_crtc->config.dpll.m2 = clock.m2; |
5758 | intel_crtc->config.dpll.p1 = clock.p1; |
5796 | intel_crtc->config.dpll.p1 = clock.p1; |
5759 | intel_crtc->config.dpll.p2 = clock.p2; |
5797 | intel_crtc->config.dpll.p2 = clock.p2; |
5760 | } |
5798 | } |
5761 | 5799 | ||
5762 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5800 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5763 | if (intel_crtc->config.has_pch_encoder) { |
5801 | if (intel_crtc->config.has_pch_encoder) { |
5764 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
5802 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
5765 | if (has_reduced_clock) |
5803 | if (has_reduced_clock) |
5766 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
5804 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
5767 | 5805 | ||
5768 | dpll = ironlake_compute_dpll(intel_crtc, |
5806 | dpll = ironlake_compute_dpll(intel_crtc, |
5769 | &fp, &reduced_clock, |
5807 | &fp, &reduced_clock, |
5770 | has_reduced_clock ? &fp2 : NULL); |
5808 | has_reduced_clock ? &fp2 : NULL); |
5771 | 5809 | ||
5772 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
5810 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
5773 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
5811 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
5774 | if (has_reduced_clock) |
5812 | if (has_reduced_clock) |
5775 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
5813 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
5776 | else |
5814 | else |
5777 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
5815 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
5778 | 5816 | ||
5779 | pll = intel_get_shared_dpll(intel_crtc); |
5817 | pll = intel_get_shared_dpll(intel_crtc); |
5780 | if (pll == NULL) { |
5818 | if (pll == NULL) { |
5781 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5819 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5782 | pipe_name(pipe)); |
5820 | pipe_name(pipe)); |
5783 | return -EINVAL; |
5821 | return -EINVAL; |
5784 | } |
5822 | } |
5785 | } else |
5823 | } else |
5786 | intel_put_shared_dpll(intel_crtc); |
5824 | intel_put_shared_dpll(intel_crtc); |
5787 | 5825 | ||
5788 | if (intel_crtc->config.has_dp_encoder) |
5826 | if (intel_crtc->config.has_dp_encoder) |
5789 | intel_dp_set_m_n(intel_crtc); |
5827 | intel_dp_set_m_n(intel_crtc); |
5790 | 5828 | ||
5791 | if (is_lvds && has_reduced_clock && i915_powersave) |
5829 | if (is_lvds && has_reduced_clock && i915_powersave) |
5792 | intel_crtc->lowfreq_avail = true; |
5830 | intel_crtc->lowfreq_avail = true; |
5793 | else |
5831 | else |
5794 | intel_crtc->lowfreq_avail = false; |
5832 | intel_crtc->lowfreq_avail = false; |
5795 | 5833 | ||
5796 | if (intel_crtc->config.has_pch_encoder) { |
5834 | if (intel_crtc->config.has_pch_encoder) { |
5797 | pll = intel_crtc_to_shared_dpll(intel_crtc); |
5835 | pll = intel_crtc_to_shared_dpll(intel_crtc); |
5798 | 5836 | ||
5799 | } |
5837 | } |
5800 | 5838 | ||
5801 | intel_set_pipe_timings(intel_crtc); |
5839 | intel_set_pipe_timings(intel_crtc); |
5802 | 5840 | ||
5803 | if (intel_crtc->config.has_pch_encoder) { |
5841 | if (intel_crtc->config.has_pch_encoder) { |
5804 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5842 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5805 | &intel_crtc->config.fdi_m_n); |
5843 | &intel_crtc->config.fdi_m_n); |
5806 | } |
5844 | } |
5807 | - | ||
5808 | if (IS_IVYBRIDGE(dev)) |
- | |
5809 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
- | |
5810 | 5845 | ||
5811 | ironlake_set_pipeconf(crtc); |
5846 | ironlake_set_pipeconf(crtc); |
5812 | 5847 | ||
5813 | /* Set up the display plane register */ |
5848 | /* Set up the display plane register */ |
5814 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
5849 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
5815 | POSTING_READ(DSPCNTR(plane)); |
5850 | POSTING_READ(DSPCNTR(plane)); |
5816 | 5851 | ||
5817 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5852 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5818 | 5853 | ||
5819 | intel_update_watermarks(dev); |
5854 | intel_update_watermarks(dev); |
5820 | 5855 | ||
5821 | return ret; |
5856 | return ret; |
5822 | } |
5857 | } |
5823 | 5858 | ||
5824 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5859 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5825 | struct intel_crtc_config *pipe_config) |
5860 | struct intel_crtc_config *pipe_config) |
5826 | { |
5861 | { |
5827 | struct drm_device *dev = crtc->base.dev; |
5862 | struct drm_device *dev = crtc->base.dev; |
5828 | struct drm_i915_private *dev_priv = dev->dev_private; |
5863 | struct drm_i915_private *dev_priv = dev->dev_private; |
5829 | enum transcoder transcoder = pipe_config->cpu_transcoder; |
5864 | enum transcoder transcoder = pipe_config->cpu_transcoder; |
5830 | 5865 | ||
5831 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
5866 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
5832 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
5867 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
5833 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
5868 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
5834 | & ~TU_SIZE_MASK; |
5869 | & ~TU_SIZE_MASK; |
5835 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
5870 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
5836 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
5871 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
5837 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
5872 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
5838 | } |
5873 | } |
5839 | 5874 | ||
5840 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5875 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5841 | struct intel_crtc_config *pipe_config) |
5876 | struct intel_crtc_config *pipe_config) |
5842 | { |
5877 | { |
5843 | struct drm_device *dev = crtc->base.dev; |
5878 | struct drm_device *dev = crtc->base.dev; |
5844 | struct drm_i915_private *dev_priv = dev->dev_private; |
5879 | struct drm_i915_private *dev_priv = dev->dev_private; |
5845 | uint32_t tmp; |
5880 | uint32_t tmp; |
5846 | 5881 | ||
5847 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
5882 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
5848 | 5883 | ||
5849 | if (tmp & PF_ENABLE) { |
5884 | if (tmp & PF_ENABLE) { |
5850 | pipe_config->pch_pfit.enabled = true; |
5885 | pipe_config->pch_pfit.enabled = true; |
5851 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
5886 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
5852 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
5887 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
5853 | 5888 | ||
5854 | /* We currently do not free assignements of panel fitters on |
5889 | /* We currently do not free assignements of panel fitters on |
5855 | * ivb/hsw (since we don't use the higher upscaling modes which |
5890 | * ivb/hsw (since we don't use the higher upscaling modes which |
5856 | * differentiates them) so just WARN about this case for now. */ |
5891 | * differentiates them) so just WARN about this case for now. */ |
5857 | if (IS_GEN7(dev)) { |
5892 | if (IS_GEN7(dev)) { |
5858 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
5893 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
5859 | PF_PIPE_SEL_IVB(crtc->pipe)); |
5894 | PF_PIPE_SEL_IVB(crtc->pipe)); |
5860 | } |
5895 | } |
5861 | } |
5896 | } |
5862 | } |
5897 | } |
5863 | 5898 | ||
5864 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5899 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5865 | struct intel_crtc_config *pipe_config) |
5900 | struct intel_crtc_config *pipe_config) |
5866 | { |
5901 | { |
5867 | struct drm_device *dev = crtc->base.dev; |
5902 | struct drm_device *dev = crtc->base.dev; |
5868 | struct drm_i915_private *dev_priv = dev->dev_private; |
5903 | struct drm_i915_private *dev_priv = dev->dev_private; |
5869 | uint32_t tmp; |
5904 | uint32_t tmp; |
5870 | 5905 | ||
5871 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5906 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5872 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5907 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5873 | 5908 | ||
5874 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5909 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5875 | if (!(tmp & PIPECONF_ENABLE)) |
5910 | if (!(tmp & PIPECONF_ENABLE)) |
5876 | return false; |
5911 | return false; |
- | 5912 | ||
- | 5913 | switch (tmp & PIPECONF_BPC_MASK) { |
|
- | 5914 | case PIPECONF_6BPC: |
|
- | 5915 | pipe_config->pipe_bpp = 18; |
|
- | 5916 | break; |
|
- | 5917 | case PIPECONF_8BPC: |
|
- | 5918 | pipe_config->pipe_bpp = 24; |
|
- | 5919 | break; |
|
- | 5920 | case PIPECONF_10BPC: |
|
- | 5921 | pipe_config->pipe_bpp = 30; |
|
- | 5922 | break; |
|
- | 5923 | case PIPECONF_12BPC: |
|
- | 5924 | pipe_config->pipe_bpp = 36; |
|
- | 5925 | break; |
|
- | 5926 | default: |
|
- | 5927 | break; |
|
- | 5928 | } |
|
5877 | 5929 | ||
5878 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
5930 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
5879 | struct intel_shared_dpll *pll; |
5931 | struct intel_shared_dpll *pll; |
5880 | 5932 | ||
5881 | pipe_config->has_pch_encoder = true; |
5933 | pipe_config->has_pch_encoder = true; |
5882 | 5934 | ||
5883 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
5935 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
5884 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
5936 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
5885 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
5937 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
5886 | 5938 | ||
5887 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
5939 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
5888 | 5940 | ||
5889 | if (HAS_PCH_IBX(dev_priv->dev)) { |
5941 | if (HAS_PCH_IBX(dev_priv->dev)) { |
5890 | pipe_config->shared_dpll = |
5942 | pipe_config->shared_dpll = |
5891 | (enum intel_dpll_id) crtc->pipe; |
5943 | (enum intel_dpll_id) crtc->pipe; |
5892 | } else { |
5944 | } else { |
5893 | tmp = I915_READ(PCH_DPLL_SEL); |
5945 | tmp = I915_READ(PCH_DPLL_SEL); |
5894 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
5946 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
5895 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
5947 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
5896 | else |
5948 | else |
5897 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
5949 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
5898 | } |
5950 | } |
5899 | 5951 | ||
5900 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
5952 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
5901 | 5953 | ||
5902 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
5954 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
5903 | &pipe_config->dpll_hw_state)); |
5955 | &pipe_config->dpll_hw_state)); |
5904 | 5956 | ||
5905 | tmp = pipe_config->dpll_hw_state.dpll; |
5957 | tmp = pipe_config->dpll_hw_state.dpll; |
5906 | pipe_config->pixel_multiplier = |
5958 | pipe_config->pixel_multiplier = |
5907 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
5959 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
5908 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
5960 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
5909 | } else { |
5961 | } else { |
5910 | pipe_config->pixel_multiplier = 1; |
5962 | pipe_config->pixel_multiplier = 1; |
5911 | } |
5963 | } |
5912 | 5964 | ||
5913 | intel_get_pipe_timings(crtc, pipe_config); |
5965 | intel_get_pipe_timings(crtc, pipe_config); |
5914 | 5966 | ||
5915 | ironlake_get_pfit_config(crtc, pipe_config); |
5967 | ironlake_get_pfit_config(crtc, pipe_config); |
5916 | 5968 | ||
5917 | return true; |
5969 | return true; |
5918 | } |
5970 | } |
5919 | 5971 | ||
5920 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
5972 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
5921 | { |
5973 | { |
5922 | struct drm_device *dev = dev_priv->dev; |
5974 | struct drm_device *dev = dev_priv->dev; |
5923 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
5975 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
5924 | struct intel_crtc *crtc; |
5976 | struct intel_crtc *crtc; |
5925 | unsigned long irqflags; |
5977 | unsigned long irqflags; |
5926 | uint32_t val; |
5978 | uint32_t val; |
5927 | 5979 | ||
5928 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
5980 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
5929 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", |
5981 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", |
5930 | pipe_name(crtc->pipe)); |
5982 | pipe_name(crtc->pipe)); |
5931 | 5983 | ||
5932 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
5984 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
5933 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
5985 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
5934 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
5986 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
5935 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
5987 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
5936 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
5988 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
5937 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
5989 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
5938 | "CPU PWM1 enabled\n"); |
5990 | "CPU PWM1 enabled\n"); |
5939 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
5991 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
5940 | "CPU PWM2 enabled\n"); |
5992 | "CPU PWM2 enabled\n"); |
5941 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
5993 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
5942 | "PCH PWM1 enabled\n"); |
5994 | "PCH PWM1 enabled\n"); |
5943 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
5995 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
5944 | "Utility pin enabled\n"); |
5996 | "Utility pin enabled\n"); |
5945 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
5997 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
5946 | 5998 | ||
5947 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
5999 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
5948 | val = I915_READ(DEIMR); |
6000 | val = I915_READ(DEIMR); |
5949 | WARN((val & ~DE_PCH_EVENT_IVB) != val, |
6001 | WARN((val & ~DE_PCH_EVENT_IVB) != val, |
5950 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6002 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
5951 | val = I915_READ(SDEIMR); |
6003 | val = I915_READ(SDEIMR); |
5952 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
6004 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
5953 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6005 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
5954 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
6006 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
5955 | } |
6007 | } |
5956 | 6008 | ||
5957 | /* |
6009 | /* |
5958 | * This function implements pieces of two sequences from BSpec: |
6010 | * This function implements pieces of two sequences from BSpec: |
5959 | * - Sequence for display software to disable LCPLL |
6011 | * - Sequence for display software to disable LCPLL |
5960 | * - Sequence for display software to allow package C8+ |
6012 | * - Sequence for display software to allow package C8+ |
5961 | * The steps implemented here are just the steps that actually touch the LCPLL |
6013 | * The steps implemented here are just the steps that actually touch the LCPLL |
5962 | * register. Callers should take care of disabling all the display engine |
6014 | * register. Callers should take care of disabling all the display engine |
5963 | * functions, doing the mode unset, fixing interrupts, etc. |
6015 | * functions, doing the mode unset, fixing interrupts, etc. |
5964 | */ |
6016 | */ |
5965 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6017 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
5966 | bool switch_to_fclk, bool allow_power_down) |
6018 | bool switch_to_fclk, bool allow_power_down) |
5967 | { |
6019 | { |
5968 | uint32_t val; |
6020 | uint32_t val; |
5969 | 6021 | ||
5970 | assert_can_disable_lcpll(dev_priv); |
6022 | assert_can_disable_lcpll(dev_priv); |
5971 | 6023 | ||
5972 | val = I915_READ(LCPLL_CTL); |
6024 | val = I915_READ(LCPLL_CTL); |
5973 | 6025 | ||
5974 | if (switch_to_fclk) { |
6026 | if (switch_to_fclk) { |
5975 | val |= LCPLL_CD_SOURCE_FCLK; |
6027 | val |= LCPLL_CD_SOURCE_FCLK; |
5976 | I915_WRITE(LCPLL_CTL, val); |
6028 | I915_WRITE(LCPLL_CTL, val); |
5977 | 6029 | ||
5978 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
6030 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
5979 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
6031 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
5980 | DRM_ERROR("Switching to FCLK failed\n"); |
6032 | DRM_ERROR("Switching to FCLK failed\n"); |
5981 | 6033 | ||
5982 | val = I915_READ(LCPLL_CTL); |
6034 | val = I915_READ(LCPLL_CTL); |
5983 | } |
6035 | } |
5984 | 6036 | ||
5985 | val |= LCPLL_PLL_DISABLE; |
6037 | val |= LCPLL_PLL_DISABLE; |
5986 | I915_WRITE(LCPLL_CTL, val); |
6038 | I915_WRITE(LCPLL_CTL, val); |
5987 | POSTING_READ(LCPLL_CTL); |
6039 | POSTING_READ(LCPLL_CTL); |
5988 | 6040 | ||
5989 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
6041 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
5990 | DRM_ERROR("LCPLL still locked\n"); |
6042 | DRM_ERROR("LCPLL still locked\n"); |
5991 | 6043 | ||
5992 | val = I915_READ(D_COMP); |
6044 | val = I915_READ(D_COMP); |
5993 | val |= D_COMP_COMP_DISABLE; |
6045 | val |= D_COMP_COMP_DISABLE; |
5994 | I915_WRITE(D_COMP, val); |
6046 | I915_WRITE(D_COMP, val); |
5995 | POSTING_READ(D_COMP); |
6047 | POSTING_READ(D_COMP); |
5996 | udelay(100); |
6048 | udelay(100); |
5997 | 6049 | ||
5998 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
6050 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
5999 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
6051 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
6000 | 6052 | ||
6001 | if (allow_power_down) { |
6053 | if (allow_power_down) { |
6002 | val = I915_READ(LCPLL_CTL); |
6054 | val = I915_READ(LCPLL_CTL); |
6003 | val |= LCPLL_POWER_DOWN_ALLOW; |
6055 | val |= LCPLL_POWER_DOWN_ALLOW; |
6004 | I915_WRITE(LCPLL_CTL, val); |
6056 | I915_WRITE(LCPLL_CTL, val); |
6005 | POSTING_READ(LCPLL_CTL); |
6057 | POSTING_READ(LCPLL_CTL); |
6006 | } |
6058 | } |
6007 | } |
6059 | } |
6008 | 6060 | ||
6009 | /* |
6061 | /* |
6010 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
6062 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
6011 | * source. |
6063 | * source. |
6012 | */ |
6064 | */ |
6013 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6065 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
6014 | { |
6066 | { |
6015 | uint32_t val; |
6067 | uint32_t val; |
6016 | 6068 | ||
6017 | val = I915_READ(LCPLL_CTL); |
6069 | val = I915_READ(LCPLL_CTL); |
6018 | 6070 | ||
6019 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
6071 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
6020 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6072 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
6021 | return; |
6073 | return; |
6022 | 6074 | ||
6023 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6075 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6024 | * we'll hang the machine! */ |
6076 | * we'll hang the machine! */ |
6025 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
6077 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
6026 | 6078 | ||
6027 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6079 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6028 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6080 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
6029 | I915_WRITE(LCPLL_CTL, val); |
6081 | I915_WRITE(LCPLL_CTL, val); |
6030 | POSTING_READ(LCPLL_CTL); |
6082 | POSTING_READ(LCPLL_CTL); |
6031 | } |
6083 | } |
6032 | 6084 | ||
6033 | val = I915_READ(D_COMP); |
6085 | val = I915_READ(D_COMP); |
6034 | val |= D_COMP_COMP_FORCE; |
6086 | val |= D_COMP_COMP_FORCE; |
6035 | val &= ~D_COMP_COMP_DISABLE; |
6087 | val &= ~D_COMP_COMP_DISABLE; |
6036 | I915_WRITE(D_COMP, val); |
6088 | I915_WRITE(D_COMP, val); |
6037 | POSTING_READ(D_COMP); |
6089 | POSTING_READ(D_COMP); |
6038 | 6090 | ||
6039 | val = I915_READ(LCPLL_CTL); |
6091 | val = I915_READ(LCPLL_CTL); |
6040 | val &= ~LCPLL_PLL_DISABLE; |
6092 | val &= ~LCPLL_PLL_DISABLE; |
6041 | I915_WRITE(LCPLL_CTL, val); |
6093 | I915_WRITE(LCPLL_CTL, val); |
6042 | 6094 | ||
6043 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
6095 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
6044 | DRM_ERROR("LCPLL not locked yet\n"); |
6096 | DRM_ERROR("LCPLL not locked yet\n"); |
6045 | 6097 | ||
6046 | if (val & LCPLL_CD_SOURCE_FCLK) { |
6098 | if (val & LCPLL_CD_SOURCE_FCLK) { |
6047 | val = I915_READ(LCPLL_CTL); |
6099 | val = I915_READ(LCPLL_CTL); |
6048 | val &= ~LCPLL_CD_SOURCE_FCLK; |
6100 | val &= ~LCPLL_CD_SOURCE_FCLK; |
6049 | I915_WRITE(LCPLL_CTL, val); |
6101 | I915_WRITE(LCPLL_CTL, val); |
6050 | 6102 | ||
6051 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6103 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
6052 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6104 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
6053 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6105 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6054 | } |
6106 | } |
6055 | 6107 | ||
6056 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
6108 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
6057 | } |
6109 | } |
6058 | 6110 | ||
6059 | void hsw_enable_pc8_work(struct work_struct *__work) |
6111 | void hsw_enable_pc8_work(struct work_struct *__work) |
6060 | { |
6112 | { |
6061 | struct drm_i915_private *dev_priv = |
6113 | struct drm_i915_private *dev_priv = |
6062 | container_of(to_delayed_work(__work), struct drm_i915_private, |
6114 | container_of(to_delayed_work(__work), struct drm_i915_private, |
6063 | pc8.enable_work); |
6115 | pc8.enable_work); |
6064 | struct drm_device *dev = dev_priv->dev; |
6116 | struct drm_device *dev = dev_priv->dev; |
6065 | uint32_t val; |
6117 | uint32_t val; |
6066 | 6118 | ||
6067 | if (dev_priv->pc8.enabled) |
6119 | if (dev_priv->pc8.enabled) |
6068 | return; |
6120 | return; |
6069 | 6121 | ||
6070 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
6122 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
6071 | 6123 | ||
6072 | dev_priv->pc8.enabled = true; |
6124 | dev_priv->pc8.enabled = true; |
6073 | 6125 | ||
6074 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6126 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6075 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6127 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6076 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6128 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
6077 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6129 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6078 | } |
6130 | } |
6079 | 6131 | ||
6080 | lpt_disable_clkout_dp(dev); |
6132 | lpt_disable_clkout_dp(dev); |
6081 | hsw_pc8_disable_interrupts(dev); |
6133 | hsw_pc8_disable_interrupts(dev); |
6082 | hsw_disable_lcpll(dev_priv, true, true); |
6134 | hsw_disable_lcpll(dev_priv, true, true); |
6083 | } |
6135 | } |
6084 | 6136 | ||
6085 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6137 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6086 | { |
6138 | { |
6087 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6139 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6088 | WARN(dev_priv->pc8.disable_count < 1, |
6140 | WARN(dev_priv->pc8.disable_count < 1, |
6089 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6141 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6090 | 6142 | ||
6091 | dev_priv->pc8.disable_count--; |
6143 | dev_priv->pc8.disable_count--; |
6092 | if (dev_priv->pc8.disable_count != 0) |
6144 | if (dev_priv->pc8.disable_count != 0) |
6093 | return; |
6145 | return; |
6094 | 6146 | ||
6095 | schedule_delayed_work(&dev_priv->pc8.enable_work, |
6147 | schedule_delayed_work(&dev_priv->pc8.enable_work, |
6096 | msecs_to_jiffies(i915_pc8_timeout)); |
6148 | msecs_to_jiffies(i915_pc8_timeout)); |
6097 | } |
6149 | } |
6098 | 6150 | ||
6099 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6151 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6100 | { |
6152 | { |
6101 | struct drm_device *dev = dev_priv->dev; |
6153 | struct drm_device *dev = dev_priv->dev; |
6102 | uint32_t val; |
6154 | uint32_t val; |
6103 | 6155 | ||
6104 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6156 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
6105 | WARN(dev_priv->pc8.disable_count < 0, |
6157 | WARN(dev_priv->pc8.disable_count < 0, |
6106 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6158 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); |
6107 | 6159 | ||
6108 | dev_priv->pc8.disable_count++; |
6160 | dev_priv->pc8.disable_count++; |
6109 | if (dev_priv->pc8.disable_count != 1) |
6161 | if (dev_priv->pc8.disable_count != 1) |
6110 | return; |
6162 | return; |
6111 | 6163 | ||
6112 | // cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6164 | // cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6113 | if (!dev_priv->pc8.enabled) |
6165 | if (!dev_priv->pc8.enabled) |
6114 | return; |
6166 | return; |
6115 | 6167 | ||
6116 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
6168 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
6117 | 6169 | ||
6118 | hsw_restore_lcpll(dev_priv); |
6170 | hsw_restore_lcpll(dev_priv); |
6119 | hsw_pc8_restore_interrupts(dev); |
6171 | hsw_pc8_restore_interrupts(dev); |
6120 | lpt_init_pch_refclk(dev); |
6172 | lpt_init_pch_refclk(dev); |
6121 | 6173 | ||
6122 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6174 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
6123 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6175 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6124 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
6176 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
6125 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6177 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
6126 | } |
6178 | } |
6127 | 6179 | ||
6128 | intel_prepare_ddi(dev); |
6180 | intel_prepare_ddi(dev); |
6129 | i915_gem_init_swizzling(dev); |
6181 | i915_gem_init_swizzling(dev); |
6130 | mutex_lock(&dev_priv->rps.hw_lock); |
6182 | mutex_lock(&dev_priv->rps.hw_lock); |
6131 | gen6_update_ring_freq(dev); |
6183 | gen6_update_ring_freq(dev); |
6132 | mutex_unlock(&dev_priv->rps.hw_lock); |
6184 | mutex_unlock(&dev_priv->rps.hw_lock); |
6133 | dev_priv->pc8.enabled = false; |
6185 | dev_priv->pc8.enabled = false; |
6134 | } |
6186 | } |
6135 | 6187 | ||
6136 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6188 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
6137 | { |
6189 | { |
6138 | mutex_lock(&dev_priv->pc8.lock); |
6190 | mutex_lock(&dev_priv->pc8.lock); |
6139 | __hsw_enable_package_c8(dev_priv); |
6191 | __hsw_enable_package_c8(dev_priv); |
6140 | mutex_unlock(&dev_priv->pc8.lock); |
6192 | mutex_unlock(&dev_priv->pc8.lock); |
6141 | } |
6193 | } |
6142 | 6194 | ||
6143 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6195 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
6144 | { |
6196 | { |
6145 | mutex_lock(&dev_priv->pc8.lock); |
6197 | mutex_lock(&dev_priv->pc8.lock); |
6146 | __hsw_disable_package_c8(dev_priv); |
6198 | __hsw_disable_package_c8(dev_priv); |
6147 | mutex_unlock(&dev_priv->pc8.lock); |
6199 | mutex_unlock(&dev_priv->pc8.lock); |
6148 | } |
6200 | } |
6149 | 6201 | ||
6150 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) |
6202 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) |
6151 | { |
6203 | { |
6152 | struct drm_device *dev = dev_priv->dev; |
6204 | struct drm_device *dev = dev_priv->dev; |
6153 | struct intel_crtc *crtc; |
6205 | struct intel_crtc *crtc; |
6154 | uint32_t val; |
6206 | uint32_t val; |
6155 | 6207 | ||
6156 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6208 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6157 | if (crtc->base.enabled) |
6209 | if (crtc->base.enabled) |
6158 | return false; |
6210 | return false; |
6159 | 6211 | ||
6160 | /* This case is still possible since we have the i915.disable_power_well |
6212 | /* This case is still possible since we have the i915.disable_power_well |
6161 | * parameter and also the KVMr or something else might be requesting the |
6213 | * parameter and also the KVMr or something else might be requesting the |
6162 | * power well. */ |
6214 | * power well. */ |
6163 | val = I915_READ(HSW_PWR_WELL_DRIVER); |
6215 | val = I915_READ(HSW_PWR_WELL_DRIVER); |
6164 | if (val != 0) { |
6216 | if (val != 0) { |
6165 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); |
6217 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); |
6166 | return false; |
6218 | return false; |
6167 | } |
6219 | } |
6168 | 6220 | ||
6169 | return true; |
6221 | return true; |
6170 | } |
6222 | } |
6171 | 6223 | ||
6172 | /* Since we're called from modeset_global_resources there's no way to |
6224 | /* Since we're called from modeset_global_resources there's no way to |
6173 | * symmetrically increase and decrease the refcount, so we use |
6225 | * symmetrically increase and decrease the refcount, so we use |
6174 | * dev_priv->pc8.requirements_met to track whether we already have the refcount |
6226 | * dev_priv->pc8.requirements_met to track whether we already have the refcount |
6175 | * or not. |
6227 | * or not. |
6176 | */ |
6228 | */ |
6177 | static void hsw_update_package_c8(struct drm_device *dev) |
6229 | static void hsw_update_package_c8(struct drm_device *dev) |
6178 | { |
6230 | { |
6179 | struct drm_i915_private *dev_priv = dev->dev_private; |
6231 | struct drm_i915_private *dev_priv = dev->dev_private; |
6180 | bool allow; |
6232 | bool allow; |
6181 | 6233 | ||
6182 | if (!i915_enable_pc8) |
6234 | if (!i915_enable_pc8) |
6183 | return; |
6235 | return; |
6184 | 6236 | ||
6185 | mutex_lock(&dev_priv->pc8.lock); |
6237 | mutex_lock(&dev_priv->pc8.lock); |
6186 | 6238 | ||
6187 | allow = hsw_can_enable_package_c8(dev_priv); |
6239 | allow = hsw_can_enable_package_c8(dev_priv); |
6188 | 6240 | ||
6189 | if (allow == dev_priv->pc8.requirements_met) |
6241 | if (allow == dev_priv->pc8.requirements_met) |
6190 | goto done; |
6242 | goto done; |
6191 | 6243 | ||
6192 | dev_priv->pc8.requirements_met = allow; |
6244 | dev_priv->pc8.requirements_met = allow; |
6193 | 6245 | ||
6194 | if (allow) |
6246 | if (allow) |
6195 | __hsw_enable_package_c8(dev_priv); |
6247 | __hsw_enable_package_c8(dev_priv); |
6196 | else |
6248 | else |
6197 | __hsw_disable_package_c8(dev_priv); |
6249 | __hsw_disable_package_c8(dev_priv); |
6198 | 6250 | ||
6199 | done: |
6251 | done: |
6200 | mutex_unlock(&dev_priv->pc8.lock); |
6252 | mutex_unlock(&dev_priv->pc8.lock); |
6201 | } |
6253 | } |
6202 | 6254 | ||
6203 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
6255 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) |
6204 | { |
6256 | { |
6205 | if (!dev_priv->pc8.gpu_idle) { |
6257 | if (!dev_priv->pc8.gpu_idle) { |
6206 | dev_priv->pc8.gpu_idle = true; |
6258 | dev_priv->pc8.gpu_idle = true; |
6207 | hsw_enable_package_c8(dev_priv); |
6259 | hsw_enable_package_c8(dev_priv); |
6208 | } |
6260 | } |
6209 | } |
6261 | } |
6210 | 6262 | ||
6211 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
6263 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) |
6212 | { |
6264 | { |
6213 | if (dev_priv->pc8.gpu_idle) { |
6265 | if (dev_priv->pc8.gpu_idle) { |
6214 | dev_priv->pc8.gpu_idle = false; |
6266 | dev_priv->pc8.gpu_idle = false; |
6215 | hsw_disable_package_c8(dev_priv); |
6267 | hsw_disable_package_c8(dev_priv); |
6216 | } |
6268 | } |
6217 | } |
6269 | } |
6218 | 6270 | ||
6219 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6271 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6220 | { |
6272 | { |
6221 | bool enable = false; |
6273 | bool enable = false; |
6222 | struct intel_crtc *crtc; |
6274 | struct intel_crtc *crtc; |
6223 | 6275 | ||
6224 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6276 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6225 | if (!crtc->base.enabled) |
6277 | if (!crtc->base.enabled) |
6226 | continue; |
6278 | continue; |
6227 | 6279 | ||
6228 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
6280 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
6229 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
6281 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
6230 | enable = true; |
6282 | enable = true; |
6231 | } |
6283 | } |
6232 | 6284 | ||
6233 | intel_set_power_well(dev, enable); |
6285 | intel_set_power_well(dev, enable); |
6234 | 6286 | ||
6235 | hsw_update_package_c8(dev); |
6287 | hsw_update_package_c8(dev); |
6236 | } |
6288 | } |
6237 | 6289 | ||
6238 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
6290 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
6239 | int x, int y, |
6291 | int x, int y, |
6240 | struct drm_framebuffer *fb) |
6292 | struct drm_framebuffer *fb) |
6241 | { |
6293 | { |
6242 | struct drm_device *dev = crtc->dev; |
6294 | struct drm_device *dev = crtc->dev; |
6243 | struct drm_i915_private *dev_priv = dev->dev_private; |
6295 | struct drm_i915_private *dev_priv = dev->dev_private; |
6244 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6245 | int plane = intel_crtc->plane; |
6297 | int plane = intel_crtc->plane; |
6246 | int ret; |
6298 | int ret; |
6247 | 6299 | ||
6248 | if (!intel_ddi_pll_mode_set(crtc)) |
6300 | if (!intel_ddi_pll_mode_set(crtc)) |
6249 | return -EINVAL; |
6301 | return -EINVAL; |
6250 | 6302 | ||
6251 | if (intel_crtc->config.has_dp_encoder) |
6303 | if (intel_crtc->config.has_dp_encoder) |
6252 | intel_dp_set_m_n(intel_crtc); |
6304 | intel_dp_set_m_n(intel_crtc); |
6253 | 6305 | ||
6254 | intel_crtc->lowfreq_avail = false; |
6306 | intel_crtc->lowfreq_avail = false; |
6255 | 6307 | ||
6256 | intel_set_pipe_timings(intel_crtc); |
6308 | intel_set_pipe_timings(intel_crtc); |
6257 | 6309 | ||
6258 | if (intel_crtc->config.has_pch_encoder) { |
6310 | if (intel_crtc->config.has_pch_encoder) { |
6259 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6311 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6260 | &intel_crtc->config.fdi_m_n); |
6312 | &intel_crtc->config.fdi_m_n); |
6261 | } |
6313 | } |
6262 | 6314 | ||
6263 | haswell_set_pipeconf(crtc); |
6315 | haswell_set_pipeconf(crtc); |
6264 | 6316 | ||
6265 | intel_set_pipe_csc(crtc); |
6317 | intel_set_pipe_csc(crtc); |
6266 | 6318 | ||
6267 | /* Set up the display plane register */ |
6319 | /* Set up the display plane register */ |
6268 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
6320 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
6269 | POSTING_READ(DSPCNTR(plane)); |
6321 | POSTING_READ(DSPCNTR(plane)); |
6270 | 6322 | ||
6271 | ret = intel_pipe_set_base(crtc, x, y, fb); |
6323 | ret = intel_pipe_set_base(crtc, x, y, fb); |
6272 | 6324 | ||
6273 | intel_update_watermarks(dev); |
6325 | intel_update_watermarks(dev); |
6274 | 6326 | ||
6275 | return ret; |
6327 | return ret; |
6276 | } |
6328 | } |
6277 | 6329 | ||
6278 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6330 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6279 | struct intel_crtc_config *pipe_config) |
6331 | struct intel_crtc_config *pipe_config) |
6280 | { |
6332 | { |
6281 | struct drm_device *dev = crtc->base.dev; |
6333 | struct drm_device *dev = crtc->base.dev; |
6282 | struct drm_i915_private *dev_priv = dev->dev_private; |
6334 | struct drm_i915_private *dev_priv = dev->dev_private; |
6283 | enum intel_display_power_domain pfit_domain; |
6335 | enum intel_display_power_domain pfit_domain; |
6284 | uint32_t tmp; |
6336 | uint32_t tmp; |
6285 | 6337 | ||
6286 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6338 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6287 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6339 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6288 | 6340 | ||
6289 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6341 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6290 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
6342 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
6291 | enum pipe trans_edp_pipe; |
6343 | enum pipe trans_edp_pipe; |
6292 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
6344 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
6293 | default: |
6345 | default: |
6294 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
6346 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
6295 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
6347 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
6296 | case TRANS_DDI_EDP_INPUT_A_ON: |
6348 | case TRANS_DDI_EDP_INPUT_A_ON: |
6297 | trans_edp_pipe = PIPE_A; |
6349 | trans_edp_pipe = PIPE_A; |
6298 | break; |
6350 | break; |
6299 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
6351 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
6300 | trans_edp_pipe = PIPE_B; |
6352 | trans_edp_pipe = PIPE_B; |
6301 | break; |
6353 | break; |
6302 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
6354 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
6303 | trans_edp_pipe = PIPE_C; |
6355 | trans_edp_pipe = PIPE_C; |
6304 | break; |
6356 | break; |
6305 | } |
6357 | } |
6306 | 6358 | ||
6307 | if (trans_edp_pipe == crtc->pipe) |
6359 | if (trans_edp_pipe == crtc->pipe) |
6308 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
6360 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
6309 | } |
6361 | } |
6310 | 6362 | ||
6311 | if (!intel_display_power_enabled(dev, |
6363 | if (!intel_display_power_enabled(dev, |
6312 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
6364 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
6313 | return false; |
6365 | return false; |
6314 | 6366 | ||
6315 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
6367 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
6316 | if (!(tmp & PIPECONF_ENABLE)) |
6368 | if (!(tmp & PIPECONF_ENABLE)) |
6317 | return false; |
6369 | return false; |
6318 | 6370 | ||
6319 | /* |
6371 | /* |
6320 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
6372 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
6321 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6373 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6322 | * the PCH transcoder is on. |
6374 | * the PCH transcoder is on. |
6323 | */ |
6375 | */ |
6324 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
6376 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
6325 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
6377 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
6326 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
6378 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
6327 | pipe_config->has_pch_encoder = true; |
6379 | pipe_config->has_pch_encoder = true; |
6328 | 6380 | ||
6329 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6381 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6330 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
6382 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
6331 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
6383 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
6332 | 6384 | ||
6333 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
6385 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
6334 | } |
6386 | } |
6335 | 6387 | ||
6336 | intel_get_pipe_timings(crtc, pipe_config); |
6388 | intel_get_pipe_timings(crtc, pipe_config); |
6337 | 6389 | ||
6338 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6390 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6339 | if (intel_display_power_enabled(dev, pfit_domain)) |
6391 | if (intel_display_power_enabled(dev, pfit_domain)) |
6340 | ironlake_get_pfit_config(crtc, pipe_config); |
6392 | ironlake_get_pfit_config(crtc, pipe_config); |
6341 | 6393 | ||
6342 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6394 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6343 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
6395 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
6344 | 6396 | ||
6345 | pipe_config->pixel_multiplier = 1; |
6397 | pipe_config->pixel_multiplier = 1; |
6346 | 6398 | ||
6347 | return true; |
6399 | return true; |
6348 | } |
6400 | } |
6349 | 6401 | ||
6350 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6402 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6351 | int x, int y, |
6403 | int x, int y, |
6352 | struct drm_framebuffer *fb) |
6404 | struct drm_framebuffer *fb) |
6353 | { |
6405 | { |
6354 | struct drm_device *dev = crtc->dev; |
6406 | struct drm_device *dev = crtc->dev; |
6355 | struct drm_i915_private *dev_priv = dev->dev_private; |
6407 | struct drm_i915_private *dev_priv = dev->dev_private; |
6356 | struct intel_encoder *encoder; |
6408 | struct intel_encoder *encoder; |
6357 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6409 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6358 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
6410 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
6359 | int pipe = intel_crtc->pipe; |
6411 | int pipe = intel_crtc->pipe; |
6360 | int ret; |
6412 | int ret; |
6361 | 6413 | ||
6362 | drm_vblank_pre_modeset(dev, pipe); |
6414 | drm_vblank_pre_modeset(dev, pipe); |
6363 | 6415 | ||
6364 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6416 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6365 | 6417 | ||
6366 | drm_vblank_post_modeset(dev, pipe); |
6418 | drm_vblank_post_modeset(dev, pipe); |
6367 | 6419 | ||
6368 | if (ret != 0) |
6420 | if (ret != 0) |
6369 | return ret; |
6421 | return ret; |
6370 | 6422 | ||
6371 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6423 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6372 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
6424 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
6373 | encoder->base.base.id, |
6425 | encoder->base.base.id, |
6374 | drm_get_encoder_name(&encoder->base), |
6426 | drm_get_encoder_name(&encoder->base), |
6375 | mode->base.id, mode->name); |
6427 | mode->base.id, mode->name); |
6376 | encoder->mode_set(encoder); |
6428 | encoder->mode_set(encoder); |
6377 | } |
6429 | } |
6378 | 6430 | ||
6379 | return 0; |
6431 | return 0; |
6380 | } |
6432 | } |
6381 | 6433 | ||
6382 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6434 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6383 | int reg_eldv, uint32_t bits_eldv, |
6435 | int reg_eldv, uint32_t bits_eldv, |
6384 | int reg_elda, uint32_t bits_elda, |
6436 | int reg_elda, uint32_t bits_elda, |
6385 | int reg_edid) |
6437 | int reg_edid) |
6386 | { |
6438 | { |
6387 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6439 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6388 | uint8_t *eld = connector->eld; |
6440 | uint8_t *eld = connector->eld; |
6389 | uint32_t i; |
6441 | uint32_t i; |
6390 | 6442 | ||
6391 | i = I915_READ(reg_eldv); |
6443 | i = I915_READ(reg_eldv); |
6392 | i &= bits_eldv; |
6444 | i &= bits_eldv; |
6393 | 6445 | ||
6394 | if (!eld[0]) |
6446 | if (!eld[0]) |
6395 | return !i; |
6447 | return !i; |
6396 | 6448 | ||
6397 | if (!i) |
6449 | if (!i) |
6398 | return false; |
6450 | return false; |
6399 | 6451 | ||
6400 | i = I915_READ(reg_elda); |
6452 | i = I915_READ(reg_elda); |
6401 | i &= ~bits_elda; |
6453 | i &= ~bits_elda; |
6402 | I915_WRITE(reg_elda, i); |
6454 | I915_WRITE(reg_elda, i); |
6403 | 6455 | ||
6404 | for (i = 0; i < eld[2]; i++) |
6456 | for (i = 0; i < eld[2]; i++) |
6405 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
6457 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
6406 | return false; |
6458 | return false; |
6407 | 6459 | ||
6408 | return true; |
6460 | return true; |
6409 | } |
6461 | } |
6410 | 6462 | ||
6411 | static void g4x_write_eld(struct drm_connector *connector, |
6463 | static void g4x_write_eld(struct drm_connector *connector, |
6412 | struct drm_crtc *crtc) |
6464 | struct drm_crtc *crtc) |
6413 | { |
6465 | { |
6414 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6466 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6415 | uint8_t *eld = connector->eld; |
6467 | uint8_t *eld = connector->eld; |
6416 | uint32_t eldv; |
6468 | uint32_t eldv; |
6417 | uint32_t len; |
6469 | uint32_t len; |
6418 | uint32_t i; |
6470 | uint32_t i; |
6419 | 6471 | ||
6420 | i = I915_READ(G4X_AUD_VID_DID); |
6472 | i = I915_READ(G4X_AUD_VID_DID); |
6421 | 6473 | ||
6422 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
6474 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
6423 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
6475 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
6424 | else |
6476 | else |
6425 | eldv = G4X_ELDV_DEVCTG; |
6477 | eldv = G4X_ELDV_DEVCTG; |
6426 | 6478 | ||
6427 | if (intel_eld_uptodate(connector, |
6479 | if (intel_eld_uptodate(connector, |
6428 | G4X_AUD_CNTL_ST, eldv, |
6480 | G4X_AUD_CNTL_ST, eldv, |
6429 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
6481 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
6430 | G4X_HDMIW_HDMIEDID)) |
6482 | G4X_HDMIW_HDMIEDID)) |
6431 | return; |
6483 | return; |
6432 | 6484 | ||
6433 | i = I915_READ(G4X_AUD_CNTL_ST); |
6485 | i = I915_READ(G4X_AUD_CNTL_ST); |
6434 | i &= ~(eldv | G4X_ELD_ADDR); |
6486 | i &= ~(eldv | G4X_ELD_ADDR); |
6435 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
6487 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
6436 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6488 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6437 | 6489 | ||
6438 | if (!eld[0]) |
6490 | if (!eld[0]) |
6439 | return; |
6491 | return; |
6440 | 6492 | ||
6441 | len = min_t(uint8_t, eld[2], len); |
6493 | len = min_t(uint8_t, eld[2], len); |
6442 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6494 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6443 | for (i = 0; i < len; i++) |
6495 | for (i = 0; i < len; i++) |
6444 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
6496 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
6445 | 6497 | ||
6446 | i = I915_READ(G4X_AUD_CNTL_ST); |
6498 | i = I915_READ(G4X_AUD_CNTL_ST); |
6447 | i |= eldv; |
6499 | i |= eldv; |
6448 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6500 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
6449 | } |
6501 | } |
6450 | 6502 | ||
6451 | static void haswell_write_eld(struct drm_connector *connector, |
6503 | static void haswell_write_eld(struct drm_connector *connector, |
6452 | struct drm_crtc *crtc) |
6504 | struct drm_crtc *crtc) |
6453 | { |
6505 | { |
6454 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6506 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6455 | uint8_t *eld = connector->eld; |
6507 | uint8_t *eld = connector->eld; |
6456 | struct drm_device *dev = crtc->dev; |
6508 | struct drm_device *dev = crtc->dev; |
6457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6458 | uint32_t eldv; |
6510 | uint32_t eldv; |
6459 | uint32_t i; |
6511 | uint32_t i; |
6460 | int len; |
6512 | int len; |
6461 | int pipe = to_intel_crtc(crtc)->pipe; |
6513 | int pipe = to_intel_crtc(crtc)->pipe; |
6462 | int tmp; |
6514 | int tmp; |
6463 | 6515 | ||
6464 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
6516 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
6465 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
6517 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
6466 | int aud_config = HSW_AUD_CFG(pipe); |
6518 | int aud_config = HSW_AUD_CFG(pipe); |
6467 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
6519 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
6468 | 6520 | ||
6469 | 6521 | ||
6470 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
6522 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
6471 | 6523 | ||
6472 | /* Audio output enable */ |
6524 | /* Audio output enable */ |
6473 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
6525 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
6474 | tmp = I915_READ(aud_cntrl_st2); |
6526 | tmp = I915_READ(aud_cntrl_st2); |
6475 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
6527 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
6476 | I915_WRITE(aud_cntrl_st2, tmp); |
6528 | I915_WRITE(aud_cntrl_st2, tmp); |
6477 | 6529 | ||
6478 | /* Wait for 1 vertical blank */ |
6530 | /* Wait for 1 vertical blank */ |
6479 | intel_wait_for_vblank(dev, pipe); |
6531 | intel_wait_for_vblank(dev, pipe); |
6480 | 6532 | ||
6481 | /* Set ELD valid state */ |
6533 | /* Set ELD valid state */ |
6482 | tmp = I915_READ(aud_cntrl_st2); |
6534 | tmp = I915_READ(aud_cntrl_st2); |
6483 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
6535 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
6484 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6536 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6485 | I915_WRITE(aud_cntrl_st2, tmp); |
6537 | I915_WRITE(aud_cntrl_st2, tmp); |
6486 | tmp = I915_READ(aud_cntrl_st2); |
6538 | tmp = I915_READ(aud_cntrl_st2); |
6487 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
6539 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
6488 | 6540 | ||
6489 | /* Enable HDMI mode */ |
6541 | /* Enable HDMI mode */ |
6490 | tmp = I915_READ(aud_config); |
6542 | tmp = I915_READ(aud_config); |
6491 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
6543 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
6492 | /* clear N_programing_enable and N_value_index */ |
6544 | /* clear N_programing_enable and N_value_index */ |
6493 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
6545 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
6494 | I915_WRITE(aud_config, tmp); |
6546 | I915_WRITE(aud_config, tmp); |
6495 | 6547 | ||
6496 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6548 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6497 | 6549 | ||
6498 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
6550 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
6499 | intel_crtc->eld_vld = true; |
6551 | intel_crtc->eld_vld = true; |
6500 | 6552 | ||
6501 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6553 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6502 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6554 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6503 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6555 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6504 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6556 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6505 | } else |
6557 | } else |
6506 | I915_WRITE(aud_config, 0); |
6558 | I915_WRITE(aud_config, 0); |
6507 | 6559 | ||
6508 | if (intel_eld_uptodate(connector, |
6560 | if (intel_eld_uptodate(connector, |
6509 | aud_cntrl_st2, eldv, |
6561 | aud_cntrl_st2, eldv, |
6510 | aud_cntl_st, IBX_ELD_ADDRESS, |
6562 | aud_cntl_st, IBX_ELD_ADDRESS, |
6511 | hdmiw_hdmiedid)) |
6563 | hdmiw_hdmiedid)) |
6512 | return; |
6564 | return; |
6513 | 6565 | ||
6514 | i = I915_READ(aud_cntrl_st2); |
6566 | i = I915_READ(aud_cntrl_st2); |
6515 | i &= ~eldv; |
6567 | i &= ~eldv; |
6516 | I915_WRITE(aud_cntrl_st2, i); |
6568 | I915_WRITE(aud_cntrl_st2, i); |
6517 | 6569 | ||
6518 | if (!eld[0]) |
6570 | if (!eld[0]) |
6519 | return; |
6571 | return; |
6520 | 6572 | ||
6521 | i = I915_READ(aud_cntl_st); |
6573 | i = I915_READ(aud_cntl_st); |
6522 | i &= ~IBX_ELD_ADDRESS; |
6574 | i &= ~IBX_ELD_ADDRESS; |
6523 | I915_WRITE(aud_cntl_st, i); |
6575 | I915_WRITE(aud_cntl_st, i); |
6524 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6576 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6525 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
6577 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
6526 | 6578 | ||
6527 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6579 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6528 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6580 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6529 | for (i = 0; i < len; i++) |
6581 | for (i = 0; i < len; i++) |
6530 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6582 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6531 | 6583 | ||
6532 | i = I915_READ(aud_cntrl_st2); |
6584 | i = I915_READ(aud_cntrl_st2); |
6533 | i |= eldv; |
6585 | i |= eldv; |
6534 | I915_WRITE(aud_cntrl_st2, i); |
6586 | I915_WRITE(aud_cntrl_st2, i); |
6535 | 6587 | ||
6536 | } |
6588 | } |
6537 | 6589 | ||
6538 | static void ironlake_write_eld(struct drm_connector *connector, |
6590 | static void ironlake_write_eld(struct drm_connector *connector, |
6539 | struct drm_crtc *crtc) |
6591 | struct drm_crtc *crtc) |
6540 | { |
6592 | { |
6541 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6593 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
6542 | uint8_t *eld = connector->eld; |
6594 | uint8_t *eld = connector->eld; |
6543 | uint32_t eldv; |
6595 | uint32_t eldv; |
6544 | uint32_t i; |
6596 | uint32_t i; |
6545 | int len; |
6597 | int len; |
6546 | int hdmiw_hdmiedid; |
6598 | int hdmiw_hdmiedid; |
6547 | int aud_config; |
6599 | int aud_config; |
6548 | int aud_cntl_st; |
6600 | int aud_cntl_st; |
6549 | int aud_cntrl_st2; |
6601 | int aud_cntrl_st2; |
6550 | int pipe = to_intel_crtc(crtc)->pipe; |
6602 | int pipe = to_intel_crtc(crtc)->pipe; |
6551 | 6603 | ||
6552 | if (HAS_PCH_IBX(connector->dev)) { |
6604 | if (HAS_PCH_IBX(connector->dev)) { |
6553 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6605 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6554 | aud_config = IBX_AUD_CFG(pipe); |
6606 | aud_config = IBX_AUD_CFG(pipe); |
6555 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
6607 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
6556 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
6608 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
6557 | } else { |
6609 | } else { |
6558 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6610 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6559 | aud_config = CPT_AUD_CFG(pipe); |
6611 | aud_config = CPT_AUD_CFG(pipe); |
6560 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
6612 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
6561 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
6613 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
6562 | } |
6614 | } |
6563 | 6615 | ||
6564 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6616 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
6565 | 6617 | ||
6566 | i = I915_READ(aud_cntl_st); |
6618 | i = I915_READ(aud_cntl_st); |
6567 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6619 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
6568 | if (!i) { |
6620 | if (!i) { |
6569 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
6621 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
6570 | /* operate blindly on all ports */ |
6622 | /* operate blindly on all ports */ |
6571 | eldv = IBX_ELD_VALIDB; |
6623 | eldv = IBX_ELD_VALIDB; |
6572 | eldv |= IBX_ELD_VALIDB << 4; |
6624 | eldv |= IBX_ELD_VALIDB << 4; |
6573 | eldv |= IBX_ELD_VALIDB << 8; |
6625 | eldv |= IBX_ELD_VALIDB << 8; |
6574 | } else { |
6626 | } else { |
6575 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
6627 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
6576 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
6628 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
6577 | } |
6629 | } |
6578 | 6630 | ||
6579 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6631 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6580 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6632 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
6581 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6633 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
6582 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6634 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6583 | } else |
6635 | } else |
6584 | I915_WRITE(aud_config, 0); |
6636 | I915_WRITE(aud_config, 0); |
6585 | 6637 | ||
6586 | if (intel_eld_uptodate(connector, |
6638 | if (intel_eld_uptodate(connector, |
6587 | aud_cntrl_st2, eldv, |
6639 | aud_cntrl_st2, eldv, |
6588 | aud_cntl_st, IBX_ELD_ADDRESS, |
6640 | aud_cntl_st, IBX_ELD_ADDRESS, |
6589 | hdmiw_hdmiedid)) |
6641 | hdmiw_hdmiedid)) |
6590 | return; |
6642 | return; |
6591 | 6643 | ||
6592 | i = I915_READ(aud_cntrl_st2); |
6644 | i = I915_READ(aud_cntrl_st2); |
6593 | i &= ~eldv; |
6645 | i &= ~eldv; |
6594 | I915_WRITE(aud_cntrl_st2, i); |
6646 | I915_WRITE(aud_cntrl_st2, i); |
6595 | 6647 | ||
6596 | if (!eld[0]) |
6648 | if (!eld[0]) |
6597 | return; |
6649 | return; |
6598 | 6650 | ||
6599 | i = I915_READ(aud_cntl_st); |
6651 | i = I915_READ(aud_cntl_st); |
6600 | i &= ~IBX_ELD_ADDRESS; |
6652 | i &= ~IBX_ELD_ADDRESS; |
6601 | I915_WRITE(aud_cntl_st, i); |
6653 | I915_WRITE(aud_cntl_st, i); |
6602 | 6654 | ||
6603 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6655 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
6604 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6656 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
6605 | for (i = 0; i < len; i++) |
6657 | for (i = 0; i < len; i++) |
6606 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6658 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
6607 | 6659 | ||
6608 | i = I915_READ(aud_cntrl_st2); |
6660 | i = I915_READ(aud_cntrl_st2); |
6609 | i |= eldv; |
6661 | i |= eldv; |
6610 | I915_WRITE(aud_cntrl_st2, i); |
6662 | I915_WRITE(aud_cntrl_st2, i); |
6611 | } |
6663 | } |
6612 | 6664 | ||
6613 | void intel_write_eld(struct drm_encoder *encoder, |
6665 | void intel_write_eld(struct drm_encoder *encoder, |
6614 | struct drm_display_mode *mode) |
6666 | struct drm_display_mode *mode) |
6615 | { |
6667 | { |
6616 | struct drm_crtc *crtc = encoder->crtc; |
6668 | struct drm_crtc *crtc = encoder->crtc; |
6617 | struct drm_connector *connector; |
6669 | struct drm_connector *connector; |
6618 | struct drm_device *dev = encoder->dev; |
6670 | struct drm_device *dev = encoder->dev; |
6619 | struct drm_i915_private *dev_priv = dev->dev_private; |
6671 | struct drm_i915_private *dev_priv = dev->dev_private; |
6620 | 6672 | ||
6621 | connector = drm_select_eld(encoder, mode); |
6673 | connector = drm_select_eld(encoder, mode); |
6622 | if (!connector) |
6674 | if (!connector) |
6623 | return; |
6675 | return; |
6624 | 6676 | ||
6625 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6677 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6626 | connector->base.id, |
6678 | connector->base.id, |
6627 | drm_get_connector_name(connector), |
6679 | drm_get_connector_name(connector), |
6628 | connector->encoder->base.id, |
6680 | connector->encoder->base.id, |
6629 | drm_get_encoder_name(connector->encoder)); |
6681 | drm_get_encoder_name(connector->encoder)); |
6630 | 6682 | ||
6631 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
6683 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
6632 | 6684 | ||
6633 | if (dev_priv->display.write_eld) |
6685 | if (dev_priv->display.write_eld) |
6634 | dev_priv->display.write_eld(connector, crtc); |
6686 | dev_priv->display.write_eld(connector, crtc); |
6635 | } |
6687 | } |
6636 | 6688 | ||
6637 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6689 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6638 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
6690 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
6639 | { |
6691 | { |
6640 | struct drm_device *dev = crtc->dev; |
6692 | struct drm_device *dev = crtc->dev; |
6641 | struct drm_i915_private *dev_priv = dev->dev_private; |
6693 | struct drm_i915_private *dev_priv = dev->dev_private; |
6642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6643 | enum pipe pipe = intel_crtc->pipe; |
6695 | enum pipe pipe = intel_crtc->pipe; |
6644 | int palreg = PALETTE(pipe); |
6696 | int palreg = PALETTE(pipe); |
6645 | int i; |
6697 | int i; |
6646 | bool reenable_ips = false; |
6698 | bool reenable_ips = false; |
6647 | 6699 | ||
6648 | /* The clocks have to be on to load the palette. */ |
6700 | /* The clocks have to be on to load the palette. */ |
6649 | if (!crtc->enabled || !intel_crtc->active) |
6701 | if (!crtc->enabled || !intel_crtc->active) |
6650 | return; |
6702 | return; |
6651 | 6703 | ||
6652 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
6704 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
6653 | assert_pll_enabled(dev_priv, pipe); |
6705 | assert_pll_enabled(dev_priv, pipe); |
6654 | 6706 | ||
6655 | /* use legacy palette for Ironlake */ |
6707 | /* use legacy palette for Ironlake */ |
6656 | if (HAS_PCH_SPLIT(dev)) |
6708 | if (HAS_PCH_SPLIT(dev)) |
6657 | palreg = LGC_PALETTE(pipe); |
6709 | palreg = LGC_PALETTE(pipe); |
6658 | 6710 | ||
6659 | /* Workaround : Do not read or write the pipe palette/gamma data while |
6711 | /* Workaround : Do not read or write the pipe palette/gamma data while |
6660 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
6712 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
6661 | */ |
6713 | */ |
6662 | if (intel_crtc->config.ips_enabled && |
6714 | if (intel_crtc->config.ips_enabled && |
6663 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
6715 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
6664 | GAMMA_MODE_MODE_SPLIT)) { |
6716 | GAMMA_MODE_MODE_SPLIT)) { |
6665 | hsw_disable_ips(intel_crtc); |
6717 | hsw_disable_ips(intel_crtc); |
6666 | reenable_ips = true; |
6718 | reenable_ips = true; |
6667 | } |
6719 | } |
6668 | 6720 | ||
6669 | for (i = 0; i < 256; i++) { |
6721 | for (i = 0; i < 256; i++) { |
6670 | I915_WRITE(palreg + 4 * i, |
6722 | I915_WRITE(palreg + 4 * i, |
6671 | (intel_crtc->lut_r[i] << 16) | |
6723 | (intel_crtc->lut_r[i] << 16) | |
6672 | (intel_crtc->lut_g[i] << 8) | |
6724 | (intel_crtc->lut_g[i] << 8) | |
6673 | intel_crtc->lut_b[i]); |
6725 | intel_crtc->lut_b[i]); |
6674 | } |
6726 | } |
6675 | 6727 | ||
6676 | if (reenable_ips) |
6728 | if (reenable_ips) |
6677 | hsw_enable_ips(intel_crtc); |
6729 | hsw_enable_ips(intel_crtc); |
6678 | } |
6730 | } |
6679 | 6731 | ||
6680 | #if 0 |
6732 | #if 0 |
6681 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6733 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6682 | { |
6734 | { |
6683 | struct drm_device *dev = crtc->dev; |
6735 | struct drm_device *dev = crtc->dev; |
6684 | struct drm_i915_private *dev_priv = dev->dev_private; |
6736 | struct drm_i915_private *dev_priv = dev->dev_private; |
6685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6737 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6686 | bool visible = base != 0; |
6738 | bool visible = base != 0; |
6687 | u32 cntl; |
6739 | u32 cntl; |
6688 | 6740 | ||
6689 | if (intel_crtc->cursor_visible == visible) |
6741 | if (intel_crtc->cursor_visible == visible) |
6690 | return; |
6742 | return; |
6691 | 6743 | ||
6692 | cntl = I915_READ(_CURACNTR); |
6744 | cntl = I915_READ(_CURACNTR); |
6693 | if (visible) { |
6745 | if (visible) { |
6694 | /* On these chipsets we can only modify the base whilst |
6746 | /* On these chipsets we can only modify the base whilst |
6695 | * the cursor is disabled. |
6747 | * the cursor is disabled. |
6696 | */ |
6748 | */ |
6697 | I915_WRITE(_CURABASE, base); |
6749 | I915_WRITE(_CURABASE, base); |
6698 | 6750 | ||
6699 | cntl &= ~(CURSOR_FORMAT_MASK); |
6751 | cntl &= ~(CURSOR_FORMAT_MASK); |
6700 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
6752 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
6701 | cntl |= CURSOR_ENABLE | |
6753 | cntl |= CURSOR_ENABLE | |
6702 | CURSOR_GAMMA_ENABLE | |
6754 | CURSOR_GAMMA_ENABLE | |
6703 | CURSOR_FORMAT_ARGB; |
6755 | CURSOR_FORMAT_ARGB; |
6704 | } else |
6756 | } else |
6705 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
6757 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
6706 | I915_WRITE(_CURACNTR, cntl); |
6758 | I915_WRITE(_CURACNTR, cntl); |
6707 | 6759 | ||
6708 | intel_crtc->cursor_visible = visible; |
6760 | intel_crtc->cursor_visible = visible; |
6709 | } |
6761 | } |
6710 | 6762 | ||
6711 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
6763 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
6712 | { |
6764 | { |
6713 | struct drm_device *dev = crtc->dev; |
6765 | struct drm_device *dev = crtc->dev; |
6714 | struct drm_i915_private *dev_priv = dev->dev_private; |
6766 | struct drm_i915_private *dev_priv = dev->dev_private; |
6715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6716 | int pipe = intel_crtc->pipe; |
6768 | int pipe = intel_crtc->pipe; |
6717 | bool visible = base != 0; |
6769 | bool visible = base != 0; |
6718 | 6770 | ||
6719 | if (intel_crtc->cursor_visible != visible) { |
6771 | if (intel_crtc->cursor_visible != visible) { |
6720 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
6772 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
6721 | if (base) { |
6773 | if (base) { |
6722 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
6774 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
6723 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6775 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6724 | cntl |= pipe << 28; /* Connect to correct pipe */ |
6776 | cntl |= pipe << 28; /* Connect to correct pipe */ |
6725 | } else { |
6777 | } else { |
6726 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6778 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6727 | cntl |= CURSOR_MODE_DISABLE; |
6779 | cntl |= CURSOR_MODE_DISABLE; |
6728 | } |
6780 | } |
6729 | I915_WRITE(CURCNTR(pipe), cntl); |
6781 | I915_WRITE(CURCNTR(pipe), cntl); |
6730 | 6782 | ||
6731 | intel_crtc->cursor_visible = visible; |
6783 | intel_crtc->cursor_visible = visible; |
6732 | } |
6784 | } |
6733 | /* and commit changes on next vblank */ |
6785 | /* and commit changes on next vblank */ |
6734 | I915_WRITE(CURBASE(pipe), base); |
6786 | I915_WRITE(CURBASE(pipe), base); |
6735 | } |
6787 | } |
6736 | 6788 | ||
6737 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6789 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6738 | { |
6790 | { |
6739 | struct drm_device *dev = crtc->dev; |
6791 | struct drm_device *dev = crtc->dev; |
6740 | struct drm_i915_private *dev_priv = dev->dev_private; |
6792 | struct drm_i915_private *dev_priv = dev->dev_private; |
6741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6742 | int pipe = intel_crtc->pipe; |
6794 | int pipe = intel_crtc->pipe; |
6743 | bool visible = base != 0; |
6795 | bool visible = base != 0; |
6744 | 6796 | ||
6745 | if (intel_crtc->cursor_visible != visible) { |
6797 | if (intel_crtc->cursor_visible != visible) { |
6746 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
6798 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
6747 | if (base) { |
6799 | if (base) { |
6748 | cntl &= ~CURSOR_MODE; |
6800 | cntl &= ~CURSOR_MODE; |
6749 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6801 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
6750 | } else { |
6802 | } else { |
6751 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6803 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6752 | cntl |= CURSOR_MODE_DISABLE; |
6804 | cntl |= CURSOR_MODE_DISABLE; |
6753 | } |
6805 | } |
6754 | if (IS_HASWELL(dev)) { |
6806 | if (IS_HASWELL(dev)) { |
6755 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
6807 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
6756 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6808 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6757 | } |
6809 | } |
6758 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6810 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6759 | 6811 | ||
6760 | intel_crtc->cursor_visible = visible; |
6812 | intel_crtc->cursor_visible = visible; |
6761 | } |
6813 | } |
6762 | /* and commit changes on next vblank */ |
6814 | /* and commit changes on next vblank */ |
6763 | I915_WRITE(CURBASE_IVB(pipe), base); |
6815 | I915_WRITE(CURBASE_IVB(pipe), base); |
6764 | } |
6816 | } |
6765 | 6817 | ||
6766 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6818 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6767 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6819 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6768 | bool on) |
6820 | bool on) |
6769 | { |
6821 | { |
6770 | struct drm_device *dev = crtc->dev; |
6822 | struct drm_device *dev = crtc->dev; |
6771 | struct drm_i915_private *dev_priv = dev->dev_private; |
6823 | struct drm_i915_private *dev_priv = dev->dev_private; |
6772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6773 | int pipe = intel_crtc->pipe; |
6825 | int pipe = intel_crtc->pipe; |
6774 | int x = intel_crtc->cursor_x; |
6826 | int x = intel_crtc->cursor_x; |
6775 | int y = intel_crtc->cursor_y; |
6827 | int y = intel_crtc->cursor_y; |
6776 | u32 base, pos; |
6828 | u32 base, pos; |
6777 | bool visible; |
6829 | bool visible; |
6778 | 6830 | ||
6779 | pos = 0; |
6831 | pos = 0; |
6780 | 6832 | ||
6781 | if (on && crtc->enabled && crtc->fb) { |
6833 | if (on && crtc->enabled && crtc->fb) { |
6782 | base = intel_crtc->cursor_addr; |
6834 | base = intel_crtc->cursor_addr; |
6783 | if (x > (int) crtc->fb->width) |
6835 | if (x > (int) crtc->fb->width) |
6784 | base = 0; |
6836 | base = 0; |
6785 | 6837 | ||
6786 | if (y > (int) crtc->fb->height) |
6838 | if (y > (int) crtc->fb->height) |
6787 | base = 0; |
6839 | base = 0; |
6788 | } else |
6840 | } else |
6789 | base = 0; |
6841 | base = 0; |
6790 | 6842 | ||
6791 | if (x < 0) { |
6843 | if (x < 0) { |
6792 | if (x + intel_crtc->cursor_width < 0) |
6844 | if (x + intel_crtc->cursor_width < 0) |
6793 | base = 0; |
6845 | base = 0; |
6794 | 6846 | ||
6795 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
6847 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
6796 | x = -x; |
6848 | x = -x; |
6797 | } |
6849 | } |
6798 | pos |= x << CURSOR_X_SHIFT; |
6850 | pos |= x << CURSOR_X_SHIFT; |
6799 | 6851 | ||
6800 | if (y < 0) { |
6852 | if (y < 0) { |
6801 | if (y + intel_crtc->cursor_height < 0) |
6853 | if (y + intel_crtc->cursor_height < 0) |
6802 | base = 0; |
6854 | base = 0; |
6803 | 6855 | ||
6804 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
6856 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
6805 | y = -y; |
6857 | y = -y; |
6806 | } |
6858 | } |
6807 | pos |= y << CURSOR_Y_SHIFT; |
6859 | pos |= y << CURSOR_Y_SHIFT; |
6808 | 6860 | ||
6809 | visible = base != 0; |
6861 | visible = base != 0; |
6810 | if (!visible && !intel_crtc->cursor_visible) |
6862 | if (!visible && !intel_crtc->cursor_visible) |
6811 | return; |
6863 | return; |
6812 | 6864 | ||
6813 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
6865 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
6814 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6866 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6815 | ivb_update_cursor(crtc, base); |
6867 | ivb_update_cursor(crtc, base); |
6816 | } else { |
6868 | } else { |
6817 | I915_WRITE(CURPOS(pipe), pos); |
6869 | I915_WRITE(CURPOS(pipe), pos); |
6818 | if (IS_845G(dev) || IS_I865G(dev)) |
6870 | if (IS_845G(dev) || IS_I865G(dev)) |
6819 | i845_update_cursor(crtc, base); |
6871 | i845_update_cursor(crtc, base); |
6820 | else |
6872 | else |
6821 | i9xx_update_cursor(crtc, base); |
6873 | i9xx_update_cursor(crtc, base); |
6822 | } |
6874 | } |
6823 | } |
6875 | } |
6824 | 6876 | ||
6825 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
6877 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
6826 | struct drm_file *file, |
6878 | struct drm_file *file, |
6827 | uint32_t handle, |
6879 | uint32_t handle, |
6828 | uint32_t width, uint32_t height) |
6880 | uint32_t width, uint32_t height) |
6829 | { |
6881 | { |
6830 | struct drm_device *dev = crtc->dev; |
6882 | struct drm_device *dev = crtc->dev; |
6831 | struct drm_i915_private *dev_priv = dev->dev_private; |
6883 | struct drm_i915_private *dev_priv = dev->dev_private; |
6832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6833 | struct drm_i915_gem_object *obj; |
6885 | struct drm_i915_gem_object *obj; |
6834 | uint32_t addr; |
6886 | uint32_t addr; |
6835 | int ret; |
6887 | int ret; |
6836 | 6888 | ||
6837 | /* if we want to turn off the cursor ignore width and height */ |
6889 | /* if we want to turn off the cursor ignore width and height */ |
6838 | if (!handle) { |
6890 | if (!handle) { |
6839 | DRM_DEBUG_KMS("cursor off\n"); |
6891 | DRM_DEBUG_KMS("cursor off\n"); |
6840 | addr = 0; |
6892 | addr = 0; |
6841 | obj = NULL; |
6893 | obj = NULL; |
6842 | mutex_lock(&dev->struct_mutex); |
6894 | mutex_lock(&dev->struct_mutex); |
6843 | goto finish; |
6895 | goto finish; |
6844 | } |
6896 | } |
6845 | 6897 | ||
6846 | /* Currently we only support 64x64 cursors */ |
6898 | /* Currently we only support 64x64 cursors */ |
6847 | if (width != 64 || height != 64) { |
6899 | if (width != 64 || height != 64) { |
6848 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
6900 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
6849 | return -EINVAL; |
6901 | return -EINVAL; |
6850 | } |
6902 | } |
6851 | 6903 | ||
6852 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
6904 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
6853 | if (&obj->base == NULL) |
6905 | if (&obj->base == NULL) |
6854 | return -ENOENT; |
6906 | return -ENOENT; |
6855 | 6907 | ||
6856 | if (obj->base.size < width * height * 4) { |
6908 | if (obj->base.size < width * height * 4) { |
6857 | DRM_ERROR("buffer is to small\n"); |
6909 | DRM_ERROR("buffer is to small\n"); |
6858 | ret = -ENOMEM; |
6910 | ret = -ENOMEM; |
6859 | goto fail; |
6911 | goto fail; |
6860 | } |
6912 | } |
6861 | 6913 | ||
6862 | /* we only need to pin inside GTT if cursor is non-phy */ |
6914 | /* we only need to pin inside GTT if cursor is non-phy */ |
6863 | mutex_lock(&dev->struct_mutex); |
6915 | mutex_lock(&dev->struct_mutex); |
6864 | if (!dev_priv->info->cursor_needs_physical) { |
6916 | if (!dev_priv->info->cursor_needs_physical) { |
6865 | unsigned alignment; |
6917 | unsigned alignment; |
6866 | 6918 | ||
6867 | if (obj->tiling_mode) { |
6919 | if (obj->tiling_mode) { |
6868 | DRM_ERROR("cursor cannot be tiled\n"); |
6920 | DRM_ERROR("cursor cannot be tiled\n"); |
6869 | ret = -EINVAL; |
6921 | ret = -EINVAL; |
6870 | goto fail_locked; |
6922 | goto fail_locked; |
6871 | } |
6923 | } |
6872 | 6924 | ||
6873 | /* Note that the w/a also requires 2 PTE of padding following |
6925 | /* Note that the w/a also requires 2 PTE of padding following |
6874 | * the bo. We currently fill all unused PTE with the shadow |
6926 | * the bo. We currently fill all unused PTE with the shadow |
6875 | * page and so we should always have valid PTE following the |
6927 | * page and so we should always have valid PTE following the |
6876 | * cursor preventing the VT-d warning. |
6928 | * cursor preventing the VT-d warning. |
6877 | */ |
6929 | */ |
6878 | alignment = 0; |
6930 | alignment = 0; |
6879 | if (need_vtd_wa(dev)) |
6931 | if (need_vtd_wa(dev)) |
6880 | alignment = 64*1024; |
6932 | alignment = 64*1024; |
6881 | 6933 | ||
6882 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
6934 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
6883 | if (ret) { |
6935 | if (ret) { |
6884 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
6936 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
6885 | goto fail_locked; |
6937 | goto fail_locked; |
6886 | } |
6938 | } |
6887 | 6939 | ||
6888 | ret = i915_gem_object_put_fence(obj); |
6940 | ret = i915_gem_object_put_fence(obj); |
6889 | if (ret) { |
6941 | if (ret) { |
6890 | DRM_ERROR("failed to release fence for cursor"); |
6942 | DRM_ERROR("failed to release fence for cursor"); |
6891 | goto fail_unpin; |
6943 | goto fail_unpin; |
6892 | } |
6944 | } |
6893 | 6945 | ||
6894 | addr = i915_gem_obj_ggtt_offset(obj); |
6946 | addr = i915_gem_obj_ggtt_offset(obj); |
6895 | } else { |
6947 | } else { |
6896 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
6948 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
6897 | ret = i915_gem_attach_phys_object(dev, obj, |
6949 | ret = i915_gem_attach_phys_object(dev, obj, |
6898 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6950 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6899 | align); |
6951 | align); |
6900 | if (ret) { |
6952 | if (ret) { |
6901 | DRM_ERROR("failed to attach phys object\n"); |
6953 | DRM_ERROR("failed to attach phys object\n"); |
6902 | goto fail_locked; |
6954 | goto fail_locked; |
6903 | } |
6955 | } |
6904 | addr = obj->phys_obj->handle->busaddr; |
6956 | addr = obj->phys_obj->handle->busaddr; |
6905 | } |
6957 | } |
6906 | 6958 | ||
6907 | if (IS_GEN2(dev)) |
6959 | if (IS_GEN2(dev)) |
6908 | I915_WRITE(CURSIZE, (height << 12) | width); |
6960 | I915_WRITE(CURSIZE, (height << 12) | width); |
6909 | 6961 | ||
6910 | finish: |
6962 | finish: |
6911 | if (intel_crtc->cursor_bo) { |
6963 | if (intel_crtc->cursor_bo) { |
6912 | if (dev_priv->info->cursor_needs_physical) { |
6964 | if (dev_priv->info->cursor_needs_physical) { |
6913 | if (intel_crtc->cursor_bo != obj) |
6965 | if (intel_crtc->cursor_bo != obj) |
6914 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6966 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6915 | } else |
6967 | } else |
6916 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
6968 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
6917 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
6969 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
6918 | } |
6970 | } |
6919 | 6971 | ||
6920 | mutex_unlock(&dev->struct_mutex); |
6972 | mutex_unlock(&dev->struct_mutex); |
6921 | 6973 | ||
6922 | intel_crtc->cursor_addr = addr; |
6974 | intel_crtc->cursor_addr = addr; |
6923 | intel_crtc->cursor_bo = obj; |
6975 | intel_crtc->cursor_bo = obj; |
6924 | intel_crtc->cursor_width = width; |
6976 | intel_crtc->cursor_width = width; |
6925 | intel_crtc->cursor_height = height; |
6977 | intel_crtc->cursor_height = height; |
6926 | 6978 | ||
6927 | if (intel_crtc->active) |
6979 | if (intel_crtc->active) |
6928 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
6980 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
6929 | 6981 | ||
6930 | return 0; |
6982 | return 0; |
6931 | fail_unpin: |
6983 | fail_unpin: |
6932 | i915_gem_object_unpin_from_display_plane(obj); |
6984 | i915_gem_object_unpin_from_display_plane(obj); |
6933 | fail_locked: |
6985 | fail_locked: |
6934 | mutex_unlock(&dev->struct_mutex); |
6986 | mutex_unlock(&dev->struct_mutex); |
6935 | fail: |
6987 | fail: |
6936 | drm_gem_object_unreference_unlocked(&obj->base); |
6988 | drm_gem_object_unreference_unlocked(&obj->base); |
6937 | return ret; |
6989 | return ret; |
6938 | } |
6990 | } |
6939 | 6991 | ||
6940 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
6992 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
6941 | { |
6993 | { |
6942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6943 | 6995 | ||
6944 | intel_crtc->cursor_x = x; |
6996 | intel_crtc->cursor_x = x; |
6945 | intel_crtc->cursor_y = y; |
6997 | intel_crtc->cursor_y = y; |
6946 | 6998 | ||
6947 | if (intel_crtc->active) |
6999 | if (intel_crtc->active) |
6948 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7000 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
6949 | 7001 | ||
6950 | return 0; |
7002 | return 0; |
6951 | } |
7003 | } |
6952 | #endif |
7004 | #endif |
6953 | 7005 | ||
6954 | /** Sets the color ramps on behalf of RandR */ |
7006 | /** Sets the color ramps on behalf of RandR */ |
6955 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
7007 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
6956 | u16 blue, int regno) |
7008 | u16 blue, int regno) |
6957 | { |
7009 | { |
6958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6959 | 7011 | ||
6960 | intel_crtc->lut_r[regno] = red >> 8; |
7012 | intel_crtc->lut_r[regno] = red >> 8; |
6961 | intel_crtc->lut_g[regno] = green >> 8; |
7013 | intel_crtc->lut_g[regno] = green >> 8; |
6962 | intel_crtc->lut_b[regno] = blue >> 8; |
7014 | intel_crtc->lut_b[regno] = blue >> 8; |
6963 | } |
7015 | } |
6964 | 7016 | ||
6965 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
7017 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6966 | u16 *blue, int regno) |
7018 | u16 *blue, int regno) |
6967 | { |
7019 | { |
6968 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6969 | 7021 | ||
6970 | *red = intel_crtc->lut_r[regno] << 8; |
7022 | *red = intel_crtc->lut_r[regno] << 8; |
6971 | *green = intel_crtc->lut_g[regno] << 8; |
7023 | *green = intel_crtc->lut_g[regno] << 8; |
6972 | *blue = intel_crtc->lut_b[regno] << 8; |
7024 | *blue = intel_crtc->lut_b[regno] << 8; |
6973 | } |
7025 | } |
6974 | 7026 | ||
6975 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7027 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
6976 | u16 *blue, uint32_t start, uint32_t size) |
7028 | u16 *blue, uint32_t start, uint32_t size) |
6977 | { |
7029 | { |
6978 | int end = (start + size > 256) ? 256 : start + size, i; |
7030 | int end = (start + size > 256) ? 256 : start + size, i; |
6979 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6980 | 7032 | ||
6981 | for (i = start; i < end; i++) { |
7033 | for (i = start; i < end; i++) { |
6982 | intel_crtc->lut_r[i] = red[i] >> 8; |
7034 | intel_crtc->lut_r[i] = red[i] >> 8; |
6983 | intel_crtc->lut_g[i] = green[i] >> 8; |
7035 | intel_crtc->lut_g[i] = green[i] >> 8; |
6984 | intel_crtc->lut_b[i] = blue[i] >> 8; |
7036 | intel_crtc->lut_b[i] = blue[i] >> 8; |
6985 | } |
7037 | } |
6986 | 7038 | ||
6987 | intel_crtc_load_lut(crtc); |
7039 | intel_crtc_load_lut(crtc); |
6988 | } |
7040 | } |
6989 | 7041 | ||
6990 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7042 | /* VESA 640x480x72Hz mode to set on the pipe */ |
6991 | static struct drm_display_mode load_detect_mode = { |
7043 | static struct drm_display_mode load_detect_mode = { |
6992 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7044 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
6993 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7045 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
6994 | }; |
7046 | }; |
6995 | 7047 | ||
6996 | static struct drm_framebuffer * |
7048 | static struct drm_framebuffer * |
6997 | intel_framebuffer_create(struct drm_device *dev, |
7049 | intel_framebuffer_create(struct drm_device *dev, |
6998 | struct drm_mode_fb_cmd2 *mode_cmd, |
7050 | struct drm_mode_fb_cmd2 *mode_cmd, |
6999 | struct drm_i915_gem_object *obj) |
7051 | struct drm_i915_gem_object *obj) |
7000 | { |
7052 | { |
7001 | struct intel_framebuffer *intel_fb; |
7053 | struct intel_framebuffer *intel_fb; |
7002 | int ret; |
7054 | int ret; |
7003 | 7055 | ||
7004 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7056 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7005 | if (!intel_fb) { |
7057 | if (!intel_fb) { |
7006 | drm_gem_object_unreference_unlocked(&obj->base); |
7058 | drm_gem_object_unreference_unlocked(&obj->base); |
7007 | return ERR_PTR(-ENOMEM); |
7059 | return ERR_PTR(-ENOMEM); |
7008 | } |
7060 | } |
7009 | 7061 | ||
7010 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7062 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7011 | if (ret) { |
7063 | if (ret) { |
7012 | drm_gem_object_unreference_unlocked(&obj->base); |
7064 | drm_gem_object_unreference_unlocked(&obj->base); |
7013 | kfree(intel_fb); |
7065 | kfree(intel_fb); |
7014 | return ERR_PTR(ret); |
7066 | return ERR_PTR(ret); |
7015 | } |
7067 | } |
7016 | 7068 | ||
7017 | return &intel_fb->base; |
7069 | return &intel_fb->base; |
7018 | } |
7070 | } |
7019 | 7071 | ||
7020 | static u32 |
7072 | static u32 |
7021 | intel_framebuffer_pitch_for_width(int width, int bpp) |
7073 | intel_framebuffer_pitch_for_width(int width, int bpp) |
7022 | { |
7074 | { |
7023 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
7075 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
7024 | return ALIGN(pitch, 64); |
7076 | return ALIGN(pitch, 64); |
7025 | } |
7077 | } |
7026 | 7078 | ||
7027 | static u32 |
7079 | static u32 |
7028 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
7080 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
7029 | { |
7081 | { |
7030 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
7082 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
7031 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
7083 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
7032 | } |
7084 | } |
7033 | 7085 | ||
7034 | static struct drm_framebuffer * |
7086 | static struct drm_framebuffer * |
7035 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
7087 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
7036 | struct drm_display_mode *mode, |
7088 | struct drm_display_mode *mode, |
7037 | int depth, int bpp) |
7089 | int depth, int bpp) |
7038 | { |
7090 | { |
7039 | struct drm_i915_gem_object *obj; |
7091 | struct drm_i915_gem_object *obj; |
7040 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
7092 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
7041 | 7093 | ||
7042 | return NULL; |
7094 | return NULL; |
7043 | } |
7095 | } |
7044 | 7096 | ||
7045 | static struct drm_framebuffer * |
7097 | static struct drm_framebuffer * |
7046 | mode_fits_in_fbdev(struct drm_device *dev, |
7098 | mode_fits_in_fbdev(struct drm_device *dev, |
7047 | struct drm_display_mode *mode) |
7099 | struct drm_display_mode *mode) |
7048 | { |
7100 | { |
7049 | struct drm_i915_private *dev_priv = dev->dev_private; |
7101 | struct drm_i915_private *dev_priv = dev->dev_private; |
7050 | struct drm_i915_gem_object *obj; |
7102 | struct drm_i915_gem_object *obj; |
7051 | struct drm_framebuffer *fb; |
7103 | struct drm_framebuffer *fb; |
7052 | 7104 | ||
7053 | // if (dev_priv->fbdev == NULL) |
7105 | if (dev_priv->fbdev == NULL) |
7054 | // return NULL; |
7106 | return NULL; |
7055 | 7107 | ||
7056 | // obj = dev_priv->fbdev->ifb.obj; |
7108 | obj = dev_priv->fbdev->ifb.obj; |
7057 | // if (obj == NULL) |
7109 | if (obj == NULL) |
7058 | return NULL; |
7110 | return NULL; |
7059 | 7111 | ||
7060 | // if (obj->base.size < mode->vdisplay * fb->pitch) |
7112 | fb = &dev_priv->fbdev->ifb.base; |
7061 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7113 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7062 | fb->bits_per_pixel)) |
7114 | fb->bits_per_pixel)) |
7063 | // return NULL; |
7115 | return NULL; |
7064 | 7116 | ||
7065 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7117 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7066 | return NULL; |
7118 | return NULL; |
7067 | 7119 | ||
7068 | // return fb; |
7120 | return fb; |
7069 | } |
7121 | } |
7070 | 7122 | ||
7071 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7123 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7072 | struct drm_display_mode *mode, |
7124 | struct drm_display_mode *mode, |
7073 | struct intel_load_detect_pipe *old) |
7125 | struct intel_load_detect_pipe *old) |
7074 | { |
7126 | { |
7075 | struct intel_crtc *intel_crtc; |
7127 | struct intel_crtc *intel_crtc; |
7076 | struct intel_encoder *intel_encoder = |
7128 | struct intel_encoder *intel_encoder = |
7077 | intel_attached_encoder(connector); |
7129 | intel_attached_encoder(connector); |
7078 | struct drm_crtc *possible_crtc; |
7130 | struct drm_crtc *possible_crtc; |
7079 | struct drm_encoder *encoder = &intel_encoder->base; |
7131 | struct drm_encoder *encoder = &intel_encoder->base; |
7080 | struct drm_crtc *crtc = NULL; |
7132 | struct drm_crtc *crtc = NULL; |
7081 | struct drm_device *dev = encoder->dev; |
7133 | struct drm_device *dev = encoder->dev; |
7082 | struct drm_framebuffer *fb; |
7134 | struct drm_framebuffer *fb; |
7083 | int i = -1; |
7135 | int i = -1; |
7084 | 7136 | ||
7085 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7137 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7086 | connector->base.id, drm_get_connector_name(connector), |
7138 | connector->base.id, drm_get_connector_name(connector), |
7087 | encoder->base.id, drm_get_encoder_name(encoder)); |
7139 | encoder->base.id, drm_get_encoder_name(encoder)); |
7088 | 7140 | ||
7089 | /* |
7141 | /* |
7090 | * Algorithm gets a little messy: |
7142 | * Algorithm gets a little messy: |
7091 | * |
7143 | * |
7092 | * - if the connector already has an assigned crtc, use it (but make |
7144 | * - if the connector already has an assigned crtc, use it (but make |
7093 | * sure it's on first) |
7145 | * sure it's on first) |
7094 | * |
7146 | * |
7095 | * - try to find the first unused crtc that can drive this connector, |
7147 | * - try to find the first unused crtc that can drive this connector, |
7096 | * and use that if we find one |
7148 | * and use that if we find one |
7097 | */ |
7149 | */ |
7098 | 7150 | ||
7099 | /* See if we already have a CRTC for this connector */ |
7151 | /* See if we already have a CRTC for this connector */ |
7100 | if (encoder->crtc) { |
7152 | if (encoder->crtc) { |
7101 | crtc = encoder->crtc; |
7153 | crtc = encoder->crtc; |
7102 | 7154 | ||
7103 | mutex_lock(&crtc->mutex); |
7155 | mutex_lock(&crtc->mutex); |
7104 | 7156 | ||
7105 | old->dpms_mode = connector->dpms; |
7157 | old->dpms_mode = connector->dpms; |
7106 | old->load_detect_temp = false; |
7158 | old->load_detect_temp = false; |
7107 | 7159 | ||
7108 | /* Make sure the crtc and connector are running */ |
7160 | /* Make sure the crtc and connector are running */ |
7109 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7161 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7110 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
7162 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
7111 | 7163 | ||
7112 | return true; |
7164 | return true; |
7113 | } |
7165 | } |
7114 | 7166 | ||
7115 | /* Find an unused one (if possible) */ |
7167 | /* Find an unused one (if possible) */ |
7116 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
7168 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
7117 | i++; |
7169 | i++; |
7118 | if (!(encoder->possible_crtcs & (1 << i))) |
7170 | if (!(encoder->possible_crtcs & (1 << i))) |
7119 | continue; |
7171 | continue; |
7120 | if (!possible_crtc->enabled) { |
7172 | if (!possible_crtc->enabled) { |
7121 | crtc = possible_crtc; |
7173 | crtc = possible_crtc; |
7122 | break; |
7174 | break; |
7123 | } |
7175 | } |
7124 | } |
7176 | } |
7125 | 7177 | ||
7126 | /* |
7178 | /* |
7127 | * If we didn't find an unused CRTC, don't use any. |
7179 | * If we didn't find an unused CRTC, don't use any. |
7128 | */ |
7180 | */ |
7129 | if (!crtc) { |
7181 | if (!crtc) { |
7130 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7182 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7131 | return false; |
7183 | return false; |
7132 | } |
7184 | } |
7133 | 7185 | ||
7134 | mutex_lock(&crtc->mutex); |
7186 | mutex_lock(&crtc->mutex); |
7135 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7187 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7136 | to_intel_connector(connector)->new_encoder = intel_encoder; |
7188 | to_intel_connector(connector)->new_encoder = intel_encoder; |
7137 | 7189 | ||
7138 | intel_crtc = to_intel_crtc(crtc); |
7190 | intel_crtc = to_intel_crtc(crtc); |
7139 | old->dpms_mode = connector->dpms; |
7191 | old->dpms_mode = connector->dpms; |
7140 | old->load_detect_temp = true; |
7192 | old->load_detect_temp = true; |
7141 | old->release_fb = NULL; |
7193 | old->release_fb = NULL; |
7142 | 7194 | ||
7143 | if (!mode) |
7195 | if (!mode) |
7144 | mode = &load_detect_mode; |
7196 | mode = &load_detect_mode; |
7145 | 7197 | ||
7146 | /* We need a framebuffer large enough to accommodate all accesses |
7198 | /* We need a framebuffer large enough to accommodate all accesses |
7147 | * that the plane may generate whilst we perform load detection. |
7199 | * that the plane may generate whilst we perform load detection. |
7148 | * We can not rely on the fbcon either being present (we get called |
7200 | * We can not rely on the fbcon either being present (we get called |
7149 | * during its initialisation to detect all boot displays, or it may |
7201 | * during its initialisation to detect all boot displays, or it may |
7150 | * not even exist) or that it is large enough to satisfy the |
7202 | * not even exist) or that it is large enough to satisfy the |
7151 | * requested mode. |
7203 | * requested mode. |
7152 | */ |
7204 | */ |
7153 | fb = mode_fits_in_fbdev(dev, mode); |
7205 | fb = mode_fits_in_fbdev(dev, mode); |
7154 | if (fb == NULL) { |
7206 | if (fb == NULL) { |
7155 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
7207 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
7156 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7208 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7157 | old->release_fb = fb; |
7209 | old->release_fb = fb; |
7158 | } else |
7210 | } else |
7159 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
7211 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
7160 | if (IS_ERR(fb)) { |
7212 | if (IS_ERR(fb)) { |
7161 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7213 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7162 | mutex_unlock(&crtc->mutex); |
7214 | mutex_unlock(&crtc->mutex); |
7163 | return false; |
7215 | return false; |
7164 | } |
7216 | } |
7165 | 7217 | ||
7166 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
7218 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
7167 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
7219 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
7168 | if (old->release_fb) |
7220 | if (old->release_fb) |
7169 | old->release_fb->funcs->destroy(old->release_fb); |
7221 | old->release_fb->funcs->destroy(old->release_fb); |
7170 | mutex_unlock(&crtc->mutex); |
7222 | mutex_unlock(&crtc->mutex); |
7171 | return false; |
7223 | return false; |
7172 | } |
7224 | } |
7173 | 7225 | ||
7174 | /* let the connector get through one full cycle before testing */ |
7226 | /* let the connector get through one full cycle before testing */ |
7175 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7227 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7176 | return true; |
7228 | return true; |
7177 | } |
7229 | } |
7178 | 7230 | ||
7179 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
7231 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
7180 | struct intel_load_detect_pipe *old) |
7232 | struct intel_load_detect_pipe *old) |
7181 | { |
7233 | { |
7182 | struct intel_encoder *intel_encoder = |
7234 | struct intel_encoder *intel_encoder = |
7183 | intel_attached_encoder(connector); |
7235 | intel_attached_encoder(connector); |
7184 | struct drm_encoder *encoder = &intel_encoder->base; |
7236 | struct drm_encoder *encoder = &intel_encoder->base; |
7185 | struct drm_crtc *crtc = encoder->crtc; |
7237 | struct drm_crtc *crtc = encoder->crtc; |
7186 | 7238 | ||
7187 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7239 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7188 | connector->base.id, drm_get_connector_name(connector), |
7240 | connector->base.id, drm_get_connector_name(connector), |
7189 | encoder->base.id, drm_get_encoder_name(encoder)); |
7241 | encoder->base.id, drm_get_encoder_name(encoder)); |
7190 | 7242 | ||
7191 | if (old->load_detect_temp) { |
7243 | if (old->load_detect_temp) { |
7192 | to_intel_connector(connector)->new_encoder = NULL; |
7244 | to_intel_connector(connector)->new_encoder = NULL; |
7193 | intel_encoder->new_crtc = NULL; |
7245 | intel_encoder->new_crtc = NULL; |
7194 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
7246 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
7195 | 7247 | ||
7196 | if (old->release_fb) { |
7248 | if (old->release_fb) { |
7197 | drm_framebuffer_unregister_private(old->release_fb); |
7249 | drm_framebuffer_unregister_private(old->release_fb); |
7198 | drm_framebuffer_unreference(old->release_fb); |
7250 | drm_framebuffer_unreference(old->release_fb); |
7199 | } |
7251 | } |
7200 | 7252 | ||
7201 | mutex_unlock(&crtc->mutex); |
7253 | mutex_unlock(&crtc->mutex); |
7202 | return; |
7254 | return; |
7203 | } |
7255 | } |
7204 | 7256 | ||
7205 | /* Switch crtc and encoder back off if necessary */ |
7257 | /* Switch crtc and encoder back off if necessary */ |
7206 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7258 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7207 | connector->funcs->dpms(connector, old->dpms_mode); |
7259 | connector->funcs->dpms(connector, old->dpms_mode); |
7208 | 7260 | ||
7209 | mutex_unlock(&crtc->mutex); |
7261 | mutex_unlock(&crtc->mutex); |
7210 | } |
7262 | } |
7211 | 7263 | ||
7212 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
7264 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
7213 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7265 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7214 | struct intel_crtc_config *pipe_config) |
7266 | struct intel_crtc_config *pipe_config) |
7215 | { |
7267 | { |
7216 | struct drm_device *dev = crtc->base.dev; |
7268 | struct drm_device *dev = crtc->base.dev; |
7217 | struct drm_i915_private *dev_priv = dev->dev_private; |
7269 | struct drm_i915_private *dev_priv = dev->dev_private; |
7218 | int pipe = pipe_config->cpu_transcoder; |
7270 | int pipe = pipe_config->cpu_transcoder; |
7219 | u32 dpll = I915_READ(DPLL(pipe)); |
7271 | u32 dpll = I915_READ(DPLL(pipe)); |
7220 | u32 fp; |
7272 | u32 fp; |
7221 | intel_clock_t clock; |
7273 | intel_clock_t clock; |
7222 | 7274 | ||
7223 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
7275 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
7224 | fp = I915_READ(FP0(pipe)); |
7276 | fp = I915_READ(FP0(pipe)); |
7225 | else |
7277 | else |
7226 | fp = I915_READ(FP1(pipe)); |
7278 | fp = I915_READ(FP1(pipe)); |
7227 | 7279 | ||
7228 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
7280 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
7229 | if (IS_PINEVIEW(dev)) { |
7281 | if (IS_PINEVIEW(dev)) { |
7230 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
7282 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
7231 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7283 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7232 | } else { |
7284 | } else { |
7233 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
7285 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
7234 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7286 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
7235 | } |
7287 | } |
7236 | 7288 | ||
7237 | if (!IS_GEN2(dev)) { |
7289 | if (!IS_GEN2(dev)) { |
7238 | if (IS_PINEVIEW(dev)) |
7290 | if (IS_PINEVIEW(dev)) |
7239 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
7291 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
7240 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
7292 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
7241 | else |
7293 | else |
7242 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
7294 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
7243 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7295 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7244 | 7296 | ||
7245 | switch (dpll & DPLL_MODE_MASK) { |
7297 | switch (dpll & DPLL_MODE_MASK) { |
7246 | case DPLLB_MODE_DAC_SERIAL: |
7298 | case DPLLB_MODE_DAC_SERIAL: |
7247 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
7299 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
7248 | 5 : 10; |
7300 | 5 : 10; |
7249 | break; |
7301 | break; |
7250 | case DPLLB_MODE_LVDS: |
7302 | case DPLLB_MODE_LVDS: |
7251 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
7303 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
7252 | 7 : 14; |
7304 | 7 : 14; |
7253 | break; |
7305 | break; |
7254 | default: |
7306 | default: |
7255 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
7307 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
7256 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7308 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7257 | pipe_config->adjusted_mode.clock = 0; |
7309 | pipe_config->adjusted_mode.clock = 0; |
7258 | return; |
7310 | return; |
7259 | } |
7311 | } |
7260 | 7312 | ||
7261 | if (IS_PINEVIEW(dev)) |
7313 | if (IS_PINEVIEW(dev)) |
7262 | pineview_clock(96000, &clock); |
7314 | pineview_clock(96000, &clock); |
7263 | else |
7315 | else |
7264 | i9xx_clock(96000, &clock); |
7316 | i9xx_clock(96000, &clock); |
7265 | } else { |
7317 | } else { |
7266 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
7318 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
7267 | 7319 | ||
7268 | if (is_lvds) { |
7320 | if (is_lvds) { |
7269 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
7321 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
7270 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7322 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7271 | clock.p2 = 14; |
7323 | clock.p2 = 14; |
7272 | 7324 | ||
7273 | if ((dpll & PLL_REF_INPUT_MASK) == |
7325 | if ((dpll & PLL_REF_INPUT_MASK) == |
7274 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
7326 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
7275 | /* XXX: might not be 66MHz */ |
7327 | /* XXX: might not be 66MHz */ |
7276 | i9xx_clock(66000, &clock); |
7328 | i9xx_clock(66000, &clock); |
7277 | } else |
7329 | } else |
7278 | i9xx_clock(48000, &clock); |
7330 | i9xx_clock(48000, &clock); |
7279 | } else { |
7331 | } else { |
7280 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
7332 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
7281 | clock.p1 = 2; |
7333 | clock.p1 = 2; |
7282 | else { |
7334 | else { |
7283 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
7335 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
7284 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
7336 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
7285 | } |
7337 | } |
7286 | if (dpll & PLL_P2_DIVIDE_BY_4) |
7338 | if (dpll & PLL_P2_DIVIDE_BY_4) |
7287 | clock.p2 = 4; |
7339 | clock.p2 = 4; |
7288 | else |
7340 | else |
7289 | clock.p2 = 2; |
7341 | clock.p2 = 2; |
7290 | 7342 | ||
7291 | i9xx_clock(48000, &clock); |
7343 | i9xx_clock(48000, &clock); |
7292 | } |
7344 | } |
7293 | } |
7345 | } |
7294 | 7346 | ||
7295 | pipe_config->adjusted_mode.clock = clock.dot; |
7347 | pipe_config->adjusted_mode.clock = clock.dot; |
7296 | } |
7348 | } |
7297 | 7349 | ||
7298 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
7350 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, |
7299 | struct intel_crtc_config *pipe_config) |
7351 | struct intel_crtc_config *pipe_config) |
7300 | { |
7352 | { |
7301 | struct drm_device *dev = crtc->base.dev; |
7353 | struct drm_device *dev = crtc->base.dev; |
7302 | struct drm_i915_private *dev_priv = dev->dev_private; |
7354 | struct drm_i915_private *dev_priv = dev->dev_private; |
7303 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7355 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7304 | int link_freq, repeat; |
7356 | int link_freq, repeat; |
7305 | u64 clock; |
7357 | u64 clock; |
7306 | u32 link_m, link_n; |
7358 | u32 link_m, link_n; |
7307 | 7359 | ||
7308 | repeat = pipe_config->pixel_multiplier; |
7360 | repeat = pipe_config->pixel_multiplier; |
7309 | 7361 | ||
7310 | /* |
7362 | /* |
7311 | * The calculation for the data clock is: |
7363 | * The calculation for the data clock is: |
7312 | * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp |
7364 | * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp |
7313 | * But we want to avoid losing precison if possible, so: |
7365 | * But we want to avoid losing precison if possible, so: |
7314 | * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp)) |
7366 | * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp)) |
7315 | * |
7367 | * |
7316 | * and the link clock is simpler: |
7368 | * and the link clock is simpler: |
7317 | * link_clock = (m * link_clock * repeat) / n |
7369 | * link_clock = (m * link_clock * repeat) / n |
7318 | */ |
7370 | */ |
7319 | 7371 | ||
7320 | /* |
7372 | /* |
7321 | * We need to get the FDI or DP link clock here to derive |
7373 | * We need to get the FDI or DP link clock here to derive |
7322 | * the M/N dividers. |
7374 | * the M/N dividers. |
7323 | * |
7375 | * |
7324 | * For FDI, we read it from the BIOS or use a fixed 2.7GHz. |
7376 | * For FDI, we read it from the BIOS or use a fixed 2.7GHz. |
7325 | * For DP, it's either 1.62GHz or 2.7GHz. |
7377 | * For DP, it's either 1.62GHz or 2.7GHz. |
7326 | * We do our calculations in 10*MHz since we don't need much precison. |
7378 | * We do our calculations in 10*MHz since we don't need much precison. |
7327 | */ |
7379 | */ |
7328 | if (pipe_config->has_pch_encoder) |
7380 | if (pipe_config->has_pch_encoder) |
7329 | link_freq = intel_fdi_link_freq(dev) * 10000; |
7381 | link_freq = intel_fdi_link_freq(dev) * 10000; |
7330 | else |
7382 | else |
7331 | link_freq = pipe_config->port_clock; |
7383 | link_freq = pipe_config->port_clock; |
7332 | 7384 | ||
7333 | link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); |
7385 | link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); |
7334 | link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder)); |
7386 | link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder)); |
7335 | 7387 | ||
7336 | if (!link_m || !link_n) |
7388 | if (!link_m || !link_n) |
7337 | return; |
7389 | return; |
7338 | 7390 | ||
7339 | clock = ((u64)link_m * (u64)link_freq * (u64)repeat); |
7391 | clock = ((u64)link_m * (u64)link_freq * (u64)repeat); |
7340 | do_div(clock, link_n); |
7392 | do_div(clock, link_n); |
7341 | 7393 | ||
7342 | pipe_config->adjusted_mode.clock = clock; |
7394 | pipe_config->adjusted_mode.clock = clock; |
7343 | } |
7395 | } |
7344 | 7396 | ||
7345 | /** Returns the currently programmed mode of the given pipe. */ |
7397 | /** Returns the currently programmed mode of the given pipe. */ |
7346 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
7398 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
7347 | struct drm_crtc *crtc) |
7399 | struct drm_crtc *crtc) |
7348 | { |
7400 | { |
7349 | struct drm_i915_private *dev_priv = dev->dev_private; |
7401 | struct drm_i915_private *dev_priv = dev->dev_private; |
7350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7351 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
7403 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
7352 | struct drm_display_mode *mode; |
7404 | struct drm_display_mode *mode; |
7353 | struct intel_crtc_config pipe_config; |
7405 | struct intel_crtc_config pipe_config; |
7354 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7406 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7355 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
7407 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
7356 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
7408 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
7357 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
7409 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
7358 | 7410 | ||
7359 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
7411 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
7360 | if (!mode) |
7412 | if (!mode) |
7361 | return NULL; |
7413 | return NULL; |
7362 | 7414 | ||
7363 | /* |
7415 | /* |
7364 | * Construct a pipe_config sufficient for getting the clock info |
7416 | * Construct a pipe_config sufficient for getting the clock info |
7365 | * back out of crtc_clock_get. |
7417 | * back out of crtc_clock_get. |
7366 | * |
7418 | * |
7367 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
7419 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
7368 | * to use a real value here instead. |
7420 | * to use a real value here instead. |
7369 | */ |
7421 | */ |
7370 | pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
7422 | pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
7371 | pipe_config.pixel_multiplier = 1; |
7423 | pipe_config.pixel_multiplier = 1; |
7372 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
7424 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
7373 | 7425 | ||
7374 | mode->clock = pipe_config.adjusted_mode.clock; |
7426 | mode->clock = pipe_config.adjusted_mode.clock; |
7375 | mode->hdisplay = (htot & 0xffff) + 1; |
7427 | mode->hdisplay = (htot & 0xffff) + 1; |
7376 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
7428 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
7377 | mode->hsync_start = (hsync & 0xffff) + 1; |
7429 | mode->hsync_start = (hsync & 0xffff) + 1; |
7378 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
7430 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
7379 | mode->vdisplay = (vtot & 0xffff) + 1; |
7431 | mode->vdisplay = (vtot & 0xffff) + 1; |
7380 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
7432 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
7381 | mode->vsync_start = (vsync & 0xffff) + 1; |
7433 | mode->vsync_start = (vsync & 0xffff) + 1; |
7382 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
7434 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
7383 | 7435 | ||
7384 | drm_mode_set_name(mode); |
7436 | drm_mode_set_name(mode); |
7385 | 7437 | ||
7386 | return mode; |
7438 | return mode; |
7387 | } |
7439 | } |
7388 | 7440 | ||
7389 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
7441 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
7390 | { |
7442 | { |
7391 | struct drm_device *dev = crtc->dev; |
7443 | struct drm_device *dev = crtc->dev; |
7392 | drm_i915_private_t *dev_priv = dev->dev_private; |
7444 | drm_i915_private_t *dev_priv = dev->dev_private; |
7393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7394 | int pipe = intel_crtc->pipe; |
7446 | int pipe = intel_crtc->pipe; |
7395 | int dpll_reg = DPLL(pipe); |
7447 | int dpll_reg = DPLL(pipe); |
7396 | int dpll; |
7448 | int dpll; |
7397 | 7449 | ||
7398 | if (HAS_PCH_SPLIT(dev)) |
7450 | if (HAS_PCH_SPLIT(dev)) |
7399 | return; |
7451 | return; |
7400 | 7452 | ||
7401 | if (!dev_priv->lvds_downclock_avail) |
7453 | if (!dev_priv->lvds_downclock_avail) |
7402 | return; |
7454 | return; |
7403 | 7455 | ||
7404 | dpll = I915_READ(dpll_reg); |
7456 | dpll = I915_READ(dpll_reg); |
7405 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
7457 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
7406 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
7458 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
7407 | 7459 | ||
7408 | assert_panel_unlocked(dev_priv, pipe); |
7460 | assert_panel_unlocked(dev_priv, pipe); |
7409 | 7461 | ||
7410 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
7462 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
7411 | I915_WRITE(dpll_reg, dpll); |
7463 | I915_WRITE(dpll_reg, dpll); |
7412 | intel_wait_for_vblank(dev, pipe); |
7464 | intel_wait_for_vblank(dev, pipe); |
7413 | 7465 | ||
7414 | dpll = I915_READ(dpll_reg); |
7466 | dpll = I915_READ(dpll_reg); |
7415 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
7467 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
7416 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
7468 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
7417 | } |
7469 | } |
7418 | } |
7470 | } |
7419 | 7471 | ||
7420 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
7472 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
7421 | { |
7473 | { |
7422 | struct drm_device *dev = crtc->dev; |
7474 | struct drm_device *dev = crtc->dev; |
7423 | drm_i915_private_t *dev_priv = dev->dev_private; |
7475 | drm_i915_private_t *dev_priv = dev->dev_private; |
7424 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7476 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7425 | 7477 | ||
7426 | if (HAS_PCH_SPLIT(dev)) |
7478 | if (HAS_PCH_SPLIT(dev)) |
7427 | return; |
7479 | return; |
7428 | 7480 | ||
7429 | if (!dev_priv->lvds_downclock_avail) |
7481 | if (!dev_priv->lvds_downclock_avail) |
7430 | return; |
7482 | return; |
7431 | 7483 | ||
7432 | /* |
7484 | /* |
7433 | * Since this is called by a timer, we should never get here in |
7485 | * Since this is called by a timer, we should never get here in |
7434 | * the manual case. |
7486 | * the manual case. |
7435 | */ |
7487 | */ |
7436 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
7488 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
7437 | int pipe = intel_crtc->pipe; |
7489 | int pipe = intel_crtc->pipe; |
7438 | int dpll_reg = DPLL(pipe); |
7490 | int dpll_reg = DPLL(pipe); |
7439 | int dpll; |
7491 | int dpll; |
7440 | 7492 | ||
7441 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
7493 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
7442 | 7494 | ||
7443 | assert_panel_unlocked(dev_priv, pipe); |
7495 | assert_panel_unlocked(dev_priv, pipe); |
7444 | 7496 | ||
7445 | dpll = I915_READ(dpll_reg); |
7497 | dpll = I915_READ(dpll_reg); |
7446 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7498 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7447 | I915_WRITE(dpll_reg, dpll); |
7499 | I915_WRITE(dpll_reg, dpll); |
7448 | intel_wait_for_vblank(dev, pipe); |
7500 | intel_wait_for_vblank(dev, pipe); |
7449 | dpll = I915_READ(dpll_reg); |
7501 | dpll = I915_READ(dpll_reg); |
7450 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
7502 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
7451 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
7503 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
7452 | } |
7504 | } |
7453 | 7505 | ||
7454 | } |
7506 | } |
7455 | 7507 | ||
7456 | void intel_mark_busy(struct drm_device *dev) |
7508 | void intel_mark_busy(struct drm_device *dev) |
7457 | { |
7509 | { |
7458 | struct drm_i915_private *dev_priv = dev->dev_private; |
7510 | struct drm_i915_private *dev_priv = dev->dev_private; |
7459 | 7511 | ||
7460 | hsw_package_c8_gpu_busy(dev_priv); |
7512 | hsw_package_c8_gpu_busy(dev_priv); |
7461 | i915_update_gfx_val(dev_priv); |
7513 | i915_update_gfx_val(dev_priv); |
7462 | } |
7514 | } |
7463 | 7515 | ||
7464 | void intel_mark_idle(struct drm_device *dev) |
7516 | void intel_mark_idle(struct drm_device *dev) |
7465 | { |
7517 | { |
7466 | struct drm_i915_private *dev_priv = dev->dev_private; |
7518 | struct drm_i915_private *dev_priv = dev->dev_private; |
7467 | struct drm_crtc *crtc; |
7519 | struct drm_crtc *crtc; |
7468 | 7520 | ||
7469 | hsw_package_c8_gpu_idle(dev_priv); |
7521 | hsw_package_c8_gpu_idle(dev_priv); |
7470 | 7522 | ||
7471 | if (!i915_powersave) |
7523 | if (!i915_powersave) |
7472 | return; |
7524 | return; |
7473 | 7525 | ||
7474 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7526 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7475 | if (!crtc->fb) |
7527 | if (!crtc->fb) |
7476 | continue; |
7528 | continue; |
7477 | 7529 | ||
7478 | intel_decrease_pllclock(crtc); |
7530 | intel_decrease_pllclock(crtc); |
7479 | } |
7531 | } |
7480 | } |
7532 | } |
7481 | 7533 | ||
7482 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7534 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7483 | struct intel_ring_buffer *ring) |
7535 | struct intel_ring_buffer *ring) |
7484 | { |
7536 | { |
7485 | struct drm_device *dev = obj->base.dev; |
7537 | struct drm_device *dev = obj->base.dev; |
7486 | struct drm_crtc *crtc; |
7538 | struct drm_crtc *crtc; |
7487 | 7539 | ||
7488 | if (!i915_powersave) |
7540 | if (!i915_powersave) |
7489 | return; |
7541 | return; |
7490 | 7542 | ||
7491 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7543 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7492 | if (!crtc->fb) |
7544 | if (!crtc->fb) |
7493 | continue; |
7545 | continue; |
7494 | 7546 | ||
7495 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7547 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7496 | continue; |
7548 | continue; |
7497 | 7549 | ||
7498 | intel_increase_pllclock(crtc); |
7550 | intel_increase_pllclock(crtc); |
7499 | if (ring && intel_fbc_enabled(dev)) |
7551 | if (ring && intel_fbc_enabled(dev)) |
7500 | ring->fbc_dirty = true; |
7552 | ring->fbc_dirty = true; |
7501 | } |
7553 | } |
7502 | } |
7554 | } |
7503 | 7555 | ||
7504 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7556 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7505 | { |
7557 | { |
7506 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7507 | struct drm_device *dev = crtc->dev; |
7559 | struct drm_device *dev = crtc->dev; |
7508 | struct intel_unpin_work *work; |
7560 | struct intel_unpin_work *work; |
7509 | unsigned long flags; |
7561 | unsigned long flags; |
7510 | 7562 | ||
7511 | spin_lock_irqsave(&dev->event_lock, flags); |
7563 | spin_lock_irqsave(&dev->event_lock, flags); |
7512 | work = intel_crtc->unpin_work; |
7564 | work = intel_crtc->unpin_work; |
7513 | intel_crtc->unpin_work = NULL; |
7565 | intel_crtc->unpin_work = NULL; |
7514 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7566 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7515 | 7567 | ||
7516 | if (work) { |
7568 | if (work) { |
7517 | // cancel_work_sync(&work->work); |
7569 | // cancel_work_sync(&work->work); |
7518 | kfree(work); |
7570 | kfree(work); |
7519 | } |
7571 | } |
7520 | 7572 | ||
7521 | drm_crtc_cleanup(crtc); |
7573 | drm_crtc_cleanup(crtc); |
7522 | 7574 | ||
7523 | kfree(intel_crtc); |
7575 | kfree(intel_crtc); |
7524 | } |
7576 | } |
7525 | 7577 | ||
7526 | #if 0 |
7578 | #if 0 |
7527 | static void intel_unpin_work_fn(struct work_struct *__work) |
7579 | static void intel_unpin_work_fn(struct work_struct *__work) |
7528 | { |
7580 | { |
7529 | struct intel_unpin_work *work = |
7581 | struct intel_unpin_work *work = |
7530 | container_of(__work, struct intel_unpin_work, work); |
7582 | container_of(__work, struct intel_unpin_work, work); |
7531 | struct drm_device *dev = work->crtc->dev; |
7583 | struct drm_device *dev = work->crtc->dev; |
7532 | 7584 | ||
7533 | mutex_lock(&dev->struct_mutex); |
7585 | mutex_lock(&dev->struct_mutex); |
7534 | intel_unpin_fb_obj(work->old_fb_obj); |
7586 | intel_unpin_fb_obj(work->old_fb_obj); |
7535 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7587 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7536 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7588 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7537 | 7589 | ||
7538 | intel_update_fbc(dev); |
7590 | intel_update_fbc(dev); |
7539 | mutex_unlock(&dev->struct_mutex); |
7591 | mutex_unlock(&dev->struct_mutex); |
7540 | 7592 | ||
7541 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
7593 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
7542 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
7594 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
7543 | 7595 | ||
7544 | kfree(work); |
7596 | kfree(work); |
7545 | } |
7597 | } |
7546 | 7598 | ||
7547 | static void do_intel_finish_page_flip(struct drm_device *dev, |
7599 | static void do_intel_finish_page_flip(struct drm_device *dev, |
7548 | struct drm_crtc *crtc) |
7600 | struct drm_crtc *crtc) |
7549 | { |
7601 | { |
7550 | drm_i915_private_t *dev_priv = dev->dev_private; |
7602 | drm_i915_private_t *dev_priv = dev->dev_private; |
7551 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7552 | struct intel_unpin_work *work; |
7604 | struct intel_unpin_work *work; |
7553 | unsigned long flags; |
7605 | unsigned long flags; |
7554 | 7606 | ||
7555 | /* Ignore early vblank irqs */ |
7607 | /* Ignore early vblank irqs */ |
7556 | if (intel_crtc == NULL) |
7608 | if (intel_crtc == NULL) |
7557 | return; |
7609 | return; |
7558 | 7610 | ||
7559 | spin_lock_irqsave(&dev->event_lock, flags); |
7611 | spin_lock_irqsave(&dev->event_lock, flags); |
7560 | work = intel_crtc->unpin_work; |
7612 | work = intel_crtc->unpin_work; |
7561 | 7613 | ||
7562 | /* Ensure we don't miss a work->pending update ... */ |
7614 | /* Ensure we don't miss a work->pending update ... */ |
7563 | smp_rmb(); |
7615 | smp_rmb(); |
7564 | 7616 | ||
7565 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
7617 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
7566 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7618 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7567 | return; |
7619 | return; |
7568 | } |
7620 | } |
7569 | 7621 | ||
7570 | /* and that the unpin work is consistent wrt ->pending. */ |
7622 | /* and that the unpin work is consistent wrt ->pending. */ |
7571 | smp_rmb(); |
7623 | smp_rmb(); |
7572 | 7624 | ||
7573 | intel_crtc->unpin_work = NULL; |
7625 | intel_crtc->unpin_work = NULL; |
7574 | 7626 | ||
7575 | if (work->event) |
7627 | if (work->event) |
7576 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
7628 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
7577 | 7629 | ||
7578 | drm_vblank_put(dev, intel_crtc->pipe); |
7630 | drm_vblank_put(dev, intel_crtc->pipe); |
7579 | 7631 | ||
7580 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7632 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7581 | 7633 | ||
7582 | wake_up_all(&dev_priv->pending_flip_queue); |
7634 | wake_up_all(&dev_priv->pending_flip_queue); |
7583 | 7635 | ||
7584 | queue_work(dev_priv->wq, &work->work); |
7636 | queue_work(dev_priv->wq, &work->work); |
7585 | 7637 | ||
7586 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
7638 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
7587 | } |
7639 | } |
7588 | 7640 | ||
7589 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7641 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7590 | { |
7642 | { |
7591 | drm_i915_private_t *dev_priv = dev->dev_private; |
7643 | drm_i915_private_t *dev_priv = dev->dev_private; |
7592 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
7644 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
7593 | 7645 | ||
7594 | do_intel_finish_page_flip(dev, crtc); |
7646 | do_intel_finish_page_flip(dev, crtc); |
7595 | } |
7647 | } |
7596 | 7648 | ||
7597 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
7649 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
7598 | { |
7650 | { |
7599 | drm_i915_private_t *dev_priv = dev->dev_private; |
7651 | drm_i915_private_t *dev_priv = dev->dev_private; |
7600 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
7652 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
7601 | 7653 | ||
7602 | do_intel_finish_page_flip(dev, crtc); |
7654 | do_intel_finish_page_flip(dev, crtc); |
7603 | } |
7655 | } |
7604 | 7656 | ||
7605 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7657 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7606 | { |
7658 | { |
7607 | drm_i915_private_t *dev_priv = dev->dev_private; |
7659 | drm_i915_private_t *dev_priv = dev->dev_private; |
7608 | struct intel_crtc *intel_crtc = |
7660 | struct intel_crtc *intel_crtc = |
7609 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
7661 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
7610 | unsigned long flags; |
7662 | unsigned long flags; |
7611 | 7663 | ||
7612 | /* NB: An MMIO update of the plane base pointer will also |
7664 | /* NB: An MMIO update of the plane base pointer will also |
7613 | * generate a page-flip completion irq, i.e. every modeset |
7665 | * generate a page-flip completion irq, i.e. every modeset |
7614 | * is also accompanied by a spurious intel_prepare_page_flip(). |
7666 | * is also accompanied by a spurious intel_prepare_page_flip(). |
7615 | */ |
7667 | */ |
7616 | spin_lock_irqsave(&dev->event_lock, flags); |
7668 | spin_lock_irqsave(&dev->event_lock, flags); |
7617 | if (intel_crtc->unpin_work) |
7669 | if (intel_crtc->unpin_work) |
7618 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
7670 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
7619 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7671 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7620 | } |
7672 | } |
7621 | 7673 | ||
7622 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7674 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7623 | { |
7675 | { |
7624 | /* Ensure that the work item is consistent when activating it ... */ |
7676 | /* Ensure that the work item is consistent when activating it ... */ |
7625 | smp_wmb(); |
7677 | smp_wmb(); |
7626 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
7678 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
7627 | /* and that it is marked active as soon as the irq could fire. */ |
7679 | /* and that it is marked active as soon as the irq could fire. */ |
7628 | smp_wmb(); |
7680 | smp_wmb(); |
7629 | } |
7681 | } |
7630 | 7682 | ||
7631 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7683 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7632 | struct drm_crtc *crtc, |
7684 | struct drm_crtc *crtc, |
7633 | struct drm_framebuffer *fb, |
7685 | struct drm_framebuffer *fb, |
7634 | struct drm_i915_gem_object *obj, |
7686 | struct drm_i915_gem_object *obj, |
7635 | uint32_t flags) |
7687 | uint32_t flags) |
7636 | { |
7688 | { |
7637 | struct drm_i915_private *dev_priv = dev->dev_private; |
7689 | struct drm_i915_private *dev_priv = dev->dev_private; |
7638 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7639 | u32 flip_mask; |
7691 | u32 flip_mask; |
7640 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7692 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7641 | int ret; |
7693 | int ret; |
7642 | 7694 | ||
7643 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7695 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7644 | if (ret) |
7696 | if (ret) |
7645 | goto err; |
7697 | goto err; |
7646 | 7698 | ||
7647 | ret = intel_ring_begin(ring, 6); |
7699 | ret = intel_ring_begin(ring, 6); |
7648 | if (ret) |
7700 | if (ret) |
7649 | goto err_unpin; |
7701 | goto err_unpin; |
7650 | 7702 | ||
7651 | /* Can't queue multiple flips, so wait for the previous |
7703 | /* Can't queue multiple flips, so wait for the previous |
7652 | * one to finish before executing the next. |
7704 | * one to finish before executing the next. |
7653 | */ |
7705 | */ |
7654 | if (intel_crtc->plane) |
7706 | if (intel_crtc->plane) |
7655 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7707 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7656 | else |
7708 | else |
7657 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7709 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7658 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7710 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7659 | intel_ring_emit(ring, MI_NOOP); |
7711 | intel_ring_emit(ring, MI_NOOP); |
7660 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7712 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7661 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7713 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7662 | intel_ring_emit(ring, fb->pitches[0]); |
7714 | intel_ring_emit(ring, fb->pitches[0]); |
7663 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7715 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7664 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
7716 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
7665 | 7717 | ||
7666 | intel_mark_page_flip_active(intel_crtc); |
7718 | intel_mark_page_flip_active(intel_crtc); |
7667 | intel_ring_advance(ring); |
7719 | intel_ring_advance(ring); |
7668 | return 0; |
7720 | return 0; |
7669 | 7721 | ||
7670 | err_unpin: |
7722 | err_unpin: |
7671 | intel_unpin_fb_obj(obj); |
7723 | intel_unpin_fb_obj(obj); |
7672 | err: |
7724 | err: |
7673 | return ret; |
7725 | return ret; |
7674 | } |
7726 | } |
7675 | 7727 | ||
7676 | static int intel_gen3_queue_flip(struct drm_device *dev, |
7728 | static int intel_gen3_queue_flip(struct drm_device *dev, |
7677 | struct drm_crtc *crtc, |
7729 | struct drm_crtc *crtc, |
7678 | struct drm_framebuffer *fb, |
7730 | struct drm_framebuffer *fb, |
7679 | struct drm_i915_gem_object *obj, |
7731 | struct drm_i915_gem_object *obj, |
7680 | uint32_t flags) |
7732 | uint32_t flags) |
7681 | { |
7733 | { |
7682 | struct drm_i915_private *dev_priv = dev->dev_private; |
7734 | struct drm_i915_private *dev_priv = dev->dev_private; |
7683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7735 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7684 | u32 flip_mask; |
7736 | u32 flip_mask; |
7685 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7737 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7686 | int ret; |
7738 | int ret; |
7687 | 7739 | ||
7688 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7740 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7689 | if (ret) |
7741 | if (ret) |
7690 | goto err; |
7742 | goto err; |
7691 | 7743 | ||
7692 | ret = intel_ring_begin(ring, 6); |
7744 | ret = intel_ring_begin(ring, 6); |
7693 | if (ret) |
7745 | if (ret) |
7694 | goto err_unpin; |
7746 | goto err_unpin; |
7695 | 7747 | ||
7696 | if (intel_crtc->plane) |
7748 | if (intel_crtc->plane) |
7697 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7749 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
7698 | else |
7750 | else |
7699 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7751 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
7700 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7752 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7701 | intel_ring_emit(ring, MI_NOOP); |
7753 | intel_ring_emit(ring, MI_NOOP); |
7702 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
7754 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
7703 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7755 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7704 | intel_ring_emit(ring, fb->pitches[0]); |
7756 | intel_ring_emit(ring, fb->pitches[0]); |
7705 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7757 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7706 | intel_ring_emit(ring, MI_NOOP); |
7758 | intel_ring_emit(ring, MI_NOOP); |
7707 | 7759 | ||
7708 | intel_mark_page_flip_active(intel_crtc); |
7760 | intel_mark_page_flip_active(intel_crtc); |
7709 | intel_ring_advance(ring); |
7761 | intel_ring_advance(ring); |
7710 | return 0; |
7762 | return 0; |
7711 | 7763 | ||
7712 | err_unpin: |
7764 | err_unpin: |
7713 | intel_unpin_fb_obj(obj); |
7765 | intel_unpin_fb_obj(obj); |
7714 | err: |
7766 | err: |
7715 | return ret; |
7767 | return ret; |
7716 | } |
7768 | } |
7717 | 7769 | ||
7718 | static int intel_gen4_queue_flip(struct drm_device *dev, |
7770 | static int intel_gen4_queue_flip(struct drm_device *dev, |
7719 | struct drm_crtc *crtc, |
7771 | struct drm_crtc *crtc, |
7720 | struct drm_framebuffer *fb, |
7772 | struct drm_framebuffer *fb, |
7721 | struct drm_i915_gem_object *obj, |
7773 | struct drm_i915_gem_object *obj, |
7722 | uint32_t flags) |
7774 | uint32_t flags) |
7723 | { |
7775 | { |
7724 | struct drm_i915_private *dev_priv = dev->dev_private; |
7776 | struct drm_i915_private *dev_priv = dev->dev_private; |
7725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7726 | uint32_t pf, pipesrc; |
7778 | uint32_t pf, pipesrc; |
7727 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7779 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7728 | int ret; |
7780 | int ret; |
7729 | 7781 | ||
7730 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7782 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7731 | if (ret) |
7783 | if (ret) |
7732 | goto err; |
7784 | goto err; |
7733 | 7785 | ||
7734 | ret = intel_ring_begin(ring, 4); |
7786 | ret = intel_ring_begin(ring, 4); |
7735 | if (ret) |
7787 | if (ret) |
7736 | goto err_unpin; |
7788 | goto err_unpin; |
7737 | 7789 | ||
7738 | /* i965+ uses the linear or tiled offsets from the |
7790 | /* i965+ uses the linear or tiled offsets from the |
7739 | * Display Registers (which do not change across a page-flip) |
7791 | * Display Registers (which do not change across a page-flip) |
7740 | * so we need only reprogram the base address. |
7792 | * so we need only reprogram the base address. |
7741 | */ |
7793 | */ |
7742 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7794 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7743 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7795 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7744 | intel_ring_emit(ring, fb->pitches[0]); |
7796 | intel_ring_emit(ring, fb->pitches[0]); |
7745 | intel_ring_emit(ring, |
7797 | intel_ring_emit(ring, |
7746 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
7798 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
7747 | obj->tiling_mode); |
7799 | obj->tiling_mode); |
7748 | 7800 | ||
7749 | /* XXX Enabling the panel-fitter across page-flip is so far |
7801 | /* XXX Enabling the panel-fitter across page-flip is so far |
7750 | * untested on non-native modes, so ignore it for now. |
7802 | * untested on non-native modes, so ignore it for now. |
7751 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
7803 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
7752 | */ |
7804 | */ |
7753 | pf = 0; |
7805 | pf = 0; |
7754 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7806 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7755 | intel_ring_emit(ring, pf | pipesrc); |
7807 | intel_ring_emit(ring, pf | pipesrc); |
7756 | 7808 | ||
7757 | intel_mark_page_flip_active(intel_crtc); |
7809 | intel_mark_page_flip_active(intel_crtc); |
7758 | intel_ring_advance(ring); |
7810 | intel_ring_advance(ring); |
7759 | return 0; |
7811 | return 0; |
7760 | 7812 | ||
7761 | err_unpin: |
7813 | err_unpin: |
7762 | intel_unpin_fb_obj(obj); |
7814 | intel_unpin_fb_obj(obj); |
7763 | err: |
7815 | err: |
7764 | return ret; |
7816 | return ret; |
7765 | } |
7817 | } |
7766 | 7818 | ||
7767 | static int intel_gen6_queue_flip(struct drm_device *dev, |
7819 | static int intel_gen6_queue_flip(struct drm_device *dev, |
7768 | struct drm_crtc *crtc, |
7820 | struct drm_crtc *crtc, |
7769 | struct drm_framebuffer *fb, |
7821 | struct drm_framebuffer *fb, |
7770 | struct drm_i915_gem_object *obj, |
7822 | struct drm_i915_gem_object *obj, |
7771 | uint32_t flags) |
7823 | uint32_t flags) |
7772 | { |
7824 | { |
7773 | struct drm_i915_private *dev_priv = dev->dev_private; |
7825 | struct drm_i915_private *dev_priv = dev->dev_private; |
7774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7826 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7775 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7827 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
7776 | uint32_t pf, pipesrc; |
7828 | uint32_t pf, pipesrc; |
7777 | int ret; |
7829 | int ret; |
7778 | 7830 | ||
7779 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7831 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7780 | if (ret) |
7832 | if (ret) |
7781 | goto err; |
7833 | goto err; |
7782 | 7834 | ||
7783 | ret = intel_ring_begin(ring, 4); |
7835 | ret = intel_ring_begin(ring, 4); |
7784 | if (ret) |
7836 | if (ret) |
7785 | goto err_unpin; |
7837 | goto err_unpin; |
7786 | 7838 | ||
7787 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7839 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7788 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7840 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
7789 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
7841 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
7790 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7842 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7791 | 7843 | ||
7792 | /* Contrary to the suggestions in the documentation, |
7844 | /* Contrary to the suggestions in the documentation, |
7793 | * "Enable Panel Fitter" does not seem to be required when page |
7845 | * "Enable Panel Fitter" does not seem to be required when page |
7794 | * flipping with a non-native mode, and worse causes a normal |
7846 | * flipping with a non-native mode, and worse causes a normal |
7795 | * modeset to fail. |
7847 | * modeset to fail. |
7796 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
7848 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
7797 | */ |
7849 | */ |
7798 | pf = 0; |
7850 | pf = 0; |
7799 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7851 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
7800 | intel_ring_emit(ring, pf | pipesrc); |
7852 | intel_ring_emit(ring, pf | pipesrc); |
7801 | 7853 | ||
7802 | intel_mark_page_flip_active(intel_crtc); |
7854 | intel_mark_page_flip_active(intel_crtc); |
7803 | intel_ring_advance(ring); |
7855 | intel_ring_advance(ring); |
7804 | return 0; |
7856 | return 0; |
7805 | 7857 | ||
7806 | err_unpin: |
7858 | err_unpin: |
7807 | intel_unpin_fb_obj(obj); |
7859 | intel_unpin_fb_obj(obj); |
7808 | err: |
7860 | err: |
7809 | return ret; |
7861 | return ret; |
7810 | } |
7862 | } |
7811 | 7863 | ||
7812 | static int intel_gen7_queue_flip(struct drm_device *dev, |
7864 | static int intel_gen7_queue_flip(struct drm_device *dev, |
7813 | struct drm_crtc *crtc, |
7865 | struct drm_crtc *crtc, |
7814 | struct drm_framebuffer *fb, |
7866 | struct drm_framebuffer *fb, |
7815 | struct drm_i915_gem_object *obj, |
7867 | struct drm_i915_gem_object *obj, |
7816 | uint32_t flags) |
7868 | uint32_t flags) |
7817 | { |
7869 | { |
7818 | struct drm_i915_private *dev_priv = dev->dev_private; |
7870 | struct drm_i915_private *dev_priv = dev->dev_private; |
7819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7820 | struct intel_ring_buffer *ring; |
7872 | struct intel_ring_buffer *ring; |
7821 | uint32_t plane_bit = 0; |
7873 | uint32_t plane_bit = 0; |
7822 | int len, ret; |
7874 | int len, ret; |
7823 | 7875 | ||
7824 | ring = obj->ring; |
7876 | ring = obj->ring; |
7825 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
7877 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
7826 | ring = &dev_priv->ring[BCS]; |
7878 | ring = &dev_priv->ring[BCS]; |
7827 | 7879 | ||
7828 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7880 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
7829 | if (ret) |
7881 | if (ret) |
7830 | goto err; |
7882 | goto err; |
7831 | 7883 | ||
7832 | switch(intel_crtc->plane) { |
7884 | switch(intel_crtc->plane) { |
7833 | case PLANE_A: |
7885 | case PLANE_A: |
7834 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
7886 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
7835 | break; |
7887 | break; |
7836 | case PLANE_B: |
7888 | case PLANE_B: |
7837 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
7889 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
7838 | break; |
7890 | break; |
7839 | case PLANE_C: |
7891 | case PLANE_C: |
7840 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
7892 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
7841 | break; |
7893 | break; |
7842 | default: |
7894 | default: |
7843 | WARN_ONCE(1, "unknown plane in flip command\n"); |
7895 | WARN_ONCE(1, "unknown plane in flip command\n"); |
7844 | ret = -ENODEV; |
7896 | ret = -ENODEV; |
7845 | goto err_unpin; |
7897 | goto err_unpin; |
7846 | } |
7898 | } |
7847 | 7899 | ||
7848 | len = 4; |
7900 | len = 4; |
7849 | if (ring->id == RCS) |
7901 | if (ring->id == RCS) |
7850 | len += 6; |
7902 | len += 6; |
7851 | 7903 | ||
7852 | ret = intel_ring_begin(ring, len); |
7904 | ret = intel_ring_begin(ring, len); |
7853 | if (ret) |
7905 | if (ret) |
7854 | goto err_unpin; |
7906 | goto err_unpin; |
7855 | 7907 | ||
7856 | /* Unmask the flip-done completion message. Note that the bspec says that |
7908 | /* Unmask the flip-done completion message. Note that the bspec says that |
7857 | * we should do this for both the BCS and RCS, and that we must not unmask |
7909 | * we should do this for both the BCS and RCS, and that we must not unmask |
7858 | * more than one flip event at any time (or ensure that one flip message |
7910 | * more than one flip event at any time (or ensure that one flip message |
7859 | * can be sent by waiting for flip-done prior to queueing new flips). |
7911 | * can be sent by waiting for flip-done prior to queueing new flips). |
7860 | * Experimentation says that BCS works despite DERRMR masking all |
7912 | * Experimentation says that BCS works despite DERRMR masking all |
7861 | * flip-done completion events and that unmasking all planes at once |
7913 | * flip-done completion events and that unmasking all planes at once |
7862 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
7914 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
7863 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
7915 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
7864 | */ |
7916 | */ |
7865 | if (ring->id == RCS) { |
7917 | if (ring->id == RCS) { |
7866 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
7918 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
7867 | intel_ring_emit(ring, DERRMR); |
7919 | intel_ring_emit(ring, DERRMR); |
7868 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
7920 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
7869 | DERRMR_PIPEB_PRI_FLIP_DONE | |
7921 | DERRMR_PIPEB_PRI_FLIP_DONE | |
7870 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
7922 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
7871 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); |
7923 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); |
7872 | intel_ring_emit(ring, DERRMR); |
7924 | intel_ring_emit(ring, DERRMR); |
7873 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
7925 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
7874 | } |
7926 | } |
7875 | 7927 | ||
7876 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
7928 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
7877 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7929 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7878 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7930 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7879 | intel_ring_emit(ring, (MI_NOOP)); |
7931 | intel_ring_emit(ring, (MI_NOOP)); |
7880 | 7932 | ||
7881 | intel_mark_page_flip_active(intel_crtc); |
7933 | intel_mark_page_flip_active(intel_crtc); |
7882 | intel_ring_advance(ring); |
7934 | intel_ring_advance(ring); |
7883 | return 0; |
7935 | return 0; |
7884 | 7936 | ||
7885 | err_unpin: |
7937 | err_unpin: |
7886 | intel_unpin_fb_obj(obj); |
7938 | intel_unpin_fb_obj(obj); |
7887 | err: |
7939 | err: |
7888 | return ret; |
7940 | return ret; |
7889 | } |
7941 | } |
7890 | 7942 | ||
7891 | static int intel_default_queue_flip(struct drm_device *dev, |
7943 | static int intel_default_queue_flip(struct drm_device *dev, |
7892 | struct drm_crtc *crtc, |
7944 | struct drm_crtc *crtc, |
7893 | struct drm_framebuffer *fb, |
7945 | struct drm_framebuffer *fb, |
7894 | struct drm_i915_gem_object *obj, |
7946 | struct drm_i915_gem_object *obj, |
7895 | uint32_t flags) |
7947 | uint32_t flags) |
7896 | { |
7948 | { |
7897 | return -ENODEV; |
7949 | return -ENODEV; |
7898 | } |
7950 | } |
7899 | 7951 | ||
7900 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7952 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7901 | struct drm_framebuffer *fb, |
7953 | struct drm_framebuffer *fb, |
7902 | struct drm_pending_vblank_event *event, |
7954 | struct drm_pending_vblank_event *event, |
7903 | uint32_t page_flip_flags) |
7955 | uint32_t page_flip_flags) |
7904 | { |
7956 | { |
7905 | struct drm_device *dev = crtc->dev; |
7957 | struct drm_device *dev = crtc->dev; |
7906 | struct drm_i915_private *dev_priv = dev->dev_private; |
7958 | struct drm_i915_private *dev_priv = dev->dev_private; |
7907 | struct drm_framebuffer *old_fb = crtc->fb; |
7959 | struct drm_framebuffer *old_fb = crtc->fb; |
7908 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
7960 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
7909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7910 | struct intel_unpin_work *work; |
7962 | struct intel_unpin_work *work; |
7911 | unsigned long flags; |
7963 | unsigned long flags; |
7912 | int ret; |
7964 | int ret; |
7913 | 7965 | ||
7914 | /* Can't change pixel format via MI display flips. */ |
7966 | /* Can't change pixel format via MI display flips. */ |
7915 | if (fb->pixel_format != crtc->fb->pixel_format) |
7967 | if (fb->pixel_format != crtc->fb->pixel_format) |
7916 | return -EINVAL; |
7968 | return -EINVAL; |
7917 | 7969 | ||
7918 | /* |
7970 | /* |
7919 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
7971 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
7920 | * Note that pitch changes could also affect these register. |
7972 | * Note that pitch changes could also affect these register. |
7921 | */ |
7973 | */ |
7922 | if (INTEL_INFO(dev)->gen > 3 && |
7974 | if (INTEL_INFO(dev)->gen > 3 && |
7923 | (fb->offsets[0] != crtc->fb->offsets[0] || |
7975 | (fb->offsets[0] != crtc->fb->offsets[0] || |
7924 | fb->pitches[0] != crtc->fb->pitches[0])) |
7976 | fb->pitches[0] != crtc->fb->pitches[0])) |
7925 | return -EINVAL; |
7977 | return -EINVAL; |
7926 | 7978 | ||
7927 | work = kzalloc(sizeof *work, GFP_KERNEL); |
7979 | work = kzalloc(sizeof *work, GFP_KERNEL); |
7928 | if (work == NULL) |
7980 | if (work == NULL) |
7929 | return -ENOMEM; |
7981 | return -ENOMEM; |
7930 | 7982 | ||
7931 | work->event = event; |
7983 | work->event = event; |
7932 | work->crtc = crtc; |
7984 | work->crtc = crtc; |
7933 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
7985 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
7934 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7986 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7935 | 7987 | ||
7936 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7988 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7937 | if (ret) |
7989 | if (ret) |
7938 | goto free_work; |
7990 | goto free_work; |
7939 | 7991 | ||
7940 | /* We borrow the event spin lock for protecting unpin_work */ |
7992 | /* We borrow the event spin lock for protecting unpin_work */ |
7941 | spin_lock_irqsave(&dev->event_lock, flags); |
7993 | spin_lock_irqsave(&dev->event_lock, flags); |
7942 | if (intel_crtc->unpin_work) { |
7994 | if (intel_crtc->unpin_work) { |
7943 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7995 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7944 | kfree(work); |
7996 | kfree(work); |
7945 | drm_vblank_put(dev, intel_crtc->pipe); |
7997 | drm_vblank_put(dev, intel_crtc->pipe); |
7946 | 7998 | ||
7947 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
7999 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
7948 | return -EBUSY; |
8000 | return -EBUSY; |
7949 | } |
8001 | } |
7950 | intel_crtc->unpin_work = work; |
8002 | intel_crtc->unpin_work = work; |
7951 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8003 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7952 | 8004 | ||
7953 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8005 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
7954 | flush_workqueue(dev_priv->wq); |
8006 | flush_workqueue(dev_priv->wq); |
7955 | 8007 | ||
7956 | ret = i915_mutex_lock_interruptible(dev); |
8008 | ret = i915_mutex_lock_interruptible(dev); |
7957 | if (ret) |
8009 | if (ret) |
7958 | goto cleanup; |
8010 | goto cleanup; |
7959 | 8011 | ||
7960 | /* Reference the objects for the scheduled work. */ |
8012 | /* Reference the objects for the scheduled work. */ |
7961 | drm_gem_object_reference(&work->old_fb_obj->base); |
8013 | drm_gem_object_reference(&work->old_fb_obj->base); |
7962 | drm_gem_object_reference(&obj->base); |
8014 | drm_gem_object_reference(&obj->base); |
7963 | 8015 | ||
7964 | crtc->fb = fb; |
8016 | crtc->fb = fb; |
7965 | 8017 | ||
7966 | work->pending_flip_obj = obj; |
8018 | work->pending_flip_obj = obj; |
7967 | 8019 | ||
7968 | work->enable_stall_check = true; |
8020 | work->enable_stall_check = true; |
7969 | 8021 | ||
7970 | atomic_inc(&intel_crtc->unpin_work_count); |
8022 | atomic_inc(&intel_crtc->unpin_work_count); |
7971 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
8023 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
7972 | 8024 | ||
7973 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8025 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
7974 | if (ret) |
8026 | if (ret) |
7975 | goto cleanup_pending; |
8027 | goto cleanup_pending; |
7976 | 8028 | ||
7977 | intel_disable_fbc(dev); |
8029 | intel_disable_fbc(dev); |
7978 | intel_mark_fb_busy(obj, NULL); |
8030 | intel_mark_fb_busy(obj, NULL); |
7979 | mutex_unlock(&dev->struct_mutex); |
8031 | mutex_unlock(&dev->struct_mutex); |
7980 | 8032 | ||
7981 | trace_i915_flip_request(intel_crtc->plane, obj); |
8033 | trace_i915_flip_request(intel_crtc->plane, obj); |
7982 | 8034 | ||
7983 | return 0; |
8035 | return 0; |
7984 | 8036 | ||
7985 | cleanup_pending: |
8037 | cleanup_pending: |
7986 | atomic_dec(&intel_crtc->unpin_work_count); |
8038 | atomic_dec(&intel_crtc->unpin_work_count); |
7987 | crtc->fb = old_fb; |
8039 | crtc->fb = old_fb; |
7988 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8040 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7989 | drm_gem_object_unreference(&obj->base); |
8041 | drm_gem_object_unreference(&obj->base); |
7990 | mutex_unlock(&dev->struct_mutex); |
8042 | mutex_unlock(&dev->struct_mutex); |
7991 | 8043 | ||
7992 | cleanup: |
8044 | cleanup: |
7993 | spin_lock_irqsave(&dev->event_lock, flags); |
8045 | spin_lock_irqsave(&dev->event_lock, flags); |
7994 | intel_crtc->unpin_work = NULL; |
8046 | intel_crtc->unpin_work = NULL; |
7995 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8047 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7996 | 8048 | ||
7997 | drm_vblank_put(dev, intel_crtc->pipe); |
8049 | drm_vblank_put(dev, intel_crtc->pipe); |
7998 | free_work: |
8050 | free_work: |
7999 | kfree(work); |
8051 | kfree(work); |
8000 | 8052 | ||
8001 | return ret; |
8053 | return ret; |
8002 | } |
8054 | } |
8003 | #endif |
8055 | #endif |
8004 | 8056 | ||
8005 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
8057 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
8006 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8058 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8007 | .load_lut = intel_crtc_load_lut, |
8059 | .load_lut = intel_crtc_load_lut, |
8008 | }; |
8060 | }; |
8009 | 8061 | ||
8010 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8062 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8011 | struct drm_crtc *crtc) |
8063 | struct drm_crtc *crtc) |
8012 | { |
8064 | { |
8013 | struct drm_device *dev; |
8065 | struct drm_device *dev; |
8014 | struct drm_crtc *tmp; |
8066 | struct drm_crtc *tmp; |
8015 | int crtc_mask = 1; |
8067 | int crtc_mask = 1; |
8016 | 8068 | ||
8017 | WARN(!crtc, "checking null crtc?\n"); |
8069 | WARN(!crtc, "checking null crtc?\n"); |
8018 | 8070 | ||
8019 | dev = crtc->dev; |
8071 | dev = crtc->dev; |
8020 | 8072 | ||
8021 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8073 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8022 | if (tmp == crtc) |
8074 | if (tmp == crtc) |
8023 | break; |
8075 | break; |
8024 | crtc_mask <<= 1; |
8076 | crtc_mask <<= 1; |
8025 | } |
8077 | } |
8026 | 8078 | ||
8027 | if (encoder->possible_crtcs & crtc_mask) |
8079 | if (encoder->possible_crtcs & crtc_mask) |
8028 | return true; |
8080 | return true; |
8029 | return false; |
8081 | return false; |
8030 | } |
8082 | } |
8031 | 8083 | ||
8032 | /** |
8084 | /** |
8033 | * intel_modeset_update_staged_output_state |
8085 | * intel_modeset_update_staged_output_state |
8034 | * |
8086 | * |
8035 | * Updates the staged output configuration state, e.g. after we've read out the |
8087 | * Updates the staged output configuration state, e.g. after we've read out the |
8036 | * current hw state. |
8088 | * current hw state. |
8037 | */ |
8089 | */ |
8038 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
8090 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
8039 | { |
8091 | { |
8040 | struct intel_encoder *encoder; |
8092 | struct intel_encoder *encoder; |
8041 | struct intel_connector *connector; |
8093 | struct intel_connector *connector; |
8042 | 8094 | ||
8043 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8095 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8044 | base.head) { |
8096 | base.head) { |
8045 | connector->new_encoder = |
8097 | connector->new_encoder = |
8046 | to_intel_encoder(connector->base.encoder); |
8098 | to_intel_encoder(connector->base.encoder); |
8047 | } |
8099 | } |
8048 | 8100 | ||
8049 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8101 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8050 | base.head) { |
8102 | base.head) { |
8051 | encoder->new_crtc = |
8103 | encoder->new_crtc = |
8052 | to_intel_crtc(encoder->base.crtc); |
8104 | to_intel_crtc(encoder->base.crtc); |
8053 | } |
8105 | } |
8054 | } |
8106 | } |
8055 | 8107 | ||
8056 | /** |
8108 | /** |
8057 | * intel_modeset_commit_output_state |
8109 | * intel_modeset_commit_output_state |
8058 | * |
8110 | * |
8059 | * This function copies the stage display pipe configuration to the real one. |
8111 | * This function copies the stage display pipe configuration to the real one. |
8060 | */ |
8112 | */ |
8061 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
8113 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
8062 | { |
8114 | { |
8063 | struct intel_encoder *encoder; |
8115 | struct intel_encoder *encoder; |
8064 | struct intel_connector *connector; |
8116 | struct intel_connector *connector; |
8065 | 8117 | ||
8066 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8118 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8067 | base.head) { |
8119 | base.head) { |
8068 | connector->base.encoder = &connector->new_encoder->base; |
8120 | connector->base.encoder = &connector->new_encoder->base; |
8069 | } |
8121 | } |
8070 | 8122 | ||
8071 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8123 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8072 | base.head) { |
8124 | base.head) { |
8073 | encoder->base.crtc = &encoder->new_crtc->base; |
8125 | encoder->base.crtc = &encoder->new_crtc->base; |
8074 | } |
8126 | } |
8075 | } |
8127 | } |
8076 | 8128 | ||
8077 | static void |
8129 | static void |
8078 | connected_sink_compute_bpp(struct intel_connector * connector, |
8130 | connected_sink_compute_bpp(struct intel_connector * connector, |
8079 | struct intel_crtc_config *pipe_config) |
8131 | struct intel_crtc_config *pipe_config) |
8080 | { |
8132 | { |
8081 | int bpp = pipe_config->pipe_bpp; |
8133 | int bpp = pipe_config->pipe_bpp; |
8082 | 8134 | ||
8083 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
8135 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
8084 | connector->base.base.id, |
8136 | connector->base.base.id, |
8085 | drm_get_connector_name(&connector->base)); |
8137 | drm_get_connector_name(&connector->base)); |
8086 | 8138 | ||
8087 | /* Don't use an invalid EDID bpc value */ |
8139 | /* Don't use an invalid EDID bpc value */ |
8088 | if (connector->base.display_info.bpc && |
8140 | if (connector->base.display_info.bpc && |
8089 | connector->base.display_info.bpc * 3 < bpp) { |
8141 | connector->base.display_info.bpc * 3 < bpp) { |
8090 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
8142 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
8091 | bpp, connector->base.display_info.bpc*3); |
8143 | bpp, connector->base.display_info.bpc*3); |
8092 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
8144 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
8093 | } |
8145 | } |
8094 | 8146 | ||
8095 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
8147 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
8096 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
8148 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
8097 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
8149 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
8098 | bpp); |
8150 | bpp); |
8099 | pipe_config->pipe_bpp = 24; |
8151 | pipe_config->pipe_bpp = 24; |
8100 | } |
8152 | } |
8101 | } |
8153 | } |
8102 | 8154 | ||
8103 | static int |
8155 | static int |
8104 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8156 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8105 | struct drm_framebuffer *fb, |
8157 | struct drm_framebuffer *fb, |
8106 | struct intel_crtc_config *pipe_config) |
8158 | struct intel_crtc_config *pipe_config) |
8107 | { |
8159 | { |
8108 | struct drm_device *dev = crtc->base.dev; |
8160 | struct drm_device *dev = crtc->base.dev; |
8109 | struct intel_connector *connector; |
8161 | struct intel_connector *connector; |
8110 | int bpp; |
8162 | int bpp; |
8111 | 8163 | ||
8112 | switch (fb->pixel_format) { |
8164 | switch (fb->pixel_format) { |
8113 | case DRM_FORMAT_C8: |
8165 | case DRM_FORMAT_C8: |
8114 | bpp = 8*3; /* since we go through a colormap */ |
8166 | bpp = 8*3; /* since we go through a colormap */ |
8115 | break; |
8167 | break; |
8116 | case DRM_FORMAT_XRGB1555: |
8168 | case DRM_FORMAT_XRGB1555: |
8117 | case DRM_FORMAT_ARGB1555: |
8169 | case DRM_FORMAT_ARGB1555: |
8118 | /* checked in intel_framebuffer_init already */ |
8170 | /* checked in intel_framebuffer_init already */ |
8119 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
8171 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
8120 | return -EINVAL; |
8172 | return -EINVAL; |
8121 | case DRM_FORMAT_RGB565: |
8173 | case DRM_FORMAT_RGB565: |
8122 | bpp = 6*3; /* min is 18bpp */ |
8174 | bpp = 6*3; /* min is 18bpp */ |
8123 | break; |
8175 | break; |
8124 | case DRM_FORMAT_XBGR8888: |
8176 | case DRM_FORMAT_XBGR8888: |
8125 | case DRM_FORMAT_ABGR8888: |
8177 | case DRM_FORMAT_ABGR8888: |
8126 | /* checked in intel_framebuffer_init already */ |
8178 | /* checked in intel_framebuffer_init already */ |
8127 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8179 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8128 | return -EINVAL; |
8180 | return -EINVAL; |
8129 | case DRM_FORMAT_XRGB8888: |
8181 | case DRM_FORMAT_XRGB8888: |
8130 | case DRM_FORMAT_ARGB8888: |
8182 | case DRM_FORMAT_ARGB8888: |
8131 | bpp = 8*3; |
8183 | bpp = 8*3; |
8132 | break; |
8184 | break; |
8133 | case DRM_FORMAT_XRGB2101010: |
8185 | case DRM_FORMAT_XRGB2101010: |
8134 | case DRM_FORMAT_ARGB2101010: |
8186 | case DRM_FORMAT_ARGB2101010: |
8135 | case DRM_FORMAT_XBGR2101010: |
8187 | case DRM_FORMAT_XBGR2101010: |
8136 | case DRM_FORMAT_ABGR2101010: |
8188 | case DRM_FORMAT_ABGR2101010: |
8137 | /* checked in intel_framebuffer_init already */ |
8189 | /* checked in intel_framebuffer_init already */ |
8138 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8190 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
8139 | return -EINVAL; |
8191 | return -EINVAL; |
8140 | bpp = 10*3; |
8192 | bpp = 10*3; |
8141 | break; |
8193 | break; |
8142 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
8194 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
8143 | default: |
8195 | default: |
8144 | DRM_DEBUG_KMS("unsupported depth\n"); |
8196 | DRM_DEBUG_KMS("unsupported depth\n"); |
8145 | return -EINVAL; |
8197 | return -EINVAL; |
8146 | } |
8198 | } |
8147 | 8199 | ||
8148 | pipe_config->pipe_bpp = bpp; |
8200 | pipe_config->pipe_bpp = bpp; |
8149 | 8201 | ||
8150 | /* Clamp display bpp to EDID value */ |
8202 | /* Clamp display bpp to EDID value */ |
8151 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8203 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8152 | base.head) { |
8204 | base.head) { |
8153 | if (!connector->new_encoder || |
8205 | if (!connector->new_encoder || |
8154 | connector->new_encoder->new_crtc != crtc) |
8206 | connector->new_encoder->new_crtc != crtc) |
8155 | continue; |
8207 | continue; |
8156 | 8208 | ||
8157 | connected_sink_compute_bpp(connector, pipe_config); |
8209 | connected_sink_compute_bpp(connector, pipe_config); |
8158 | } |
8210 | } |
8159 | 8211 | ||
8160 | return bpp; |
8212 | return bpp; |
8161 | } |
8213 | } |
8162 | 8214 | ||
8163 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8215 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8164 | struct intel_crtc_config *pipe_config, |
8216 | struct intel_crtc_config *pipe_config, |
8165 | const char *context) |
8217 | const char *context) |
8166 | { |
8218 | { |
8167 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
8219 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
8168 | context, pipe_name(crtc->pipe)); |
8220 | context, pipe_name(crtc->pipe)); |
8169 | 8221 | ||
8170 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
8222 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
8171 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
8223 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
8172 | pipe_config->pipe_bpp, pipe_config->dither); |
8224 | pipe_config->pipe_bpp, pipe_config->dither); |
8173 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8225 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8174 | pipe_config->has_pch_encoder, |
8226 | pipe_config->has_pch_encoder, |
8175 | pipe_config->fdi_lanes, |
8227 | pipe_config->fdi_lanes, |
8176 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
8228 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
8177 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
8229 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
8178 | pipe_config->fdi_m_n.tu); |
8230 | pipe_config->fdi_m_n.tu); |
8179 | DRM_DEBUG_KMS("requested mode:\n"); |
8231 | DRM_DEBUG_KMS("requested mode:\n"); |
8180 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
8232 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
8181 | DRM_DEBUG_KMS("adjusted mode:\n"); |
8233 | DRM_DEBUG_KMS("adjusted mode:\n"); |
8182 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
8234 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
8183 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8235 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8184 | pipe_config->gmch_pfit.control, |
8236 | pipe_config->gmch_pfit.control, |
8185 | pipe_config->gmch_pfit.pgm_ratios, |
8237 | pipe_config->gmch_pfit.pgm_ratios, |
8186 | pipe_config->gmch_pfit.lvds_border_bits); |
8238 | pipe_config->gmch_pfit.lvds_border_bits); |
8187 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
8239 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
8188 | pipe_config->pch_pfit.pos, |
8240 | pipe_config->pch_pfit.pos, |
8189 | pipe_config->pch_pfit.size, |
8241 | pipe_config->pch_pfit.size, |
8190 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8242 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
8191 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
8243 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
8192 | } |
8244 | } |
8193 | 8245 | ||
8194 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8246 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8195 | { |
8247 | { |
8196 | int num_encoders = 0; |
8248 | int num_encoders = 0; |
8197 | bool uncloneable_encoders = false; |
8249 | bool uncloneable_encoders = false; |
8198 | struct intel_encoder *encoder; |
8250 | struct intel_encoder *encoder; |
8199 | 8251 | ||
8200 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, |
8252 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, |
8201 | base.head) { |
8253 | base.head) { |
8202 | if (&encoder->new_crtc->base != crtc) |
8254 | if (&encoder->new_crtc->base != crtc) |
8203 | continue; |
8255 | continue; |
8204 | 8256 | ||
8205 | num_encoders++; |
8257 | num_encoders++; |
8206 | if (!encoder->cloneable) |
8258 | if (!encoder->cloneable) |
8207 | uncloneable_encoders = true; |
8259 | uncloneable_encoders = true; |
8208 | } |
8260 | } |
8209 | 8261 | ||
8210 | return !(num_encoders > 1 && uncloneable_encoders); |
8262 | return !(num_encoders > 1 && uncloneable_encoders); |
8211 | } |
8263 | } |
8212 | 8264 | ||
8213 | static struct intel_crtc_config * |
8265 | static struct intel_crtc_config * |
8214 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
8266 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
8215 | struct drm_framebuffer *fb, |
8267 | struct drm_framebuffer *fb, |
8216 | struct drm_display_mode *mode) |
8268 | struct drm_display_mode *mode) |
8217 | { |
8269 | { |
8218 | struct drm_device *dev = crtc->dev; |
8270 | struct drm_device *dev = crtc->dev; |
8219 | struct intel_encoder *encoder; |
8271 | struct intel_encoder *encoder; |
8220 | struct intel_crtc_config *pipe_config; |
8272 | struct intel_crtc_config *pipe_config; |
8221 | int plane_bpp, ret = -EINVAL; |
8273 | int plane_bpp, ret = -EINVAL; |
8222 | bool retry = true; |
8274 | bool retry = true; |
8223 | 8275 | ||
8224 | if (!check_encoder_cloning(crtc)) { |
8276 | if (!check_encoder_cloning(crtc)) { |
8225 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
8277 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
8226 | return ERR_PTR(-EINVAL); |
8278 | return ERR_PTR(-EINVAL); |
8227 | } |
8279 | } |
8228 | 8280 | ||
8229 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8281 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8230 | if (!pipe_config) |
8282 | if (!pipe_config) |
8231 | return ERR_PTR(-ENOMEM); |
8283 | return ERR_PTR(-ENOMEM); |
8232 | 8284 | ||
8233 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8285 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8234 | drm_mode_copy(&pipe_config->requested_mode, mode); |
8286 | drm_mode_copy(&pipe_config->requested_mode, mode); |
8235 | pipe_config->cpu_transcoder = |
8287 | pipe_config->cpu_transcoder = |
8236 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
8288 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
8237 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8289 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8238 | 8290 | ||
8239 | /* |
8291 | /* |
8240 | * Sanitize sync polarity flags based on requested ones. If neither |
8292 | * Sanitize sync polarity flags based on requested ones. If neither |
8241 | * positive or negative polarity is requested, treat this as meaning |
8293 | * positive or negative polarity is requested, treat this as meaning |
8242 | * negative polarity. |
8294 | * negative polarity. |
8243 | */ |
8295 | */ |
8244 | if (!(pipe_config->adjusted_mode.flags & |
8296 | if (!(pipe_config->adjusted_mode.flags & |
8245 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
8297 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
8246 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
8298 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
8247 | 8299 | ||
8248 | if (!(pipe_config->adjusted_mode.flags & |
8300 | if (!(pipe_config->adjusted_mode.flags & |
8249 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
8301 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
8250 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
8302 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
8251 | 8303 | ||
8252 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8304 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8253 | * plane pixel format and any sink constraints into account. Returns the |
8305 | * plane pixel format and any sink constraints into account. Returns the |
8254 | * source plane bpp so that dithering can be selected on mismatches |
8306 | * source plane bpp so that dithering can be selected on mismatches |
8255 | * after encoders and crtc also have had their say. */ |
8307 | * after encoders and crtc also have had their say. */ |
8256 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
8308 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
8257 | fb, pipe_config); |
8309 | fb, pipe_config); |
8258 | if (plane_bpp < 0) |
8310 | if (plane_bpp < 0) |
8259 | goto fail; |
8311 | goto fail; |
8260 | 8312 | ||
8261 | encoder_retry: |
8313 | encoder_retry: |
8262 | /* Ensure the port clock defaults are reset when retrying. */ |
8314 | /* Ensure the port clock defaults are reset when retrying. */ |
8263 | pipe_config->port_clock = 0; |
8315 | pipe_config->port_clock = 0; |
8264 | pipe_config->pixel_multiplier = 1; |
8316 | pipe_config->pixel_multiplier = 1; |
8265 | 8317 | ||
8266 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8318 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8267 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); |
8319 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); |
8268 | 8320 | ||
8269 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8321 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8270 | * adjust it according to limitations or connector properties, and also |
8322 | * adjust it according to limitations or connector properties, and also |
8271 | * a chance to reject the mode entirely. |
8323 | * a chance to reject the mode entirely. |
8272 | */ |
8324 | */ |
8273 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8325 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8274 | base.head) { |
8326 | base.head) { |
8275 | 8327 | ||
8276 | if (&encoder->new_crtc->base != crtc) |
8328 | if (&encoder->new_crtc->base != crtc) |
8277 | continue; |
8329 | continue; |
8278 | 8330 | ||
8279 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8331 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8280 | DRM_DEBUG_KMS("Encoder config failure\n"); |
8332 | DRM_DEBUG_KMS("Encoder config failure\n"); |
8281 | goto fail; |
8333 | goto fail; |
8282 | } |
8334 | } |
8283 | } |
8335 | } |
8284 | 8336 | ||
8285 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8337 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8286 | * done afterwards in case the encoder adjusts the mode. */ |
8338 | * done afterwards in case the encoder adjusts the mode. */ |
8287 | if (!pipe_config->port_clock) |
8339 | if (!pipe_config->port_clock) |
8288 | pipe_config->port_clock = pipe_config->adjusted_mode.clock; |
8340 | pipe_config->port_clock = pipe_config->adjusted_mode.clock; |
8289 | 8341 | ||
8290 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8342 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8291 | if (ret < 0) { |
8343 | if (ret < 0) { |
8292 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8344 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8293 | goto fail; |
8345 | goto fail; |
8294 | } |
8346 | } |
8295 | 8347 | ||
8296 | if (ret == RETRY) { |
8348 | if (ret == RETRY) { |
8297 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
8349 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
8298 | ret = -EINVAL; |
8350 | ret = -EINVAL; |
8299 | goto fail; |
8351 | goto fail; |
8300 | } |
8352 | } |
8301 | 8353 | ||
8302 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
8354 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
8303 | retry = false; |
8355 | retry = false; |
8304 | goto encoder_retry; |
8356 | goto encoder_retry; |
8305 | } |
8357 | } |
8306 | 8358 | ||
8307 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8359 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8308 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
8360 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
8309 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
8361 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
8310 | 8362 | ||
8311 | return pipe_config; |
8363 | return pipe_config; |
8312 | fail: |
8364 | fail: |
8313 | kfree(pipe_config); |
8365 | kfree(pipe_config); |
8314 | return ERR_PTR(ret); |
8366 | return ERR_PTR(ret); |
8315 | } |
8367 | } |
8316 | 8368 | ||
8317 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8369 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8318 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
8370 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
8319 | static void |
8371 | static void |
8320 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
8372 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
8321 | unsigned *prepare_pipes, unsigned *disable_pipes) |
8373 | unsigned *prepare_pipes, unsigned *disable_pipes) |
8322 | { |
8374 | { |
8323 | struct intel_crtc *intel_crtc; |
8375 | struct intel_crtc *intel_crtc; |
8324 | struct drm_device *dev = crtc->dev; |
8376 | struct drm_device *dev = crtc->dev; |
8325 | struct intel_encoder *encoder; |
8377 | struct intel_encoder *encoder; |
8326 | struct intel_connector *connector; |
8378 | struct intel_connector *connector; |
8327 | struct drm_crtc *tmp_crtc; |
8379 | struct drm_crtc *tmp_crtc; |
8328 | 8380 | ||
8329 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
8381 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
8330 | 8382 | ||
8331 | /* Check which crtcs have changed outputs connected to them, these need |
8383 | /* Check which crtcs have changed outputs connected to them, these need |
8332 | * to be part of the prepare_pipes mask. We don't (yet) support global |
8384 | * to be part of the prepare_pipes mask. We don't (yet) support global |
8333 | * modeset across multiple crtcs, so modeset_pipes will only have one |
8385 | * modeset across multiple crtcs, so modeset_pipes will only have one |
8334 | * bit set at most. */ |
8386 | * bit set at most. */ |
8335 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8387 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8336 | base.head) { |
8388 | base.head) { |
8337 | if (connector->base.encoder == &connector->new_encoder->base) |
8389 | if (connector->base.encoder == &connector->new_encoder->base) |
8338 | continue; |
8390 | continue; |
8339 | 8391 | ||
8340 | if (connector->base.encoder) { |
8392 | if (connector->base.encoder) { |
8341 | tmp_crtc = connector->base.encoder->crtc; |
8393 | tmp_crtc = connector->base.encoder->crtc; |
8342 | 8394 | ||
8343 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8395 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8344 | } |
8396 | } |
8345 | 8397 | ||
8346 | if (connector->new_encoder) |
8398 | if (connector->new_encoder) |
8347 | *prepare_pipes |= |
8399 | *prepare_pipes |= |
8348 | 1 << connector->new_encoder->new_crtc->pipe; |
8400 | 1 << connector->new_encoder->new_crtc->pipe; |
8349 | } |
8401 | } |
8350 | 8402 | ||
8351 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8403 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8352 | base.head) { |
8404 | base.head) { |
8353 | if (encoder->base.crtc == &encoder->new_crtc->base) |
8405 | if (encoder->base.crtc == &encoder->new_crtc->base) |
8354 | continue; |
8406 | continue; |
8355 | 8407 | ||
8356 | if (encoder->base.crtc) { |
8408 | if (encoder->base.crtc) { |
8357 | tmp_crtc = encoder->base.crtc; |
8409 | tmp_crtc = encoder->base.crtc; |
8358 | 8410 | ||
8359 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8411 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
8360 | } |
8412 | } |
8361 | 8413 | ||
8362 | if (encoder->new_crtc) |
8414 | if (encoder->new_crtc) |
8363 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
8415 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
8364 | } |
8416 | } |
8365 | 8417 | ||
8366 | /* Check for any pipes that will be fully disabled ... */ |
8418 | /* Check for any pipes that will be fully disabled ... */ |
8367 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8419 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8368 | base.head) { |
8420 | base.head) { |
8369 | bool used = false; |
8421 | bool used = false; |
8370 | 8422 | ||
8371 | /* Don't try to disable disabled crtcs. */ |
8423 | /* Don't try to disable disabled crtcs. */ |
8372 | if (!intel_crtc->base.enabled) |
8424 | if (!intel_crtc->base.enabled) |
8373 | continue; |
8425 | continue; |
8374 | 8426 | ||
8375 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8427 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8376 | base.head) { |
8428 | base.head) { |
8377 | if (encoder->new_crtc == intel_crtc) |
8429 | if (encoder->new_crtc == intel_crtc) |
8378 | used = true; |
8430 | used = true; |
8379 | } |
8431 | } |
8380 | 8432 | ||
8381 | if (!used) |
8433 | if (!used) |
8382 | *disable_pipes |= 1 << intel_crtc->pipe; |
8434 | *disable_pipes |= 1 << intel_crtc->pipe; |
8383 | } |
8435 | } |
8384 | 8436 | ||
8385 | 8437 | ||
8386 | /* set_mode is also used to update properties on life display pipes. */ |
8438 | /* set_mode is also used to update properties on life display pipes. */ |
8387 | intel_crtc = to_intel_crtc(crtc); |
8439 | intel_crtc = to_intel_crtc(crtc); |
8388 | if (crtc->enabled) |
8440 | if (crtc->enabled) |
8389 | *prepare_pipes |= 1 << intel_crtc->pipe; |
8441 | *prepare_pipes |= 1 << intel_crtc->pipe; |
8390 | 8442 | ||
8391 | /* |
8443 | /* |
8392 | * For simplicity do a full modeset on any pipe where the output routing |
8444 | * For simplicity do a full modeset on any pipe where the output routing |
8393 | * changed. We could be more clever, but that would require us to be |
8445 | * changed. We could be more clever, but that would require us to be |
8394 | * more careful with calling the relevant encoder->mode_set functions. |
8446 | * more careful with calling the relevant encoder->mode_set functions. |
8395 | */ |
8447 | */ |
8396 | if (*prepare_pipes) |
8448 | if (*prepare_pipes) |
8397 | *modeset_pipes = *prepare_pipes; |
8449 | *modeset_pipes = *prepare_pipes; |
8398 | 8450 | ||
8399 | /* ... and mask these out. */ |
8451 | /* ... and mask these out. */ |
8400 | *modeset_pipes &= ~(*disable_pipes); |
8452 | *modeset_pipes &= ~(*disable_pipes); |
8401 | *prepare_pipes &= ~(*disable_pipes); |
8453 | *prepare_pipes &= ~(*disable_pipes); |
8402 | 8454 | ||
8403 | /* |
8455 | /* |
8404 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
8456 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
8405 | * obies this rule, but the modeset restore mode of |
8457 | * obies this rule, but the modeset restore mode of |
8406 | * intel_modeset_setup_hw_state does not. |
8458 | * intel_modeset_setup_hw_state does not. |
8407 | */ |
8459 | */ |
8408 | *modeset_pipes &= 1 << intel_crtc->pipe; |
8460 | *modeset_pipes &= 1 << intel_crtc->pipe; |
8409 | *prepare_pipes &= 1 << intel_crtc->pipe; |
8461 | *prepare_pipes &= 1 << intel_crtc->pipe; |
8410 | 8462 | ||
8411 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
8463 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
8412 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
8464 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
8413 | } |
8465 | } |
8414 | 8466 | ||
8415 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
8467 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
8416 | { |
8468 | { |
8417 | struct drm_encoder *encoder; |
8469 | struct drm_encoder *encoder; |
8418 | struct drm_device *dev = crtc->dev; |
8470 | struct drm_device *dev = crtc->dev; |
8419 | 8471 | ||
8420 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8472 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8421 | if (encoder->crtc == crtc) |
8473 | if (encoder->crtc == crtc) |
8422 | return true; |
8474 | return true; |
8423 | 8475 | ||
8424 | return false; |
8476 | return false; |
8425 | } |
8477 | } |
8426 | 8478 | ||
8427 | static void |
8479 | static void |
8428 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
8480 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
8429 | { |
8481 | { |
8430 | struct intel_encoder *intel_encoder; |
8482 | struct intel_encoder *intel_encoder; |
8431 | struct intel_crtc *intel_crtc; |
8483 | struct intel_crtc *intel_crtc; |
8432 | struct drm_connector *connector; |
8484 | struct drm_connector *connector; |
8433 | 8485 | ||
8434 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
8486 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
8435 | base.head) { |
8487 | base.head) { |
8436 | if (!intel_encoder->base.crtc) |
8488 | if (!intel_encoder->base.crtc) |
8437 | continue; |
8489 | continue; |
8438 | 8490 | ||
8439 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
8491 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
8440 | 8492 | ||
8441 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
8493 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
8442 | intel_encoder->connectors_active = false; |
8494 | intel_encoder->connectors_active = false; |
8443 | } |
8495 | } |
8444 | 8496 | ||
8445 | intel_modeset_commit_output_state(dev); |
8497 | intel_modeset_commit_output_state(dev); |
8446 | 8498 | ||
8447 | /* Update computed state. */ |
8499 | /* Update computed state. */ |
8448 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8500 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
8449 | base.head) { |
8501 | base.head) { |
8450 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
8502 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); |
8451 | } |
8503 | } |
8452 | 8504 | ||
8453 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
8505 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
8454 | if (!connector->encoder || !connector->encoder->crtc) |
8506 | if (!connector->encoder || !connector->encoder->crtc) |
8455 | continue; |
8507 | continue; |
8456 | 8508 | ||
8457 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
8509 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
8458 | 8510 | ||
8459 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
8511 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
8460 | struct drm_property *dpms_property = |
8512 | struct drm_property *dpms_property = |
8461 | dev->mode_config.dpms_property; |
8513 | dev->mode_config.dpms_property; |
8462 | 8514 | ||
8463 | connector->dpms = DRM_MODE_DPMS_ON; |
8515 | connector->dpms = DRM_MODE_DPMS_ON; |
8464 | drm_object_property_set_value(&connector->base, |
8516 | drm_object_property_set_value(&connector->base, |
8465 | dpms_property, |
8517 | dpms_property, |
8466 | DRM_MODE_DPMS_ON); |
8518 | DRM_MODE_DPMS_ON); |
8467 | 8519 | ||
8468 | intel_encoder = to_intel_encoder(connector->encoder); |
8520 | intel_encoder = to_intel_encoder(connector->encoder); |
8469 | intel_encoder->connectors_active = true; |
8521 | intel_encoder->connectors_active = true; |
8470 | } |
8522 | } |
8471 | } |
8523 | } |
8472 | 8524 | ||
8473 | } |
8525 | } |
8474 | 8526 | ||
8475 | static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur, |
8527 | static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur, |
8476 | struct intel_crtc_config *new) |
8528 | struct intel_crtc_config *new) |
8477 | { |
8529 | { |
8478 | int clock1, clock2, diff; |
8530 | int clock1, clock2, diff; |
8479 | 8531 | ||
8480 | clock1 = cur->adjusted_mode.clock; |
8532 | clock1 = cur->adjusted_mode.clock; |
8481 | clock2 = new->adjusted_mode.clock; |
8533 | clock2 = new->adjusted_mode.clock; |
8482 | 8534 | ||
8483 | if (clock1 == clock2) |
8535 | if (clock1 == clock2) |
8484 | return true; |
8536 | return true; |
8485 | 8537 | ||
8486 | if (!clock1 || !clock2) |
8538 | if (!clock1 || !clock2) |
8487 | return false; |
8539 | return false; |
8488 | 8540 | ||
8489 | diff = abs(clock1 - clock2); |
8541 | diff = abs(clock1 - clock2); |
8490 | 8542 | ||
8491 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
8543 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
8492 | return true; |
8544 | return true; |
8493 | 8545 | ||
8494 | return false; |
8546 | return false; |
8495 | } |
8547 | } |
8496 | 8548 | ||
8497 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8549 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8498 | list_for_each_entry((intel_crtc), \ |
8550 | list_for_each_entry((intel_crtc), \ |
8499 | &(dev)->mode_config.crtc_list, \ |
8551 | &(dev)->mode_config.crtc_list, \ |
8500 | base.head) \ |
8552 | base.head) \ |
8501 | if (mask & (1 <<(intel_crtc)->pipe)) |
8553 | if (mask & (1 <<(intel_crtc)->pipe)) |
8502 | 8554 | ||
8503 | static bool |
8555 | static bool |
8504 | intel_pipe_config_compare(struct drm_device *dev, |
8556 | intel_pipe_config_compare(struct drm_device *dev, |
8505 | struct intel_crtc_config *current_config, |
8557 | struct intel_crtc_config *current_config, |
8506 | struct intel_crtc_config *pipe_config) |
8558 | struct intel_crtc_config *pipe_config) |
8507 | { |
8559 | { |
8508 | #define PIPE_CONF_CHECK_X(name) \ |
8560 | #define PIPE_CONF_CHECK_X(name) \ |
8509 | if (current_config->name != pipe_config->name) { \ |
8561 | if (current_config->name != pipe_config->name) { \ |
8510 | DRM_ERROR("mismatch in " #name " " \ |
8562 | DRM_ERROR("mismatch in " #name " " \ |
8511 | "(expected 0x%08x, found 0x%08x)\n", \ |
8563 | "(expected 0x%08x, found 0x%08x)\n", \ |
8512 | current_config->name, \ |
8564 | current_config->name, \ |
8513 | pipe_config->name); \ |
8565 | pipe_config->name); \ |
8514 | return false; \ |
8566 | return false; \ |
8515 | } |
8567 | } |
8516 | 8568 | ||
8517 | #define PIPE_CONF_CHECK_I(name) \ |
8569 | #define PIPE_CONF_CHECK_I(name) \ |
8518 | if (current_config->name != pipe_config->name) { \ |
8570 | if (current_config->name != pipe_config->name) { \ |
8519 | DRM_ERROR("mismatch in " #name " " \ |
8571 | DRM_ERROR("mismatch in " #name " " \ |
8520 | "(expected %i, found %i)\n", \ |
8572 | "(expected %i, found %i)\n", \ |
8521 | current_config->name, \ |
8573 | current_config->name, \ |
8522 | pipe_config->name); \ |
8574 | pipe_config->name); \ |
8523 | return false; \ |
8575 | return false; \ |
8524 | } |
8576 | } |
8525 | 8577 | ||
8526 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8578 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8527 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
8579 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
8528 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
8580 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
8529 | "(expected %i, found %i)\n", \ |
8581 | "(expected %i, found %i)\n", \ |
8530 | current_config->name & (mask), \ |
8582 | current_config->name & (mask), \ |
8531 | pipe_config->name & (mask)); \ |
8583 | pipe_config->name & (mask)); \ |
8532 | return false; \ |
8584 | return false; \ |
8533 | } |
8585 | } |
8534 | 8586 | ||
8535 | #define PIPE_CONF_QUIRK(quirk) \ |
8587 | #define PIPE_CONF_QUIRK(quirk) \ |
8536 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
8588 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
8537 | 8589 | ||
8538 | PIPE_CONF_CHECK_I(cpu_transcoder); |
8590 | PIPE_CONF_CHECK_I(cpu_transcoder); |
8539 | 8591 | ||
8540 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8592 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8541 | PIPE_CONF_CHECK_I(fdi_lanes); |
8593 | PIPE_CONF_CHECK_I(fdi_lanes); |
8542 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8594 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8543 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
8595 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
8544 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
8596 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
8545 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
8597 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
8546 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
8598 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
8547 | 8599 | ||
8548 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8600 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8549 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
8601 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
8550 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
8602 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
8551 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
8603 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
8552 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
8604 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
8553 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
8605 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
8554 | 8606 | ||
8555 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
8607 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
8556 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
8608 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
8557 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
8609 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
8558 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
8610 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
8559 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
8611 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
8560 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
8612 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
8561 | 8613 | ||
8562 | PIPE_CONF_CHECK_I(pixel_multiplier); |
8614 | PIPE_CONF_CHECK_I(pixel_multiplier); |
8563 | 8615 | ||
8564 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8616 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8565 | DRM_MODE_FLAG_INTERLACE); |
8617 | DRM_MODE_FLAG_INTERLACE); |
8566 | 8618 | ||
8567 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
8619 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
8568 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8620 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8569 | DRM_MODE_FLAG_PHSYNC); |
8621 | DRM_MODE_FLAG_PHSYNC); |
8570 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8622 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8571 | DRM_MODE_FLAG_NHSYNC); |
8623 | DRM_MODE_FLAG_NHSYNC); |
8572 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8624 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8573 | DRM_MODE_FLAG_PVSYNC); |
8625 | DRM_MODE_FLAG_PVSYNC); |
8574 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8626 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8575 | DRM_MODE_FLAG_NVSYNC); |
8627 | DRM_MODE_FLAG_NVSYNC); |
8576 | } |
8628 | } |
8577 | 8629 | ||
8578 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); |
8630 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); |
8579 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); |
8631 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); |
8580 | 8632 | ||
8581 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8633 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8582 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
8634 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
8583 | if (INTEL_INFO(dev)->gen < 4) |
8635 | if (INTEL_INFO(dev)->gen < 4) |
8584 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
8636 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
8585 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
8637 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
8586 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
8638 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
8587 | if (current_config->pch_pfit.enabled) { |
8639 | if (current_config->pch_pfit.enabled) { |
8588 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
8640 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
8589 | PIPE_CONF_CHECK_I(pch_pfit.size); |
8641 | PIPE_CONF_CHECK_I(pch_pfit.size); |
8590 | } |
8642 | } |
8591 | 8643 | ||
8592 | PIPE_CONF_CHECK_I(ips_enabled); |
8644 | PIPE_CONF_CHECK_I(ips_enabled); |
8593 | 8645 | ||
8594 | PIPE_CONF_CHECK_I(shared_dpll); |
8646 | PIPE_CONF_CHECK_I(shared_dpll); |
8595 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8647 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8596 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
8648 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
8597 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8649 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8598 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
8650 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
- | 8651 | ||
- | 8652 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
|
- | 8653 | PIPE_CONF_CHECK_I(pipe_bpp); |
|
8599 | 8654 | ||
8600 | #undef PIPE_CONF_CHECK_X |
8655 | #undef PIPE_CONF_CHECK_X |
8601 | #undef PIPE_CONF_CHECK_I |
8656 | #undef PIPE_CONF_CHECK_I |
8602 | #undef PIPE_CONF_CHECK_FLAGS |
8657 | #undef PIPE_CONF_CHECK_FLAGS |
8603 | #undef PIPE_CONF_QUIRK |
8658 | #undef PIPE_CONF_QUIRK |
8604 | 8659 | ||
8605 | if (!IS_HASWELL(dev)) { |
8660 | if (!IS_HASWELL(dev)) { |
8606 | if (!intel_fuzzy_clock_check(current_config, pipe_config)) { |
8661 | if (!intel_fuzzy_clock_check(current_config, pipe_config)) { |
8607 | DRM_ERROR("mismatch in clock (expected %d, found %d)\n", |
8662 | DRM_ERROR("mismatch in clock (expected %d, found %d)\n", |
8608 | current_config->adjusted_mode.clock, |
8663 | current_config->adjusted_mode.clock, |
8609 | pipe_config->adjusted_mode.clock); |
8664 | pipe_config->adjusted_mode.clock); |
8610 | return false; |
8665 | return false; |
8611 | } |
8666 | } |
8612 | } |
8667 | } |
8613 | 8668 | ||
8614 | return true; |
8669 | return true; |
8615 | } |
8670 | } |
8616 | 8671 | ||
8617 | static void |
8672 | static void |
8618 | check_connector_state(struct drm_device *dev) |
8673 | check_connector_state(struct drm_device *dev) |
8619 | { |
8674 | { |
8620 | struct intel_connector *connector; |
8675 | struct intel_connector *connector; |
8621 | 8676 | ||
8622 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8677 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8623 | base.head) { |
8678 | base.head) { |
8624 | /* This also checks the encoder/connector hw state with the |
8679 | /* This also checks the encoder/connector hw state with the |
8625 | * ->get_hw_state callbacks. */ |
8680 | * ->get_hw_state callbacks. */ |
8626 | intel_connector_check_state(connector); |
8681 | intel_connector_check_state(connector); |
8627 | 8682 | ||
8628 | WARN(&connector->new_encoder->base != connector->base.encoder, |
8683 | WARN(&connector->new_encoder->base != connector->base.encoder, |
8629 | "connector's staged encoder doesn't match current encoder\n"); |
8684 | "connector's staged encoder doesn't match current encoder\n"); |
8630 | } |
8685 | } |
8631 | } |
8686 | } |
8632 | 8687 | ||
8633 | static void |
8688 | static void |
8634 | check_encoder_state(struct drm_device *dev) |
8689 | check_encoder_state(struct drm_device *dev) |
8635 | { |
8690 | { |
8636 | struct intel_encoder *encoder; |
8691 | struct intel_encoder *encoder; |
8637 | struct intel_connector *connector; |
8692 | struct intel_connector *connector; |
8638 | 8693 | ||
8639 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8694 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8640 | base.head) { |
8695 | base.head) { |
8641 | bool enabled = false; |
8696 | bool enabled = false; |
8642 | bool active = false; |
8697 | bool active = false; |
8643 | enum pipe pipe, tracked_pipe; |
8698 | enum pipe pipe, tracked_pipe; |
8644 | 8699 | ||
8645 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
8700 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
8646 | encoder->base.base.id, |
8701 | encoder->base.base.id, |
8647 | drm_get_encoder_name(&encoder->base)); |
8702 | drm_get_encoder_name(&encoder->base)); |
8648 | 8703 | ||
8649 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8704 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8650 | "encoder's stage crtc doesn't match current crtc\n"); |
8705 | "encoder's stage crtc doesn't match current crtc\n"); |
8651 | WARN(encoder->connectors_active && !encoder->base.crtc, |
8706 | WARN(encoder->connectors_active && !encoder->base.crtc, |
8652 | "encoder's active_connectors set, but no crtc\n"); |
8707 | "encoder's active_connectors set, but no crtc\n"); |
8653 | 8708 | ||
8654 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8709 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8655 | base.head) { |
8710 | base.head) { |
8656 | if (connector->base.encoder != &encoder->base) |
8711 | if (connector->base.encoder != &encoder->base) |
8657 | continue; |
8712 | continue; |
8658 | enabled = true; |
8713 | enabled = true; |
8659 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
8714 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
8660 | active = true; |
8715 | active = true; |
8661 | } |
8716 | } |
8662 | WARN(!!encoder->base.crtc != enabled, |
8717 | WARN(!!encoder->base.crtc != enabled, |
8663 | "encoder's enabled state mismatch " |
8718 | "encoder's enabled state mismatch " |
8664 | "(expected %i, found %i)\n", |
8719 | "(expected %i, found %i)\n", |
8665 | !!encoder->base.crtc, enabled); |
8720 | !!encoder->base.crtc, enabled); |
8666 | WARN(active && !encoder->base.crtc, |
8721 | WARN(active && !encoder->base.crtc, |
8667 | "active encoder with no crtc\n"); |
8722 | "active encoder with no crtc\n"); |
8668 | 8723 | ||
8669 | WARN(encoder->connectors_active != active, |
8724 | WARN(encoder->connectors_active != active, |
8670 | "encoder's computed active state doesn't match tracked active state " |
8725 | "encoder's computed active state doesn't match tracked active state " |
8671 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
8726 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
8672 | 8727 | ||
8673 | active = encoder->get_hw_state(encoder, &pipe); |
8728 | active = encoder->get_hw_state(encoder, &pipe); |
8674 | WARN(active != encoder->connectors_active, |
8729 | WARN(active != encoder->connectors_active, |
8675 | "encoder's hw state doesn't match sw tracking " |
8730 | "encoder's hw state doesn't match sw tracking " |
8676 | "(expected %i, found %i)\n", |
8731 | "(expected %i, found %i)\n", |
8677 | encoder->connectors_active, active); |
8732 | encoder->connectors_active, active); |
8678 | 8733 | ||
8679 | if (!encoder->base.crtc) |
8734 | if (!encoder->base.crtc) |
8680 | continue; |
8735 | continue; |
8681 | 8736 | ||
8682 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
8737 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
8683 | WARN(active && pipe != tracked_pipe, |
8738 | WARN(active && pipe != tracked_pipe, |
8684 | "active encoder's pipe doesn't match" |
8739 | "active encoder's pipe doesn't match" |
8685 | "(expected %i, found %i)\n", |
8740 | "(expected %i, found %i)\n", |
8686 | tracked_pipe, pipe); |
8741 | tracked_pipe, pipe); |
8687 | 8742 | ||
8688 | } |
8743 | } |
8689 | } |
8744 | } |
8690 | 8745 | ||
8691 | static void |
8746 | static void |
8692 | check_crtc_state(struct drm_device *dev) |
8747 | check_crtc_state(struct drm_device *dev) |
8693 | { |
8748 | { |
8694 | drm_i915_private_t *dev_priv = dev->dev_private; |
8749 | drm_i915_private_t *dev_priv = dev->dev_private; |
8695 | struct intel_crtc *crtc; |
8750 | struct intel_crtc *crtc; |
8696 | struct intel_encoder *encoder; |
8751 | struct intel_encoder *encoder; |
8697 | struct intel_crtc_config pipe_config; |
8752 | struct intel_crtc_config pipe_config; |
8698 | 8753 | ||
8699 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8754 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8700 | base.head) { |
8755 | base.head) { |
8701 | bool enabled = false; |
8756 | bool enabled = false; |
8702 | bool active = false; |
8757 | bool active = false; |
8703 | 8758 | ||
8704 | memset(&pipe_config, 0, sizeof(pipe_config)); |
8759 | memset(&pipe_config, 0, sizeof(pipe_config)); |
8705 | 8760 | ||
8706 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
8761 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
8707 | crtc->base.base.id); |
8762 | crtc->base.base.id); |
8708 | 8763 | ||
8709 | WARN(crtc->active && !crtc->base.enabled, |
8764 | WARN(crtc->active && !crtc->base.enabled, |
8710 | "active crtc, but not enabled in sw tracking\n"); |
8765 | "active crtc, but not enabled in sw tracking\n"); |
8711 | 8766 | ||
8712 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8767 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8713 | base.head) { |
8768 | base.head) { |
8714 | if (encoder->base.crtc != &crtc->base) |
8769 | if (encoder->base.crtc != &crtc->base) |
8715 | continue; |
8770 | continue; |
8716 | enabled = true; |
8771 | enabled = true; |
8717 | if (encoder->connectors_active) |
8772 | if (encoder->connectors_active) |
8718 | active = true; |
8773 | active = true; |
8719 | } |
8774 | } |
8720 | 8775 | ||
8721 | WARN(active != crtc->active, |
8776 | WARN(active != crtc->active, |
8722 | "crtc's computed active state doesn't match tracked active state " |
8777 | "crtc's computed active state doesn't match tracked active state " |
8723 | "(expected %i, found %i)\n", active, crtc->active); |
8778 | "(expected %i, found %i)\n", active, crtc->active); |
8724 | WARN(enabled != crtc->base.enabled, |
8779 | WARN(enabled != crtc->base.enabled, |
8725 | "crtc's computed enabled state doesn't match tracked enabled state " |
8780 | "crtc's computed enabled state doesn't match tracked enabled state " |
8726 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
8781 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
8727 | 8782 | ||
8728 | active = dev_priv->display.get_pipe_config(crtc, |
8783 | active = dev_priv->display.get_pipe_config(crtc, |
8729 | &pipe_config); |
8784 | &pipe_config); |
8730 | 8785 | ||
8731 | /* hw state is inconsistent with the pipe A quirk */ |
8786 | /* hw state is inconsistent with the pipe A quirk */ |
8732 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
8787 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
8733 | active = crtc->active; |
8788 | active = crtc->active; |
8734 | 8789 | ||
8735 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8790 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8736 | base.head) { |
8791 | base.head) { |
8737 | enum pipe pipe; |
8792 | enum pipe pipe; |
8738 | if (encoder->base.crtc != &crtc->base) |
8793 | if (encoder->base.crtc != &crtc->base) |
8739 | continue; |
8794 | continue; |
8740 | if (encoder->get_config && |
8795 | if (encoder->get_config && |
8741 | encoder->get_hw_state(encoder, &pipe)) |
8796 | encoder->get_hw_state(encoder, &pipe)) |
8742 | encoder->get_config(encoder, &pipe_config); |
8797 | encoder->get_config(encoder, &pipe_config); |
8743 | } |
8798 | } |
8744 | 8799 | ||
8745 | if (dev_priv->display.get_clock) |
8800 | if (dev_priv->display.get_clock) |
8746 | dev_priv->display.get_clock(crtc, &pipe_config); |
8801 | dev_priv->display.get_clock(crtc, &pipe_config); |
8747 | 8802 | ||
8748 | WARN(crtc->active != active, |
8803 | WARN(crtc->active != active, |
8749 | "crtc active state doesn't match with hw state " |
8804 | "crtc active state doesn't match with hw state " |
8750 | "(expected %i, found %i)\n", crtc->active, active); |
8805 | "(expected %i, found %i)\n", crtc->active, active); |
8751 | 8806 | ||
8752 | if (active && |
8807 | if (active && |
8753 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
8808 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
8754 | WARN(1, "pipe state doesn't match!\n"); |
8809 | WARN(1, "pipe state doesn't match!\n"); |
8755 | intel_dump_pipe_config(crtc, &pipe_config, |
8810 | intel_dump_pipe_config(crtc, &pipe_config, |
8756 | "[hw state]"); |
8811 | "[hw state]"); |
8757 | intel_dump_pipe_config(crtc, &crtc->config, |
8812 | intel_dump_pipe_config(crtc, &crtc->config, |
8758 | "[sw state]"); |
8813 | "[sw state]"); |
8759 | } |
8814 | } |
8760 | } |
8815 | } |
8761 | } |
8816 | } |
8762 | 8817 | ||
8763 | static void |
8818 | static void |
8764 | check_shared_dpll_state(struct drm_device *dev) |
8819 | check_shared_dpll_state(struct drm_device *dev) |
8765 | { |
8820 | { |
8766 | drm_i915_private_t *dev_priv = dev->dev_private; |
8821 | drm_i915_private_t *dev_priv = dev->dev_private; |
8767 | struct intel_crtc *crtc; |
8822 | struct intel_crtc *crtc; |
8768 | struct intel_dpll_hw_state dpll_hw_state; |
8823 | struct intel_dpll_hw_state dpll_hw_state; |
8769 | int i; |
8824 | int i; |
8770 | 8825 | ||
8771 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
8826 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
8772 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
8827 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
8773 | int enabled_crtcs = 0, active_crtcs = 0; |
8828 | int enabled_crtcs = 0, active_crtcs = 0; |
8774 | bool active; |
8829 | bool active; |
8775 | 8830 | ||
8776 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
8831 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
8777 | 8832 | ||
8778 | DRM_DEBUG_KMS("%s\n", pll->name); |
8833 | DRM_DEBUG_KMS("%s\n", pll->name); |
8779 | 8834 | ||
8780 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
8835 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
8781 | 8836 | ||
8782 | WARN(pll->active > pll->refcount, |
8837 | WARN(pll->active > pll->refcount, |
8783 | "more active pll users than references: %i vs %i\n", |
8838 | "more active pll users than references: %i vs %i\n", |
8784 | pll->active, pll->refcount); |
8839 | pll->active, pll->refcount); |
8785 | WARN(pll->active && !pll->on, |
8840 | WARN(pll->active && !pll->on, |
8786 | "pll in active use but not on in sw tracking\n"); |
8841 | "pll in active use but not on in sw tracking\n"); |
8787 | WARN(pll->on && !pll->active, |
8842 | WARN(pll->on && !pll->active, |
8788 | "pll in on but not on in use in sw tracking\n"); |
8843 | "pll in on but not on in use in sw tracking\n"); |
8789 | WARN(pll->on != active, |
8844 | WARN(pll->on != active, |
8790 | "pll on state mismatch (expected %i, found %i)\n", |
8845 | "pll on state mismatch (expected %i, found %i)\n", |
8791 | pll->on, active); |
8846 | pll->on, active); |
8792 | 8847 | ||
8793 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8848 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
8794 | base.head) { |
8849 | base.head) { |
8795 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
8850 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
8796 | enabled_crtcs++; |
8851 | enabled_crtcs++; |
8797 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
8852 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
8798 | active_crtcs++; |
8853 | active_crtcs++; |
8799 | } |
8854 | } |
8800 | WARN(pll->active != active_crtcs, |
8855 | WARN(pll->active != active_crtcs, |
8801 | "pll active crtcs mismatch (expected %i, found %i)\n", |
8856 | "pll active crtcs mismatch (expected %i, found %i)\n", |
8802 | pll->active, active_crtcs); |
8857 | pll->active, active_crtcs); |
8803 | WARN(pll->refcount != enabled_crtcs, |
8858 | WARN(pll->refcount != enabled_crtcs, |
8804 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
8859 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
8805 | pll->refcount, enabled_crtcs); |
8860 | pll->refcount, enabled_crtcs); |
8806 | 8861 | ||
8807 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
8862 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
8808 | sizeof(dpll_hw_state)), |
8863 | sizeof(dpll_hw_state)), |
8809 | "pll hw state mismatch\n"); |
8864 | "pll hw state mismatch\n"); |
8810 | } |
8865 | } |
8811 | } |
8866 | } |
8812 | 8867 | ||
8813 | void |
8868 | void |
8814 | intel_modeset_check_state(struct drm_device *dev) |
8869 | intel_modeset_check_state(struct drm_device *dev) |
8815 | { |
8870 | { |
8816 | check_connector_state(dev); |
8871 | check_connector_state(dev); |
8817 | check_encoder_state(dev); |
8872 | check_encoder_state(dev); |
8818 | check_crtc_state(dev); |
8873 | check_crtc_state(dev); |
8819 | check_shared_dpll_state(dev); |
8874 | check_shared_dpll_state(dev); |
8820 | } |
8875 | } |
8821 | 8876 | ||
8822 | static int __intel_set_mode(struct drm_crtc *crtc, |
8877 | static int __intel_set_mode(struct drm_crtc *crtc, |
8823 | struct drm_display_mode *mode, |
8878 | struct drm_display_mode *mode, |
8824 | int x, int y, struct drm_framebuffer *fb) |
8879 | int x, int y, struct drm_framebuffer *fb) |
8825 | { |
8880 | { |
8826 | struct drm_device *dev = crtc->dev; |
8881 | struct drm_device *dev = crtc->dev; |
8827 | drm_i915_private_t *dev_priv = dev->dev_private; |
8882 | drm_i915_private_t *dev_priv = dev->dev_private; |
8828 | struct drm_display_mode *saved_mode, *saved_hwmode; |
8883 | struct drm_display_mode *saved_mode, *saved_hwmode; |
8829 | struct intel_crtc_config *pipe_config = NULL; |
8884 | struct intel_crtc_config *pipe_config = NULL; |
8830 | struct intel_crtc *intel_crtc; |
8885 | struct intel_crtc *intel_crtc; |
8831 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
8886 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
8832 | int ret = 0; |
8887 | int ret = 0; |
8833 | 8888 | ||
8834 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
8889 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
8835 | if (!saved_mode) |
8890 | if (!saved_mode) |
8836 | return -ENOMEM; |
8891 | return -ENOMEM; |
8837 | saved_hwmode = saved_mode + 1; |
8892 | saved_hwmode = saved_mode + 1; |
8838 | 8893 | ||
8839 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
8894 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
8840 | &prepare_pipes, &disable_pipes); |
8895 | &prepare_pipes, &disable_pipes); |
8841 | 8896 | ||
8842 | *saved_hwmode = crtc->hwmode; |
8897 | *saved_hwmode = crtc->hwmode; |
8843 | *saved_mode = crtc->mode; |
8898 | *saved_mode = crtc->mode; |
8844 | 8899 | ||
8845 | /* Hack: Because we don't (yet) support global modeset on multiple |
8900 | /* Hack: Because we don't (yet) support global modeset on multiple |
8846 | * crtcs, we don't keep track of the new mode for more than one crtc. |
8901 | * crtcs, we don't keep track of the new mode for more than one crtc. |
8847 | * Hence simply check whether any bit is set in modeset_pipes in all the |
8902 | * Hence simply check whether any bit is set in modeset_pipes in all the |
8848 | * pieces of code that are not yet converted to deal with mutliple crtcs |
8903 | * pieces of code that are not yet converted to deal with mutliple crtcs |
8849 | * changing their mode at the same time. */ |
8904 | * changing their mode at the same time. */ |
8850 | if (modeset_pipes) { |
8905 | if (modeset_pipes) { |
8851 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
8906 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
8852 | if (IS_ERR(pipe_config)) { |
8907 | if (IS_ERR(pipe_config)) { |
8853 | ret = PTR_ERR(pipe_config); |
8908 | ret = PTR_ERR(pipe_config); |
8854 | pipe_config = NULL; |
8909 | pipe_config = NULL; |
8855 | 8910 | ||
8856 | goto out; |
8911 | goto out; |
8857 | } |
8912 | } |
8858 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
8913 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
8859 | "[modeset]"); |
8914 | "[modeset]"); |
8860 | } |
8915 | } |
8861 | 8916 | ||
8862 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
8917 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
8863 | intel_crtc_disable(&intel_crtc->base); |
8918 | intel_crtc_disable(&intel_crtc->base); |
8864 | 8919 | ||
8865 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
8920 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
8866 | if (intel_crtc->base.enabled) |
8921 | if (intel_crtc->base.enabled) |
8867 | dev_priv->display.crtc_disable(&intel_crtc->base); |
8922 | dev_priv->display.crtc_disable(&intel_crtc->base); |
8868 | } |
8923 | } |
8869 | 8924 | ||
8870 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
8925 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
8871 | * to set it here already despite that we pass it down the callchain. |
8926 | * to set it here already despite that we pass it down the callchain. |
8872 | */ |
8927 | */ |
8873 | if (modeset_pipes) { |
8928 | if (modeset_pipes) { |
8874 | crtc->mode = *mode; |
8929 | crtc->mode = *mode; |
8875 | /* mode_set/enable/disable functions rely on a correct pipe |
8930 | /* mode_set/enable/disable functions rely on a correct pipe |
8876 | * config. */ |
8931 | * config. */ |
8877 | to_intel_crtc(crtc)->config = *pipe_config; |
8932 | to_intel_crtc(crtc)->config = *pipe_config; |
8878 | } |
8933 | } |
8879 | 8934 | ||
8880 | /* Only after disabling all output pipelines that will be changed can we |
8935 | /* Only after disabling all output pipelines that will be changed can we |
8881 | * update the the output configuration. */ |
8936 | * update the the output configuration. */ |
8882 | intel_modeset_update_state(dev, prepare_pipes); |
8937 | intel_modeset_update_state(dev, prepare_pipes); |
8883 | 8938 | ||
8884 | if (dev_priv->display.modeset_global_resources) |
8939 | if (dev_priv->display.modeset_global_resources) |
8885 | dev_priv->display.modeset_global_resources(dev); |
8940 | dev_priv->display.modeset_global_resources(dev); |
8886 | 8941 | ||
8887 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
8942 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
8888 | * on the DPLL. |
8943 | * on the DPLL. |
8889 | */ |
8944 | */ |
8890 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
8945 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
8891 | ret = intel_crtc_mode_set(&intel_crtc->base, |
8946 | ret = intel_crtc_mode_set(&intel_crtc->base, |
8892 | x, y, fb); |
8947 | x, y, fb); |
8893 | if (ret) |
8948 | if (ret) |
8894 | goto done; |
8949 | goto done; |
8895 | } |
8950 | } |
8896 | 8951 | ||
8897 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
8952 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
8898 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
8953 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
8899 | dev_priv->display.crtc_enable(&intel_crtc->base); |
8954 | dev_priv->display.crtc_enable(&intel_crtc->base); |
8900 | 8955 | ||
8901 | if (modeset_pipes) { |
8956 | if (modeset_pipes) { |
8902 | /* Store real post-adjustment hardware mode. */ |
8957 | /* Store real post-adjustment hardware mode. */ |
8903 | crtc->hwmode = pipe_config->adjusted_mode; |
8958 | crtc->hwmode = pipe_config->adjusted_mode; |
8904 | 8959 | ||
8905 | /* Calculate and store various constants which |
8960 | /* Calculate and store various constants which |
8906 | * are later needed by vblank and swap-completion |
8961 | * are later needed by vblank and swap-completion |
8907 | * timestamping. They are derived from true hwmode. |
8962 | * timestamping. They are derived from true hwmode. |
8908 | */ |
8963 | */ |
8909 | drm_calc_timestamping_constants(crtc); |
8964 | drm_calc_timestamping_constants(crtc); |
8910 | } |
8965 | } |
8911 | 8966 | ||
8912 | /* FIXME: add subpixel order */ |
8967 | /* FIXME: add subpixel order */ |
8913 | done: |
8968 | done: |
8914 | if (ret && crtc->enabled) { |
8969 | if (ret && crtc->enabled) { |
8915 | crtc->hwmode = *saved_hwmode; |
8970 | crtc->hwmode = *saved_hwmode; |
8916 | crtc->mode = *saved_mode; |
8971 | crtc->mode = *saved_mode; |
8917 | } |
8972 | } |
8918 | 8973 | ||
8919 | out: |
8974 | out: |
8920 | kfree(pipe_config); |
8975 | kfree(pipe_config); |
8921 | kfree(saved_mode); |
8976 | kfree(saved_mode); |
8922 | return ret; |
8977 | return ret; |
8923 | } |
8978 | } |
8924 | 8979 | ||
8925 | static int intel_set_mode(struct drm_crtc *crtc, |
8980 | static int intel_set_mode(struct drm_crtc *crtc, |
8926 | struct drm_display_mode *mode, |
8981 | struct drm_display_mode *mode, |
8927 | int x, int y, struct drm_framebuffer *fb) |
8982 | int x, int y, struct drm_framebuffer *fb) |
8928 | { |
8983 | { |
8929 | int ret; |
8984 | int ret; |
8930 | 8985 | ||
8931 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
8986 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
8932 | 8987 | ||
8933 | if (ret == 0) |
8988 | if (ret == 0) |
8934 | intel_modeset_check_state(crtc->dev); |
8989 | intel_modeset_check_state(crtc->dev); |
8935 | 8990 | ||
8936 | return ret; |
8991 | return ret; |
8937 | } |
8992 | } |
8938 | 8993 | ||
8939 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
8994 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
8940 | { |
8995 | { |
8941 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
8996 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
8942 | } |
8997 | } |
8943 | 8998 | ||
8944 | #undef for_each_intel_crtc_masked |
8999 | #undef for_each_intel_crtc_masked |
8945 | 9000 | ||
8946 | static void intel_set_config_free(struct intel_set_config *config) |
9001 | static void intel_set_config_free(struct intel_set_config *config) |
8947 | { |
9002 | { |
8948 | if (!config) |
9003 | if (!config) |
8949 | return; |
9004 | return; |
8950 | 9005 | ||
8951 | kfree(config->save_connector_encoders); |
9006 | kfree(config->save_connector_encoders); |
8952 | kfree(config->save_encoder_crtcs); |
9007 | kfree(config->save_encoder_crtcs); |
8953 | kfree(config); |
9008 | kfree(config); |
8954 | } |
9009 | } |
8955 | 9010 | ||
8956 | static int intel_set_config_save_state(struct drm_device *dev, |
9011 | static int intel_set_config_save_state(struct drm_device *dev, |
8957 | struct intel_set_config *config) |
9012 | struct intel_set_config *config) |
8958 | { |
9013 | { |
8959 | struct drm_encoder *encoder; |
9014 | struct drm_encoder *encoder; |
8960 | struct drm_connector *connector; |
9015 | struct drm_connector *connector; |
8961 | int count; |
9016 | int count; |
8962 | 9017 | ||
8963 | config->save_encoder_crtcs = |
9018 | config->save_encoder_crtcs = |
8964 | kcalloc(dev->mode_config.num_encoder, |
9019 | kcalloc(dev->mode_config.num_encoder, |
8965 | sizeof(struct drm_crtc *), GFP_KERNEL); |
9020 | sizeof(struct drm_crtc *), GFP_KERNEL); |
8966 | if (!config->save_encoder_crtcs) |
9021 | if (!config->save_encoder_crtcs) |
8967 | return -ENOMEM; |
9022 | return -ENOMEM; |
8968 | 9023 | ||
8969 | config->save_connector_encoders = |
9024 | config->save_connector_encoders = |
8970 | kcalloc(dev->mode_config.num_connector, |
9025 | kcalloc(dev->mode_config.num_connector, |
8971 | sizeof(struct drm_encoder *), GFP_KERNEL); |
9026 | sizeof(struct drm_encoder *), GFP_KERNEL); |
8972 | if (!config->save_connector_encoders) |
9027 | if (!config->save_connector_encoders) |
8973 | return -ENOMEM; |
9028 | return -ENOMEM; |
8974 | 9029 | ||
8975 | /* Copy data. Note that driver private data is not affected. |
9030 | /* Copy data. Note that driver private data is not affected. |
8976 | * Should anything bad happen only the expected state is |
9031 | * Should anything bad happen only the expected state is |
8977 | * restored, not the drivers personal bookkeeping. |
9032 | * restored, not the drivers personal bookkeeping. |
8978 | */ |
9033 | */ |
8979 | count = 0; |
9034 | count = 0; |
8980 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
9035 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
8981 | config->save_encoder_crtcs[count++] = encoder->crtc; |
9036 | config->save_encoder_crtcs[count++] = encoder->crtc; |
8982 | } |
9037 | } |
8983 | 9038 | ||
8984 | count = 0; |
9039 | count = 0; |
8985 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
9040 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
8986 | config->save_connector_encoders[count++] = connector->encoder; |
9041 | config->save_connector_encoders[count++] = connector->encoder; |
8987 | } |
9042 | } |
8988 | 9043 | ||
8989 | return 0; |
9044 | return 0; |
8990 | } |
9045 | } |
8991 | 9046 | ||
8992 | static void intel_set_config_restore_state(struct drm_device *dev, |
9047 | static void intel_set_config_restore_state(struct drm_device *dev, |
8993 | struct intel_set_config *config) |
9048 | struct intel_set_config *config) |
8994 | { |
9049 | { |
8995 | struct intel_encoder *encoder; |
9050 | struct intel_encoder *encoder; |
8996 | struct intel_connector *connector; |
9051 | struct intel_connector *connector; |
8997 | int count; |
9052 | int count; |
8998 | 9053 | ||
8999 | count = 0; |
9054 | count = 0; |
9000 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9055 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9001 | encoder->new_crtc = |
9056 | encoder->new_crtc = |
9002 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
9057 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
9003 | } |
9058 | } |
9004 | 9059 | ||
9005 | count = 0; |
9060 | count = 0; |
9006 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9061 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9007 | connector->new_encoder = |
9062 | connector->new_encoder = |
9008 | to_intel_encoder(config->save_connector_encoders[count++]); |
9063 | to_intel_encoder(config->save_connector_encoders[count++]); |
9009 | } |
9064 | } |
9010 | } |
9065 | } |
9011 | 9066 | ||
9012 | static bool |
9067 | static bool |
9013 | is_crtc_connector_off(struct drm_mode_set *set) |
9068 | is_crtc_connector_off(struct drm_mode_set *set) |
9014 | { |
9069 | { |
9015 | int i; |
9070 | int i; |
9016 | 9071 | ||
9017 | if (set->num_connectors == 0) |
9072 | if (set->num_connectors == 0) |
9018 | return false; |
9073 | return false; |
9019 | 9074 | ||
9020 | if (WARN_ON(set->connectors == NULL)) |
9075 | if (WARN_ON(set->connectors == NULL)) |
9021 | return false; |
9076 | return false; |
9022 | 9077 | ||
9023 | for (i = 0; i < set->num_connectors; i++) |
9078 | for (i = 0; i < set->num_connectors; i++) |
9024 | if (set->connectors[i]->encoder && |
9079 | if (set->connectors[i]->encoder && |
9025 | set->connectors[i]->encoder->crtc == set->crtc && |
9080 | set->connectors[i]->encoder->crtc == set->crtc && |
9026 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
9081 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
9027 | return true; |
9082 | return true; |
9028 | 9083 | ||
9029 | return false; |
9084 | return false; |
9030 | } |
9085 | } |
9031 | 9086 | ||
9032 | static void |
9087 | static void |
9033 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
9088 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
9034 | struct intel_set_config *config) |
9089 | struct intel_set_config *config) |
9035 | { |
9090 | { |
9036 | 9091 | ||
9037 | /* We should be able to check here if the fb has the same properties |
9092 | /* We should be able to check here if the fb has the same properties |
9038 | * and then just flip_or_move it */ |
9093 | * and then just flip_or_move it */ |
9039 | if (is_crtc_connector_off(set)) { |
9094 | if (is_crtc_connector_off(set)) { |
9040 | config->mode_changed = true; |
9095 | config->mode_changed = true; |
9041 | } else if (set->crtc->fb != set->fb) { |
9096 | } else if (set->crtc->fb != set->fb) { |
9042 | /* If we have no fb then treat it as a full mode set */ |
9097 | /* If we have no fb then treat it as a full mode set */ |
9043 | if (set->crtc->fb == NULL) { |
9098 | if (set->crtc->fb == NULL) { |
9044 | struct intel_crtc *intel_crtc = |
9099 | struct intel_crtc *intel_crtc = |
9045 | to_intel_crtc(set->crtc); |
9100 | to_intel_crtc(set->crtc); |
9046 | 9101 | ||
9047 | if (intel_crtc->active && i915_fastboot) { |
9102 | if (intel_crtc->active && i915_fastboot) { |
9048 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9103 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9049 | config->fb_changed = true; |
9104 | config->fb_changed = true; |
9050 | } else { |
9105 | } else { |
9051 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
9106 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
9052 | config->mode_changed = true; |
9107 | config->mode_changed = true; |
9053 | } |
9108 | } |
9054 | } else if (set->fb == NULL) { |
9109 | } else if (set->fb == NULL) { |
9055 | config->mode_changed = true; |
9110 | config->mode_changed = true; |
9056 | } else if (set->fb->pixel_format != |
9111 | } else if (set->fb->pixel_format != |
9057 | set->crtc->fb->pixel_format) { |
9112 | set->crtc->fb->pixel_format) { |
9058 | config->mode_changed = true; |
9113 | config->mode_changed = true; |
9059 | } else { |
9114 | } else { |
9060 | config->fb_changed = true; |
9115 | config->fb_changed = true; |
9061 | } |
9116 | } |
9062 | } |
9117 | } |
9063 | 9118 | ||
9064 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
9119 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
9065 | config->fb_changed = true; |
9120 | config->fb_changed = true; |
9066 | 9121 | ||
9067 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
9122 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
9068 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
9123 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
9069 | drm_mode_debug_printmodeline(&set->crtc->mode); |
9124 | drm_mode_debug_printmodeline(&set->crtc->mode); |
9070 | drm_mode_debug_printmodeline(set->mode); |
9125 | drm_mode_debug_printmodeline(set->mode); |
9071 | config->mode_changed = true; |
9126 | config->mode_changed = true; |
9072 | } |
9127 | } |
9073 | 9128 | ||
9074 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
9129 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
9075 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
9130 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
9076 | } |
9131 | } |
9077 | 9132 | ||
9078 | static int |
9133 | static int |
9079 | intel_modeset_stage_output_state(struct drm_device *dev, |
9134 | intel_modeset_stage_output_state(struct drm_device *dev, |
9080 | struct drm_mode_set *set, |
9135 | struct drm_mode_set *set, |
9081 | struct intel_set_config *config) |
9136 | struct intel_set_config *config) |
9082 | { |
9137 | { |
9083 | struct drm_crtc *new_crtc; |
9138 | struct drm_crtc *new_crtc; |
9084 | struct intel_connector *connector; |
9139 | struct intel_connector *connector; |
9085 | struct intel_encoder *encoder; |
9140 | struct intel_encoder *encoder; |
9086 | int ro; |
9141 | int ro; |
9087 | 9142 | ||
9088 | /* The upper layers ensure that we either disable a crtc or have a list |
9143 | /* The upper layers ensure that we either disable a crtc or have a list |
9089 | * of connectors. For paranoia, double-check this. */ |
9144 | * of connectors. For paranoia, double-check this. */ |
9090 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
9145 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
9091 | WARN_ON(set->fb && (set->num_connectors == 0)); |
9146 | WARN_ON(set->fb && (set->num_connectors == 0)); |
9092 | 9147 | ||
9093 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9148 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9094 | base.head) { |
9149 | base.head) { |
9095 | /* Otherwise traverse passed in connector list and get encoders |
9150 | /* Otherwise traverse passed in connector list and get encoders |
9096 | * for them. */ |
9151 | * for them. */ |
9097 | for (ro = 0; ro < set->num_connectors; ro++) { |
9152 | for (ro = 0; ro < set->num_connectors; ro++) { |
9098 | if (set->connectors[ro] == &connector->base) { |
9153 | if (set->connectors[ro] == &connector->base) { |
9099 | connector->new_encoder = connector->encoder; |
9154 | connector->new_encoder = connector->encoder; |
9100 | break; |
9155 | break; |
9101 | } |
9156 | } |
9102 | } |
9157 | } |
9103 | 9158 | ||
9104 | /* If we disable the crtc, disable all its connectors. Also, if |
9159 | /* If we disable the crtc, disable all its connectors. Also, if |
9105 | * the connector is on the changing crtc but not on the new |
9160 | * the connector is on the changing crtc but not on the new |
9106 | * connector list, disable it. */ |
9161 | * connector list, disable it. */ |
9107 | if ((!set->fb || ro == set->num_connectors) && |
9162 | if ((!set->fb || ro == set->num_connectors) && |
9108 | connector->base.encoder && |
9163 | connector->base.encoder && |
9109 | connector->base.encoder->crtc == set->crtc) { |
9164 | connector->base.encoder->crtc == set->crtc) { |
9110 | connector->new_encoder = NULL; |
9165 | connector->new_encoder = NULL; |
9111 | 9166 | ||
9112 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
9167 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
9113 | connector->base.base.id, |
9168 | connector->base.base.id, |
9114 | drm_get_connector_name(&connector->base)); |
9169 | drm_get_connector_name(&connector->base)); |
9115 | } |
9170 | } |
9116 | 9171 | ||
9117 | 9172 | ||
9118 | if (&connector->new_encoder->base != connector->base.encoder) { |
9173 | if (&connector->new_encoder->base != connector->base.encoder) { |
9119 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
9174 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
9120 | config->mode_changed = true; |
9175 | config->mode_changed = true; |
9121 | } |
9176 | } |
9122 | } |
9177 | } |
9123 | /* connector->new_encoder is now updated for all connectors. */ |
9178 | /* connector->new_encoder is now updated for all connectors. */ |
9124 | 9179 | ||
9125 | /* Update crtc of enabled connectors. */ |
9180 | /* Update crtc of enabled connectors. */ |
9126 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9181 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9127 | base.head) { |
9182 | base.head) { |
9128 | if (!connector->new_encoder) |
9183 | if (!connector->new_encoder) |
9129 | continue; |
9184 | continue; |
9130 | 9185 | ||
9131 | new_crtc = connector->new_encoder->base.crtc; |
9186 | new_crtc = connector->new_encoder->base.crtc; |
9132 | 9187 | ||
9133 | for (ro = 0; ro < set->num_connectors; ro++) { |
9188 | for (ro = 0; ro < set->num_connectors; ro++) { |
9134 | if (set->connectors[ro] == &connector->base) |
9189 | if (set->connectors[ro] == &connector->base) |
9135 | new_crtc = set->crtc; |
9190 | new_crtc = set->crtc; |
9136 | } |
9191 | } |
9137 | 9192 | ||
9138 | /* Make sure the new CRTC will work with the encoder */ |
9193 | /* Make sure the new CRTC will work with the encoder */ |
9139 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9194 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9140 | new_crtc)) { |
9195 | new_crtc)) { |
9141 | return -EINVAL; |
9196 | return -EINVAL; |
9142 | } |
9197 | } |
9143 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9198 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9144 | 9199 | ||
9145 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
9200 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
9146 | connector->base.base.id, |
9201 | connector->base.base.id, |
9147 | drm_get_connector_name(&connector->base), |
9202 | drm_get_connector_name(&connector->base), |
9148 | new_crtc->base.id); |
9203 | new_crtc->base.id); |
9149 | } |
9204 | } |
9150 | 9205 | ||
9151 | /* Check for any encoders that needs to be disabled. */ |
9206 | /* Check for any encoders that needs to be disabled. */ |
9152 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9207 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9153 | base.head) { |
9208 | base.head) { |
9154 | list_for_each_entry(connector, |
9209 | list_for_each_entry(connector, |
9155 | &dev->mode_config.connector_list, |
9210 | &dev->mode_config.connector_list, |
9156 | base.head) { |
9211 | base.head) { |
9157 | if (connector->new_encoder == encoder) { |
9212 | if (connector->new_encoder == encoder) { |
9158 | WARN_ON(!connector->new_encoder->new_crtc); |
9213 | WARN_ON(!connector->new_encoder->new_crtc); |
9159 | 9214 | ||
9160 | goto next_encoder; |
9215 | goto next_encoder; |
9161 | } |
9216 | } |
9162 | } |
9217 | } |
9163 | encoder->new_crtc = NULL; |
9218 | encoder->new_crtc = NULL; |
9164 | next_encoder: |
9219 | next_encoder: |
9165 | /* Only now check for crtc changes so we don't miss encoders |
9220 | /* Only now check for crtc changes so we don't miss encoders |
9166 | * that will be disabled. */ |
9221 | * that will be disabled. */ |
9167 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
9222 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
9168 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
9223 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
9169 | config->mode_changed = true; |
9224 | config->mode_changed = true; |
9170 | } |
9225 | } |
9171 | } |
9226 | } |
9172 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
9227 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
9173 | 9228 | ||
9174 | return 0; |
9229 | return 0; |
9175 | } |
9230 | } |
9176 | 9231 | ||
9177 | static int intel_crtc_set_config(struct drm_mode_set *set) |
9232 | static int intel_crtc_set_config(struct drm_mode_set *set) |
9178 | { |
9233 | { |
9179 | struct drm_device *dev; |
9234 | struct drm_device *dev; |
9180 | struct drm_mode_set save_set; |
9235 | struct drm_mode_set save_set; |
9181 | struct intel_set_config *config; |
9236 | struct intel_set_config *config; |
9182 | int ret; |
9237 | int ret; |
9183 | 9238 | ||
9184 | BUG_ON(!set); |
9239 | BUG_ON(!set); |
9185 | BUG_ON(!set->crtc); |
9240 | BUG_ON(!set->crtc); |
9186 | BUG_ON(!set->crtc->helper_private); |
9241 | BUG_ON(!set->crtc->helper_private); |
9187 | 9242 | ||
9188 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9243 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9189 | BUG_ON(!set->mode && set->fb); |
9244 | BUG_ON(!set->mode && set->fb); |
9190 | BUG_ON(set->fb && set->num_connectors == 0); |
9245 | BUG_ON(set->fb && set->num_connectors == 0); |
9191 | 9246 | ||
9192 | if (set->fb) { |
9247 | if (set->fb) { |
9193 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
9248 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
9194 | set->crtc->base.id, set->fb->base.id, |
9249 | set->crtc->base.id, set->fb->base.id, |
9195 | (int)set->num_connectors, set->x, set->y); |
9250 | (int)set->num_connectors, set->x, set->y); |
9196 | } else { |
9251 | } else { |
9197 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
9252 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
9198 | } |
9253 | } |
9199 | 9254 | ||
9200 | dev = set->crtc->dev; |
9255 | dev = set->crtc->dev; |
9201 | 9256 | ||
9202 | ret = -ENOMEM; |
9257 | ret = -ENOMEM; |
9203 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
9258 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
9204 | if (!config) |
9259 | if (!config) |
9205 | goto out_config; |
9260 | goto out_config; |
9206 | 9261 | ||
9207 | ret = intel_set_config_save_state(dev, config); |
9262 | ret = intel_set_config_save_state(dev, config); |
9208 | if (ret) |
9263 | if (ret) |
9209 | goto out_config; |
9264 | goto out_config; |
9210 | 9265 | ||
9211 | save_set.crtc = set->crtc; |
9266 | save_set.crtc = set->crtc; |
9212 | save_set.mode = &set->crtc->mode; |
9267 | save_set.mode = &set->crtc->mode; |
9213 | save_set.x = set->crtc->x; |
9268 | save_set.x = set->crtc->x; |
9214 | save_set.y = set->crtc->y; |
9269 | save_set.y = set->crtc->y; |
9215 | save_set.fb = set->crtc->fb; |
9270 | save_set.fb = set->crtc->fb; |
9216 | 9271 | ||
9217 | /* Compute whether we need a full modeset, only an fb base update or no |
9272 | /* Compute whether we need a full modeset, only an fb base update or no |
9218 | * change at all. In the future we might also check whether only the |
9273 | * change at all. In the future we might also check whether only the |
9219 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
9274 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
9220 | * such cases. */ |
9275 | * such cases. */ |
9221 | intel_set_config_compute_mode_changes(set, config); |
9276 | intel_set_config_compute_mode_changes(set, config); |
9222 | 9277 | ||
9223 | ret = intel_modeset_stage_output_state(dev, set, config); |
9278 | ret = intel_modeset_stage_output_state(dev, set, config); |
9224 | if (ret) |
9279 | if (ret) |
9225 | goto fail; |
9280 | goto fail; |
9226 | 9281 | ||
9227 | if (config->mode_changed) { |
9282 | if (config->mode_changed) { |
9228 | ret = intel_set_mode(set->crtc, set->mode, |
9283 | ret = intel_set_mode(set->crtc, set->mode, |
9229 | set->x, set->y, set->fb); |
9284 | set->x, set->y, set->fb); |
9230 | } else if (config->fb_changed) { |
9285 | } else if (config->fb_changed) { |
9231 | // intel_crtc_wait_for_pending_flips(set->crtc); |
9286 | // intel_crtc_wait_for_pending_flips(set->crtc); |
9232 | 9287 | ||
9233 | ret = intel_pipe_set_base(set->crtc, |
9288 | ret = intel_pipe_set_base(set->crtc, |
9234 | set->x, set->y, set->fb); |
9289 | set->x, set->y, set->fb); |
9235 | } |
9290 | } |
9236 | 9291 | ||
9237 | if (ret) { |
9292 | if (ret) { |
9238 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9293 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9239 | set->crtc->base.id, ret); |
9294 | set->crtc->base.id, ret); |
9240 | fail: |
9295 | fail: |
9241 | intel_set_config_restore_state(dev, config); |
9296 | intel_set_config_restore_state(dev, config); |
9242 | 9297 | ||
9243 | /* Try to restore the config */ |
9298 | /* Try to restore the config */ |
9244 | if (config->mode_changed && |
9299 | if (config->mode_changed && |
9245 | intel_set_mode(save_set.crtc, save_set.mode, |
9300 | intel_set_mode(save_set.crtc, save_set.mode, |
9246 | save_set.x, save_set.y, save_set.fb)) |
9301 | save_set.x, save_set.y, save_set.fb)) |
9247 | DRM_ERROR("failed to restore config after modeset failure\n"); |
9302 | DRM_ERROR("failed to restore config after modeset failure\n"); |
9248 | } |
9303 | } |
9249 | 9304 | ||
9250 | out_config: |
9305 | out_config: |
9251 | intel_set_config_free(config); |
9306 | intel_set_config_free(config); |
9252 | return ret; |
9307 | return ret; |
9253 | } |
9308 | } |
9254 | 9309 | ||
9255 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
9310 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
9256 | // .cursor_set = intel_crtc_cursor_set, |
9311 | // .cursor_set = intel_crtc_cursor_set, |
9257 | // .cursor_move = intel_crtc_cursor_move, |
9312 | // .cursor_move = intel_crtc_cursor_move, |
9258 | .gamma_set = intel_crtc_gamma_set, |
9313 | .gamma_set = intel_crtc_gamma_set, |
9259 | .set_config = intel_crtc_set_config, |
9314 | .set_config = intel_crtc_set_config, |
9260 | .destroy = intel_crtc_destroy, |
9315 | .destroy = intel_crtc_destroy, |
9261 | // .page_flip = intel_crtc_page_flip, |
9316 | // .page_flip = intel_crtc_page_flip, |
9262 | }; |
9317 | }; |
9263 | 9318 | ||
9264 | static void intel_cpu_pll_init(struct drm_device *dev) |
9319 | static void intel_cpu_pll_init(struct drm_device *dev) |
9265 | { |
9320 | { |
9266 | if (HAS_DDI(dev)) |
9321 | if (HAS_DDI(dev)) |
9267 | intel_ddi_pll_init(dev); |
9322 | intel_ddi_pll_init(dev); |
9268 | } |
9323 | } |
9269 | 9324 | ||
9270 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9325 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9271 | struct intel_shared_dpll *pll, |
9326 | struct intel_shared_dpll *pll, |
9272 | struct intel_dpll_hw_state *hw_state) |
9327 | struct intel_dpll_hw_state *hw_state) |
9273 | { |
9328 | { |
9274 | uint32_t val; |
9329 | uint32_t val; |
9275 | 9330 | ||
9276 | val = I915_READ(PCH_DPLL(pll->id)); |
9331 | val = I915_READ(PCH_DPLL(pll->id)); |
9277 | hw_state->dpll = val; |
9332 | hw_state->dpll = val; |
9278 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
9333 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
9279 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
9334 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
9280 | 9335 | ||
9281 | return val & DPLL_VCO_ENABLE; |
9336 | return val & DPLL_VCO_ENABLE; |
9282 | } |
9337 | } |
9283 | 9338 | ||
9284 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
9339 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
9285 | struct intel_shared_dpll *pll) |
9340 | struct intel_shared_dpll *pll) |
9286 | { |
9341 | { |
9287 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
9342 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
9288 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
9343 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
9289 | } |
9344 | } |
9290 | 9345 | ||
9291 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9346 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9292 | struct intel_shared_dpll *pll) |
9347 | struct intel_shared_dpll *pll) |
9293 | { |
9348 | { |
9294 | /* PCH refclock must be enabled first */ |
9349 | /* PCH refclock must be enabled first */ |
9295 | assert_pch_refclk_enabled(dev_priv); |
9350 | assert_pch_refclk_enabled(dev_priv); |
9296 | 9351 | ||
9297 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9352 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9298 | 9353 | ||
9299 | /* Wait for the clocks to stabilize. */ |
9354 | /* Wait for the clocks to stabilize. */ |
9300 | POSTING_READ(PCH_DPLL(pll->id)); |
9355 | POSTING_READ(PCH_DPLL(pll->id)); |
9301 | udelay(150); |
9356 | udelay(150); |
9302 | 9357 | ||
9303 | /* The pixel multiplier can only be updated once the |
9358 | /* The pixel multiplier can only be updated once the |
9304 | * DPLL is enabled and the clocks are stable. |
9359 | * DPLL is enabled and the clocks are stable. |
9305 | * |
9360 | * |
9306 | * So write it again. |
9361 | * So write it again. |
9307 | */ |
9362 | */ |
9308 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9363 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9309 | POSTING_READ(PCH_DPLL(pll->id)); |
9364 | POSTING_READ(PCH_DPLL(pll->id)); |
9310 | udelay(200); |
9365 | udelay(200); |
9311 | } |
9366 | } |
9312 | 9367 | ||
9313 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
9368 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
9314 | struct intel_shared_dpll *pll) |
9369 | struct intel_shared_dpll *pll) |
9315 | { |
9370 | { |
9316 | struct drm_device *dev = dev_priv->dev; |
9371 | struct drm_device *dev = dev_priv->dev; |
9317 | struct intel_crtc *crtc; |
9372 | struct intel_crtc *crtc; |
9318 | 9373 | ||
9319 | /* Make sure no transcoder isn't still depending on us. */ |
9374 | /* Make sure no transcoder isn't still depending on us. */ |
9320 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
9375 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
9321 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
9376 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
9322 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
9377 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
9323 | } |
9378 | } |
9324 | 9379 | ||
9325 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9380 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9326 | POSTING_READ(PCH_DPLL(pll->id)); |
9381 | POSTING_READ(PCH_DPLL(pll->id)); |
9327 | udelay(200); |
9382 | udelay(200); |
9328 | } |
9383 | } |
9329 | 9384 | ||
9330 | static char *ibx_pch_dpll_names[] = { |
9385 | static char *ibx_pch_dpll_names[] = { |
9331 | "PCH DPLL A", |
9386 | "PCH DPLL A", |
9332 | "PCH DPLL B", |
9387 | "PCH DPLL B", |
9333 | }; |
9388 | }; |
9334 | 9389 | ||
9335 | static void ibx_pch_dpll_init(struct drm_device *dev) |
9390 | static void ibx_pch_dpll_init(struct drm_device *dev) |
9336 | { |
9391 | { |
9337 | struct drm_i915_private *dev_priv = dev->dev_private; |
9392 | struct drm_i915_private *dev_priv = dev->dev_private; |
9338 | int i; |
9393 | int i; |
9339 | 9394 | ||
9340 | dev_priv->num_shared_dpll = 2; |
9395 | dev_priv->num_shared_dpll = 2; |
9341 | 9396 | ||
9342 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9397 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9343 | dev_priv->shared_dplls[i].id = i; |
9398 | dev_priv->shared_dplls[i].id = i; |
9344 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
9399 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
9345 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
9400 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
9346 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
9401 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
9347 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
9402 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
9348 | dev_priv->shared_dplls[i].get_hw_state = |
9403 | dev_priv->shared_dplls[i].get_hw_state = |
9349 | ibx_pch_dpll_get_hw_state; |
9404 | ibx_pch_dpll_get_hw_state; |
9350 | } |
9405 | } |
9351 | } |
9406 | } |
9352 | 9407 | ||
9353 | static void intel_shared_dpll_init(struct drm_device *dev) |
9408 | static void intel_shared_dpll_init(struct drm_device *dev) |
9354 | { |
9409 | { |
9355 | struct drm_i915_private *dev_priv = dev->dev_private; |
9410 | struct drm_i915_private *dev_priv = dev->dev_private; |
9356 | 9411 | ||
9357 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
9412 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
9358 | ibx_pch_dpll_init(dev); |
9413 | ibx_pch_dpll_init(dev); |
9359 | else |
9414 | else |
9360 | dev_priv->num_shared_dpll = 0; |
9415 | dev_priv->num_shared_dpll = 0; |
9361 | 9416 | ||
9362 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
9417 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
9363 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", |
9418 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", |
9364 | dev_priv->num_shared_dpll); |
9419 | dev_priv->num_shared_dpll); |
9365 | } |
9420 | } |
9366 | 9421 | ||
9367 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
9422 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
9368 | { |
9423 | { |
9369 | drm_i915_private_t *dev_priv = dev->dev_private; |
9424 | drm_i915_private_t *dev_priv = dev->dev_private; |
9370 | struct intel_crtc *intel_crtc; |
9425 | struct intel_crtc *intel_crtc; |
9371 | int i; |
9426 | int i; |
9372 | 9427 | ||
9373 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
9428 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
9374 | if (intel_crtc == NULL) |
9429 | if (intel_crtc == NULL) |
9375 | return; |
9430 | return; |
9376 | 9431 | ||
9377 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
9432 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
9378 | 9433 | ||
9379 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
9434 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
9380 | for (i = 0; i < 256; i++) { |
9435 | for (i = 0; i < 256; i++) { |
9381 | intel_crtc->lut_r[i] = i; |
9436 | intel_crtc->lut_r[i] = i; |
9382 | intel_crtc->lut_g[i] = i; |
9437 | intel_crtc->lut_g[i] = i; |
9383 | intel_crtc->lut_b[i] = i; |
9438 | intel_crtc->lut_b[i] = i; |
9384 | } |
9439 | } |
9385 | 9440 | ||
9386 | /* Swap pipes & planes for FBC on pre-965 */ |
9441 | /* Swap pipes & planes for FBC on pre-965 */ |
9387 | intel_crtc->pipe = pipe; |
9442 | intel_crtc->pipe = pipe; |
9388 | intel_crtc->plane = pipe; |
9443 | intel_crtc->plane = pipe; |
9389 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
9444 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
9390 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
9445 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
9391 | intel_crtc->plane = !pipe; |
9446 | intel_crtc->plane = !pipe; |
9392 | } |
9447 | } |
9393 | 9448 | ||
9394 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9449 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9395 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
9450 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
9396 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
9451 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
9397 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
9452 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
9398 | 9453 | ||
9399 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
9454 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
9400 | } |
9455 | } |
9401 | 9456 | ||
9402 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
9457 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
9403 | struct drm_file *file) |
9458 | struct drm_file *file) |
9404 | { |
9459 | { |
9405 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
9460 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
9406 | struct drm_mode_object *drmmode_obj; |
9461 | struct drm_mode_object *drmmode_obj; |
9407 | struct intel_crtc *crtc; |
9462 | struct intel_crtc *crtc; |
9408 | 9463 | ||
9409 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9464 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9410 | return -ENODEV; |
9465 | return -ENODEV; |
9411 | 9466 | ||
9412 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9467 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9413 | DRM_MODE_OBJECT_CRTC); |
9468 | DRM_MODE_OBJECT_CRTC); |
9414 | 9469 | ||
9415 | if (!drmmode_obj) { |
9470 | if (!drmmode_obj) { |
9416 | DRM_ERROR("no such CRTC id\n"); |
9471 | DRM_ERROR("no such CRTC id\n"); |
9417 | return -EINVAL; |
9472 | return -EINVAL; |
9418 | } |
9473 | } |
9419 | 9474 | ||
9420 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9475 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9421 | pipe_from_crtc_id->pipe = crtc->pipe; |
9476 | pipe_from_crtc_id->pipe = crtc->pipe; |
9422 | 9477 | ||
9423 | return 0; |
9478 | return 0; |
9424 | } |
9479 | } |
9425 | 9480 | ||
9426 | static int intel_encoder_clones(struct intel_encoder *encoder) |
9481 | static int intel_encoder_clones(struct intel_encoder *encoder) |
9427 | { |
9482 | { |
9428 | struct drm_device *dev = encoder->base.dev; |
9483 | struct drm_device *dev = encoder->base.dev; |
9429 | struct intel_encoder *source_encoder; |
9484 | struct intel_encoder *source_encoder; |
9430 | int index_mask = 0; |
9485 | int index_mask = 0; |
9431 | int entry = 0; |
9486 | int entry = 0; |
9432 | 9487 | ||
9433 | list_for_each_entry(source_encoder, |
9488 | list_for_each_entry(source_encoder, |
9434 | &dev->mode_config.encoder_list, base.head) { |
9489 | &dev->mode_config.encoder_list, base.head) { |
9435 | 9490 | ||
9436 | if (encoder == source_encoder) |
9491 | if (encoder == source_encoder) |
9437 | index_mask |= (1 << entry); |
9492 | index_mask |= (1 << entry); |
9438 | 9493 | ||
9439 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
9494 | /* Intel hw has only one MUX where enocoders could be cloned. */ |
9440 | if (encoder->cloneable && source_encoder->cloneable) |
9495 | if (encoder->cloneable && source_encoder->cloneable) |
9441 | index_mask |= (1 << entry); |
9496 | index_mask |= (1 << entry); |
9442 | 9497 | ||
9443 | entry++; |
9498 | entry++; |
9444 | } |
9499 | } |
9445 | 9500 | ||
9446 | return index_mask; |
9501 | return index_mask; |
9447 | } |
9502 | } |
9448 | 9503 | ||
9449 | static bool has_edp_a(struct drm_device *dev) |
9504 | static bool has_edp_a(struct drm_device *dev) |
9450 | { |
9505 | { |
9451 | struct drm_i915_private *dev_priv = dev->dev_private; |
9506 | struct drm_i915_private *dev_priv = dev->dev_private; |
9452 | 9507 | ||
9453 | if (!IS_MOBILE(dev)) |
9508 | if (!IS_MOBILE(dev)) |
9454 | return false; |
9509 | return false; |
9455 | 9510 | ||
9456 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
9511 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
9457 | return false; |
9512 | return false; |
9458 | 9513 | ||
9459 | if (IS_GEN5(dev) && |
9514 | if (IS_GEN5(dev) && |
9460 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
9515 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
9461 | return false; |
9516 | return false; |
9462 | 9517 | ||
9463 | return true; |
9518 | return true; |
9464 | } |
9519 | } |
9465 | 9520 | ||
9466 | static void intel_setup_outputs(struct drm_device *dev) |
9521 | static void intel_setup_outputs(struct drm_device *dev) |
9467 | { |
9522 | { |
9468 | struct drm_i915_private *dev_priv = dev->dev_private; |
9523 | struct drm_i915_private *dev_priv = dev->dev_private; |
9469 | struct intel_encoder *encoder; |
9524 | struct intel_encoder *encoder; |
9470 | bool dpd_is_edp = false; |
9525 | bool dpd_is_edp = false; |
9471 | 9526 | ||
9472 | intel_lvds_init(dev); |
9527 | intel_lvds_init(dev); |
9473 | 9528 | ||
9474 | if (!IS_ULT(dev)) |
9529 | if (!IS_ULT(dev)) |
9475 | intel_crt_init(dev); |
9530 | intel_crt_init(dev); |
9476 | 9531 | ||
9477 | if (HAS_DDI(dev)) { |
9532 | if (HAS_DDI(dev)) { |
9478 | int found; |
9533 | int found; |
9479 | 9534 | ||
9480 | /* Haswell uses DDI functions to detect digital outputs */ |
9535 | /* Haswell uses DDI functions to detect digital outputs */ |
9481 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
9536 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
9482 | /* DDI A only supports eDP */ |
9537 | /* DDI A only supports eDP */ |
9483 | if (found) |
9538 | if (found) |
9484 | intel_ddi_init(dev, PORT_A); |
9539 | intel_ddi_init(dev, PORT_A); |
9485 | 9540 | ||
9486 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
9541 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
9487 | * register */ |
9542 | * register */ |
9488 | found = I915_READ(SFUSE_STRAP); |
9543 | found = I915_READ(SFUSE_STRAP); |
9489 | 9544 | ||
9490 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
9545 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
9491 | intel_ddi_init(dev, PORT_B); |
9546 | intel_ddi_init(dev, PORT_B); |
9492 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
9547 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
9493 | intel_ddi_init(dev, PORT_C); |
9548 | intel_ddi_init(dev, PORT_C); |
9494 | if (found & SFUSE_STRAP_DDID_DETECTED) |
9549 | if (found & SFUSE_STRAP_DDID_DETECTED) |
9495 | intel_ddi_init(dev, PORT_D); |
9550 | intel_ddi_init(dev, PORT_D); |
9496 | } else if (HAS_PCH_SPLIT(dev)) { |
9551 | } else if (HAS_PCH_SPLIT(dev)) { |
9497 | int found; |
9552 | int found; |
9498 | dpd_is_edp = intel_dpd_is_edp(dev); |
9553 | dpd_is_edp = intel_dpd_is_edp(dev); |
9499 | 9554 | ||
9500 | if (has_edp_a(dev)) |
9555 | if (has_edp_a(dev)) |
9501 | intel_dp_init(dev, DP_A, PORT_A); |
9556 | intel_dp_init(dev, DP_A, PORT_A); |
9502 | 9557 | ||
9503 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
9558 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
9504 | /* PCH SDVOB multiplex with HDMIB */ |
9559 | /* PCH SDVOB multiplex with HDMIB */ |
9505 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
9560 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
9506 | if (!found) |
9561 | if (!found) |
9507 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
9562 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
9508 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
9563 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
9509 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
9564 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
9510 | } |
9565 | } |
9511 | 9566 | ||
9512 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
9567 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
9513 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
9568 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
9514 | 9569 | ||
9515 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
9570 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
9516 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
9571 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
9517 | 9572 | ||
9518 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
9573 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
9519 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
9574 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
9520 | 9575 | ||
9521 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
9576 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
9522 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
9577 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
9523 | } else if (IS_VALLEYVIEW(dev)) { |
9578 | } else if (IS_VALLEYVIEW(dev)) { |
9524 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
9579 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
9525 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9580 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9526 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
9581 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
9527 | PORT_C); |
9582 | PORT_C); |
9528 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
9583 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
9529 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, |
9584 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, |
9530 | PORT_C); |
9585 | PORT_C); |
9531 | } |
9586 | } |
9532 | 9587 | ||
9533 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
9588 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
9534 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9589 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9535 | PORT_B); |
9590 | PORT_B); |
9536 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9591 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9537 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
9592 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
9538 | } |
9593 | } |
9539 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
9594 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
9540 | bool found = false; |
9595 | bool found = false; |
9541 | 9596 | ||
9542 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9597 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9543 | DRM_DEBUG_KMS("probing SDVOB\n"); |
9598 | DRM_DEBUG_KMS("probing SDVOB\n"); |
9544 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
9599 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
9545 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9600 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9546 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
9601 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
9547 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
9602 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
9548 | } |
9603 | } |
9549 | 9604 | ||
9550 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
9605 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
9551 | intel_dp_init(dev, DP_B, PORT_B); |
9606 | intel_dp_init(dev, DP_B, PORT_B); |
9552 | } |
9607 | } |
9553 | 9608 | ||
9554 | /* Before G4X SDVOC doesn't have its own detect register */ |
9609 | /* Before G4X SDVOC doesn't have its own detect register */ |
9555 | 9610 | ||
9556 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9611 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
9557 | DRM_DEBUG_KMS("probing SDVOC\n"); |
9612 | DRM_DEBUG_KMS("probing SDVOC\n"); |
9558 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
9613 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
9559 | } |
9614 | } |
9560 | 9615 | ||
9561 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
9616 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
9562 | 9617 | ||
9563 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9618 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9564 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
9619 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
9565 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
9620 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
9566 | } |
9621 | } |
9567 | if (SUPPORTS_INTEGRATED_DP(dev)) |
9622 | if (SUPPORTS_INTEGRATED_DP(dev)) |
9568 | intel_dp_init(dev, DP_C, PORT_C); |
9623 | intel_dp_init(dev, DP_C, PORT_C); |
9569 | } |
9624 | } |
9570 | 9625 | ||
9571 | if (SUPPORTS_INTEGRATED_DP(dev) && |
9626 | if (SUPPORTS_INTEGRATED_DP(dev) && |
9572 | (I915_READ(DP_D) & DP_DETECTED)) |
9627 | (I915_READ(DP_D) & DP_DETECTED)) |
9573 | intel_dp_init(dev, DP_D, PORT_D); |
9628 | intel_dp_init(dev, DP_D, PORT_D); |
9574 | } else if (IS_GEN2(dev)) |
9629 | } else if (IS_GEN2(dev)) |
9575 | intel_dvo_init(dev); |
9630 | intel_dvo_init(dev); |
9576 | 9631 | ||
9577 | // if (SUPPORTS_TV(dev)) |
9632 | // if (SUPPORTS_TV(dev)) |
9578 | // intel_tv_init(dev); |
9633 | // intel_tv_init(dev); |
9579 | 9634 | ||
9580 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9635 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9581 | encoder->base.possible_crtcs = encoder->crtc_mask; |
9636 | encoder->base.possible_crtcs = encoder->crtc_mask; |
9582 | encoder->base.possible_clones = |
9637 | encoder->base.possible_clones = |
9583 | intel_encoder_clones(encoder); |
9638 | intel_encoder_clones(encoder); |
9584 | } |
9639 | } |
9585 | 9640 | ||
9586 | intel_init_pch_refclk(dev); |
9641 | intel_init_pch_refclk(dev); |
9587 | 9642 | ||
9588 | drm_helper_move_panel_connectors_to_head(dev); |
9643 | drm_helper_move_panel_connectors_to_head(dev); |
9589 | } |
9644 | } |
9590 | 9645 | ||
9591 | 9646 | ||
9592 | 9647 | ||
9593 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
9648 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
9594 | // .destroy = intel_user_framebuffer_destroy, |
9649 | // .destroy = intel_user_framebuffer_destroy, |
9595 | // .create_handle = intel_user_framebuffer_create_handle, |
9650 | // .create_handle = intel_user_framebuffer_create_handle, |
9596 | }; |
9651 | }; |
9597 | 9652 | ||
9598 | int intel_framebuffer_init(struct drm_device *dev, |
9653 | int intel_framebuffer_init(struct drm_device *dev, |
9599 | struct intel_framebuffer *intel_fb, |
9654 | struct intel_framebuffer *intel_fb, |
9600 | struct drm_mode_fb_cmd2 *mode_cmd, |
9655 | struct drm_mode_fb_cmd2 *mode_cmd, |
9601 | struct drm_i915_gem_object *obj) |
9656 | struct drm_i915_gem_object *obj) |
9602 | { |
9657 | { |
9603 | int pitch_limit; |
9658 | int pitch_limit; |
9604 | int ret; |
9659 | int ret; |
9605 | 9660 | ||
9606 | if (obj->tiling_mode == I915_TILING_Y) { |
9661 | if (obj->tiling_mode == I915_TILING_Y) { |
9607 | DRM_DEBUG("hardware does not support tiling Y\n"); |
9662 | DRM_DEBUG("hardware does not support tiling Y\n"); |
9608 | return -EINVAL; |
9663 | return -EINVAL; |
9609 | } |
9664 | } |
9610 | 9665 | ||
9611 | if (mode_cmd->pitches[0] & 63) { |
9666 | if (mode_cmd->pitches[0] & 63) { |
9612 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
9667 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
9613 | mode_cmd->pitches[0]); |
9668 | mode_cmd->pitches[0]); |
9614 | return -EINVAL; |
9669 | return -EINVAL; |
9615 | } |
9670 | } |
9616 | 9671 | ||
9617 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9672 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9618 | pitch_limit = 32*1024; |
9673 | pitch_limit = 32*1024; |
9619 | } else if (INTEL_INFO(dev)->gen >= 4) { |
9674 | } else if (INTEL_INFO(dev)->gen >= 4) { |
9620 | if (obj->tiling_mode) |
9675 | if (obj->tiling_mode) |
9621 | pitch_limit = 16*1024; |
9676 | pitch_limit = 16*1024; |
9622 | else |
9677 | else |
9623 | pitch_limit = 32*1024; |
9678 | pitch_limit = 32*1024; |
9624 | } else if (INTEL_INFO(dev)->gen >= 3) { |
9679 | } else if (INTEL_INFO(dev)->gen >= 3) { |
9625 | if (obj->tiling_mode) |
9680 | if (obj->tiling_mode) |
9626 | pitch_limit = 8*1024; |
9681 | pitch_limit = 8*1024; |
9627 | else |
9682 | else |
9628 | pitch_limit = 16*1024; |
9683 | pitch_limit = 16*1024; |
9629 | } else |
9684 | } else |
9630 | /* XXX DSPC is limited to 4k tiled */ |
9685 | /* XXX DSPC is limited to 4k tiled */ |
9631 | pitch_limit = 8*1024; |
9686 | pitch_limit = 8*1024; |
9632 | 9687 | ||
9633 | if (mode_cmd->pitches[0] > pitch_limit) { |
9688 | if (mode_cmd->pitches[0] > pitch_limit) { |
9634 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
9689 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
9635 | obj->tiling_mode ? "tiled" : "linear", |
9690 | obj->tiling_mode ? "tiled" : "linear", |
9636 | mode_cmd->pitches[0], pitch_limit); |
9691 | mode_cmd->pitches[0], pitch_limit); |
9637 | return -EINVAL; |
9692 | return -EINVAL; |
9638 | } |
9693 | } |
9639 | 9694 | ||
9640 | if (obj->tiling_mode != I915_TILING_NONE && |
9695 | if (obj->tiling_mode != I915_TILING_NONE && |
9641 | mode_cmd->pitches[0] != obj->stride) { |
9696 | mode_cmd->pitches[0] != obj->stride) { |
9642 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
9697 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
9643 | mode_cmd->pitches[0], obj->stride); |
9698 | mode_cmd->pitches[0], obj->stride); |
9644 | return -EINVAL; |
9699 | return -EINVAL; |
9645 | } |
9700 | } |
9646 | 9701 | ||
9647 | /* Reject formats not supported by any plane early. */ |
9702 | /* Reject formats not supported by any plane early. */ |
9648 | switch (mode_cmd->pixel_format) { |
9703 | switch (mode_cmd->pixel_format) { |
9649 | case DRM_FORMAT_C8: |
9704 | case DRM_FORMAT_C8: |
9650 | case DRM_FORMAT_RGB565: |
9705 | case DRM_FORMAT_RGB565: |
9651 | case DRM_FORMAT_XRGB8888: |
9706 | case DRM_FORMAT_XRGB8888: |
9652 | case DRM_FORMAT_ARGB8888: |
9707 | case DRM_FORMAT_ARGB8888: |
9653 | break; |
9708 | break; |
9654 | case DRM_FORMAT_XRGB1555: |
9709 | case DRM_FORMAT_XRGB1555: |
9655 | case DRM_FORMAT_ARGB1555: |
9710 | case DRM_FORMAT_ARGB1555: |
9656 | if (INTEL_INFO(dev)->gen > 3) { |
9711 | if (INTEL_INFO(dev)->gen > 3) { |
9657 | DRM_DEBUG("unsupported pixel format: %s\n", |
9712 | DRM_DEBUG("unsupported pixel format: %s\n", |
9658 | drm_get_format_name(mode_cmd->pixel_format)); |
9713 | drm_get_format_name(mode_cmd->pixel_format)); |
9659 | return -EINVAL; |
9714 | return -EINVAL; |
9660 | } |
9715 | } |
9661 | break; |
9716 | break; |
9662 | case DRM_FORMAT_XBGR8888: |
9717 | case DRM_FORMAT_XBGR8888: |
9663 | case DRM_FORMAT_ABGR8888: |
9718 | case DRM_FORMAT_ABGR8888: |
9664 | case DRM_FORMAT_XRGB2101010: |
9719 | case DRM_FORMAT_XRGB2101010: |
9665 | case DRM_FORMAT_ARGB2101010: |
9720 | case DRM_FORMAT_ARGB2101010: |
9666 | case DRM_FORMAT_XBGR2101010: |
9721 | case DRM_FORMAT_XBGR2101010: |
9667 | case DRM_FORMAT_ABGR2101010: |
9722 | case DRM_FORMAT_ABGR2101010: |
9668 | if (INTEL_INFO(dev)->gen < 4) { |
9723 | if (INTEL_INFO(dev)->gen < 4) { |
9669 | DRM_DEBUG("unsupported pixel format: %s\n", |
9724 | DRM_DEBUG("unsupported pixel format: %s\n", |
9670 | drm_get_format_name(mode_cmd->pixel_format)); |
9725 | drm_get_format_name(mode_cmd->pixel_format)); |
9671 | return -EINVAL; |
9726 | return -EINVAL; |
9672 | } |
9727 | } |
9673 | break; |
9728 | break; |
9674 | case DRM_FORMAT_YUYV: |
9729 | case DRM_FORMAT_YUYV: |
9675 | case DRM_FORMAT_UYVY: |
9730 | case DRM_FORMAT_UYVY: |
9676 | case DRM_FORMAT_YVYU: |
9731 | case DRM_FORMAT_YVYU: |
9677 | case DRM_FORMAT_VYUY: |
9732 | case DRM_FORMAT_VYUY: |
9678 | if (INTEL_INFO(dev)->gen < 5) { |
9733 | if (INTEL_INFO(dev)->gen < 5) { |
9679 | DRM_DEBUG("unsupported pixel format: %s\n", |
9734 | DRM_DEBUG("unsupported pixel format: %s\n", |
9680 | drm_get_format_name(mode_cmd->pixel_format)); |
9735 | drm_get_format_name(mode_cmd->pixel_format)); |
9681 | return -EINVAL; |
9736 | return -EINVAL; |
9682 | } |
9737 | } |
9683 | break; |
9738 | break; |
9684 | default: |
9739 | default: |
9685 | DRM_DEBUG("unsupported pixel format: %s\n", |
9740 | DRM_DEBUG("unsupported pixel format: %s\n", |
9686 | drm_get_format_name(mode_cmd->pixel_format)); |
9741 | drm_get_format_name(mode_cmd->pixel_format)); |
9687 | return -EINVAL; |
9742 | return -EINVAL; |
9688 | } |
9743 | } |
9689 | 9744 | ||
9690 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9745 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9691 | if (mode_cmd->offsets[0] != 0) |
9746 | if (mode_cmd->offsets[0] != 0) |
9692 | return -EINVAL; |
9747 | return -EINVAL; |
9693 | 9748 | ||
9694 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
9749 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
9695 | intel_fb->obj = obj; |
9750 | intel_fb->obj = obj; |
9696 | 9751 | ||
9697 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9752 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9698 | if (ret) { |
9753 | if (ret) { |
9699 | DRM_ERROR("framebuffer init failed %d\n", ret); |
9754 | DRM_ERROR("framebuffer init failed %d\n", ret); |
9700 | return ret; |
9755 | return ret; |
9701 | } |
9756 | } |
9702 | 9757 | ||
9703 | return 0; |
9758 | return 0; |
9704 | } |
9759 | } |
9705 | 9760 | ||
9706 | 9761 | ||
9707 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
9762 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
9708 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
9763 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
9709 | .output_poll_changed = intel_fb_output_poll_changed, |
9764 | .output_poll_changed = intel_fb_output_poll_changed, |
9710 | }; |
9765 | }; |
9711 | 9766 | ||
9712 | /* Set up chip specific display functions */ |
9767 | /* Set up chip specific display functions */ |
9713 | static void intel_init_display(struct drm_device *dev) |
9768 | static void intel_init_display(struct drm_device *dev) |
9714 | { |
9769 | { |
9715 | struct drm_i915_private *dev_priv = dev->dev_private; |
9770 | struct drm_i915_private *dev_priv = dev->dev_private; |
9716 | 9771 | ||
9717 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
9772 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
9718 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
9773 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
9719 | else if (IS_VALLEYVIEW(dev)) |
9774 | else if (IS_VALLEYVIEW(dev)) |
9720 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
9775 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
9721 | else if (IS_PINEVIEW(dev)) |
9776 | else if (IS_PINEVIEW(dev)) |
9722 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
9777 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
9723 | else |
9778 | else |
9724 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
9779 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
9725 | 9780 | ||
9726 | if (HAS_DDI(dev)) { |
9781 | if (HAS_DDI(dev)) { |
9727 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
9782 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
9728 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
9783 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
9729 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
9784 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
9730 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
9785 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
9731 | dev_priv->display.off = haswell_crtc_off; |
9786 | dev_priv->display.off = haswell_crtc_off; |
9732 | dev_priv->display.update_plane = ironlake_update_plane; |
9787 | dev_priv->display.update_plane = ironlake_update_plane; |
9733 | } else if (HAS_PCH_SPLIT(dev)) { |
9788 | } else if (HAS_PCH_SPLIT(dev)) { |
9734 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
9789 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
9735 | dev_priv->display.get_clock = ironlake_crtc_clock_get; |
9790 | dev_priv->display.get_clock = ironlake_crtc_clock_get; |
9736 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
9791 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
9737 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9792 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9738 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
9793 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
9739 | dev_priv->display.off = ironlake_crtc_off; |
9794 | dev_priv->display.off = ironlake_crtc_off; |
9740 | dev_priv->display.update_plane = ironlake_update_plane; |
9795 | dev_priv->display.update_plane = ironlake_update_plane; |
9741 | } else if (IS_VALLEYVIEW(dev)) { |
9796 | } else if (IS_VALLEYVIEW(dev)) { |
9742 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9797 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9743 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
9798 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
9744 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9799 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9745 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
9800 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
9746 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9801 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9747 | dev_priv->display.off = i9xx_crtc_off; |
9802 | dev_priv->display.off = i9xx_crtc_off; |
9748 | dev_priv->display.update_plane = i9xx_update_plane; |
9803 | dev_priv->display.update_plane = i9xx_update_plane; |
9749 | } else { |
9804 | } else { |
9750 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9805 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
9751 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
9806 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
9752 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9807 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9753 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
9808 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
9754 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9809 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
9755 | dev_priv->display.off = i9xx_crtc_off; |
9810 | dev_priv->display.off = i9xx_crtc_off; |
9756 | dev_priv->display.update_plane = i9xx_update_plane; |
9811 | dev_priv->display.update_plane = i9xx_update_plane; |
9757 | } |
9812 | } |
9758 | 9813 | ||
9759 | /* Returns the core display clock speed */ |
9814 | /* Returns the core display clock speed */ |
9760 | if (IS_VALLEYVIEW(dev)) |
9815 | if (IS_VALLEYVIEW(dev)) |
9761 | dev_priv->display.get_display_clock_speed = |
9816 | dev_priv->display.get_display_clock_speed = |
9762 | valleyview_get_display_clock_speed; |
9817 | valleyview_get_display_clock_speed; |
9763 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
9818 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
9764 | dev_priv->display.get_display_clock_speed = |
9819 | dev_priv->display.get_display_clock_speed = |
9765 | i945_get_display_clock_speed; |
9820 | i945_get_display_clock_speed; |
9766 | else if (IS_I915G(dev)) |
9821 | else if (IS_I915G(dev)) |
9767 | dev_priv->display.get_display_clock_speed = |
9822 | dev_priv->display.get_display_clock_speed = |
9768 | i915_get_display_clock_speed; |
9823 | i915_get_display_clock_speed; |
9769 | else if (IS_I945GM(dev) || IS_845G(dev)) |
9824 | else if (IS_I945GM(dev) || IS_845G(dev)) |
9770 | dev_priv->display.get_display_clock_speed = |
9825 | dev_priv->display.get_display_clock_speed = |
9771 | i9xx_misc_get_display_clock_speed; |
9826 | i9xx_misc_get_display_clock_speed; |
9772 | else if (IS_PINEVIEW(dev)) |
9827 | else if (IS_PINEVIEW(dev)) |
9773 | dev_priv->display.get_display_clock_speed = |
9828 | dev_priv->display.get_display_clock_speed = |
9774 | pnv_get_display_clock_speed; |
9829 | pnv_get_display_clock_speed; |
9775 | else if (IS_I915GM(dev)) |
9830 | else if (IS_I915GM(dev)) |
9776 | dev_priv->display.get_display_clock_speed = |
9831 | dev_priv->display.get_display_clock_speed = |
9777 | i915gm_get_display_clock_speed; |
9832 | i915gm_get_display_clock_speed; |
9778 | else if (IS_I865G(dev)) |
9833 | else if (IS_I865G(dev)) |
9779 | dev_priv->display.get_display_clock_speed = |
9834 | dev_priv->display.get_display_clock_speed = |
9780 | i865_get_display_clock_speed; |
9835 | i865_get_display_clock_speed; |
9781 | else if (IS_I85X(dev)) |
9836 | else if (IS_I85X(dev)) |
9782 | dev_priv->display.get_display_clock_speed = |
9837 | dev_priv->display.get_display_clock_speed = |
9783 | i855_get_display_clock_speed; |
9838 | i855_get_display_clock_speed; |
9784 | else /* 852, 830 */ |
9839 | else /* 852, 830 */ |
9785 | dev_priv->display.get_display_clock_speed = |
9840 | dev_priv->display.get_display_clock_speed = |
9786 | i830_get_display_clock_speed; |
9841 | i830_get_display_clock_speed; |
9787 | 9842 | ||
9788 | if (HAS_PCH_SPLIT(dev)) { |
9843 | if (HAS_PCH_SPLIT(dev)) { |
9789 | if (IS_GEN5(dev)) { |
9844 | if (IS_GEN5(dev)) { |
9790 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
9845 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
9791 | dev_priv->display.write_eld = ironlake_write_eld; |
9846 | dev_priv->display.write_eld = ironlake_write_eld; |
9792 | } else if (IS_GEN6(dev)) { |
9847 | } else if (IS_GEN6(dev)) { |
9793 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
9848 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
9794 | dev_priv->display.write_eld = ironlake_write_eld; |
9849 | dev_priv->display.write_eld = ironlake_write_eld; |
9795 | } else if (IS_IVYBRIDGE(dev)) { |
9850 | } else if (IS_IVYBRIDGE(dev)) { |
9796 | /* FIXME: detect B0+ stepping and use auto training */ |
9851 | /* FIXME: detect B0+ stepping and use auto training */ |
9797 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
9852 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
9798 | dev_priv->display.write_eld = ironlake_write_eld; |
9853 | dev_priv->display.write_eld = ironlake_write_eld; |
9799 | dev_priv->display.modeset_global_resources = |
9854 | dev_priv->display.modeset_global_resources = |
9800 | ivb_modeset_global_resources; |
9855 | ivb_modeset_global_resources; |
9801 | } else if (IS_HASWELL(dev)) { |
9856 | } else if (IS_HASWELL(dev)) { |
9802 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
9857 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
9803 | dev_priv->display.write_eld = haswell_write_eld; |
9858 | dev_priv->display.write_eld = haswell_write_eld; |
9804 | dev_priv->display.modeset_global_resources = |
9859 | dev_priv->display.modeset_global_resources = |
9805 | haswell_modeset_global_resources; |
9860 | haswell_modeset_global_resources; |
9806 | } |
9861 | } |
9807 | } else if (IS_G4X(dev)) { |
9862 | } else if (IS_G4X(dev)) { |
9808 | dev_priv->display.write_eld = g4x_write_eld; |
9863 | dev_priv->display.write_eld = g4x_write_eld; |
9809 | } |
9864 | } |
9810 | 9865 | ||
9811 | /* Default just returns -ENODEV to indicate unsupported */ |
9866 | /* Default just returns -ENODEV to indicate unsupported */ |
9812 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
9867 | // dev_priv->display.queue_flip = intel_default_queue_flip; |
9813 | 9868 | ||
9814 | 9869 | ||
9815 | 9870 | ||
9816 | 9871 | ||
9817 | } |
9872 | } |
9818 | 9873 | ||
9819 | /* |
9874 | /* |
9820 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
9875 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
9821 | * resume, or other times. This quirk makes sure that's the case for |
9876 | * resume, or other times. This quirk makes sure that's the case for |
9822 | * affected systems. |
9877 | * affected systems. |
9823 | */ |
9878 | */ |
9824 | static void quirk_pipea_force(struct drm_device *dev) |
9879 | static void quirk_pipea_force(struct drm_device *dev) |
9825 | { |
9880 | { |
9826 | struct drm_i915_private *dev_priv = dev->dev_private; |
9881 | struct drm_i915_private *dev_priv = dev->dev_private; |
9827 | 9882 | ||
9828 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
9883 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
9829 | DRM_INFO("applying pipe a force quirk\n"); |
9884 | DRM_INFO("applying pipe a force quirk\n"); |
9830 | } |
9885 | } |
9831 | 9886 | ||
9832 | /* |
9887 | /* |
9833 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
9888 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
9834 | */ |
9889 | */ |
9835 | static void quirk_ssc_force_disable(struct drm_device *dev) |
9890 | static void quirk_ssc_force_disable(struct drm_device *dev) |
9836 | { |
9891 | { |
9837 | struct drm_i915_private *dev_priv = dev->dev_private; |
9892 | struct drm_i915_private *dev_priv = dev->dev_private; |
9838 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
9893 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
9839 | DRM_INFO("applying lvds SSC disable quirk\n"); |
9894 | DRM_INFO("applying lvds SSC disable quirk\n"); |
9840 | } |
9895 | } |
9841 | 9896 | ||
9842 | /* |
9897 | /* |
9843 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9898 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9844 | * brightness value |
9899 | * brightness value |
9845 | */ |
9900 | */ |
9846 | static void quirk_invert_brightness(struct drm_device *dev) |
9901 | static void quirk_invert_brightness(struct drm_device *dev) |
9847 | { |
9902 | { |
9848 | struct drm_i915_private *dev_priv = dev->dev_private; |
9903 | struct drm_i915_private *dev_priv = dev->dev_private; |
9849 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
9904 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
9850 | DRM_INFO("applying inverted panel brightness quirk\n"); |
9905 | DRM_INFO("applying inverted panel brightness quirk\n"); |
9851 | } |
9906 | } |
9852 | 9907 | ||
9853 | /* |
9908 | /* |
9854 | * Some machines (Dell XPS13) suffer broken backlight controls if |
9909 | * Some machines (Dell XPS13) suffer broken backlight controls if |
9855 | * BLM_PCH_PWM_ENABLE is set. |
9910 | * BLM_PCH_PWM_ENABLE is set. |
9856 | */ |
9911 | */ |
9857 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) |
9912 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) |
9858 | { |
9913 | { |
9859 | struct drm_i915_private *dev_priv = dev->dev_private; |
9914 | struct drm_i915_private *dev_priv = dev->dev_private; |
9860 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; |
9915 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; |
9861 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); |
9916 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); |
9862 | } |
9917 | } |
9863 | 9918 | ||
9864 | struct intel_quirk { |
9919 | struct intel_quirk { |
9865 | int device; |
9920 | int device; |
9866 | int subsystem_vendor; |
9921 | int subsystem_vendor; |
9867 | int subsystem_device; |
9922 | int subsystem_device; |
9868 | void (*hook)(struct drm_device *dev); |
9923 | void (*hook)(struct drm_device *dev); |
9869 | }; |
9924 | }; |
9870 | 9925 | ||
9871 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
9926 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
9872 | struct intel_dmi_quirk { |
9927 | struct intel_dmi_quirk { |
9873 | void (*hook)(struct drm_device *dev); |
9928 | void (*hook)(struct drm_device *dev); |
9874 | const struct dmi_system_id (*dmi_id_list)[]; |
9929 | const struct dmi_system_id (*dmi_id_list)[]; |
9875 | }; |
9930 | }; |
9876 | 9931 | ||
9877 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
9932 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
9878 | { |
9933 | { |
9879 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
9934 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
9880 | return 1; |
9935 | return 1; |
9881 | } |
9936 | } |
9882 | 9937 | ||
9883 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
9938 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
9884 | { |
9939 | { |
9885 | .dmi_id_list = &(const struct dmi_system_id[]) { |
9940 | .dmi_id_list = &(const struct dmi_system_id[]) { |
9886 | { |
9941 | { |
9887 | .callback = intel_dmi_reverse_brightness, |
9942 | .callback = intel_dmi_reverse_brightness, |
9888 | .ident = "NCR Corporation", |
9943 | .ident = "NCR Corporation", |
9889 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
9944 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
9890 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
9945 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
9891 | }, |
9946 | }, |
9892 | }, |
9947 | }, |
9893 | { } /* terminating entry */ |
9948 | { } /* terminating entry */ |
9894 | }, |
9949 | }, |
9895 | .hook = quirk_invert_brightness, |
9950 | .hook = quirk_invert_brightness, |
9896 | }, |
9951 | }, |
9897 | }; |
9952 | }; |
9898 | 9953 | ||
9899 | static struct intel_quirk intel_quirks[] = { |
9954 | static struct intel_quirk intel_quirks[] = { |
9900 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
9955 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
9901 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
9956 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
9902 | 9957 | ||
9903 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
9958 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
9904 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
9959 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
9905 | 9960 | ||
9906 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
9961 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
9907 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
9962 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
9908 | 9963 | ||
9909 | /* 830/845 need to leave pipe A & dpll A up */ |
9964 | /* 830/845 need to leave pipe A & dpll A up */ |
9910 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
9965 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
9911 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
9966 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
9912 | 9967 | ||
9913 | /* Lenovo U160 cannot use SSC on LVDS */ |
9968 | /* Lenovo U160 cannot use SSC on LVDS */ |
9914 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
9969 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
9915 | 9970 | ||
9916 | /* Sony Vaio Y cannot use SSC on LVDS */ |
9971 | /* Sony Vaio Y cannot use SSC on LVDS */ |
9917 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
9972 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
9918 | 9973 | ||
9919 | /* Acer Aspire 5734Z must invert backlight brightness */ |
9974 | /* Acer Aspire 5734Z must invert backlight brightness */ |
9920 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
9975 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
9921 | 9976 | ||
9922 | /* Acer/eMachines G725 */ |
9977 | /* Acer/eMachines G725 */ |
9923 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
9978 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
9924 | 9979 | ||
9925 | /* Acer/eMachines e725 */ |
9980 | /* Acer/eMachines e725 */ |
9926 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
9981 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
9927 | 9982 | ||
9928 | /* Acer/Packard Bell NCL20 */ |
9983 | /* Acer/Packard Bell NCL20 */ |
9929 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
9984 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
9930 | 9985 | ||
9931 | /* Acer Aspire 4736Z */ |
9986 | /* Acer Aspire 4736Z */ |
9932 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
9987 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
9933 | 9988 | ||
9934 | /* Dell XPS13 HD Sandy Bridge */ |
9989 | /* Dell XPS13 HD Sandy Bridge */ |
9935 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, |
9990 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, |
9936 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ |
9991 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ |
9937 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, |
9992 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, |
9938 | }; |
9993 | }; |
9939 | 9994 | ||
9940 | static void intel_init_quirks(struct drm_device *dev) |
9995 | static void intel_init_quirks(struct drm_device *dev) |
9941 | { |
9996 | { |
9942 | struct pci_dev *d = dev->pdev; |
9997 | struct pci_dev *d = dev->pdev; |
9943 | int i; |
9998 | int i; |
9944 | 9999 | ||
9945 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
10000 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
9946 | struct intel_quirk *q = &intel_quirks[i]; |
10001 | struct intel_quirk *q = &intel_quirks[i]; |
9947 | 10002 | ||
9948 | if (d->device == q->device && |
10003 | if (d->device == q->device && |
9949 | (d->subsystem_vendor == q->subsystem_vendor || |
10004 | (d->subsystem_vendor == q->subsystem_vendor || |
9950 | q->subsystem_vendor == PCI_ANY_ID) && |
10005 | q->subsystem_vendor == PCI_ANY_ID) && |
9951 | (d->subsystem_device == q->subsystem_device || |
10006 | (d->subsystem_device == q->subsystem_device || |
9952 | q->subsystem_device == PCI_ANY_ID)) |
10007 | q->subsystem_device == PCI_ANY_ID)) |
9953 | q->hook(dev); |
10008 | q->hook(dev); |
9954 | } |
10009 | } |
9955 | // for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
- | |
9956 | // if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
- | |
9957 | // intel_dmi_quirks[i].hook(dev); |
- | |
9958 | // } |
- | |
9959 | } |
10010 | } |
9960 | 10011 | ||
9961 | /* Disable the VGA plane that we never use */ |
10012 | /* Disable the VGA plane that we never use */ |
9962 | static void i915_disable_vga(struct drm_device *dev) |
10013 | static void i915_disable_vga(struct drm_device *dev) |
9963 | { |
10014 | { |
9964 | struct drm_i915_private *dev_priv = dev->dev_private; |
10015 | struct drm_i915_private *dev_priv = dev->dev_private; |
9965 | u8 sr1; |
10016 | u8 sr1; |
9966 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10017 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9967 | 10018 | ||
9968 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
10019 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
9969 | out8(SR01, VGA_SR_INDEX); |
10020 | out8(SR01, VGA_SR_INDEX); |
9970 | sr1 = in8(VGA_SR_DATA); |
10021 | sr1 = in8(VGA_SR_DATA); |
9971 | out8(sr1 | 1<<5, VGA_SR_DATA); |
10022 | out8(sr1 | 1<<5, VGA_SR_DATA); |
9972 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
10023 | // vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
9973 | udelay(300); |
10024 | udelay(300); |
9974 | 10025 | ||
9975 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
10026 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9976 | POSTING_READ(vga_reg); |
10027 | POSTING_READ(vga_reg); |
9977 | } |
10028 | } |
9978 | 10029 | ||
9979 | void intel_modeset_init_hw(struct drm_device *dev) |
10030 | void intel_modeset_init_hw(struct drm_device *dev) |
9980 | { |
10031 | { |
9981 | intel_init_power_well(dev); |
10032 | intel_init_power_well(dev); |
9982 | 10033 | ||
9983 | intel_prepare_ddi(dev); |
10034 | intel_prepare_ddi(dev); |
9984 | 10035 | ||
9985 | intel_init_clock_gating(dev); |
10036 | intel_init_clock_gating(dev); |
9986 | 10037 | ||
9987 | mutex_lock(&dev->struct_mutex); |
10038 | mutex_lock(&dev->struct_mutex); |
9988 | intel_enable_gt_powersave(dev); |
10039 | intel_enable_gt_powersave(dev); |
9989 | mutex_unlock(&dev->struct_mutex); |
10040 | mutex_unlock(&dev->struct_mutex); |
9990 | } |
10041 | } |
9991 | 10042 | ||
9992 | void intel_modeset_init(struct drm_device *dev) |
10043 | void intel_modeset_init(struct drm_device *dev) |
9993 | { |
10044 | { |
9994 | struct drm_i915_private *dev_priv = dev->dev_private; |
10045 | struct drm_i915_private *dev_priv = dev->dev_private; |
9995 | int i, j, ret; |
10046 | int i, j, ret; |
9996 | 10047 | ||
9997 | drm_mode_config_init(dev); |
10048 | drm_mode_config_init(dev); |
9998 | 10049 | ||
9999 | dev->mode_config.min_width = 0; |
10050 | dev->mode_config.min_width = 0; |
10000 | dev->mode_config.min_height = 0; |
10051 | dev->mode_config.min_height = 0; |
10001 | 10052 | ||
10002 | dev->mode_config.preferred_depth = 24; |
10053 | dev->mode_config.preferred_depth = 24; |
10003 | dev->mode_config.prefer_shadow = 1; |
10054 | dev->mode_config.prefer_shadow = 1; |
10004 | 10055 | ||
10005 | dev->mode_config.funcs = &intel_mode_funcs; |
10056 | dev->mode_config.funcs = &intel_mode_funcs; |
10006 | 10057 | ||
10007 | intel_init_quirks(dev); |
10058 | intel_init_quirks(dev); |
10008 | 10059 | ||
10009 | intel_init_pm(dev); |
10060 | intel_init_pm(dev); |
10010 | 10061 | ||
10011 | if (INTEL_INFO(dev)->num_pipes == 0) |
10062 | if (INTEL_INFO(dev)->num_pipes == 0) |
10012 | return; |
10063 | return; |
10013 | 10064 | ||
10014 | intel_init_display(dev); |
10065 | intel_init_display(dev); |
10015 | 10066 | ||
10016 | if (IS_GEN2(dev)) { |
10067 | if (IS_GEN2(dev)) { |
10017 | dev->mode_config.max_width = 2048; |
10068 | dev->mode_config.max_width = 2048; |
10018 | dev->mode_config.max_height = 2048; |
10069 | dev->mode_config.max_height = 2048; |
10019 | } else if (IS_GEN3(dev)) { |
10070 | } else if (IS_GEN3(dev)) { |
10020 | dev->mode_config.max_width = 4096; |
10071 | dev->mode_config.max_width = 4096; |
10021 | dev->mode_config.max_height = 4096; |
10072 | dev->mode_config.max_height = 4096; |
10022 | } else { |
10073 | } else { |
10023 | dev->mode_config.max_width = 8192; |
10074 | dev->mode_config.max_width = 8192; |
10024 | dev->mode_config.max_height = 8192; |
10075 | dev->mode_config.max_height = 8192; |
10025 | } |
10076 | } |
10026 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
10077 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
10027 | 10078 | ||
10028 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
10079 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
10029 | INTEL_INFO(dev)->num_pipes, |
10080 | INTEL_INFO(dev)->num_pipes, |
10030 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
10081 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
10031 | 10082 | ||
10032 | for_each_pipe(i) { |
10083 | for_each_pipe(i) { |
10033 | intel_crtc_init(dev, i); |
10084 | intel_crtc_init(dev, i); |
10034 | for (j = 0; j < dev_priv->num_plane; j++) { |
10085 | for (j = 0; j < dev_priv->num_plane; j++) { |
10035 | ret = intel_plane_init(dev, i, j); |
10086 | ret = intel_plane_init(dev, i, j); |
10036 | if (ret) |
10087 | if (ret) |
10037 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10088 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10038 | pipe_name(i), sprite_name(i, j), ret); |
10089 | pipe_name(i), sprite_name(i, j), ret); |
10039 | } |
10090 | } |
10040 | } |
10091 | } |
10041 | 10092 | ||
10042 | intel_cpu_pll_init(dev); |
10093 | intel_cpu_pll_init(dev); |
10043 | intel_shared_dpll_init(dev); |
10094 | intel_shared_dpll_init(dev); |
10044 | 10095 | ||
10045 | /* Just disable it once at startup */ |
10096 | /* Just disable it once at startup */ |
10046 | i915_disable_vga(dev); |
10097 | i915_disable_vga(dev); |
10047 | intel_setup_outputs(dev); |
10098 | intel_setup_outputs(dev); |
10048 | 10099 | ||
10049 | /* Just in case the BIOS is doing something questionable. */ |
10100 | /* Just in case the BIOS is doing something questionable. */ |
10050 | intel_disable_fbc(dev); |
10101 | intel_disable_fbc(dev); |
10051 | } |
10102 | } |
10052 | 10103 | ||
10053 | static void |
10104 | static void |
10054 | intel_connector_break_all_links(struct intel_connector *connector) |
10105 | intel_connector_break_all_links(struct intel_connector *connector) |
10055 | { |
10106 | { |
10056 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10107 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10057 | connector->base.encoder = NULL; |
10108 | connector->base.encoder = NULL; |
10058 | connector->encoder->connectors_active = false; |
10109 | connector->encoder->connectors_active = false; |
10059 | connector->encoder->base.crtc = NULL; |
10110 | connector->encoder->base.crtc = NULL; |
10060 | } |
10111 | } |
10061 | 10112 | ||
10062 | static void intel_enable_pipe_a(struct drm_device *dev) |
10113 | static void intel_enable_pipe_a(struct drm_device *dev) |
10063 | { |
10114 | { |
10064 | struct intel_connector *connector; |
10115 | struct intel_connector *connector; |
10065 | struct drm_connector *crt = NULL; |
10116 | struct drm_connector *crt = NULL; |
10066 | struct intel_load_detect_pipe load_detect_temp; |
10117 | struct intel_load_detect_pipe load_detect_temp; |
10067 | 10118 | ||
10068 | /* We can't just switch on the pipe A, we need to set things up with a |
10119 | /* We can't just switch on the pipe A, we need to set things up with a |
10069 | * proper mode and output configuration. As a gross hack, enable pipe A |
10120 | * proper mode and output configuration. As a gross hack, enable pipe A |
10070 | * by enabling the load detect pipe once. */ |
10121 | * by enabling the load detect pipe once. */ |
10071 | list_for_each_entry(connector, |
10122 | list_for_each_entry(connector, |
10072 | &dev->mode_config.connector_list, |
10123 | &dev->mode_config.connector_list, |
10073 | base.head) { |
10124 | base.head) { |
10074 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
10125 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
10075 | crt = &connector->base; |
10126 | crt = &connector->base; |
10076 | break; |
10127 | break; |
10077 | } |
10128 | } |
10078 | } |
10129 | } |
10079 | 10130 | ||
10080 | if (!crt) |
10131 | if (!crt) |
10081 | return; |
10132 | return; |
10082 | 10133 | ||
10083 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
10134 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
10084 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
10135 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
10085 | 10136 | ||
10086 | 10137 | ||
10087 | } |
10138 | } |
10088 | 10139 | ||
10089 | static bool |
10140 | static bool |
10090 | intel_check_plane_mapping(struct intel_crtc *crtc) |
10141 | intel_check_plane_mapping(struct intel_crtc *crtc) |
10091 | { |
10142 | { |
10092 | struct drm_device *dev = crtc->base.dev; |
10143 | struct drm_device *dev = crtc->base.dev; |
10093 | struct drm_i915_private *dev_priv = dev->dev_private; |
10144 | struct drm_i915_private *dev_priv = dev->dev_private; |
10094 | u32 reg, val; |
10145 | u32 reg, val; |
10095 | 10146 | ||
10096 | if (INTEL_INFO(dev)->num_pipes == 1) |
10147 | if (INTEL_INFO(dev)->num_pipes == 1) |
10097 | return true; |
10148 | return true; |
10098 | 10149 | ||
10099 | reg = DSPCNTR(!crtc->plane); |
10150 | reg = DSPCNTR(!crtc->plane); |
10100 | val = I915_READ(reg); |
10151 | val = I915_READ(reg); |
10101 | 10152 | ||
10102 | if ((val & DISPLAY_PLANE_ENABLE) && |
10153 | if ((val & DISPLAY_PLANE_ENABLE) && |
10103 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
10154 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
10104 | return false; |
10155 | return false; |
10105 | 10156 | ||
10106 | return true; |
10157 | return true; |
10107 | } |
10158 | } |
10108 | 10159 | ||
10109 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10160 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10110 | { |
10161 | { |
10111 | struct drm_device *dev = crtc->base.dev; |
10162 | struct drm_device *dev = crtc->base.dev; |
10112 | struct drm_i915_private *dev_priv = dev->dev_private; |
10163 | struct drm_i915_private *dev_priv = dev->dev_private; |
10113 | u32 reg; |
10164 | u32 reg; |
10114 | 10165 | ||
10115 | /* Clear any frame start delays used for debugging left by the BIOS */ |
10166 | /* Clear any frame start delays used for debugging left by the BIOS */ |
10116 | reg = PIPECONF(crtc->config.cpu_transcoder); |
10167 | reg = PIPECONF(crtc->config.cpu_transcoder); |
10117 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10168 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10118 | 10169 | ||
10119 | /* We need to sanitize the plane -> pipe mapping first because this will |
10170 | /* We need to sanitize the plane -> pipe mapping first because this will |
10120 | * disable the crtc (and hence change the state) if it is wrong. Note |
10171 | * disable the crtc (and hence change the state) if it is wrong. Note |
10121 | * that gen4+ has a fixed plane -> pipe mapping. */ |
10172 | * that gen4+ has a fixed plane -> pipe mapping. */ |
10122 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
10173 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
10123 | struct intel_connector *connector; |
10174 | struct intel_connector *connector; |
10124 | bool plane; |
10175 | bool plane; |
10125 | 10176 | ||
10126 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10177 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10127 | crtc->base.base.id); |
10178 | crtc->base.base.id); |
10128 | 10179 | ||
10129 | /* Pipe has the wrong plane attached and the plane is active. |
10180 | /* Pipe has the wrong plane attached and the plane is active. |
10130 | * Temporarily change the plane mapping and disable everything |
10181 | * Temporarily change the plane mapping and disable everything |
10131 | * ... */ |
10182 | * ... */ |
10132 | plane = crtc->plane; |
10183 | plane = crtc->plane; |
10133 | crtc->plane = !plane; |
10184 | crtc->plane = !plane; |
10134 | dev_priv->display.crtc_disable(&crtc->base); |
10185 | dev_priv->display.crtc_disable(&crtc->base); |
10135 | crtc->plane = plane; |
10186 | crtc->plane = plane; |
10136 | 10187 | ||
10137 | /* ... and break all links. */ |
10188 | /* ... and break all links. */ |
10138 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10189 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10139 | base.head) { |
10190 | base.head) { |
10140 | if (connector->encoder->base.crtc != &crtc->base) |
10191 | if (connector->encoder->base.crtc != &crtc->base) |
10141 | continue; |
10192 | continue; |
10142 | 10193 | ||
10143 | intel_connector_break_all_links(connector); |
10194 | intel_connector_break_all_links(connector); |
10144 | } |
10195 | } |
10145 | 10196 | ||
10146 | WARN_ON(crtc->active); |
10197 | WARN_ON(crtc->active); |
10147 | crtc->base.enabled = false; |
10198 | crtc->base.enabled = false; |
10148 | } |
10199 | } |
10149 | 10200 | ||
10150 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10201 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10151 | crtc->pipe == PIPE_A && !crtc->active) { |
10202 | crtc->pipe == PIPE_A && !crtc->active) { |
10152 | /* BIOS forgot to enable pipe A, this mostly happens after |
10203 | /* BIOS forgot to enable pipe A, this mostly happens after |
10153 | * resume. Force-enable the pipe to fix this, the update_dpms |
10204 | * resume. Force-enable the pipe to fix this, the update_dpms |
10154 | * call below we restore the pipe to the right state, but leave |
10205 | * call below we restore the pipe to the right state, but leave |
10155 | * the required bits on. */ |
10206 | * the required bits on. */ |
10156 | intel_enable_pipe_a(dev); |
10207 | intel_enable_pipe_a(dev); |
10157 | } |
10208 | } |
10158 | 10209 | ||
10159 | /* Adjust the state of the output pipe according to whether we |
10210 | /* Adjust the state of the output pipe according to whether we |
10160 | * have active connectors/encoders. */ |
10211 | * have active connectors/encoders. */ |
10161 | intel_crtc_update_dpms(&crtc->base); |
10212 | intel_crtc_update_dpms(&crtc->base); |
10162 | 10213 | ||
10163 | if (crtc->active != crtc->base.enabled) { |
10214 | if (crtc->active != crtc->base.enabled) { |
10164 | struct intel_encoder *encoder; |
10215 | struct intel_encoder *encoder; |
10165 | 10216 | ||
10166 | /* This can happen either due to bugs in the get_hw_state |
10217 | /* This can happen either due to bugs in the get_hw_state |
10167 | * functions or because the pipe is force-enabled due to the |
10218 | * functions or because the pipe is force-enabled due to the |
10168 | * pipe A quirk. */ |
10219 | * pipe A quirk. */ |
10169 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
10220 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
10170 | crtc->base.base.id, |
10221 | crtc->base.base.id, |
10171 | crtc->base.enabled ? "enabled" : "disabled", |
10222 | crtc->base.enabled ? "enabled" : "disabled", |
10172 | crtc->active ? "enabled" : "disabled"); |
10223 | crtc->active ? "enabled" : "disabled"); |
10173 | 10224 | ||
10174 | crtc->base.enabled = crtc->active; |
10225 | crtc->base.enabled = crtc->active; |
10175 | 10226 | ||
10176 | /* Because we only establish the connector -> encoder -> |
10227 | /* Because we only establish the connector -> encoder -> |
10177 | * crtc links if something is active, this means the |
10228 | * crtc links if something is active, this means the |
10178 | * crtc is now deactivated. Break the links. connector |
10229 | * crtc is now deactivated. Break the links. connector |
10179 | * -> encoder links are only establish when things are |
10230 | * -> encoder links are only establish when things are |
10180 | * actually up, hence no need to break them. */ |
10231 | * actually up, hence no need to break them. */ |
10181 | WARN_ON(crtc->active); |
10232 | WARN_ON(crtc->active); |
10182 | 10233 | ||
10183 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
10234 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
10184 | WARN_ON(encoder->connectors_active); |
10235 | WARN_ON(encoder->connectors_active); |
10185 | encoder->base.crtc = NULL; |
10236 | encoder->base.crtc = NULL; |
10186 | } |
10237 | } |
10187 | } |
10238 | } |
10188 | } |
10239 | } |
10189 | 10240 | ||
10190 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
10241 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
10191 | { |
10242 | { |
10192 | struct intel_connector *connector; |
10243 | struct intel_connector *connector; |
10193 | struct drm_device *dev = encoder->base.dev; |
10244 | struct drm_device *dev = encoder->base.dev; |
10194 | 10245 | ||
10195 | /* We need to check both for a crtc link (meaning that the |
10246 | /* We need to check both for a crtc link (meaning that the |
10196 | * encoder is active and trying to read from a pipe) and the |
10247 | * encoder is active and trying to read from a pipe) and the |
10197 | * pipe itself being active. */ |
10248 | * pipe itself being active. */ |
10198 | bool has_active_crtc = encoder->base.crtc && |
10249 | bool has_active_crtc = encoder->base.crtc && |
10199 | to_intel_crtc(encoder->base.crtc)->active; |
10250 | to_intel_crtc(encoder->base.crtc)->active; |
10200 | 10251 | ||
10201 | if (encoder->connectors_active && !has_active_crtc) { |
10252 | if (encoder->connectors_active && !has_active_crtc) { |
10202 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
10253 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
10203 | encoder->base.base.id, |
10254 | encoder->base.base.id, |
10204 | drm_get_encoder_name(&encoder->base)); |
10255 | drm_get_encoder_name(&encoder->base)); |
10205 | 10256 | ||
10206 | /* Connector is active, but has no active pipe. This is |
10257 | /* Connector is active, but has no active pipe. This is |
10207 | * fallout from our resume register restoring. Disable |
10258 | * fallout from our resume register restoring. Disable |
10208 | * the encoder manually again. */ |
10259 | * the encoder manually again. */ |
10209 | if (encoder->base.crtc) { |
10260 | if (encoder->base.crtc) { |
10210 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
10261 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
10211 | encoder->base.base.id, |
10262 | encoder->base.base.id, |
10212 | drm_get_encoder_name(&encoder->base)); |
10263 | drm_get_encoder_name(&encoder->base)); |
10213 | encoder->disable(encoder); |
10264 | encoder->disable(encoder); |
10214 | } |
10265 | } |
10215 | 10266 | ||
10216 | /* Inconsistent output/port/pipe state happens presumably due to |
10267 | /* Inconsistent output/port/pipe state happens presumably due to |
10217 | * a bug in one of the get_hw_state functions. Or someplace else |
10268 | * a bug in one of the get_hw_state functions. Or someplace else |
10218 | * in our code, like the register restore mess on resume. Clamp |
10269 | * in our code, like the register restore mess on resume. Clamp |
10219 | * things to off as a safer default. */ |
10270 | * things to off as a safer default. */ |
10220 | list_for_each_entry(connector, |
10271 | list_for_each_entry(connector, |
10221 | &dev->mode_config.connector_list, |
10272 | &dev->mode_config.connector_list, |
10222 | base.head) { |
10273 | base.head) { |
10223 | if (connector->encoder != encoder) |
10274 | if (connector->encoder != encoder) |
10224 | continue; |
10275 | continue; |
10225 | 10276 | ||
10226 | intel_connector_break_all_links(connector); |
10277 | intel_connector_break_all_links(connector); |
10227 | } |
10278 | } |
10228 | } |
10279 | } |
10229 | /* Enabled encoders without active connectors will be fixed in |
10280 | /* Enabled encoders without active connectors will be fixed in |
10230 | * the crtc fixup. */ |
10281 | * the crtc fixup. */ |
10231 | } |
10282 | } |
10232 | 10283 | ||
10233 | void i915_redisable_vga(struct drm_device *dev) |
10284 | void i915_redisable_vga(struct drm_device *dev) |
10234 | { |
10285 | { |
10235 | struct drm_i915_private *dev_priv = dev->dev_private; |
10286 | struct drm_i915_private *dev_priv = dev->dev_private; |
10236 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10287 | u32 vga_reg = i915_vgacntrl_reg(dev); |
10237 | 10288 | ||
10238 | /* This function can be called both from intel_modeset_setup_hw_state or |
10289 | /* This function can be called both from intel_modeset_setup_hw_state or |
10239 | * at a very early point in our resume sequence, where the power well |
10290 | * at a very early point in our resume sequence, where the power well |
10240 | * structures are not yet restored. Since this function is at a very |
10291 | * structures are not yet restored. Since this function is at a very |
10241 | * paranoid "someone might have enabled VGA while we were not looking" |
10292 | * paranoid "someone might have enabled VGA while we were not looking" |
10242 | * level, just check if the power well is enabled instead of trying to |
10293 | * level, just check if the power well is enabled instead of trying to |
10243 | * follow the "don't touch the power well if we don't need it" policy |
10294 | * follow the "don't touch the power well if we don't need it" policy |
10244 | * the rest of the driver uses. */ |
10295 | * the rest of the driver uses. */ |
10245 | if (HAS_POWER_WELL(dev) && |
10296 | if (HAS_POWER_WELL(dev) && |
10246 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
10297 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
10247 | return; |
10298 | return; |
10248 | 10299 | ||
10249 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10300 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10250 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
10301 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
10251 | i915_disable_vga(dev); |
10302 | i915_disable_vga(dev); |
10252 | } |
10303 | } |
10253 | } |
10304 | } |
10254 | 10305 | ||
10255 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
10306 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
10256 | { |
10307 | { |
10257 | struct drm_i915_private *dev_priv = dev->dev_private; |
10308 | struct drm_i915_private *dev_priv = dev->dev_private; |
10258 | enum pipe pipe; |
10309 | enum pipe pipe; |
10259 | struct intel_crtc *crtc; |
10310 | struct intel_crtc *crtc; |
10260 | struct intel_encoder *encoder; |
10311 | struct intel_encoder *encoder; |
10261 | struct intel_connector *connector; |
10312 | struct intel_connector *connector; |
10262 | int i; |
10313 | int i; |
10263 | 10314 | ||
10264 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10315 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10265 | base.head) { |
10316 | base.head) { |
10266 | memset(&crtc->config, 0, sizeof(crtc->config)); |
10317 | memset(&crtc->config, 0, sizeof(crtc->config)); |
10267 | 10318 | ||
10268 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10319 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10269 | &crtc->config); |
10320 | &crtc->config); |
10270 | 10321 | ||
10271 | crtc->base.enabled = crtc->active; |
10322 | crtc->base.enabled = crtc->active; |
10272 | 10323 | ||
10273 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
10324 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
10274 | crtc->base.base.id, |
10325 | crtc->base.base.id, |
10275 | crtc->active ? "enabled" : "disabled"); |
10326 | crtc->active ? "enabled" : "disabled"); |
10276 | } |
10327 | } |
10277 | 10328 | ||
10278 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
10329 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
10279 | if (HAS_DDI(dev)) |
10330 | if (HAS_DDI(dev)) |
10280 | intel_ddi_setup_hw_pll_state(dev); |
10331 | intel_ddi_setup_hw_pll_state(dev); |
10281 | 10332 | ||
10282 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10333 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10283 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10334 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10284 | 10335 | ||
10285 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
10336 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
10286 | pll->active = 0; |
10337 | pll->active = 0; |
10287 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10338 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10288 | base.head) { |
10339 | base.head) { |
10289 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
10340 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
10290 | pll->active++; |
10341 | pll->active++; |
10291 | } |
10342 | } |
10292 | pll->refcount = pll->active; |
10343 | pll->refcount = pll->active; |
10293 | 10344 | ||
10294 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
10345 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
10295 | pll->name, pll->refcount, pll->on); |
10346 | pll->name, pll->refcount, pll->on); |
10296 | } |
10347 | } |
10297 | 10348 | ||
10298 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10349 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10299 | base.head) { |
10350 | base.head) { |
10300 | pipe = 0; |
10351 | pipe = 0; |
10301 | 10352 | ||
10302 | if (encoder->get_hw_state(encoder, &pipe)) { |
10353 | if (encoder->get_hw_state(encoder, &pipe)) { |
10303 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10354 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10304 | encoder->base.crtc = &crtc->base; |
10355 | encoder->base.crtc = &crtc->base; |
10305 | if (encoder->get_config) |
10356 | if (encoder->get_config) |
10306 | encoder->get_config(encoder, &crtc->config); |
10357 | encoder->get_config(encoder, &crtc->config); |
10307 | } else { |
10358 | } else { |
10308 | encoder->base.crtc = NULL; |
10359 | encoder->base.crtc = NULL; |
10309 | } |
10360 | } |
10310 | 10361 | ||
10311 | encoder->connectors_active = false; |
10362 | encoder->connectors_active = false; |
10312 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
10363 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", |
10313 | encoder->base.base.id, |
10364 | encoder->base.base.id, |
10314 | drm_get_encoder_name(&encoder->base), |
10365 | drm_get_encoder_name(&encoder->base), |
10315 | encoder->base.crtc ? "enabled" : "disabled", |
10366 | encoder->base.crtc ? "enabled" : "disabled", |
10316 | pipe); |
10367 | pipe); |
10317 | } |
10368 | } |
10318 | 10369 | ||
10319 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10370 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10320 | base.head) { |
10371 | base.head) { |
10321 | if (!crtc->active) |
10372 | if (!crtc->active) |
10322 | continue; |
10373 | continue; |
10323 | if (dev_priv->display.get_clock) |
10374 | if (dev_priv->display.get_clock) |
10324 | dev_priv->display.get_clock(crtc, |
10375 | dev_priv->display.get_clock(crtc, |
10325 | &crtc->config); |
10376 | &crtc->config); |
10326 | } |
10377 | } |
10327 | 10378 | ||
10328 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10379 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10329 | base.head) { |
10380 | base.head) { |
10330 | if (connector->get_hw_state(connector)) { |
10381 | if (connector->get_hw_state(connector)) { |
10331 | connector->base.dpms = DRM_MODE_DPMS_ON; |
10382 | connector->base.dpms = DRM_MODE_DPMS_ON; |
10332 | connector->encoder->connectors_active = true; |
10383 | connector->encoder->connectors_active = true; |
10333 | connector->base.encoder = &connector->encoder->base; |
10384 | connector->base.encoder = &connector->encoder->base; |
10334 | } else { |
10385 | } else { |
10335 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10386 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
10336 | connector->base.encoder = NULL; |
10387 | connector->base.encoder = NULL; |
10337 | } |
10388 | } |
10338 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
10389 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
10339 | connector->base.base.id, |
10390 | connector->base.base.id, |
10340 | drm_get_connector_name(&connector->base), |
10391 | drm_get_connector_name(&connector->base), |
10341 | connector->base.encoder ? "enabled" : "disabled"); |
10392 | connector->base.encoder ? "enabled" : "disabled"); |
10342 | } |
10393 | } |
10343 | } |
10394 | } |
10344 | 10395 | ||
10345 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
10396 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
10346 | * and i915 state tracking structures. */ |
10397 | * and i915 state tracking structures. */ |
10347 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
10398 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
10348 | bool force_restore) |
10399 | bool force_restore) |
10349 | { |
10400 | { |
10350 | struct drm_i915_private *dev_priv = dev->dev_private; |
10401 | struct drm_i915_private *dev_priv = dev->dev_private; |
10351 | enum pipe pipe; |
10402 | enum pipe pipe; |
10352 | struct drm_plane *plane; |
10403 | struct drm_plane *plane; |
10353 | struct intel_crtc *crtc; |
10404 | struct intel_crtc *crtc; |
10354 | struct intel_encoder *encoder; |
10405 | struct intel_encoder *encoder; |
10355 | int i; |
10406 | int i; |
10356 | 10407 | ||
10357 | intel_modeset_readout_hw_state(dev); |
10408 | intel_modeset_readout_hw_state(dev); |
10358 | 10409 | ||
10359 | /* |
10410 | /* |
10360 | * Now that we have the config, copy it to each CRTC struct |
10411 | * Now that we have the config, copy it to each CRTC struct |
10361 | * Note that this could go away if we move to using crtc_config |
10412 | * Note that this could go away if we move to using crtc_config |
10362 | * checking everywhere. |
10413 | * checking everywhere. |
10363 | */ |
10414 | */ |
10364 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10415 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10365 | base.head) { |
10416 | base.head) { |
10366 | if (crtc->active && i915_fastboot) { |
10417 | if (crtc->active && i915_fastboot) { |
10367 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
10418 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
10368 | 10419 | ||
10369 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
10420 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
10370 | crtc->base.base.id); |
10421 | crtc->base.base.id); |
10371 | drm_mode_debug_printmodeline(&crtc->base.mode); |
10422 | drm_mode_debug_printmodeline(&crtc->base.mode); |
10372 | } |
10423 | } |
10373 | } |
10424 | } |
10374 | 10425 | ||
10375 | /* HW state is read out, now we need to sanitize this mess. */ |
10426 | /* HW state is read out, now we need to sanitize this mess. */ |
10376 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10427 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10377 | base.head) { |
10428 | base.head) { |
10378 | intel_sanitize_encoder(encoder); |
10429 | intel_sanitize_encoder(encoder); |
10379 | } |
10430 | } |
10380 | 10431 | ||
10381 | for_each_pipe(pipe) { |
10432 | for_each_pipe(pipe) { |
10382 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10433 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10383 | intel_sanitize_crtc(crtc); |
10434 | intel_sanitize_crtc(crtc); |
10384 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
10435 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
10385 | } |
10436 | } |
10386 | 10437 | ||
10387 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10438 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10388 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10439 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
10389 | 10440 | ||
10390 | if (!pll->on || pll->active) |
10441 | if (!pll->on || pll->active) |
10391 | continue; |
10442 | continue; |
10392 | 10443 | ||
10393 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
10444 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
10394 | 10445 | ||
10395 | pll->disable(dev_priv, pll); |
10446 | pll->disable(dev_priv, pll); |
10396 | pll->on = false; |
10447 | pll->on = false; |
10397 | } |
10448 | } |
10398 | 10449 | ||
10399 | if (force_restore) { |
10450 | if (force_restore) { |
10400 | /* |
10451 | /* |
10401 | * We need to use raw interfaces for restoring state to avoid |
10452 | * We need to use raw interfaces for restoring state to avoid |
10402 | * checking (bogus) intermediate states. |
10453 | * checking (bogus) intermediate states. |
10403 | */ |
10454 | */ |
10404 | for_each_pipe(pipe) { |
10455 | for_each_pipe(pipe) { |
10405 | struct drm_crtc *crtc = |
10456 | struct drm_crtc *crtc = |
10406 | dev_priv->pipe_to_crtc_mapping[pipe]; |
10457 | dev_priv->pipe_to_crtc_mapping[pipe]; |
10407 | 10458 | ||
10408 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
10459 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
10409 | crtc->fb); |
10460 | crtc->fb); |
10410 | } |
10461 | } |
10411 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
10462 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
10412 | intel_plane_restore(plane); |
10463 | intel_plane_restore(plane); |
10413 | 10464 | ||
10414 | i915_redisable_vga(dev); |
10465 | i915_redisable_vga(dev); |
10415 | } else { |
10466 | } else { |
10416 | intel_modeset_update_staged_output_state(dev); |
10467 | intel_modeset_update_staged_output_state(dev); |
10417 | } |
10468 | } |
10418 | 10469 | ||
10419 | intel_modeset_check_state(dev); |
10470 | intel_modeset_check_state(dev); |
10420 | 10471 | ||
10421 | drm_mode_config_reset(dev); |
10472 | drm_mode_config_reset(dev); |
10422 | } |
10473 | } |
10423 | 10474 | ||
10424 | void intel_modeset_gem_init(struct drm_device *dev) |
10475 | void intel_modeset_gem_init(struct drm_device *dev) |
10425 | { |
10476 | { |
10426 | intel_modeset_init_hw(dev); |
10477 | intel_modeset_init_hw(dev); |
10427 | 10478 | ||
10428 | // intel_setup_overlay(dev); |
10479 | // intel_setup_overlay(dev); |
10429 | 10480 | ||
10430 | intel_modeset_setup_hw_state(dev, false); |
10481 | intel_modeset_setup_hw_state(dev, false); |
10431 | } |
10482 | } |
10432 | 10483 | ||
10433 | void intel_modeset_cleanup(struct drm_device *dev) |
10484 | void intel_modeset_cleanup(struct drm_device *dev) |
10434 | { |
10485 | { |
10435 | #if 0 |
10486 | #if 0 |
10436 | struct drm_i915_private *dev_priv = dev->dev_private; |
10487 | struct drm_i915_private *dev_priv = dev->dev_private; |
10437 | struct drm_crtc *crtc; |
10488 | struct drm_crtc *crtc; |
10438 | 10489 | ||
10439 | /* |
10490 | /* |
10440 | * Interrupts and polling as the first thing to avoid creating havoc. |
10491 | * Interrupts and polling as the first thing to avoid creating havoc. |
10441 | * Too much stuff here (turning of rps, connectors, ...) would |
10492 | * Too much stuff here (turning of rps, connectors, ...) would |
10442 | * experience fancy races otherwise. |
10493 | * experience fancy races otherwise. |
10443 | */ |
10494 | */ |
10444 | drm_irq_uninstall(dev); |
10495 | drm_irq_uninstall(dev); |
10445 | cancel_work_sync(&dev_priv->hotplug_work); |
10496 | cancel_work_sync(&dev_priv->hotplug_work); |
10446 | /* |
10497 | /* |
10447 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
10498 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
10448 | * poll handlers. Hence disable polling after hpd handling is shut down. |
10499 | * poll handlers. Hence disable polling after hpd handling is shut down. |
10449 | */ |
10500 | */ |
10450 | // drm_kms_helper_poll_fini(dev); |
10501 | // drm_kms_helper_poll_fini(dev); |
10451 | 10502 | ||
10452 | mutex_lock(&dev->struct_mutex); |
10503 | mutex_lock(&dev->struct_mutex); |
10453 | 10504 | ||
10454 | // intel_unregister_dsm_handler(); |
10505 | // intel_unregister_dsm_handler(); |
10455 | 10506 | ||
10456 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10507 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10457 | /* Skip inactive CRTCs */ |
10508 | /* Skip inactive CRTCs */ |
10458 | if (!crtc->fb) |
10509 | if (!crtc->fb) |
10459 | continue; |
10510 | continue; |
10460 | 10511 | ||
10461 | intel_increase_pllclock(crtc); |
10512 | intel_increase_pllclock(crtc); |
10462 | } |
10513 | } |
10463 | 10514 | ||
10464 | intel_disable_fbc(dev); |
10515 | intel_disable_fbc(dev); |
10465 | 10516 | ||
10466 | intel_disable_gt_powersave(dev); |
10517 | intel_disable_gt_powersave(dev); |
10467 | 10518 | ||
10468 | ironlake_teardown_rc6(dev); |
10519 | ironlake_teardown_rc6(dev); |
10469 | 10520 | ||
10470 | mutex_unlock(&dev->struct_mutex); |
10521 | mutex_unlock(&dev->struct_mutex); |
10471 | 10522 | ||
10472 | /* flush any delayed tasks or pending work */ |
10523 | /* flush any delayed tasks or pending work */ |
10473 | flush_scheduled_work(); |
10524 | flush_scheduled_work(); |
10474 | // cancel_work_sync(&dev_priv->hotplug_work); |
- | |
10475 | // cancel_work_sync(&dev_priv->rps.work); |
- | |
10476 | 10525 | ||
10477 | /* flush any delayed tasks or pending work */ |
10526 | /* destroy backlight, if any, before the connectors */ |
10478 | // flush_scheduled_work(); |
10527 | intel_panel_destroy_backlight(dev); |
10479 | 10528 | ||
10480 | drm_mode_config_cleanup(dev); |
10529 | drm_mode_config_cleanup(dev); |
10481 | #endif |
10530 | #endif |
10482 | } |
10531 | } |
10483 | 10532 | ||
10484 | /* |
10533 | /* |
10485 | * Return which encoder is currently attached for connector. |
10534 | * Return which encoder is currently attached for connector. |
10486 | */ |
10535 | */ |
10487 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
10536 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
10488 | { |
10537 | { |
10489 | return &intel_attached_encoder(connector)->base; |
10538 | return &intel_attached_encoder(connector)->base; |
10490 | } |
10539 | } |
10491 | 10540 | ||
10492 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10541 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10493 | struct intel_encoder *encoder) |
10542 | struct intel_encoder *encoder) |
10494 | { |
10543 | { |
10495 | connector->encoder = encoder; |
10544 | connector->encoder = encoder; |
10496 | drm_mode_connector_attach_encoder(&connector->base, |
10545 | drm_mode_connector_attach_encoder(&connector->base, |
10497 | &encoder->base); |
10546 | &encoder->base); |
10498 | } |
10547 | } |
10499 | 10548 | ||
10500 | /* |
10549 | /* |
10501 | * set vga decode state - true == enable VGA decode |
10550 | * set vga decode state - true == enable VGA decode |
10502 | */ |
10551 | */ |
10503 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
10552 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
10504 | { |
10553 | { |
10505 | struct drm_i915_private *dev_priv = dev->dev_private; |
10554 | struct drm_i915_private *dev_priv = dev->dev_private; |
10506 | u16 gmch_ctrl; |
10555 | u16 gmch_ctrl; |
10507 | 10556 | ||
10508 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
10557 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
10509 | if (state) |
10558 | if (state) |
10510 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
10559 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
10511 | else |
10560 | else |
10512 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
10561 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
10513 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
10562 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
10514 | return 0; |
10563 | return 0; |
10515 | } |
10564 | } |
10516 | 10565 | ||
10517 | #ifdef CONFIG_DEBUG_FS |
10566 | #ifdef CONFIG_DEBUG_FS |
10518 | #include |
10567 | #include |
10519 | 10568 | ||
10520 | struct intel_display_error_state { |
10569 | struct intel_display_error_state { |
10521 | 10570 | ||
10522 | u32 power_well_driver; |
10571 | u32 power_well_driver; |
10523 | 10572 | ||
10524 | int num_transcoders; |
10573 | int num_transcoders; |
10525 | 10574 | ||
10526 | struct intel_cursor_error_state { |
10575 | struct intel_cursor_error_state { |
10527 | u32 control; |
10576 | u32 control; |
10528 | u32 position; |
10577 | u32 position; |
10529 | u32 base; |
10578 | u32 base; |
10530 | u32 size; |
10579 | u32 size; |
10531 | } cursor[I915_MAX_PIPES]; |
10580 | } cursor[I915_MAX_PIPES]; |
10532 | 10581 | ||
10533 | struct intel_pipe_error_state { |
10582 | struct intel_pipe_error_state { |
10534 | u32 source; |
10583 | u32 source; |
10535 | } pipe[I915_MAX_PIPES]; |
10584 | } pipe[I915_MAX_PIPES]; |
10536 | 10585 | ||
10537 | struct intel_plane_error_state { |
10586 | struct intel_plane_error_state { |
10538 | u32 control; |
10587 | u32 control; |
10539 | u32 stride; |
10588 | u32 stride; |
10540 | u32 size; |
10589 | u32 size; |
10541 | u32 pos; |
10590 | u32 pos; |
10542 | u32 addr; |
10591 | u32 addr; |
10543 | u32 surface; |
10592 | u32 surface; |
10544 | u32 tile_offset; |
10593 | u32 tile_offset; |
10545 | } plane[I915_MAX_PIPES]; |
10594 | } plane[I915_MAX_PIPES]; |
10546 | 10595 | ||
10547 | struct intel_transcoder_error_state { |
10596 | struct intel_transcoder_error_state { |
10548 | enum transcoder cpu_transcoder; |
10597 | enum transcoder cpu_transcoder; |
10549 | 10598 | ||
10550 | u32 conf; |
10599 | u32 conf; |
10551 | 10600 | ||
10552 | u32 htotal; |
10601 | u32 htotal; |
10553 | u32 hblank; |
10602 | u32 hblank; |
10554 | u32 hsync; |
10603 | u32 hsync; |
10555 | u32 vtotal; |
10604 | u32 vtotal; |
10556 | u32 vblank; |
10605 | u32 vblank; |
10557 | u32 vsync; |
10606 | u32 vsync; |
10558 | } transcoder[4]; |
10607 | } transcoder[4]; |
10559 | }; |
10608 | }; |
10560 | 10609 | ||
10561 | struct intel_display_error_state * |
10610 | struct intel_display_error_state * |
10562 | intel_display_capture_error_state(struct drm_device *dev) |
10611 | intel_display_capture_error_state(struct drm_device *dev) |
10563 | { |
10612 | { |
10564 | drm_i915_private_t *dev_priv = dev->dev_private; |
10613 | drm_i915_private_t *dev_priv = dev->dev_private; |
10565 | struct intel_display_error_state *error; |
10614 | struct intel_display_error_state *error; |
10566 | int transcoders[] = { |
10615 | int transcoders[] = { |
10567 | TRANSCODER_A, |
10616 | TRANSCODER_A, |
10568 | TRANSCODER_B, |
10617 | TRANSCODER_B, |
10569 | TRANSCODER_C, |
10618 | TRANSCODER_C, |
10570 | TRANSCODER_EDP, |
10619 | TRANSCODER_EDP, |
10571 | }; |
10620 | }; |
10572 | int i; |
10621 | int i; |
10573 | 10622 | ||
10574 | if (INTEL_INFO(dev)->num_pipes == 0) |
10623 | if (INTEL_INFO(dev)->num_pipes == 0) |
10575 | return NULL; |
10624 | return NULL; |
10576 | 10625 | ||
10577 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10626 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10578 | if (error == NULL) |
10627 | if (error == NULL) |
10579 | return NULL; |
10628 | return NULL; |
10580 | 10629 | ||
10581 | if (HAS_POWER_WELL(dev)) |
10630 | if (HAS_POWER_WELL(dev)) |
10582 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
10631 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
10583 | 10632 | ||
10584 | for_each_pipe(i) { |
10633 | for_each_pipe(i) { |
10585 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
10634 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
10586 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
10635 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
10587 | error->cursor[i].position = I915_READ(CURPOS(i)); |
10636 | error->cursor[i].position = I915_READ(CURPOS(i)); |
10588 | error->cursor[i].base = I915_READ(CURBASE(i)); |
10637 | error->cursor[i].base = I915_READ(CURBASE(i)); |
10589 | } else { |
10638 | } else { |
10590 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
10639 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
10591 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
10640 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
10592 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
10641 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
10593 | } |
10642 | } |
10594 | 10643 | ||
10595 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
10644 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
10596 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
10645 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
10597 | if (INTEL_INFO(dev)->gen <= 3) { |
10646 | if (INTEL_INFO(dev)->gen <= 3) { |
10598 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
10647 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
10599 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
10648 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
10600 | } |
10649 | } |
10601 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10650 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10602 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
10651 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
10603 | if (INTEL_INFO(dev)->gen >= 4) { |
10652 | if (INTEL_INFO(dev)->gen >= 4) { |
10604 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
10653 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
10605 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
10654 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
10606 | } |
10655 | } |
10607 | 10656 | ||
10608 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
10657 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
10609 | } |
10658 | } |
10610 | 10659 | ||
10611 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
10660 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
10612 | if (HAS_DDI(dev_priv->dev)) |
10661 | if (HAS_DDI(dev_priv->dev)) |
10613 | error->num_transcoders++; /* Account for eDP. */ |
10662 | error->num_transcoders++; /* Account for eDP. */ |
10614 | 10663 | ||
10615 | for (i = 0; i < error->num_transcoders; i++) { |
10664 | for (i = 0; i < error->num_transcoders; i++) { |
10616 | enum transcoder cpu_transcoder = transcoders[i]; |
10665 | enum transcoder cpu_transcoder = transcoders[i]; |
10617 | 10666 | ||
10618 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
10667 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
10619 | 10668 | ||
10620 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
10669 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
10621 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
10670 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
10622 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
10671 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
10623 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
10672 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
10624 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
10673 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
10625 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
10674 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
10626 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
10675 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
10627 | } |
10676 | } |
10628 | 10677 | ||
10629 | /* In the code above we read the registers without checking if the power |
10678 | /* In the code above we read the registers without checking if the power |
10630 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to |
10679 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to |
10631 | * prevent the next I915_WRITE from detecting it and printing an error |
10680 | * prevent the next I915_WRITE from detecting it and printing an error |
10632 | * message. */ |
10681 | * message. */ |
10633 | intel_uncore_clear_errors(dev); |
10682 | intel_uncore_clear_errors(dev); |
10634 | 10683 | ||
10635 | return error; |
10684 | return error; |
10636 | } |
10685 | } |
10637 | 10686 | ||
10638 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
10687 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
10639 | 10688 | ||
10640 | void |
10689 | void |
10641 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
10690 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
10642 | struct drm_device *dev, |
10691 | struct drm_device *dev, |
10643 | struct intel_display_error_state *error) |
10692 | struct intel_display_error_state *error) |
10644 | { |
10693 | { |
10645 | int i; |
10694 | int i; |
10646 | 10695 | ||
10647 | if (!error) |
10696 | if (!error) |
10648 | return; |
10697 | return; |
10649 | 10698 | ||
10650 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
10699 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
10651 | if (HAS_POWER_WELL(dev)) |
10700 | if (HAS_POWER_WELL(dev)) |
10652 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
10701 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
10653 | error->power_well_driver); |
10702 | error->power_well_driver); |
10654 | for_each_pipe(i) { |
10703 | for_each_pipe(i) { |
10655 | err_printf(m, "Pipe [%d]:\n", i); |
10704 | err_printf(m, "Pipe [%d]:\n", i); |
10656 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
10705 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
10657 | 10706 | ||
10658 | err_printf(m, "Plane [%d]:\n", i); |
10707 | err_printf(m, "Plane [%d]:\n", i); |
10659 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
10708 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
10660 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
10709 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
10661 | if (INTEL_INFO(dev)->gen <= 3) { |
10710 | if (INTEL_INFO(dev)->gen <= 3) { |
10662 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
10711 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
10663 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
10712 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
10664 | } |
10713 | } |
10665 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10714 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10666 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
10715 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
10667 | if (INTEL_INFO(dev)->gen >= 4) { |
10716 | if (INTEL_INFO(dev)->gen >= 4) { |
10668 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
10717 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
10669 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
10718 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
10670 | } |
10719 | } |
10671 | 10720 | ||
10672 | err_printf(m, "Cursor [%d]:\n", i); |
10721 | err_printf(m, "Cursor [%d]:\n", i); |
10673 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
10722 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
10674 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
10723 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
10675 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
10724 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
10676 | } |
10725 | } |
10677 | 10726 | ||
10678 | for (i = 0; i < error->num_transcoders; i++) { |
10727 | for (i = 0; i < error->num_transcoders; i++) { |
10679 | err_printf(m, " CPU transcoder: %c\n", |
10728 | err_printf(m, " CPU transcoder: %c\n", |
10680 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
10729 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
10681 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
10730 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
10682 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
10731 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
10683 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
10732 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
10684 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
10733 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
10685 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
10734 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
10686 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
10735 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
10687 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
10736 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
10688 | } |
10737 | } |
10689 | } |
10738 | } |
10690 | #endif>=>=>>=>=>=>>>>>5,><5,>>>>>><>><>>>>>>>>(intel_crtc)-><(intel_crtc)->>><>><>><>><>><>><>><>><>><>><>>>>>>=><=>>><>>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>>>>><>><>><>><>><>>>><>><>><>><>->>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>>><>>><>><>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>=>=>>>><>><>><>><>><>><>><>>>>>>>>>>>>><>><>><>>>>>>><>>>>>>=>=>>=>>>=>=>=>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |
10739 | #endif>=>=>>=>=>=>>>>>5,><5,>>>>><>><>>>>>>>>(intel_crtc)-><(intel_crtc)->>><>><>><>><>><>><>><>><>><>><>>>>>>=><=>>><>>>>><>><>><>><>>><>><>>>><>><>>>><>><>><>><>>>><>><>><>><>>><>><>><>><>>>>>>><>><>><>><>><>>>><>><>><>><>->>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>>><>>><>><>><>><>><>><>><>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>=>=>>>><>><>><>><>><>><>><>>>>>>>>>>>>><>><>><>><>>>>>>><>>>>>>=>=>>=>>>=>=>=>=>>>=>=>=>=>>>>>>>>>>=>=>>>>>>>>> |