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Rev 4104 | Rev 4280 | ||
---|---|---|---|
Line 1826... | Line 1826... | ||
1826 | { |
1826 | { |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
1828 | u32 alignment; |
1828 | u32 alignment; |
1829 | int ret; |
1829 | int ret; |
Line -... | Line 1830... | ||
- | 1830 | ||
- | 1831 | ENTER(); |
|
1830 | 1832 | ||
1831 | switch (obj->tiling_mode) { |
1833 | switch (obj->tiling_mode) { |
1832 | case I915_TILING_NONE: |
1834 | case I915_TILING_NONE: |
1833 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1835 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1834 | alignment = 128 * 1024; |
1836 | alignment = 128 * 1024; |
Line 1874... | Line 1876... | ||
1874 | goto err_unpin; |
1876 | goto err_unpin; |
Line 1875... | Line 1877... | ||
1875 | 1877 | ||
Line 1876... | Line 1878... | ||
1876 | i915_gem_object_pin_fence(obj); |
1878 | i915_gem_object_pin_fence(obj); |
- | 1879 | ||
- | 1880 | dev_priv->mm.interruptible = true; |
|
- | 1881 | ||
1877 | 1882 | LEAVE(); |
|
Line 1878... | Line 1883... | ||
1878 | dev_priv->mm.interruptible = true; |
1883 | |
1879 | return 0; |
1884 | return 0; |
1880 | 1885 | ||
Line 2238... | Line 2243... | ||
2238 | INTEL_INFO(dev)->num_pipes); |
2243 | INTEL_INFO(dev)->num_pipes); |
2239 | return -EINVAL; |
2244 | return -EINVAL; |
2240 | } |
2245 | } |
Line 2241... | Line 2246... | ||
2241 | 2246 | ||
2242 | mutex_lock(&dev->struct_mutex); |
2247 | mutex_lock(&dev->struct_mutex); |
2243 | // ret = intel_pin_and_fence_fb_obj(dev, |
2248 | ret = intel_pin_and_fence_fb_obj(dev, |
2244 | // to_intel_framebuffer(fb)->obj, |
2249 | to_intel_framebuffer(fb)->obj, |
2245 | // NULL); |
2250 | NULL); |
2246 | // if (ret != 0) { |
2251 | if (ret != 0) { |
2247 | // mutex_unlock(&dev->struct_mutex); |
2252 | mutex_unlock(&dev->struct_mutex); |
2248 | // DRM_ERROR("pin & fence failed\n"); |
2253 | DRM_ERROR("pin & fence failed\n"); |
2249 | // return ret; |
2254 | return ret; |
Line -... | Line 2255... | ||
- | 2255 | } |
|
- | 2256 | ||
- | 2257 | /* Update pipe size and adjust fitter if needed */ |
|
- | 2258 | if (i915_fastboot) { |
|
- | 2259 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
|
- | 2260 | ((crtc->mode.hdisplay - 1) << 16) | |
|
- | 2261 | (crtc->mode.vdisplay - 1)); |
|
- | 2262 | if (!intel_crtc->config.pch_pfit.enabled && |
|
- | 2263 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
|
- | 2264 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
|
- | 2265 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
|
- | 2266 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
|
- | 2267 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
|
Line 2250... | Line 2268... | ||
2250 | // } |
2268 | } |
2251 | 2269 | } |
|
2252 | 2270 | ||
2253 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2271 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
Line 2315... | Line 2333... | ||
2315 | if (IS_IVYBRIDGE(dev)) |
2333 | if (IS_IVYBRIDGE(dev)) |
2316 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2334 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2317 | FDI_FE_ERRC_ENABLE); |
2335 | FDI_FE_ERRC_ENABLE); |
2318 | } |
2336 | } |
Line 2319... | Line 2337... | ||
2319 | 2337 | ||
2320 | static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) |
2338 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
2321 | { |
2339 | { |
- | 2340 | return crtc->base.enabled && crtc->active && |
|
2322 | return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder; |
2341 | crtc->config.has_pch_encoder; |
Line 2323... | Line 2342... | ||
2323 | } |
2342 | } |
2324 | 2343 | ||
2325 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2344 | static void ivb_modeset_global_resources(struct drm_device *dev) |
Line 2969... | Line 2988... | ||
2969 | I915_READ(VSYNC(cpu_transcoder))); |
2988 | I915_READ(VSYNC(cpu_transcoder))); |
2970 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
2989 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
2971 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
2990 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
2972 | } |
2991 | } |
Line -... | Line 2992... | ||
- | 2992 | ||
- | 2993 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
|
- | 2994 | { |
|
- | 2995 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2996 | uint32_t temp; |
|
- | 2997 | ||
- | 2998 | temp = I915_READ(SOUTH_CHICKEN1); |
|
- | 2999 | if (temp & FDI_BC_BIFURCATION_SELECT) |
|
- | 3000 | return; |
|
- | 3001 | ||
- | 3002 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
|
- | 3003 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
|
- | 3004 | ||
- | 3005 | temp |= FDI_BC_BIFURCATION_SELECT; |
|
- | 3006 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
|
- | 3007 | I915_WRITE(SOUTH_CHICKEN1, temp); |
|
- | 3008 | POSTING_READ(SOUTH_CHICKEN1); |
|
- | 3009 | } |
|
- | 3010 | ||
- | 3011 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
|
- | 3012 | { |
|
- | 3013 | struct drm_device *dev = intel_crtc->base.dev; |
|
- | 3014 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3015 | ||
- | 3016 | switch (intel_crtc->pipe) { |
|
- | 3017 | case PIPE_A: |
|
- | 3018 | break; |
|
- | 3019 | case PIPE_B: |
|
- | 3020 | if (intel_crtc->config.fdi_lanes > 2) |
|
- | 3021 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
|
- | 3022 | else |
|
- | 3023 | cpt_enable_fdi_bc_bifurcation(dev); |
|
- | 3024 | ||
- | 3025 | break; |
|
- | 3026 | case PIPE_C: |
|
- | 3027 | cpt_enable_fdi_bc_bifurcation(dev); |
|
- | 3028 | ||
- | 3029 | break; |
|
- | 3030 | default: |
|
- | 3031 | BUG(); |
|
- | 3032 | } |
|
- | 3033 | } |
|
2973 | 3034 | ||
2974 | /* |
3035 | /* |
2975 | * Enable PCH resources required for PCH ports: |
3036 | * Enable PCH resources required for PCH ports: |
2976 | * - PCH PLLs |
3037 | * - PCH PLLs |
2977 | * - FDI training & RX/TX |
3038 | * - FDI training & RX/TX |
Line 2987... | Line 3048... | ||
2987 | int pipe = intel_crtc->pipe; |
3048 | int pipe = intel_crtc->pipe; |
2988 | u32 reg, temp; |
3049 | u32 reg, temp; |
Line 2989... | Line 3050... | ||
2989 | 3050 | ||
Line -... | Line 3051... | ||
- | 3051 | assert_pch_transcoder_disabled(dev_priv, pipe); |
|
- | 3052 | ||
- | 3053 | if (IS_IVYBRIDGE(dev)) |
|
2990 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3054 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
2991 | 3055 | ||
2992 | /* Write the TU size bits before fdi link training, so that error |
3056 | /* Write the TU size bits before fdi link training, so that error |
2993 | * detection works. */ |
3057 | * detection works. */ |
Line 3850... | Line 3914... | ||
3850 | dev_priv->display.off(crtc); |
3914 | dev_priv->display.off(crtc); |
Line 3851... | Line 3915... | ||
3851 | 3915 | ||
3852 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3916 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
Line 3853... | Line 3917... | ||
3853 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3917 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
3854 | 3918 | ||
3855 | // if (crtc->fb) { |
3919 | if (crtc->fb) { |
3856 | // mutex_lock(&dev->struct_mutex); |
3920 | mutex_lock(&dev->struct_mutex); |
3857 | // intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3921 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
3858 | // mutex_unlock(&dev->struct_mutex); |
3922 | mutex_unlock(&dev->struct_mutex); |
Line 3859... | Line 3923... | ||
3859 | // crtc->fb = NULL; |
3923 | crtc->fb = NULL; |
3860 | // } |
3924 | } |
3861 | 3925 | ||
3862 | /* Update computed state. */ |
3926 | /* Update computed state. */ |
Line 4975... | Line 5039... | ||
4975 | 5039 | ||
4976 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5040 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
4977 | if (!(tmp & PIPECONF_ENABLE)) |
5041 | if (!(tmp & PIPECONF_ENABLE)) |
Line -... | Line 5042... | ||
- | 5042 | return false; |
|
- | 5043 | ||
- | 5044 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
|
- | 5045 | switch (tmp & PIPECONF_BPC_MASK) { |
|
- | 5046 | case PIPECONF_6BPC: |
|
- | 5047 | pipe_config->pipe_bpp = 18; |
|
- | 5048 | break; |
|
- | 5049 | case PIPECONF_8BPC: |
|
- | 5050 | pipe_config->pipe_bpp = 24; |
|
- | 5051 | break; |
|
- | 5052 | case PIPECONF_10BPC: |
|
- | 5053 | pipe_config->pipe_bpp = 30; |
|
- | 5054 | break; |
|
- | 5055 | default: |
|
- | 5056 | break; |
|
- | 5057 | } |
|
4978 | return false; |
5058 | } |
Line 4979... | Line 5059... | ||
4979 | 5059 | ||
Line 4980... | Line 5060... | ||
4980 | intel_get_pipe_timings(crtc, pipe_config); |
5060 | intel_get_pipe_timings(crtc, pipe_config); |
Line 5568... | Line 5648... | ||
5568 | } |
5648 | } |
Line 5569... | Line 5649... | ||
5569 | 5649 | ||
5570 | return true; |
5650 | return true; |
Line 5571... | Line -... | ||
5571 | } |
- | |
5572 | - | ||
5573 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
- | |
5574 | { |
- | |
5575 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
5576 | uint32_t temp; |
- | |
5577 | - | ||
5578 | temp = I915_READ(SOUTH_CHICKEN1); |
- | |
5579 | if (temp & FDI_BC_BIFURCATION_SELECT) |
- | |
5580 | return; |
- | |
5581 | - | ||
5582 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
- | |
5583 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
- | |
5584 | - | ||
5585 | temp |= FDI_BC_BIFURCATION_SELECT; |
- | |
5586 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
- | |
5587 | I915_WRITE(SOUTH_CHICKEN1, temp); |
- | |
5588 | POSTING_READ(SOUTH_CHICKEN1); |
- | |
5589 | } |
- | |
5590 | - | ||
5591 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
- | |
5592 | { |
- | |
5593 | struct drm_device *dev = intel_crtc->base.dev; |
- | |
5594 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
5595 | - | ||
5596 | switch (intel_crtc->pipe) { |
- | |
5597 | case PIPE_A: |
- | |
5598 | break; |
- | |
5599 | case PIPE_B: |
- | |
5600 | if (intel_crtc->config.fdi_lanes > 2) |
- | |
5601 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
- | |
5602 | else |
- | |
5603 | cpt_enable_fdi_bc_bifurcation(dev); |
- | |
5604 | - | ||
5605 | break; |
- | |
5606 | case PIPE_C: |
- | |
5607 | cpt_enable_fdi_bc_bifurcation(dev); |
- | |
5608 | - | ||
5609 | break; |
- | |
5610 | default: |
- | |
5611 | BUG(); |
- | |
5612 | } |
- | |
5613 | } |
5651 | } |
5614 | 5652 | ||
5615 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5653 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5616 | { |
5654 | { |
5617 | /* |
5655 | /* |
Line 5803... | Line 5841... | ||
5803 | if (intel_crtc->config.has_pch_encoder) { |
5841 | if (intel_crtc->config.has_pch_encoder) { |
5804 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5842 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5805 | &intel_crtc->config.fdi_m_n); |
5843 | &intel_crtc->config.fdi_m_n); |
5806 | } |
5844 | } |
Line 5807... | Line -... | ||
5807 | - | ||
5808 | if (IS_IVYBRIDGE(dev)) |
- | |
5809 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
- | |
5810 | 5845 | ||
Line 5811... | Line 5846... | ||
5811 | ironlake_set_pipeconf(crtc); |
5846 | ironlake_set_pipeconf(crtc); |
5812 | 5847 | ||
5813 | /* Set up the display plane register */ |
5848 | /* Set up the display plane register */ |
Line 5873... | Line 5908... | ||
5873 | 5908 | ||
5874 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5909 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5875 | if (!(tmp & PIPECONF_ENABLE)) |
5910 | if (!(tmp & PIPECONF_ENABLE)) |
Line -... | Line 5911... | ||
- | 5911 | return false; |
|
- | 5912 | ||
- | 5913 | switch (tmp & PIPECONF_BPC_MASK) { |
|
- | 5914 | case PIPECONF_6BPC: |
|
- | 5915 | pipe_config->pipe_bpp = 18; |
|
- | 5916 | break; |
|
- | 5917 | case PIPECONF_8BPC: |
|
- | 5918 | pipe_config->pipe_bpp = 24; |
|
- | 5919 | break; |
|
- | 5920 | case PIPECONF_10BPC: |
|
- | 5921 | pipe_config->pipe_bpp = 30; |
|
- | 5922 | break; |
|
- | 5923 | case PIPECONF_12BPC: |
|
- | 5924 | pipe_config->pipe_bpp = 36; |
|
- | 5925 | break; |
|
- | 5926 | default: |
|
- | 5927 | break; |
|
5876 | return false; |
5928 | } |
5877 | 5929 | ||
Line 5878... | Line 5930... | ||
5878 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
5930 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
Line 7048... | Line 7100... | ||
7048 | { |
7100 | { |
7049 | struct drm_i915_private *dev_priv = dev->dev_private; |
7101 | struct drm_i915_private *dev_priv = dev->dev_private; |
7050 | struct drm_i915_gem_object *obj; |
7102 | struct drm_i915_gem_object *obj; |
7051 | struct drm_framebuffer *fb; |
7103 | struct drm_framebuffer *fb; |
Line 7052... | Line 7104... | ||
7052 | 7104 | ||
7053 | // if (dev_priv->fbdev == NULL) |
7105 | if (dev_priv->fbdev == NULL) |
Line 7054... | Line 7106... | ||
7054 | // return NULL; |
7106 | return NULL; |
7055 | 7107 | ||
7056 | // obj = dev_priv->fbdev->ifb.obj; |
7108 | obj = dev_priv->fbdev->ifb.obj; |
Line 7057... | Line 7109... | ||
7057 | // if (obj == NULL) |
7109 | if (obj == NULL) |
7058 | return NULL; |
7110 | return NULL; |
7059 | 7111 | ||
7060 | // if (obj->base.size < mode->vdisplay * fb->pitch) |
7112 | fb = &dev_priv->fbdev->ifb.base; |
Line 7061... | Line 7113... | ||
7061 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7113 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7062 | fb->bits_per_pixel)) |
7114 | fb->bits_per_pixel)) |
Line 7063... | Line 7115... | ||
7063 | // return NULL; |
7115 | return NULL; |
7064 | 7116 | ||
Line 7065... | Line 7117... | ||
7065 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7117 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
7066 | return NULL; |
7118 | return NULL; |
7067 | 7119 | ||
Line 8595... | Line 8647... | ||
8595 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8647 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8596 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
8648 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
8597 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8649 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8598 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
8650 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
Line -... | Line 8651... | ||
- | 8651 | ||
- | 8652 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
|
- | 8653 | PIPE_CONF_CHECK_I(pipe_bpp); |
|
8599 | 8654 | ||
8600 | #undef PIPE_CONF_CHECK_X |
8655 | #undef PIPE_CONF_CHECK_X |
8601 | #undef PIPE_CONF_CHECK_I |
8656 | #undef PIPE_CONF_CHECK_I |
8602 | #undef PIPE_CONF_CHECK_FLAGS |
8657 | #undef PIPE_CONF_CHECK_FLAGS |
Line 9950... | Line 10005... | ||
9950 | q->subsystem_vendor == PCI_ANY_ID) && |
10005 | q->subsystem_vendor == PCI_ANY_ID) && |
9951 | (d->subsystem_device == q->subsystem_device || |
10006 | (d->subsystem_device == q->subsystem_device || |
9952 | q->subsystem_device == PCI_ANY_ID)) |
10007 | q->subsystem_device == PCI_ANY_ID)) |
9953 | q->hook(dev); |
10008 | q->hook(dev); |
9954 | } |
10009 | } |
9955 | // for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
- | |
9956 | // if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
- | |
9957 | // intel_dmi_quirks[i].hook(dev); |
- | |
9958 | // } |
- | |
9959 | } |
10010 | } |
Line 9960... | Line 10011... | ||
9960 | 10011 | ||
9961 | /* Disable the VGA plane that we never use */ |
10012 | /* Disable the VGA plane that we never use */ |
9962 | static void i915_disable_vga(struct drm_device *dev) |
10013 | static void i915_disable_vga(struct drm_device *dev) |
Line 10469... | Line 10520... | ||
10469 | 10520 | ||
Line 10470... | Line 10521... | ||
10470 | mutex_unlock(&dev->struct_mutex); |
10521 | mutex_unlock(&dev->struct_mutex); |
10471 | 10522 | ||
10472 | /* flush any delayed tasks or pending work */ |
- | |
10473 | flush_scheduled_work(); |
- | |
Line 10474... | Line 10523... | ||
10474 | // cancel_work_sync(&dev_priv->hotplug_work); |
10523 | /* flush any delayed tasks or pending work */ |
10475 | // cancel_work_sync(&dev_priv->rps.work); |
10524 | flush_scheduled_work(); |
Line 10476... | Line 10525... | ||
10476 | 10525 | ||
10477 | /* flush any delayed tasks or pending work */ |
10526 | /* destroy backlight, if any, before the connectors */ |
10478 | // flush_scheduled_work(); |
10527 | intel_panel_destroy_backlight(dev); |