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| Rev 2351 | Rev 2360 | ||
|---|---|---|---|
| Line 1857... | Line 1857... | ||
| 1857 | 1857 | ||
| 1858 | enable_fbc = i915_enable_fbc; |
1858 | enable_fbc = i915_enable_fbc; |
| 1859 | if (enable_fbc < 0) { |
1859 | if (enable_fbc < 0) { |
| 1860 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
1860 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
| 1861 | enable_fbc = 1; |
1861 | enable_fbc = 1; |
| 1862 | if (INTEL_INFO(dev)->gen <= 5) |
1862 | if (INTEL_INFO(dev)->gen <= 6) |
| 1863 | enable_fbc = 0; |
1863 | enable_fbc = 0; |
| 1864 | } |
1864 | } |
| 1865 | if (!enable_fbc) { |
1865 | if (!enable_fbc) { |
| 1866 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
1866 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
| Line 2169... | Line 2169... | ||
| 2169 | { |
2169 | { |
| 2170 | struct drm_device *dev = crtc->dev; |
2170 | struct drm_device *dev = crtc->dev; |
| 2171 | struct drm_i915_private *dev_priv = dev->dev_private; |
2171 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2172 | int ret; |
2172 | int ret; |
| Line 2173... | Line -... | ||
| 2173 | - | ||
| 2174 | ENTER(); |
- | |
| 2175 | 2173 | ||
| 2176 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
2174 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
| 2177 | if (ret) |
- | |
| 2178 | { |
- | |
| 2179 | LEAVE(); |
2175 | if (ret) |
| 2180 | return ret; |
- | |
| Line 2181... | Line 2176... | ||
| 2181 | }; |
2176 | return ret; |
| 2182 | 2177 | ||
| 2183 | intel_update_fbc(dev); |
- | |
| Line 2184... | Line 2178... | ||
| 2184 | intel_increase_pllclock(crtc); |
2178 | intel_update_fbc(dev); |
| 2185 | LEAVE(); |
2179 | intel_increase_pllclock(crtc); |
| Line 2186... | Line 2180... | ||
| 2186 | 2180 | ||
| Line 2233... | Line 2227... | ||
| 2233 | 2227 | ||
| 2234 | 2228 | ||
| Line 2235... | Line -... | ||
| 2235 | LEAVE(); |
- | |
| 2236 | return 0; |
- | |
| 2237 | - | ||
| 2238 | #if 0 |
- | |
| 2239 | if (!dev->primary->master) |
- | |
| 2240 | { |
- | |
| 2241 | LEAVE(); |
- | |
| 2242 | return 0; |
- | |
| 2243 | }; |
- | |
| 2244 | - | ||
| 2245 | master_priv = dev->primary->master->driver_priv; |
- | |
| 2246 | if (!master_priv->sarea_priv) |
- | |
| 2247 | { |
- | |
| 2248 | LEAVE(); |
- | |
| 2249 | return 0; |
- | |
| 2250 | }; |
- | |
| 2251 | - | ||
| 2252 | if (intel_crtc->pipe) { |
- | |
| 2253 | master_priv->sarea_priv->pipeB_x = x; |
- | |
| 2254 | master_priv->sarea_priv->pipeB_y = y; |
- | |
| 2255 | } else { |
- | |
| 2256 | master_priv->sarea_priv->pipeA_x = x; |
- | |
| 2257 | master_priv->sarea_priv->pipeA_y = y; |
- | |
| 2258 | } |
- | |
| 2259 | LEAVE(); |
- | |
| Line 2260... | Line 2229... | ||
| 2260 | 2229 | LEAVE(); |
|
| Line 2261... | Line 2230... | ||
| 2261 | return 0; |
2230 | return 0; |
| 2262 | #endif |
2231 | |
| Line 2833... | Line 2802... | ||
| 2833 | if (crtc->fb == NULL) |
2802 | if (crtc->fb == NULL) |
| 2834 | return; |
2803 | return; |
| Line 2835... | Line 2804... | ||
| 2835 | 2804 | ||
| 2836 | obj = to_intel_framebuffer(crtc->fb)->obj; |
2805 | obj = to_intel_framebuffer(crtc->fb)->obj; |
| 2837 | dev_priv = crtc->dev->dev_private; |
2806 | dev_priv = crtc->dev->dev_private; |
| 2838 | // wait_event(dev_priv->pending_flip_queue, |
2807 | wait_event(dev_priv->pending_flip_queue, |
| 2839 | // atomic_read(&obj->pending_flip) == 0); |
2808 | atomic_read(&obj->pending_flip) == 0); |
| Line 2840... | Line 2809... | ||
| 2840 | } |
2809 | } |
| 2841 | 2810 | ||
| 2842 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2811 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
| Line 5290... | Line 5259... | ||
| 5290 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
5259 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
| 5291 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5260 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 5292 | } |
5261 | } |
| 5293 | } |
5262 | } |
| Line -... | Line 5263... | ||
| - | 5263 | ||
| 5294 | 5264 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
|
| 5295 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5265 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 5296 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5266 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 5297 | /* the chip adds 2 halflines automatically */ |
5267 | /* the chip adds 2 halflines automatically */ |
| 5298 | adjusted_mode->crtc_vdisplay -= 1; |
5268 | adjusted_mode->crtc_vdisplay -= 1; |
| 5299 | adjusted_mode->crtc_vtotal -= 1; |
5269 | adjusted_mode->crtc_vtotal -= 1; |
| 5300 | adjusted_mode->crtc_vblank_start -= 1; |
5270 | adjusted_mode->crtc_vblank_start -= 1; |
| 5301 | adjusted_mode->crtc_vblank_end -= 1; |
5271 | adjusted_mode->crtc_vblank_end -= 1; |
| 5302 | adjusted_mode->crtc_vsync_end -= 1; |
5272 | adjusted_mode->crtc_vsync_end -= 1; |
| 5303 | adjusted_mode->crtc_vsync_start -= 1; |
5273 | adjusted_mode->crtc_vsync_start -= 1; |
| 5304 | } else |
5274 | } else |
| Line 5305... | Line 5275... | ||
| 5305 | pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */ |
5275 | pipeconf |= PIPECONF_PROGRESSIVE; |
| 5306 | 5276 | ||
| 5307 | I915_WRITE(HTOTAL(pipe), |
5277 | I915_WRITE(HTOTAL(pipe), |
| 5308 | (adjusted_mode->crtc_hdisplay - 1) | |
5278 | (adjusted_mode->crtc_hdisplay - 1) | |
| Line 5887... | Line 5857... | ||
| 5887 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5857 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 5888 | } |
5858 | } |
| 5889 | } |
5859 | } |
| 5890 | } |
5860 | } |
| Line -... | Line 5861... | ||
| - | 5861 | ||
| 5891 | 5862 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
|
| 5892 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5863 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 5893 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5864 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 5894 | /* the chip adds 2 halflines automatically */ |
5865 | /* the chip adds 2 halflines automatically */ |
| 5895 | adjusted_mode->crtc_vdisplay -= 1; |
5866 | adjusted_mode->crtc_vdisplay -= 1; |
| 5896 | adjusted_mode->crtc_vtotal -= 1; |
5867 | adjusted_mode->crtc_vtotal -= 1; |
| 5897 | adjusted_mode->crtc_vblank_start -= 1; |
5868 | adjusted_mode->crtc_vblank_start -= 1; |
| 5898 | adjusted_mode->crtc_vblank_end -= 1; |
5869 | adjusted_mode->crtc_vblank_end -= 1; |
| 5899 | adjusted_mode->crtc_vsync_end -= 1; |
5870 | adjusted_mode->crtc_vsync_end -= 1; |
| 5900 | adjusted_mode->crtc_vsync_start -= 1; |
5871 | adjusted_mode->crtc_vsync_start -= 1; |
| 5901 | } else |
5872 | } else |
| Line 5902... | Line 5873... | ||
| 5902 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ |
5873 | pipeconf |= PIPECONF_PROGRESSIVE; |
| 5903 | 5874 | ||
| 5904 | I915_WRITE(HTOTAL(pipe), |
5875 | I915_WRITE(HTOTAL(pipe), |
| 5905 | (adjusted_mode->crtc_hdisplay - 1) | |
5876 | (adjusted_mode->crtc_hdisplay - 1) | |
| Line 7041... | Line 7012... | ||
| 7041 | } |
7012 | } |
| Line 7042... | Line -... | ||
| 7042 | - | ||
| 7043 | - | ||
| 7044 | - | ||
| 7045 | - | ||
| Line 7046... | Line 7013... | ||
| 7046 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
7013 | |
| Line 7098... | Line 7065... | ||
| 7098 | intel_fb->obj = obj; |
7065 | intel_fb->obj = obj; |
| 7099 | return 0; |
7066 | return 0; |
| 7100 | } |
7067 | } |
| Line -... | Line 7068... | ||
| - | 7068 | ||
| - | 7069 | ||
| - | 7070 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
|
| 7101 | 7071 | .fb_create = NULL /*intel_user_framebuffer_create*/, |
|