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Rev 5354 Rev 6084
Line 29... Line 29...
29 
#include "intel_drv.h"
 29 
#include "intel_drv.h"
Line 30... Line 30...
30 
 
 30 
 
31 
struct ddi_buf_trans {
 31 
struct ddi_buf_trans {
32 
	u32 trans1;	/* balance leg enable, de-emph level */
 32 
	u32 trans1;	/* balance leg enable, de-emph level */
- 
 
 33 
	u32 trans2;	/* vref sel, vswing */
33 
	u32 trans2;	/* vref sel, vswing */
 34 
	u8 i_boost;	/* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
Line 34... Line 35...
34 
};
 35 
};
35 
 
 36 
 
36 
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
 37 
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 
 * them for both DP and FDI transports, allowing those ports to
 38 
 * them for both DP and FDI transports, allowing those ports to
38 
 * automatically adapt to HDMI connections as well
 39 
 * automatically adapt to HDMI connections as well
39 
 */
 40 
 */
40 
static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
 41 
static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 
	{ 0x00FFFFFF, 0x0006000E },
 42 
	{ 0x00FFFFFF, 0x0006000E, 0x0 },
42 
	{ 0x00D75FFF, 0x0005000A },
 43 
	{ 0x00D75FFF, 0x0005000A, 0x0 },
43 
	{ 0x00C30FFF, 0x00040006 },
 44 
	{ 0x00C30FFF, 0x00040006, 0x0 },
44 
	{ 0x80AAAFFF, 0x000B0000 },
 45 
	{ 0x80AAAFFF, 0x000B0000, 0x0 },
45 
	{ 0x00FFFFFF, 0x0005000A },
 46 
	{ 0x00FFFFFF, 0x0005000A, 0x0 },
46 
	{ 0x00D75FFF, 0x000C0004 },
 47 
	{ 0x00D75FFF, 0x000C0004, 0x0 },
47 
	{ 0x80C30FFF, 0x000B0000 },
 48 
	{ 0x80C30FFF, 0x000B0000, 0x0 },
48 
	{ 0x00FFFFFF, 0x00040006 },
 49 
	{ 0x00FFFFFF, 0x00040006, 0x0 },
Line 49... Line 50...
49 
	{ 0x80D75FFF, 0x000B0000 },
 50 
	{ 0x80D75FFF, 0x000B0000, 0x0 },
50 
};
 51 
};
51 
 
 52 
 
52 
static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
 53 
static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 
	{ 0x00FFFFFF, 0x0007000E },
 54 
	{ 0x00FFFFFF, 0x0007000E, 0x0 },
54 
	{ 0x00D75FFF, 0x000F000A },
 55 
	{ 0x00D75FFF, 0x000F000A, 0x0 },
55 
	{ 0x00C30FFF, 0x00060006 },
 56 
	{ 0x00C30FFF, 0x00060006, 0x0 },
56 
	{ 0x00AAAFFF, 0x001E0000 },
 57 
	{ 0x00AAAFFF, 0x001E0000, 0x0 },
57 
	{ 0x00FFFFFF, 0x000F000A },
 58 
	{ 0x00FFFFFF, 0x000F000A, 0x0 },
58 
	{ 0x00D75FFF, 0x00160004 },
 59 
	{ 0x00D75FFF, 0x00160004, 0x0 },
59 
	{ 0x00C30FFF, 0x001E0000 },
 60 
	{ 0x00C30FFF, 0x001E0000, 0x0 },
Line 60... Line 61...
60 
	{ 0x00FFFFFF, 0x00060006 },
 61 
	{ 0x00FFFFFF, 0x00060006, 0x0 },
61 
	{ 0x00D75FFF, 0x001E0000 },
 62 
	{ 0x00D75FFF, 0x001E0000, 0x0 },
62 
};
 63 
};
63 
 
 64 
 
64 
static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 65 
static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 
					/* Idx	NT mV d	T mV d	db	*/
 66 
					/* Idx	NT mV d	T mV d	db	*/
66 
	{ 0x00FFFFFF, 0x0006000E },	/* 0:	400	400	0	*/
 67 
	{ 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:	400	400	0	*/
67 
	{ 0x00E79FFF, 0x000E000C },	/* 1:	400	500	2	*/
 68 
	{ 0x00E79FFF, 0x000E000C, 0x0 },/* 1:	400	500	2	*/
68 
	{ 0x00D75FFF, 0x0005000A },	/* 2:	400	600	3.5	*/
 69 
	{ 0x00D75FFF, 0x0005000A, 0x0 },/* 2:	400	600	3.5	*/
69 
	{ 0x00FFFFFF, 0x0005000A },	/* 3:	600	600	0	*/
 70 
	{ 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:	600	600	0	*/
70 
	{ 0x00E79FFF, 0x001D0007 },	/* 4:	600	750	2	*/
 71 
	{ 0x00E79FFF, 0x001D0007, 0x0 },/* 4:	600	750	2	*/
71 
	{ 0x00D75FFF, 0x000C0004 },	/* 5:	600	900	3.5	*/
 72 
	{ 0x00D75FFF, 0x000C0004, 0x0 },/* 5:	600	900	3.5	*/
72 
	{ 0x00FFFFFF, 0x00040006 },	/* 6:	800	800	0	*/
 73 
	{ 0x00FFFFFF, 0x00040006, 0x0 },/* 6:	800	800	0	*/
73 
	{ 0x80E79FFF, 0x00030002 },	/* 7:	800	1000	2	*/
 74 
	{ 0x80E79FFF, 0x00030002, 0x0 },/* 7:	800	1000	2	*/
74 
	{ 0x00FFFFFF, 0x00140005 },	/* 8:	850	850	0	*/
 75 
	{ 0x00FFFFFF, 0x00140005, 0x0 },/* 8:	850	850	0	*/
Line 75... Line 76...
75 
	{ 0x00FFFFFF, 0x000C0004 },	/* 9:	900	900	0	*/
 76 
	{ 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:	900	900	0	*/
76 
	{ 0x00FFFFFF, 0x001C0003 },	/* 10:	950	950	0	*/
 77 
	{ 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:	950	950	0	*/
77 
	{ 0x80FFFFFF, 0x00030002 },	/* 11:	1000	1000	0	*/
 78 
	{ 0x80FFFFFF, 0x00030002, 0x0 },/* 11:	1000	1000	0	*/
78 
};
 79 
};
79 
 
 80 
 
80 
static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 81 
static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 
	{ 0x00FFFFFF, 0x00000012 },
 82 
	{ 0x00FFFFFF, 0x00000012, 0x0 },
82 
	{ 0x00EBAFFF, 0x00020011 },
 83 
	{ 0x00EBAFFF, 0x00020011, 0x0 },
83 
	{ 0x00C71FFF, 0x0006000F },
 84 
	{ 0x00C71FFF, 0x0006000F, 0x0 },
84 
	{ 0x00AAAFFF, 0x000E000A },
 85 
	{ 0x00AAAFFF, 0x000E000A, 0x0 },
85 
	{ 0x00FFFFFF, 0x00020011 },
 86 
	{ 0x00FFFFFF, 0x00020011, 0x0 },
Line 86... Line 87...
86 
	{ 0x00DB6FFF, 0x0005000F },
 87 
	{ 0x00DB6FFF, 0x0005000F, 0x0 },
87 
	{ 0x00BEEFFF, 0x000A000C },
 88 
	{ 0x00BEEFFF, 0x000A000C, 0x0 },
88 
	{ 0x00FFFFFF, 0x0005000F },
 89 
	{ 0x00FFFFFF, 0x0005000F, 0x0 },
89 
	{ 0x00DB6FFF, 0x000A000C },
 90 
	{ 0x00DB6FFF, 0x000A000C, 0x0 },
90 
};
 91 
};
91 
 
 92 
 
92 
static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 93 
static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 
	{ 0x00FFFFFF, 0x0007000E },
 94 
	{ 0x00FFFFFF, 0x0007000E, 0x0 },
94 
	{ 0x00D75FFF, 0x000E000A },
 95 
	{ 0x00D75FFF, 0x000E000A, 0x0 },
95 
	{ 0x00BEFFFF, 0x00140006 },
 96 
	{ 0x00BEFFFF, 0x00140006, 0x0 },
96 
	{ 0x80B2CFFF, 0x001B0002 },
 97 
	{ 0x80B2CFFF, 0x001B0002, 0x0 },
Line 97... Line 98...
97 
	{ 0x00FFFFFF, 0x000E000A },
 98 
	{ 0x00FFFFFF, 0x000E000A, 0x0 },
98 
	{ 0x00DB6FFF, 0x00160005 },
 99 
	{ 0x00DB6FFF, 0x00160005, 0x0 },
99 
	{ 0x80C71FFF, 0x001A0002 },
 100 
	{ 0x80C71FFF, 0x001A0002, 0x0 },
100 
	{ 0x00F7DFFF, 0x00180004 },
 101 
	{ 0x00F7DFFF, 0x00180004, 0x0 },
101 
	{ 0x80D75FFF, 0x001B0002 },
 102 
	{ 0x80D75FFF, 0x001B0002, 0x0 },
102 
};
 103 
};
103 
 
 104 
 
104 
static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 105 
static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 
	{ 0x00FFFFFF, 0x0001000E },
 106 
	{ 0x00FFFFFF, 0x0001000E, 0x0 },
106 
	{ 0x00D75FFF, 0x0004000A },
 107 
	{ 0x00D75FFF, 0x0004000A, 0x0 },
107 
	{ 0x00C30FFF, 0x00070006 },
 108 
	{ 0x00C30FFF, 0x00070006, 0x0 },
Line 108... Line 109...
108 
	{ 0x00AAAFFF, 0x000C0000 },
 109 
	{ 0x00AAAFFF, 0x000C0000, 0x0 },
109 
	{ 0x00FFFFFF, 0x0004000A },
 110 
	{ 0x00FFFFFF, 0x0004000A, 0x0 },
110 
	{ 0x00D75FFF, 0x00090004 },
 111 
	{ 0x00D75FFF, 0x00090004, 0x0 },
111 
	{ 0x00C30FFF, 0x000C0000 },
 112 
	{ 0x00C30FFF, 0x000C0000, 0x0 },
112 
	{ 0x00FFFFFF, 0x00070006 },
 113 
	{ 0x00FFFFFF, 0x00070006, 0x0 },
113 
	{ 0x00D75FFF, 0x000C0000 },
 114 
	{ 0x00D75FFF, 0x000C0000, 0x0 },
114 
};
 115 
};
115 
 
 116 
 
116 
static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 117 
static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 
					/* Idx	NT mV d	T mV df	db	*/
 118 
					/* Idx	NT mV d	T mV df	db	*/
118 
	{ 0x00FFFFFF, 0x0007000E },	/* 0:	400	400	0	*/
 119 
	{ 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:	400	400	0	*/
119 
	{ 0x00D75FFF, 0x000E000A },	/* 1:	400	600	3.5	*/
 120 
	{ 0x00D75FFF, 0x000E000A, 0x0 },/* 1:	400	600	3.5	*/
120 
	{ 0x00BEFFFF, 0x00140006 },	/* 2:	400	800	6	*/
 121 
	{ 0x00BEFFFF, 0x00140006, 0x0 },/* 2:	400	800	6	*/
Line -... Line 122...
- 
 
 122 
	{ 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:	450	450	0	*/
121 
	{ 0x00FFFFFF, 0x0009000D },	/* 3:	450	450	0	*/
 123 
	{ 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:	600	600	0	*/
122 
	{ 0x00FFFFFF, 0x000E000A },	/* 4:	600	600	0	*/
 124 
	{ 0x00D7FFFF, 0x00140006, 0x0 },/* 5:	600	800	2.5	*/
123 
	{ 0x00D7FFFF, 0x00140006 },	/* 5:	600	800	2.5	*/
 125 
	{ 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:	600	1000	4.5	*/
124 
	{ 0x80CB2FFF, 0x001B0002 },	/* 6:	600	1000	4.5	*/
 126 
	{ 0x00FFFFFF, 0x00140006, 0x0 },/* 7:	800	800	0	*/
125 
	{ 0x00FFFFFF, 0x00140006 },	/* 7:	800	800	0	*/
 127 
	{ 0x80E79FFF, 0x001B0002, 0x0 },/* 8:	800	1000	2	*/
126 
	{ 0x80E79FFF, 0x001B0002 },	/* 8:	800	1000	2	*/
 128 
	{ 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:	1000	1000	0	*/
127 
	{ 0x80FFFFFF, 0x001B0002 },	/* 9:	1000	1000	0	*/
 129 
};
128 
};
 130 
 
129 
 
 131 
/* Skylake H and S */
130 
static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 132 
static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
131 
	{ 0x00000018, 0x000000a0 },
 133 
	{ 0x00002016, 0x000000A0, 0x0 },
Line -... Line 134...
- 
 
 134 
	{ 0x00005012, 0x0000009B, 0x0 },
- 
 
 135 
	{ 0x00007011, 0x00000088, 0x0 },
- 
 
 136 
	{ 0x00009010, 0x000000C7, 0x0 },
- 
 
 137 
	{ 0x00002016, 0x0000009B, 0x0 },
- 
 
 138 
	{ 0x00005012, 0x00000088, 0x0 },
- 
 
 139 
	{ 0x00007011, 0x000000C7, 0x0 },
- 
 
 140 
	{ 0x00002016, 0x000000DF, 0x0 },
- 
 
 141 
	{ 0x00005012, 0x000000C7, 0x0 },
- 
 
 142 
};
- 
 
 143 
 
- 
 
 144 
/* Skylake U */
- 
 
 145 
static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
- 
 
 146 
	{ 0x0000201B, 0x000000A2, 0x0 },
- 
 
 147 
	{ 0x00005012, 0x00000088, 0x0 },
- 
 
 148 
	{ 0x00007011, 0x00000087, 0x0 },
- 
 
 149 
	{ 0x80009010, 0x000000C7, 0x1 },	/* Uses I_boost level 0x1 */
- 
 
 150 
	{ 0x0000201B, 0x0000009D, 0x0 },
- 
 
 151 
	{ 0x00005012, 0x000000C7, 0x0 },
- 
 
 152 
	{ 0x00007011, 0x000000C7, 0x0 },
- 
 
 153 
	{ 0x00002016, 0x00000088, 0x0 },
- 
 
 154 
	{ 0x00005012, 0x000000C7, 0x0 },
- 
 
 155 
};
- 
 
 156 
 
- 
 
 157 
/* Skylake Y */
- 
 
 158 
static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
- 
 
 159 
	{ 0x00000018, 0x000000A2, 0x0 },
- 
 
 160 
	{ 0x00005012, 0x00000088, 0x0 },
- 
 
 161 
	{ 0x00007011, 0x00000087, 0x0 },
- 
 
 162 
	{ 0x80009010, 0x000000C7, 0x3 },	/* Uses I_boost level 0x3 */
- 
 
 163 
	{ 0x00000018, 0x0000009D, 0x0 },
- 
 
 164 
	{ 0x00005012, 0x000000C7, 0x0 },
- 
 
 165 
	{ 0x00007011, 0x000000C7, 0x0 },
- 
 
 166 
	{ 0x00000018, 0x00000088, 0x0 },
- 
 
 167 
	{ 0x00005012, 0x000000C7, 0x0 },
- 
 
 168 
};
- 
 
 169 
 
- 
 
 170 
/*
- 
 
 171 
 * Skylake H and S
- 
 
 172 
 * eDP 1.4 low vswing translation parameters
- 
 
 173 
 */
- 
 
 174 
static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
- 
 
 175 
	{ 0x00000018, 0x000000A8, 0x0 },
- 
 
 176 
	{ 0x00004013, 0x000000A9, 0x0 },
- 
 
 177 
	{ 0x00007011, 0x000000A2, 0x0 },
- 
 
 178 
	{ 0x00009010, 0x0000009C, 0x0 },
- 
 
 179 
	{ 0x00000018, 0x000000A9, 0x0 },
- 
 
 180 
	{ 0x00006013, 0x000000A2, 0x0 },
- 
 
 181 
	{ 0x00007011, 0x000000A6, 0x0 },
- 
 
 182 
	{ 0x00000018, 0x000000AB, 0x0 },
- 
 
 183 
	{ 0x00007013, 0x0000009F, 0x0 },
- 
 
 184 
	{ 0x00000018, 0x000000DF, 0x0 },
- 
 
 185 
};
- 
 
 186 
 
- 
 
 187 
/*
- 
 
 188 
 * Skylake U
- 
 
 189 
 * eDP 1.4 low vswing translation parameters
- 
 
 190 
 */
- 
 
 191 
static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
- 
 
 192 
	{ 0x00000018, 0x000000A8, 0x0 },
- 
 
 193 
	{ 0x00004013, 0x000000A9, 0x0 },
- 
 
 194 
	{ 0x00007011, 0x000000A2, 0x0 },
- 
 
 195 
	{ 0x00009010, 0x0000009C, 0x0 },
- 
 
 196 
	{ 0x00000018, 0x000000A9, 0x0 },
- 
 
 197 
	{ 0x00006013, 0x000000A2, 0x0 },
- 
 
 198 
	{ 0x00007011, 0x000000A6, 0x0 },
- 
 
 199 
	{ 0x00002016, 0x000000AB, 0x0 },
- 
 
 200 
	{ 0x00005013, 0x0000009F, 0x0 },
- 
 
 201 
	{ 0x00000018, 0x000000DF, 0x0 },
- 
 
 202 
};
- 
 
 203 
 
- 
 
 204 
/*
- 
 
 205 
 * Skylake Y
- 
 
 206 
 * eDP 1.4 low vswing translation parameters
- 
 
 207 
 */
- 
 
 208 
static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
- 
 
 209 
	{ 0x00000018, 0x000000A8, 0x0 },
- 
 
 210 
	{ 0x00004013, 0x000000AB, 0x0 },
- 
 
 211 
	{ 0x00007011, 0x000000A4, 0x0 },
132 
	{ 0x00004014, 0x00000098 },
 212 
	{ 0x00009010, 0x000000DF, 0x0 },
133 
	{ 0x00006012, 0x00000088 },
 213 
	{ 0x00000018, 0x000000AA, 0x0 },
134 
	{ 0x00008010, 0x00000080 },
 214 
	{ 0x00006013, 0x000000A4, 0x0 },
135 
	{ 0x00000018, 0x00000098 },
 215 
	{ 0x00007011, 0x0000009D, 0x0 },
136 
	{ 0x00004014, 0x00000088 },
 216 
	{ 0x00000018, 0x000000A0, 0x0 },
137 
	{ 0x00006012, 0x00000080 },
 217 
	{ 0x00006012, 0x000000DF, 0x0 },
138 
	{ 0x00000018, 0x00000088 },
 218 
	{ 0x00000018, 0x0000008A, 0x0 },
139 
	{ 0x00004014, 0x00000080 },
 219 
};
140 
};
 220 
 
141 
 
 221 
/* Skylake U, H and S */
142 
static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 222 
static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
143 
					/* Idx	NT mV   T mV    db  */
 223 
	{ 0x00000018, 0x000000AC, 0x0 },
144 
	{ 0x00000018, 0x000000a0 },	/* 0:	400	400	0   */
 224 
	{ 0x00005012, 0x0000009D, 0x0 },
Line -... Line 225...
- 
 
 225 
	{ 0x00007011, 0x00000088, 0x0 },
- 
 
 226 
	{ 0x00000018, 0x000000A1, 0x0 },
- 
 
 227 
	{ 0x00000018, 0x00000098, 0x0 },
- 
 
 228 
	{ 0x00004013, 0x00000088, 0x0 },
- 
 
 229 
	{ 0x00006012, 0x00000087, 0x0 },
- 
 
 230 
	{ 0x00000018, 0x000000DF, 0x0 },
- 
 
 231 
	{ 0x00003015, 0x00000087, 0x0 },	/* Default */
- 
 
 232 
	{ 0x00003015, 0x000000C7, 0x0 },
- 
 
 233 
	{ 0x00000018, 0x000000C7, 0x0 },
- 
 
 234 
};
- 
 
 235 
 
- 
 
 236 
/* Skylake Y */
- 
 
 237 
static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
- 
 
 238 
	{ 0x00000018, 0x000000A1, 0x0 },
- 
 
 239 
	{ 0x00005012, 0x000000DF, 0x0 },
- 
 
 240 
	{ 0x00007011, 0x00000084, 0x0 },
- 
 
 241 
	{ 0x00000018, 0x000000A4, 0x0 },
- 
 
 242 
	{ 0x00000018, 0x0000009D, 0x0 },
- 
 
 243 
	{ 0x00004013, 0x00000080, 0x0 },
- 
 
 244 
	{ 0x00006013, 0x000000C7, 0x0 },
- 
 
 245 
	{ 0x00000018, 0x0000008A, 0x0 },
- 
 
 246 
	{ 0x00003015, 0x000000C7, 0x0 },	/* Default */
- 
 
 247 
	{ 0x80003015, 0x000000C7, 0x7 },	/* Uses I_boost level 0x7 */
- 
 
 248 
	{ 0x00000018, 0x000000C7, 0x0 },
- 
 
 249 
};
- 
 
 250 
 
- 
 
 251 
struct bxt_ddi_buf_trans {
- 
 
 252 
	u32 margin;	/* swing value */
- 
 
 253 
	u32 scale;	/* scale value */
- 
 
 254 
	u32 enable;	/* scale enable */
- 
 
 255 
	u32 deemphasis;
- 
 
 256 
	bool default_index; /* true if the entry represents default value */
- 
 
 257 
};
- 
 
 258 
 
- 
 
 259 
static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
- 
 
 260 
					/* Idx	NT mV diff	db  */
- 
 
 261 
	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
- 
 
 262 
	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
- 
 
 263 
	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
- 
 
 264 
	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
- 
 
 265 
	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
- 
 
 266 
	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
- 
 
 267 
	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
- 
 
 268 
	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
- 
 
 269 
	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
- 
 
 270 
	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
- 
 
 271 
};
- 
 
 272 
 
- 
 
 273 
static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
- 
 
 274 
					/* Idx	NT mV diff	db  */
- 
 
 275 
	{ 26, 0, 0, 128, false },	/* 0:	200		0   */
- 
 
 276 
	{ 38, 0, 0, 112, false },	/* 1:	200		1.5 */
- 
 
 277 
	{ 48, 0, 0, 96,  false },	/* 2:	200		4   */
- 
 
 278 
	{ 54, 0, 0, 69,  false },	/* 3:	200		6   */
- 
 
 279 
	{ 32, 0, 0, 128, false },	/* 4:	250		0   */
- 
 
 280 
	{ 48, 0, 0, 104, false },	/* 5:	250		1.5 */
- 
 
 281 
	{ 54, 0, 0, 85,  false },	/* 6:	250		4   */
- 
 
 282 
	{ 43, 0, 0, 128, false },	/* 7:	300		0   */
- 
 
 283 
	{ 54, 0, 0, 101, false },	/* 8:	300		1.5 */
- 
 
 284 
	{ 48, 0, 0, 128, false },	/* 9:	300		0   */
- 
 
 285 
};
- 
 
 286 
 
- 
 
 287 
/* BSpec has 2 recommended values - entries 0 and 8.
- 
 
 288 
 * Using the entry with higher vswing.
- 
 
 289 
 */
- 
 
 290 
static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
- 
 
 291 
					/* Idx	NT mV diff	db  */
- 
 
 292 
	{ 52,  0x9A, 0, 128, false },	/* 0:	400		0   */
- 
 
 293 
	{ 52,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
- 
 
 294 
	{ 52,  0x9A, 0, 64,  false },	/* 2:	400		6   */
- 
 
 295 
	{ 42,  0x9A, 0, 43,  false },	/* 3:	400		9.5 */
145 
	{ 0x00004014, 0x00000098 },	/* 1:	400	600	3.5 */
 296 
	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
- 
 
 297 
	{ 77,  0x9A, 0, 85,  false },	/* 5:	600		3.5 */
- 
 
 298 
	{ 77,  0x9A, 0, 64,  false },	/* 6:	600		6   */
146 
	{ 0x00006012, 0x00000088 },	/* 2:	400	800	6   */
 299 
	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
147 
	{ 0x00000018, 0x0000003c },	/* 3:	450	450	0   */
 300 
	{ 102, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
148 
	{ 0x00000018, 0x00000098 },	/* 4:	600	600	0   */
 - 
 
Line -... Line 301...
- 
 
 301 
	{ 154, 0x9A, 1, 128, true },	/* 9:	1200		0   */
149 
	{ 0x00003015, 0x00000088 },	/* 5:	600	800	2.5 */
 302 
};
150 
	{ 0x00005013, 0x00000080 },	/* 6:	600	1000	4.5 */
 303 
 
151 
	{ 0x00000018, 0x00000088 },	/* 7:	800	800	0   */
 304 
static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
- 
 
 305 
				    enum port port, int type);
152 
	{ 0x00000096, 0x00000080 },	/* 8:	800	1000	2   */
 306 
 
- 
 
 307 
static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
153 
	{ 0x00000018, 0x00000080 },	/* 9:	1200	1200	0   */
 308 
				 struct intel_digital_port **dig_port,
154 
};
 309 
				 enum port *port)
155 
 
 310 
{
156 
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 311 
	struct drm_encoder *encoder = &intel_encoder->base;
- 
 
 312 
 
- 
 
 313 
	switch (intel_encoder->type) {
- 
 
 314 
	case INTEL_OUTPUT_DP_MST:
- 
 
 315 
		*dig_port = enc_to_mst(encoder)->primary;
- 
 
 316 
		*port = (*dig_port)->port;
- 
 
 317 
		break;
- 
 
 318 
	case INTEL_OUTPUT_DISPLAYPORT:
- 
 
 319 
	case INTEL_OUTPUT_EDP:
- 
 
 320 
	case INTEL_OUTPUT_HDMI:
- 
 
 321 
	case INTEL_OUTPUT_UNKNOWN:
Line -... Line 322...
- 
 
 322 
		*dig_port = enc_to_dig_port(encoder);
- 
 
 323 
		*port = (*dig_port)->port;
157 
{
 324 
		break;
- 
 
 325 
	case INTEL_OUTPUT_ANALOG:
- 
 
 326 
		*dig_port = NULL;
- 
 
 327 
		*port = PORT_E;
- 
 
 328 
		break;
158 
	struct drm_encoder *encoder = &intel_encoder->base;
 329 
	default:
- 
 
 330 
		WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
- 
 
 331 
		break;
- 
 
 332 
	}
- 
 
 333 
}
- 
 
 334 
 
- 
 
 335 
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
- 
 
 336 
{
- 
 
 337 
	struct intel_digital_port *dig_port;
- 
 
 338 
	enum port port;
- 
 
 339 
 
- 
 
 340 
	ddi_get_encoder_port(intel_encoder, &dig_port, &port);
- 
 
 341 
 
Line -... Line 342...
- 
 
 342 
	return port;
- 
 
 343 
}
- 
 
 344 
 
- 
 
 345 
static bool
- 
 
 346 
intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
- 
 
 347 
{
159 
	int type = intel_encoder->type;
 348 
	return intel_dig_port->hdmi.hdmi_reg;
160 
 
 349 
}
- 
 
 350 
 
- 
 
 351 
static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
- 
 
 352 
							int *n_entries)
- 
 
 353 
{
- 
 
 354 
	const struct ddi_buf_trans *ddi_translations;
- 
 
 355 
 
- 
 
 356 
	if (IS_SKL_ULX(dev)) {
- 
 
 357 
		ddi_translations = skl_y_ddi_translations_dp;
- 
 
 358 
		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
- 
 
 359 
	} else if (IS_SKL_ULT(dev)) {
- 
 
 360 
		ddi_translations = skl_u_ddi_translations_dp;
- 
 
 361 
		*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
- 
 
 362 
	} else {
- 
 
 363 
		ddi_translations = skl_ddi_translations_dp;
- 
 
 364 
		*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
- 
 
 365 
	}
- 
 
 366 
 
- 
 
 367 
	return ddi_translations;
- 
 
 368 
}
- 
 
 369 
 
- 
 
 370 
static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
- 
 
 371 
							 int *n_entries)
- 
 
 372 
{
- 
 
 373 
	struct drm_i915_private *dev_priv = dev->dev_private;
- 
 
 374 
	const struct ddi_buf_trans *ddi_translations;
- 
 
 375 
 
- 
 
 376 
	if (IS_SKL_ULX(dev)) {
- 
 
 377 
		if (dev_priv->edp_low_vswing) {
- 
 
 378 
			ddi_translations = skl_y_ddi_translations_edp;
- 
 
 379 
			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
- 
 
 380 
		} else {
- 
 
 381 
			ddi_translations = skl_y_ddi_translations_dp;
161 
	if (type == INTEL_OUTPUT_DP_MST) {
 382 
			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
- 
 
 383 
		}
- 
 
 384 
	} else if (IS_SKL_ULT(dev)) {
- 
 
 385 
		if (dev_priv->edp_low_vswing) {
- 
 
 386 
			ddi_translations = skl_u_ddi_translations_edp;
- 
 
 387 
			*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
- 
 
 388 
		} else {
- 
 
 389 
			ddi_translations = skl_u_ddi_translations_dp;
- 
 
 390 
			*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
- 
 
 391 
		}
- 
 
 392 
	} else {
- 
 
 393 
		if (dev_priv->edp_low_vswing) {
- 
 
 394 
			ddi_translations = skl_ddi_translations_edp;
- 
 
 395 
			*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
- 
 
 396 
		} else {
- 
 
 397 
			ddi_translations = skl_ddi_translations_dp;
- 
 
 398 
			*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
- 
 
 399 
		}
- 
 
 400 
	}
- 
 
 401 
 
- 
 
 402 
	return ddi_translations;
162 
		struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 403 
}
- 
 
 404 
 
- 
 
 405 
static const struct ddi_buf_trans *
163 
		return intel_dig_port->port;
 406 
skl_get_buf_trans_hdmi(struct drm_device *dev,
Line 164... Line 407...
164 
	} else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 407 
		       int *n_entries)
165 
	    type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 408 
{
166 
		struct intel_digital_port *intel_dig_port =
 409 
	const struct ddi_buf_trans *ddi_translations;
167 
			enc_to_dig_port(encoder);
 410 
 
168 
		return intel_dig_port->port;
 411 
	if (IS_SKL_ULX(dev)) {
169 
 
 412 
		ddi_translations = skl_y_ddi_translations_hdmi;
170 
	} else if (type == INTEL_OUTPUT_ANALOG) {
 413 
		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
171 
		return PORT_E;
 414 
	} else {
- 
 
 415 
		ddi_translations = skl_ddi_translations_hdmi;
172 
 
 416 
		*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
173 
	} else {
 417 
	}
174 
		DRM_ERROR("Invalid DDI encoder type %d\n", type);
 418 
 
175 
		BUG();
 419 
	return ddi_translations;
- 
 
 420 
}
176 
	}
 421 
 
177 
}
 422 
/*
178 
 
 423 
 * Starting with Haswell, DDI port buffers must be programmed with correct
179 
/*
 424 
 * values in advance. The buffer values are different for FDI and DP modes,
180 
 * Starting with Haswell, DDI port buffers must be programmed with correct
 425 
 * but the HDMI/DVI fields are shared among those. So we program the DDI
181 
 * values in advance. The buffer values are different for FDI and DP modes,
 426 
 * in either FDI or DP modes only, as HDMI connections will work with both
Line -... Line 427...
- 
 
 427 
 * of those
- 
 
 428 
 */
- 
 
 429 
static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
- 
 
 430 
				      bool supports_hdmi)
- 
 
 431 
{
- 
 
 432 
	struct drm_i915_private *dev_priv = dev->dev_private;
- 
 
 433 
	u32 iboost_bit = 0;
- 
 
 434 
	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
182 
 * but the HDMI/DVI fields are shared among those. So we program the DDI
 435 
	    size;
183 
 * in either FDI or DP modes only, as HDMI connections will work with both
 436 
	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
184 
 * of those
 437 
	const struct ddi_buf_trans *ddi_translations_fdi;
- 
 
 438 
	const struct ddi_buf_trans *ddi_translations_dp;
185 
 */
 439 
	const struct ddi_buf_trans *ddi_translations_edp;
- 
 
 440 
	const struct ddi_buf_trans *ddi_translations_hdmi;
186 
static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 441 
	const struct ddi_buf_trans *ddi_translations;
187 
{
 442 
 
188 
	struct drm_i915_private *dev_priv = dev->dev_private;
 443 
	if (IS_BROXTON(dev)) {
- 
 
 444 
		if (!supports_hdmi)
- 
 
 445 
			return;
- 
 
 446 
 
- 
 
 447 
		/* Vswing programming for HDMI */
189 
	u32 reg;
 448 
		bxt_ddi_vswing_sequence(dev, hdmi_level, port,
190 
	int i, n_hdmi_entries, hdmi_800mV_0dB;
 449 
					INTEL_OUTPUT_HDMI);
191 
	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 450 
		return;
192 
	const struct ddi_buf_trans *ddi_translations_fdi;
 451 
	} else if (IS_SKYLAKE(dev)) {
193 
	const struct ddi_buf_trans *ddi_translations_dp;
 452 
		ddi_translations_fdi = NULL;
- 
 
 453 
		ddi_translations_dp =
- 
 
 454 
				skl_get_buf_trans_dp(dev, &n_dp_entries);
194 
	const struct ddi_buf_trans *ddi_translations_edp;
 455 
		ddi_translations_edp =
195 
	const struct ddi_buf_trans *ddi_translations_hdmi;
 456 
				skl_get_buf_trans_edp(dev, &n_edp_entries);
196 
	const struct ddi_buf_trans *ddi_translations;
 457 
		ddi_translations_hdmi =
197 
 
 458 
				skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
198 
	if (IS_SKYLAKE(dev)) {
 459 
		hdmi_default_entry = 8;
199 
		ddi_translations_fdi = NULL;
 460 
		/* If we're boosting the current, set bit 31 of trans1 */
200 
		ddi_translations_dp = skl_ddi_translations_dp;
 461 
		if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
- 
 
 462 
		    dev_priv->vbt.ddi_port_info[port].dp_boost_level)
201 
		ddi_translations_edp = skl_ddi_translations_dp;
 463 
			iboost_bit = 1<<31;
202 
		ddi_translations_hdmi = skl_ddi_translations_hdmi;
 464 
	} else if (IS_BROADWELL(dev)) {
203 
		n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 465 
		ddi_translations_fdi = bdw_ddi_translations_fdi;
204 
		hdmi_800mV_0dB = 7;
 466 
		ddi_translations_dp = bdw_ddi_translations_dp;
205 
	} else if (IS_BROADWELL(dev)) {
 467 
		ddi_translations_edp = bdw_ddi_translations_edp;
206 
		ddi_translations_fdi = bdw_ddi_translations_fdi;
 468 
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
207 
		ddi_translations_dp = bdw_ddi_translations_dp;
 469 
		n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
208 
		ddi_translations_edp = bdw_ddi_translations_edp;
 470 
		n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
- 
 
 471 
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
- 
 
 472 
		hdmi_default_entry = 7;
209 
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 473 
	} else if (IS_HASWELL(dev)) {
210 
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 474 
		ddi_translations_fdi = hsw_ddi_translations_fdi;
211 
		hdmi_800mV_0dB = 7;
 475 
		ddi_translations_dp = hsw_ddi_translations_dp;
Line 212... Line 476...
212 
	} else if (IS_HASWELL(dev)) {
 476 
		ddi_translations_edp = hsw_ddi_translations_dp;
213 
		ddi_translations_fdi = hsw_ddi_translations_fdi;
 477 
		ddi_translations_hdmi = hsw_ddi_translations_hdmi;
214 
		ddi_translations_dp = hsw_ddi_translations_dp;
 478 
		n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
- 
 
 479 
		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
215 
		ddi_translations_edp = hsw_ddi_translations_dp;
 480 
		hdmi_default_entry = 6;
216 
		ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 481 
	} else {
217 
		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 482 
		WARN(1, "ddi translation table missing\n");
218 
		hdmi_800mV_0dB = 6;
 483 
		ddi_translations_edp = bdw_ddi_translations_dp;
- 
 
 484 
		ddi_translations_fdi = bdw_ddi_translations_fdi;
219 
	} else {
 485 
		ddi_translations_dp = bdw_ddi_translations_dp;
220 
		WARN(1, "ddi translation table missing\n");
 486 
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
221 
		ddi_translations_edp = bdw_ddi_translations_dp;
 487 
		n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
222 
		ddi_translations_fdi = bdw_ddi_translations_fdi;
 488 
		n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
- 
 
 489 
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
223 
		ddi_translations_dp = bdw_ddi_translations_dp;
 490 
		hdmi_default_entry = 7;
224 
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 491 
	}
- 
 
 492 
 
- 
 
 493 
	switch (port) {
225 
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 494 
	case PORT_A:
226 
		hdmi_800mV_0dB = 7;
 495 
		ddi_translations = ddi_translations_edp;
227 
	}
 496 
		size = n_edp_entries;
228 
 
 497 
		break;
229 
	switch (port) {
 498 
	case PORT_B:
230 
	case PORT_A:
 499 
	case PORT_C:
- 
 
 500 
		ddi_translations = ddi_translations_dp;
231 
		ddi_translations = ddi_translations_edp;
 501 
		size = n_dp_entries;
232 
		break;
 502 
		break;
233 
	case PORT_B:
 503 
	case PORT_D:
234 
	case PORT_C:
 504 
		if (intel_dp_is_edp(dev, PORT_D)) {
Line 235... Line 505...
235 
		ddi_translations = ddi_translations_dp;
 505 
			ddi_translations = ddi_translations_edp;
236 
		break;
 506 
			size = n_edp_entries;
237 
	case PORT_D:
 507 
		} else {
238 
		if (intel_dp_is_edp(dev, PORT_D))
 508 
			ddi_translations = ddi_translations_dp;
239 
			ddi_translations = ddi_translations_edp;
 509 
			size = n_dp_entries;
240 
		else
 - 
 
241 
			ddi_translations = ddi_translations_dp;
 510 
		}
Line -... Line 511...
- 
 
 511 
		break;
- 
 
 512 
	case PORT_E:
- 
 
 513 
		if (ddi_translations_fdi)
242 
		break;
 514 
			ddi_translations = ddi_translations_fdi;
243 
	case PORT_E:
 515 
		else
244 
		if (ddi_translations_fdi)
 516 
			ddi_translations = ddi_translations_dp;
245 
		ddi_translations = ddi_translations_fdi;
 517 
		size = n_dp_entries;
Line 246... Line 518...
246 
		else
 518 
		break;
- 
 
 519 
	default:
247 
			ddi_translations = ddi_translations_dp;
 520 
		BUG();
248 
		break;
 521 
	}
249 
	default:
 522 
 
250 
		BUG();
 - 
 
251 
	}
 523 
	for (i = 0; i < size; i++) {
Line 252... Line 524...
252 
 
 524 
		I915_WRITE(DDI_BUF_TRANS_LO(port, i),
253 
	for (i = 0, reg = DDI_BUF_TRANS(port);
 525 
			   ddi_translations[i].trans1 | iboost_bit);
254 
	     i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 526 
		I915_WRITE(DDI_BUF_TRANS_HI(port, i),
255 
		I915_WRITE(reg, ddi_translations[i].trans1);
 527 
			   ddi_translations[i].trans2);
256 
		reg += 4;
 528 
	}
257 
		I915_WRITE(reg, ddi_translations[i].trans2);
 529 
 
- 
 
 530 
	if (!supports_hdmi)
Line 258... Line 531...
258 
		reg += 4;
 531 
		return;
259 
	}
 532 
 
Line -... Line 533...
- 
 
 533 
	/* Choose a good default if VBT is badly populated */
260 
 
 534 
	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
- 
 
 535 
	    hdmi_level >= n_hdmi_entries)
- 
 
 536 
		hdmi_level = hdmi_default_entry;
- 
 
 537 
 
- 
 
 538 
	/* Entry 9 is for HDMI: */
- 
 
 539 
	I915_WRITE(DDI_BUF_TRANS_LO(port, i),
- 
 
 540 
		   ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
- 
 
 541 
	I915_WRITE(DDI_BUF_TRANS_HI(port, i),
- 
 
 542 
		   ddi_translations_hdmi[hdmi_level].trans2);
- 
 
 543 
}
- 
 
 544 
 
- 
 
 545 
/* Program DDI buffers translations for DP. By default, program ports A-D in DP
- 
 
 546 
 * mode and port E for FDI.
- 
 
 547 
 */
261 
	/* Choose a good default if VBT is badly populated */
 548 
void intel_prepare_ddi(struct drm_device *dev)
- 
 
 549 
{
- 
 
 550 
	struct intel_encoder *intel_encoder;
262 
	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 551 
	bool visited[I915_MAX_PORTS] = { 0, };
Line 263... Line 552...
263 
	    hdmi_level >= n_hdmi_entries)
 552 
 
264 
		hdmi_level = hdmi_800mV_0dB;
 553 
	if (!HAS_DDI(dev))
265 
 
 554 
		return;
266 
	/* Entry 9 is for HDMI: */
 555 
 
267 
	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
 556 
	for_each_intel_encoder(dev, intel_encoder) {
Line 268... Line 557...
268 
	reg += 4;
 557 
		struct intel_digital_port *intel_dig_port;
269 
	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
 558 
		enum port port;
270 
		reg += 4;
 559 
		bool supports_hdmi;
271 
}
 560 
 
272 
 
 561 
		if (intel_encoder->type == INTEL_OUTPUT_DSI)
273 
/* Program DDI buffers translations for DP. By default, program ports A-D in DP
 562 
			continue;
Line 319... Line 608...
319 
	 * - TP1 to TP2 time with the default value
 608 
	 * - TP1 to TP2 time with the default value
320 
	 * - FDI delay to 90h
 609 
	 * - FDI delay to 90h
321 
	 *
 610 
	 *
322 
	 * WaFDIAutoLinkSetTimingOverrride:hsw
 611 
	 * WaFDIAutoLinkSetTimingOverrride:hsw
323 
	 */
 612 
	 */
324 
	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 613 
	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
325 
				  FDI_RX_PWRDN_LANE0_VAL(2) |
 614 
				  FDI_RX_PWRDN_LANE0_VAL(2) |
326 
				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 615 
				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
Line 327... Line 616...
327 
 
 616 
 
328 
	/* Enable the PCH Receiver FDI PLL */
 617 
	/* Enable the PCH Receiver FDI PLL */
329 
	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 618 
	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
330 
		     FDI_RX_PLL_ENABLE |
 619 
		     FDI_RX_PLL_ENABLE |
331 
		     FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 620 
		     FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
332 
	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 621 
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
333 
	POSTING_READ(_FDI_RXA_CTL);
 622 
	POSTING_READ(FDI_RX_CTL(PIPE_A));
Line 334... Line 623...
334 
	udelay(220);
 623 
	udelay(220);
335 
 
 624 
 
336 
	/* Switch from Rawclk to PCDclk */
 625 
	/* Switch from Rawclk to PCDclk */
Line 337... Line 626...
337 
	rx_ctl_val |= FDI_PCDCLK;
 626 
	rx_ctl_val |= FDI_PCDCLK;
338 
	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 627 
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
339 
 
 628 
 
Line 340... Line 629...
340 
	/* Configure Port Clock Select */
 629 
	/* Configure Port Clock Select */
341 
	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 630 
	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
342 
	WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 631 
	WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
343 
 
 632 
 
Line 355... Line 644...
355 
		 * DDI E does not support port reversal, the functionality is
 644 
		 * DDI E does not support port reversal, the functionality is
356 
		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 645 
		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 
		 * port reversal bit */
 646 
		 * port reversal bit */
358 
		I915_WRITE(DDI_BUF_CTL(PORT_E),
 647 
		I915_WRITE(DDI_BUF_CTL(PORT_E),
359 
				DDI_BUF_CTL_ENABLE |
 648 
			   DDI_BUF_CTL_ENABLE |
360 
			   ((intel_crtc->config.fdi_lanes - 1) << 1) |
 649 
			   ((intel_crtc->config->fdi_lanes - 1) << 1) |
361 
			   DDI_BUF_TRANS_SELECT(i / 2));
 650 
			   DDI_BUF_TRANS_SELECT(i / 2));
362 
		POSTING_READ(DDI_BUF_CTL(PORT_E));
 651 
		POSTING_READ(DDI_BUF_CTL(PORT_E));
Line 363... Line 652...
363 
 
 652 
 
Line 364... Line 653...
364 
		udelay(600);
 653 
		udelay(600);
365 
 
 654 
 
Line 366... Line 655...
366 
		/* Program PCH FDI Receiver TU */
 655 
		/* Program PCH FDI Receiver TU */
367 
		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 656 
		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
368 
 
 657 
 
369 
		/* Enable PCH FDI Receiver with auto-training */
 658 
		/* Enable PCH FDI Receiver with auto-training */
Line 370... Line 659...
370 
		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 659 
		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
371 
		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 660 
		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
Line 372... Line 661...
372 
		POSTING_READ(_FDI_RXA_CTL);
 661 
		POSTING_READ(FDI_RX_CTL(PIPE_A));
373 
 
 662 
 
374 
		/* Wait for FDI receiver lane calibration */
 663 
		/* Wait for FDI receiver lane calibration */
375 
		udelay(30);
 664 
		udelay(30);
376 
 
 665 
 
Line 377... Line 666...
377 
		/* Unset FDI_RX_MISC pwrdn lanes */
 666 
		/* Unset FDI_RX_MISC pwrdn lanes */
378 
		temp = I915_READ(_FDI_RXA_MISC);
 667 
		temp = I915_READ(FDI_RX_MISC(PIPE_A));
Line 379... Line 668...
379 
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 668 
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
Line 410... Line 699...
410 
		POSTING_READ(DP_TP_CTL(PORT_E));
 699 
		POSTING_READ(DP_TP_CTL(PORT_E));
Line 411... Line 700...
411 
 
 700 
 
Line 412... Line 701...
412 
		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 701 
		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
413 
 
 702 
 
414 
		rx_ctl_val &= ~FDI_RX_ENABLE;
 703 
		rx_ctl_val &= ~FDI_RX_ENABLE;
Line 415... Line 704...
415 
		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 704 
		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
416 
		POSTING_READ(_FDI_RXA_CTL);
 705 
		POSTING_READ(FDI_RX_CTL(PIPE_A));
417 
 
 706 
 
418 
		/* Reset FDI_RX_MISC pwrdn lanes */
 707 
		/* Reset FDI_RX_MISC pwrdn lanes */
419 
		temp = I915_READ(_FDI_RXA_MISC);
 708 
		temp = I915_READ(FDI_RX_MISC(PIPE_A));
420 
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 709 
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
421 
		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 710 
		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
Line 422... Line 711...
422 
		I915_WRITE(_FDI_RXA_MISC, temp);
 711 
		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
423 
		POSTING_READ(_FDI_RXA_MISC);
 712 
		POSTING_READ(FDI_RX_MISC(PIPE_A));
Line 433... Line 722...
433 
		enc_to_dig_port(&encoder->base);
 722 
		enc_to_dig_port(&encoder->base);
Line 434... Line 723...
434 
 
 723 
 
435 
	intel_dp->DP = intel_dig_port->saved_port_bits |
 724 
	intel_dp->DP = intel_dig_port->saved_port_bits |
436 
		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 725 
		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
437 
	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 - 
 
438 
 
 726 
	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
Line 439... Line 727...
439 
}
 727 
}
440 
 
 728 
 
441 
static struct intel_encoder *
 729 
static struct intel_encoder *
Line 457... Line 745...
457 
 
 745 
 
458 
	BUG_ON(ret == NULL);
 746 
	BUG_ON(ret == NULL);
459 
	return ret;
 747 
	return ret;
Line 460... Line 748...
460 
}
 748 
}
461 
 
 749 
 
462 
static struct intel_encoder *
 750 
struct intel_encoder *
463 
intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
 751 
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
464 
{
 752 
{
- 
 
 753 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- 
 
 754 
	struct intel_encoder *ret = NULL;
- 
 
 755 
	struct drm_atomic_state *state;
465 
	struct drm_device *dev = crtc->base.dev;
 756 
	struct drm_connector *connector;
- 
 
 757 
	struct drm_connector_state *connector_state;
Line -... Line 758...
- 
 
 758 
	int num_encoders = 0;
- 
 
 759 
	int i;
466 
	struct intel_encoder *intel_encoder, *ret = NULL;
 760 
 
467 
	int num_encoders = 0;
 761 
	state = crtc_state->base.state;
468 
 
 762 
 
- 
 
 763 
	for_each_connector_in_state(state, connector, connector_state, i) {
- 
 
 764 
		if (connector_state->crtc != crtc_state->base.crtc)
469 
	for_each_intel_encoder(dev, intel_encoder) {
 765 
			continue;
470 
		if (intel_encoder->new_crtc == crtc) {
 766 
 
471 
			ret = intel_encoder;
 - 
 
Line 472... Line 767...
472 
			num_encoders++;
 767 
		ret = to_intel_encoder(connector_state->best_encoder);
473 
		}
 768 
		num_encoders++;
Line 474... Line 769...
474 
	}
 769 
	}
Line 497... Line 792...
497 
	typeof(a) __a = (a);			\
 792 
	typeof(a) __a = (a);			\
498 
	typeof(b) __b = (b);			\
 793 
	typeof(b) __b = (b);			\
499 
	(void) (&__a == &__b);			\
 794 
	(void) (&__a == &__b);			\
500 
	__a > __b ? (__a - __b) : (__b - __a); })
 795 
	__a > __b ? (__a - __b) : (__b - __a); })
Line 501... Line 796...
501 
 
 796 
 
502 
struct wrpll_rnp {
 797 
struct hsw_wrpll_rnp {
503 
	unsigned p, n2, r2;
 798 
	unsigned p, n2, r2;
Line 504... Line 799...
504 
};
 799 
};
505 
 
 800 
 
506 
static unsigned wrpll_get_budget_for_freq(int clock)
 801 
static unsigned hsw_wrpll_get_budget_for_freq(int clock)
Line 507... Line 802...
507 
{
 802 
{
508 
	unsigned budget;
 803 
	unsigned budget;
Line 575... Line 870...
575 
	}
 870 
	}
Line 576... Line 871...
576 
 
 871 
 
577 
	return budget;
 872 
	return budget;
Line 578... Line 873...
578 
}
 873 
}
579 
 
 874 
 
580 
static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 875 
static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
581 
			     unsigned r2, unsigned n2, unsigned p,
 876 
				 unsigned r2, unsigned n2, unsigned p,
582 
			     struct wrpll_rnp *best)
 877 
				 struct hsw_wrpll_rnp *best)
Line 583... Line 878...
583 
{
 878 
{
584 
	uint64_t a, b, c, d, diff, diff_best;
 879 
	uint64_t a, b, c, d, diff, diff_best;
Line 634... Line 929...
634 
		}
 929 
		}
635 
	}
 930 
	}
636 
	/* Otherwise a < c && b >= d, do nothing */
 931 
	/* Otherwise a < c && b >= d, do nothing */
637 
}
 932 
}
Line 638... Line 933...
638 
 
 933 
 
639 
static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 - 
 
640 
				     int reg)
 934 
static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
641 
{
 935 
{
642 
	int refclk = LC_FREQ;
 936 
	int refclk = LC_FREQ;
643 
	int n, p, r;
 937 
	int n, p, r;
Line 675... Line 969...
675 
{
 969 
{
676 
	uint32_t cfgcr1_reg, cfgcr2_reg;
 970 
	uint32_t cfgcr1_reg, cfgcr2_reg;
677 
	uint32_t cfgcr1_val, cfgcr2_val;
 971 
	uint32_t cfgcr1_val, cfgcr2_val;
678 
	uint32_t p0, p1, p2, dco_freq;
 972 
	uint32_t p0, p1, p2, dco_freq;
Line 679... Line 973...
679 
 
 973 
 
680 
	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
 974 
	cfgcr1_reg = DPLL_CFGCR1(dpll);
Line 681... Line 975...
681 
	cfgcr2_reg = GET_CFG_CR2_REG(dpll);
 975 
	cfgcr2_reg = DPLL_CFGCR2(dpll);
682 
 
 976 
 
Line 683... Line 977...
683 
	cfgcr1_val = I915_READ(cfgcr1_reg);
 977 
	cfgcr1_val = I915_READ(cfgcr1_reg);
Line 728... Line 1022...
728 
		1000) / 0x8000;
 1022 
		1000) / 0x8000;
Line 729... Line 1023...
729 
 
 1023 
 
730 
	return dco_freq / (p0 * p1 * p2 * 5);
 1024 
	return dco_freq / (p0 * p1 * p2 * 5);
Line -... Line 1025...
- 
 
 1025 
}
- 
 
 1026 
 
- 
 
 1027 
static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
- 
 
 1028 
{
- 
 
 1029 
	int dotclock;
- 
 
 1030 
 
- 
 
 1031 
	if (pipe_config->has_pch_encoder)
- 
 
 1032 
		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
- 
 
 1033 
						    &pipe_config->fdi_m_n);
- 
 
 1034 
	else if (pipe_config->has_dp_encoder)
- 
 
 1035 
		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
- 
 
 1036 
						    &pipe_config->dp_m_n);
- 
 
 1037 
	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
- 
 
 1038 
		dotclock = pipe_config->port_clock * 2 / 3;
- 
 
 1039 
	else
- 
 
 1040 
		dotclock = pipe_config->port_clock;
- 
 
 1041 
 
- 
 
 1042 
	if (pipe_config->pixel_multiplier)
- 
 
 1043 
		dotclock /= pipe_config->pixel_multiplier;
- 
 
 1044 
 
Line 731... Line 1045...
731 
}
 1045 
	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
732 
 
 1046 
}
733 
 
 1047 
 
734 
static void skl_ddi_clock_get(struct intel_encoder *encoder,
 1048 
static void skl_ddi_clock_get(struct intel_encoder *encoder,
735 
				struct intel_crtc_config *pipe_config)
 1049 
				struct intel_crtc_state *pipe_config)
736 
{
 1050 
{
Line 743... Line 1057...
743 
	dpll_ctl1 = I915_READ(DPLL_CTRL1);
 1057 
	dpll_ctl1 = I915_READ(DPLL_CTRL1);
Line 744... Line 1058...
744 
 
 1058 
 
745 
	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 1059 
	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
746 
		link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 1060 
		link_clock = skl_calc_wrpll_link(dev_priv, dpll);
747 
	} else {
 1061 
	} else {
748 
		link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
 1062 
		link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
Line 749... Line 1063...
749 
		link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
 1063 
		link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
750 
 
 1064 
 
751 
		switch (link_clock) {
 1065 
		switch (link_clock) {
752 
		case DPLL_CRTL1_LINK_RATE_810:
 1066 
		case DPLL_CTRL1_LINK_RATE_810:
- 
 
 1067 
			link_clock = 81000;
- 
 
 1068 
			break;
- 
 
 1069 
		case DPLL_CTRL1_LINK_RATE_1080:
753 
			link_clock = 81000;
 1070 
			link_clock = 108000;
754 
			break;
 1071 
			break;
755 
		case DPLL_CRTL1_LINK_RATE_1350:
 1072 
		case DPLL_CTRL1_LINK_RATE_1350:
- 
 
 1073 
			link_clock = 135000;
- 
 
 1074 
			break;
- 
 
 1075 
		case DPLL_CTRL1_LINK_RATE_1620:
- 
 
 1076 
			link_clock = 162000;
- 
 
 1077 
			break;
- 
 
 1078 
		case DPLL_CTRL1_LINK_RATE_2160:
756 
			link_clock = 135000;
 1079 
			link_clock = 216000;
757 
			break;
 1080 
			break;
758 
		case DPLL_CRTL1_LINK_RATE_2700:
 1081 
		case DPLL_CTRL1_LINK_RATE_2700:
759 
			link_clock = 270000;
 1082 
			link_clock = 270000;
760 
			break;
 1083 
			break;
761 
		default:
 1084 
		default:
Line 765... Line 1088...
765 
		link_clock *= 2;
 1088 
		link_clock *= 2;
766 
	}
 1089 
	}
Line 767... Line 1090...
767 
 
 1090 
 
Line 768... Line -...
768 
	pipe_config->port_clock = link_clock;
 - 
 
769 
 
 - 
 
770 
	if (pipe_config->has_dp_encoder)
 1091 
	pipe_config->port_clock = link_clock;
771 
		pipe_config->adjusted_mode.crtc_clock =
 - 
 
772 
			intel_dotclock_calculate(pipe_config->port_clock,
 - 
 
773 
						 &pipe_config->dp_m_n);
 - 
 
774 
	else
 1092 
 
Line 775... Line 1093...
775 
		pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 1093 
	ddi_dotclock_get(pipe_config);
776 
}
 1094 
}
777 
 
 1095 
 
778 
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 1096 
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
779 
				struct intel_crtc_config *pipe_config)
 1097 
			      struct intel_crtc_state *pipe_config)
780 
{
 1098 
{
Line 792... Line 1110...
792 
		break;
 1110 
		break;
793 
	case PORT_CLK_SEL_LCPLL_2700:
 1111 
	case PORT_CLK_SEL_LCPLL_2700:
794 
		link_clock = 270000;
 1112 
		link_clock = 270000;
795 
		break;
 1113 
		break;
796 
	case PORT_CLK_SEL_WRPLL1:
 1114 
	case PORT_CLK_SEL_WRPLL1:
797 
		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 1115 
		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
798 
		break;
 1116 
		break;
799 
	case PORT_CLK_SEL_WRPLL2:
 1117 
	case PORT_CLK_SEL_WRPLL2:
800 
		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 1118 
		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
801 
		break;
 1119 
		break;
802 
	case PORT_CLK_SEL_SPLL:
 1120 
	case PORT_CLK_SEL_SPLL:
803 
		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 1121 
		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
804 
		if (pll == SPLL_PLL_FREQ_810MHz)
 1122 
		if (pll == SPLL_PLL_FREQ_810MHz)
805 
			link_clock = 81000;
 1123 
			link_clock = 81000;
Line 817... Line 1135...
817 
		return;
 1135 
		return;
818 
	}
 1136 
	}
Line 819... Line 1137...
819 
 
 1137 
 
Line 820... Line 1138...
820 
	pipe_config->port_clock = link_clock * 2;
 1138 
	pipe_config->port_clock = link_clock * 2;
- 
 
 1139 
 
- 
 
 1140 
	ddi_dotclock_get(pipe_config);
- 
 
 1141 
}
- 
 
 1142 
 
- 
 
 1143 
static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
821 
 
 1144 
				enum intel_dpll_id dpll)
- 
 
 1145 
{
822 
	if (pipe_config->has_pch_encoder)
 1146 
	struct intel_shared_dpll *pll;
- 
 
 1147 
	struct intel_dpll_hw_state *state;
- 
 
 1148 
	intel_clock_t clock;
- 
 
 1149 
 
- 
 
 1150 
	/* For DDI ports we always use a shared PLL. */
- 
 
 1151 
	if (WARN_ON(dpll == DPLL_ID_PRIVATE))
- 
 
 1152 
		return 0;
823 
		pipe_config->adjusted_mode.crtc_clock =
 1153 
 
- 
 
 1154 
	pll = &dev_priv->shared_dplls[dpll];
- 
 
 1155 
	state = &pll->config.hw_state;
- 
 
 1156 
 
824 
			intel_dotclock_calculate(pipe_config->port_clock,
 1157 
	clock.m1 = 2;
- 
 
 1158 
	clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
- 
 
 1159 
	if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
- 
 
 1160 
		clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
- 
 
 1161 
	clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
- 
 
 1162 
	clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
825 
						 &pipe_config->fdi_m_n);
 1163 
	clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
- 
 
 1164 
 
- 
 
 1165 
	return chv_calc_dpll_params(100000, &clock);
826 
	else if (pipe_config->has_dp_encoder)
 1166 
}
827 
		pipe_config->adjusted_mode.crtc_clock =
 1167 
 
828 
			intel_dotclock_calculate(pipe_config->port_clock,
 1168 
static void bxt_ddi_clock_get(struct intel_encoder *encoder,
- 
 
 1169 
				struct intel_crtc_state *pipe_config)
- 
 
 1170 
{
- 
 
 1171 
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
- 
 
 1172 
	enum port port = intel_ddi_get_encoder_port(encoder);
829 
						 &pipe_config->dp_m_n);
 1173 
	uint32_t dpll = port;
- 
 
 1174 
 
- 
 
 1175 
	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
830 
	else
 1176 
 
Line 831... Line 1177...
831 
		pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 1177 
	ddi_dotclock_get(pipe_config);
832 
}
 1178 
}
833 
 
 1179 
 
- 
 
 1180 
void intel_ddi_clock_get(struct intel_encoder *encoder,
- 
 
 1181 
			 struct intel_crtc_state *pipe_config)
- 
 
 1182 
{
834 
void intel_ddi_clock_get(struct intel_encoder *encoder,
 1183 
	struct drm_device *dev = encoder->base.dev;
- 
 
 1184 
 
- 
 
 1185 
	if (INTEL_INFO(dev)->gen <= 8)
- 
 
 1186 
		hsw_ddi_clock_get(encoder, pipe_config);
- 
 
 1187 
	else if (IS_SKYLAKE(dev))
835 
			 struct intel_crtc_config *pipe_config)
 1188 
		skl_ddi_clock_get(encoder, pipe_config);
Line 836... Line 1189...
836 
{
 1189 
	else if (IS_BROXTON(dev))
837 
	hsw_ddi_clock_get(encoder, pipe_config);
 1190 
		bxt_ddi_clock_get(encoder, pipe_config);
838 
}
 1191 
}
839 
 
 1192 
 
840 
static void
 1193 
static void
841 
hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 1194 
hsw_ddi_calculate_wrpll(int clock /* in Hz */,
842 
			  unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 1195 
			unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
843 
{
 1196 
{
Line 844... Line 1197...
844 
	uint64_t freq2k;
 1197 
	uint64_t freq2k;
Line 845... Line 1198...
845 
	unsigned p, n2, r2;
 1198 
	unsigned p, n2, r2;
Line 846... Line 1199...
846 
	struct wrpll_rnp best = { 0, 0, 0 };
 1199 
	struct hsw_wrpll_rnp best = { 0, 0, 0 };
847 
	unsigned budget;
 1200 
	unsigned budget;
848 
 
 1201 
 
849 
	freq2k = clock / 100;
 1202 
	freq2k = clock / 100;
Line 890... Line 1243...
890 
		for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 1243 
		for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
891 
		     n2 <= VCO_MAX * r2 / LC_FREQ;
 1244 
		     n2 <= VCO_MAX * r2 / LC_FREQ;
892 
		     n2++) {
 1245 
		     n2++) {
Line 893... Line 1246...
893 
 
 1246 
 
894 
			for (p = P_MIN; p <= P_MAX; p += P_INC)
 1247 
			for (p = P_MIN; p <= P_MAX; p += P_INC)
895 
				wrpll_update_rnp(freq2k, budget,
 1248 
				hsw_wrpll_update_rnp(freq2k, budget,
896 
						 r2, n2, p, &best);
 1249 
						     r2, n2, p, &best);
897 
		}
 1250 
		}
Line 898... Line 1251...
898 
	}
 1251 
	}
Line 902... Line 1255...
902 
	*r2_out = best.r2;
 1255 
	*r2_out = best.r2;
903 
}
 1256 
}
Line 904... Line 1257...
904 
 
 1257 
 
905 
static bool
 1258 
static bool
906 
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 1259 
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
907 
		   struct intel_encoder *intel_encoder,
 1260 
		   struct intel_crtc_state *crtc_state,
908 
		   int clock)
 1261 
		   struct intel_encoder *intel_encoder)
- 
 
 1262 
{
- 
 
 1263 
	int clock = crtc_state->port_clock;
909 
{
 1264 
 
910 
	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 1265 
	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
911 
		struct intel_shared_dpll *pll;
 1266 
		struct intel_shared_dpll *pll;
912 
		uint32_t val;
 1267 
		uint32_t val;
Line 916... Line 1271...
916 
 
 1271 
 
917 
		val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 1272 
		val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
918 
		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 1273 
		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
Line 919... Line 1274...
919 
		      WRPLL_DIVIDER_POST(p);
 1274 
		      WRPLL_DIVIDER_POST(p);
- 
 
 1275 
 
Line -... Line 1276...
- 
 
 1276 
		memset(&crtc_state->dpll_hw_state, 0,
- 
 
 1277 
		       sizeof(crtc_state->dpll_hw_state));
920 
 
 1278 
 
921 
		intel_crtc->new_config->dpll_hw_state.wrpll = val;
 1279 
		crtc_state->dpll_hw_state.wrpll = val;
922 
 
 1280 
 
923 
		pll = intel_get_shared_dpll(intel_crtc);
 1281 
		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
924 
		if (pll == NULL) {
 1282 
		if (pll == NULL) {
925 
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 1283 
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Line 926... Line 1284...
926 
					 pipe_name(intel_crtc->pipe));
 1284 
					 pipe_name(intel_crtc->pipe));
- 
 
 1285 
			return false;
- 
 
 1286 
		}
- 
 
 1287 
 
- 
 
 1288 
		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
- 
 
 1289 
	} else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
- 
 
 1290 
		struct drm_atomic_state *state = crtc_state->base.state;
- 
 
 1291 
		struct intel_shared_dpll_config *spll =
- 
 
 1292 
			&intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
- 
 
 1293 
 
- 
 
 1294 
		if (spll->crtc_mask &&
- 
 
 1295 
		    WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
- 
 
 1296 
			return false;
927 
			return false;
 1297 
 
Line 928... Line 1298...
928 
		}
 1298 
		crtc_state->shared_dpll = DPLL_ID_SPLL;
929 
 
 1299 
		spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
Line -... Line 1300...
- 
 
 1300 
		spll->crtc_mask |= 1 << intel_crtc->pipe;
- 
 
 1301 
	}
- 
 
 1302 
 
- 
 
 1303 
	return true;
- 
 
 1304 
}
- 
 
 1305 
 
- 
 
 1306 
struct skl_wrpll_context {
- 
 
 1307 
	uint64_t min_deviation;		/* current minimal deviation */
- 
 
 1308 
	uint64_t central_freq;		/* chosen central freq */
- 
 
 1309 
	uint64_t dco_freq;		/* chosen dco freq */
- 
 
 1310 
	unsigned int p;			/* chosen divider */
- 
 
 1311 
};
- 
 
 1312 
 
- 
 
 1313 
static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
- 
 
 1314 
{
- 
 
 1315 
	memset(ctx, 0, sizeof(*ctx));
- 
 
 1316 
 
- 
 
 1317 
	ctx->min_deviation = U64_MAX;
- 
 
 1318 
}
- 
 
 1319 
 
- 
 
 1320 
/* DCO freq must be within +1%/-6%  of the DCO central freq */
- 
 
 1321 
#define SKL_DCO_MAX_PDEVIATION	100
- 
 
 1322 
#define SKL_DCO_MAX_NDEVIATION	600
- 
 
 1323 
 
- 
 
 1324 
static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
- 
 
 1325 
				  uint64_t central_freq,
- 
 
 1326 
				  uint64_t dco_freq,
- 
 
 1327 
				  unsigned int divider)
- 
 
 1328 
{
- 
 
 1329 
	uint64_t deviation;
- 
 
 1330 
 
- 
 
 1331 
	deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
- 
 
 1332 
			      central_freq);
- 
 
 1333 
 
- 
 
 1334 
	/* positive deviation */
- 
 
 1335 
	if (dco_freq >= central_freq) {
- 
 
 1336 
		if (deviation < SKL_DCO_MAX_PDEVIATION &&
- 
 
 1337 
		    deviation < ctx->min_deviation) {
- 
 
 1338 
			ctx->min_deviation = deviation;
- 
 
 1339 
			ctx->central_freq = central_freq;
- 
 
 1340 
			ctx->dco_freq = dco_freq;
- 
 
 1341 
			ctx->p = divider;
- 
 
 1342 
		}
- 
 
 1343 
	/* negative deviation */
- 
 
 1344 
	} else if (deviation < SKL_DCO_MAX_NDEVIATION &&
- 
 
 1345 
		   deviation < ctx->min_deviation) {
- 
 
 1346 
		ctx->min_deviation = deviation;
- 
 
 1347 
		ctx->central_freq = central_freq;
- 
 
 1348 
		ctx->dco_freq = dco_freq;
- 
 
 1349 
		ctx->p = divider;
- 
 
 1350 
	}
- 
 
 1351 
}
- 
 
 1352 
 
- 
 
 1353 
static void skl_wrpll_get_multipliers(unsigned int p,
- 
 
 1354 
				      unsigned int *p0 /* out */,
- 
 
 1355 
				      unsigned int *p1 /* out */,
- 
 
 1356 
				      unsigned int *p2 /* out */)
- 
 
 1357 
{
- 
 
 1358 
	/* even dividers */
- 
 
 1359 
	if (p % 2 == 0) {
- 
 
 1360 
		unsigned int half = p / 2;
- 
 
 1361 
 
- 
 
 1362 
		if (half == 1 || half == 2 || half == 3 || half == 5) {
- 
 
 1363 
			*p0 = 2;
- 
 
 1364 
			*p1 = 1;
- 
 
 1365 
			*p2 = half;
- 
 
 1366 
		} else if (half % 2 == 0) {
- 
 
 1367 
			*p0 = 2;
- 
 
 1368 
			*p1 = half / 2;
- 
 
 1369 
			*p2 = 2;
- 
 
 1370 
		} else if (half % 3 == 0) {
- 
 
 1371 
			*p0 = 3;
- 
 
 1372 
			*p1 = half / 3;
- 
 
 1373 
			*p2 = 2;
- 
 
 1374 
		} else if (half % 7 == 0) {
- 
 
 1375 
			*p0 = 7;
- 
 
 1376 
			*p1 = half / 7;
- 
 
 1377 
			*p2 = 2;
- 
 
 1378 
		}
- 
 
 1379 
	} else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
- 
 
 1380 
		*p0 = 3;
- 
 
 1381 
		*p1 = 1;
- 
 
 1382 
		*p2 = p / 3;
- 
 
 1383 
	} else if (p == 5 || p == 7) {
- 
 
 1384 
		*p0 = p;
- 
 
 1385 
		*p1 = 1;
- 
 
 1386 
		*p2 = 1;
- 
 
 1387 
	} else if (p == 15) {
- 
 
 1388 
		*p0 = 3;
- 
 
 1389 
		*p1 = 1;
- 
 
 1390 
		*p2 = 5;
- 
 
 1391 
	} else if (p == 21) {
- 
 
 1392 
		*p0 = 7;
- 
 
 1393 
		*p1 = 1;
- 
 
 1394 
		*p2 = 3;
- 
 
 1395 
	} else if (p == 35) {
930 
		intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 1396 
		*p0 = 7;
931 
	}
 1397 
		*p1 = 1;
932 
 
 1398 
		*p2 = 5;
933 
	return true;
 1399 
	}
934 
}
 1400 
}
935 
 
 1401 
 
936 
struct skl_wrpll_params {
 1402 
struct skl_wrpll_params {
937 
	uint32_t        dco_fraction;
 1403 
	uint32_t        dco_fraction;
938 
	uint32_t        dco_integer;
 1404 
	uint32_t        dco_integer;
Line -... Line 1405...
- 
 
 1405 
	uint32_t        qdiv_ratio;
939 
	uint32_t        qdiv_ratio;
 1406 
	uint32_t        qdiv_mode;
940 
	uint32_t        qdiv_mode;
 1407 
	uint32_t        kdiv;
941 
	uint32_t        kdiv;
 1408 
	uint32_t        pdiv;
942 
	uint32_t        pdiv;
 1409 
	uint32_t        central_freq;
943 
	uint32_t        central_freq;
 - 
 
944 
};
 - 
 
945 
 
 - 
 
946 
static void
 - 
 
947 
skl_ddi_calculate_wrpll(int clock /* in Hz */,
 - 
 
948 
			struct skl_wrpll_params *wrpll_params)
 - 
 
949 
{
 - 
 
950 
	uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
 - 
 
951 
	uint64_t dco_central_freq[3] = {8400000000ULL,
 - 
 
952 
					9000000000ULL,
 - 
 
953 
					9600000000ULL};
 - 
 
954 
	uint32_t min_dco_deviation = 400;
 - 
 
955 
	uint32_t min_dco_index = 3;
 - 
 
956 
	uint32_t P0[4] = {1, 2, 3, 7};
 - 
 
957 
	uint32_t P2[4] = {1, 2, 3, 5};
 - 
 
958 
	bool found = false;
 1410 
};
Line 959... Line -...
959 
	uint32_t candidate_p = 0;
 - 
 
960 
	uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
 - 
 
961 
	uint32_t candidate_p2[3] = {0};
 - 
 
962 
	uint32_t dco_central_freq_deviation[3];
 - 
 
963 
	uint32_t i, P1, k, dco_count;
 - 
 
964 
	bool retry_with_odd = false;
 - 
 
965 
	uint64_t dco_freq;
 - 
 
966 
 
 - 
 
967 
	/* Determine P0, P1 or P2 */
 - 
 
968 
	for (dco_count = 0; dco_count < 3; dco_count++) {
 - 
 
969 
		found = false;
 - 
 
970 
		candidate_p =
 - 
 
971 
			div64_u64(dco_central_freq[dco_count], afe_clock);
 - 
 
972 
		if (retry_with_odd == false)
 - 
 
973 
			candidate_p = (candidate_p % 2 == 0 ?
 - 
 
974 
				candidate_p : candidate_p + 1);
 - 
 
975 
 
 - 
 
976 
		for (P1 = 1; P1 < candidate_p; P1++) {
 - 
 
977 
			for (i = 0; i < 4; i++) {
 - 
 
978 
				if (!(P0[i] != 1 || P1 == 1))
 - 
 
979 
					continue;
 - 
 
980 
 
 - 
 
981 
				for (k = 0; k < 4; k++) {
 - 
 
982 
					if (P1 != 1 && P2[k] != 2)
 - 
 
983 
						continue;
 - 
 
984 
 
 - 
 
985 
					if (candidate_p == P0[i] * P1 * P2[k]) {
 - 
 
986 
						/* Found possible P0, P1, P2 */
 - 
 
987 
						found = true;
 - 
 
988 
						candidate_p0[dco_count] = P0[i];
 - 
 
989 
						candidate_p1[dco_count] = P1;
 - 
 
990 
						candidate_p2[dco_count] = P2[k];
 - 
 
991 
						goto found;
 - 
 
992 
					}
 - 
 
993 
 
 - 
 
994 
				}
 - 
 
995 
			}
 - 
 
996 
		}
 - 
 
997 
 
 - 
 
998 
found:
 - 
 
999 
		if (found) {
 - 
 
1000 
			dco_central_freq_deviation[dco_count] =
 - 
 
1001 
				div64_u64(10000 *
 - 
 
1002 
					  abs_diff((candidate_p * afe_clock),
 - 
 
1003 
						   dco_central_freq[dco_count]),
 - 
 
1004 
					  dco_central_freq[dco_count]);
 - 
 
1005 
 
 - 
 
1006 
			if (dco_central_freq_deviation[dco_count] <
 - 
 
1007 
				min_dco_deviation) {
 - 
 
1008 
				min_dco_deviation =
 - 
 
1009 
					dco_central_freq_deviation[dco_count];
 - 
 
1010 
				min_dco_index = dco_count;
 - 
 
1011 
			}
 - 
 
1012 
		}
 - 
 
1013 
 
 - 
 
1014 
		if (min_dco_index > 2 && dco_count == 2) {
 - 
 
1015 
			retry_with_odd = true;
 - 
 
1016 
			dco_count = 0;
 - 
 
1017 
		}
 1411 
 
1018 
	}
 1412 
static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1019 
 
 1413 
				      uint64_t afe_clock,
1020 
	if (min_dco_index > 2) {
 1414 
				      uint64_t central_freq,
1021 
		WARN(1, "No valid values found for the given pixel clock\n");
 1415 
				      uint32_t p0, uint32_t p1, uint32_t p2)
1022 
	} else {
 1416 
{
1023 
		 wrpll_params->central_freq = dco_central_freq[min_dco_index];
 1417 
	uint64_t dco_freq;
1024 
 
 1418 
 
1025 
		 switch (dco_central_freq[min_dco_index]) {
 1419 
	switch (central_freq) {
1026 
		 case 9600000000ULL:
 1420 
	case 9600000000ULL:
Line 1027... Line 1421...
1027 
			wrpll_params->central_freq = 0;
 1421 
		params->central_freq = 0;
1028 
			break;
 1422 
		break;
1029 
		 case 9000000000ULL:
 1423 
	case 9000000000ULL:
1030 
			wrpll_params->central_freq = 1;
 1424 
		params->central_freq = 1;
1031 
			break;
 1425 
		break;
1032 
		 case 8400000000ULL:
 1426 
	case 8400000000ULL:
1033 
			wrpll_params->central_freq = 3;
 1427 
		params->central_freq = 3;
1034 
		 }
 1428 
	}
1035 
 
 1429 
 
1036 
		 switch (candidate_p0[min_dco_index]) {
 1430 
	switch (p0) {
1037 
		 case 1:
 1431 
	case 1:
1038 
			wrpll_params->pdiv = 0;
 1432 
		params->pdiv = 0;
1039 
			break;
 1433 
		break;
1040 
		 case 2:
 1434 
	case 2:
1041 
			wrpll_params->pdiv = 1;
 1435 
		params->pdiv = 1;
1042 
			break;
 1436 
		break;
Line 1043... Line 1437...
1043 
		 case 3:
 1437 
	case 3:
1044 
			wrpll_params->pdiv = 2;
 1438 
		params->pdiv = 2;
1045 
			break;
 1439 
		break;
1046 
		 case 7:
 1440 
	case 7:
1047 
			wrpll_params->pdiv = 4;
 1441 
		params->pdiv = 4;
1048 
			break;
 1442 
		break;
1049 
		 default:
 1443 
	default:
1050 
			WARN(1, "Incorrect PDiv\n");
 1444 
		WARN(1, "Incorrect PDiv\n");
1051 
		 }
 1445 
	}
1052 
 
 1446 
 
1053 
		 switch (candidate_p2[min_dco_index]) {
 1447 
	switch (p2) {
1054 
		 case 5:
 1448 
	case 5:
1055 
			wrpll_params->kdiv = 0;
 1449 
		params->kdiv = 0;
1056 
			break;
 1450 
		break;
1057 
		 case 2:
 1451 
	case 2:
1058 
			wrpll_params->kdiv = 1;
 1452 
		params->kdiv = 1;
Line 1059... Line -...
1059 
			break;
 - 
 
1060 
		 case 3:
 1453 
		break;
1061 
			wrpll_params->kdiv = 2;
 1454 
	case 3:
1062 
			break;
 1455 
		params->kdiv = 2;
1063 
		 case 1:
 - 
 
1064 
			wrpll_params->kdiv = 3;
 - 
 
1065 
			break;
 1456 
		break;
Line 1066... Line 1457...
1066 
		 default:
 1457 
	case 1:
1067 
			WARN(1, "Incorrect KDiv\n");
 1458 
		params->kdiv = 3;
1068 
		 }
 1459 
		break;
1069 
 
 1460 
	default:
1070 
		 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
 1461 
		WARN(1, "Incorrect KDiv\n");
1071 
		 wrpll_params->qdiv_mode =
 1462 
	}
1072 
			(wrpll_params->qdiv_ratio == 1) ? 0 : 1;
 1463 
 
1073 
 
 1464 
	params->qdiv_ratio = p1;
- 
 
 1465 
	params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
- 
 
 1466 
 
- 
 
 1467 
	dco_freq = p0 * p1 * p2 * afe_clock;
- 
 
 1468 
 
- 
 
 1469 
	/*
- 
 
 1470 
	 * Intermediate values are in Hz.
- 
 
 1471 
	 * Divide by MHz to match bsepc
- 
 
 1472 
	 */
- 
 
 1473 
	params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
- 
 
 1474 
	params->dco_fraction =
- 
 
 1475 
		div_u64((div_u64(dco_freq, 24) -
- 
 
 1476 
			 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
- 
 
 1477 
}
- 
 
 1478 
 
- 
 
 1479 
static bool
- 
 
 1480 
skl_ddi_calculate_wrpll(int clock /* in Hz */,
- 
 
 1481 
			struct skl_wrpll_params *wrpll_params)
- 
 
 1482 
{
- 
 
 1483 
	uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
- 
 
 1484 
	uint64_t dco_central_freq[3] = {8400000000ULL,
- 
 
 1485 
					9000000000ULL,
- 
 
 1486 
					9600000000ULL};
- 
 
 1487 
	static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
- 
 
 1488 
					     24, 28, 30, 32, 36, 40, 42, 44,
- 
 
 1489 
					     48, 52, 54, 56, 60, 64, 66, 68,
- 
 
 1490 
					     70, 72, 76, 78, 80, 84, 88, 90,
- 
 
 1491 
					     92, 96, 98 };
- 
 
 1492 
	static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
- 
 
 1493 
	static const struct {
- 
 
 1494 
		const int *list;
- 
 
 1495 
		int n_dividers;
- 
 
 1496 
	} dividers[] = {
- 
 
 1497 
		{ even_dividers, ARRAY_SIZE(even_dividers) },
- 
 
 1498 
		{ odd_dividers, ARRAY_SIZE(odd_dividers) },
- 
 
 1499 
	};
- 
 
 1500 
	struct skl_wrpll_context ctx;
- 
 
 1501 
	unsigned int dco, d, i;
- 
 
 1502 
	unsigned int p0, p1, p2;
- 
 
 1503 
 
- 
 
 1504 
	skl_wrpll_context_init(&ctx);
- 
 
 1505 
 
- 
 
 1506 
	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
- 
 
 1507 
		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
- 
 
 1508 
			for (i = 0; i < dividers[d].n_dividers; i++) {
- 
 
 1509 
				unsigned int p = dividers[d].list[i];
- 
 
 1510 
				uint64_t dco_freq = p * afe_clock;
- 
 
 1511 
 
- 
 
 1512 
				skl_wrpll_try_divider(&ctx,
Line -... Line 1513...
- 
 
 1513 
						      dco_central_freq[dco],
- 
 
 1514 
						      dco_freq,
- 
 
 1515 
						      p);
- 
 
 1516 
				/*
- 
 
 1517 
				 * Skip the remaining dividers if we're sure to
- 
 
 1518 
				 * have found the definitive divider, we can't
- 
 
 1519 
				 * improve a 0 deviation.
1074 
		 dco_freq = candidate_p0[min_dco_index] *
 1520 
				 */
- 
 
 1521 
				if (ctx.min_deviation == 0)
- 
 
 1522 
					goto skip_remaining_dividers;
- 
 
 1523 
			}
- 
 
 1524 
		}
1075 
			 candidate_p1[min_dco_index] *
 1525 
 
Line -... Line 1526...
- 
 
 1526 
skip_remaining_dividers:
- 
 
 1527 
		/*
- 
 
 1528 
		 * If a solution is found with an even divider, prefer
- 
 
 1529 
		 * this one.
- 
 
 1530 
		 */
- 
 
 1531 
		if (d == 0 && ctx.p)
- 
 
 1532 
			break;
- 
 
 1533 
	}
- 
 
 1534 
 
- 
 
 1535 
	if (!ctx.p) {
- 
 
 1536 
		DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
Line 1076... Line 1537...
1076 
			 candidate_p2[min_dco_index] * afe_clock;
 1537 
		return false;
1077 
 
 1538 
	}
1078 
		/*
 1539 
 
1079 
		* Intermediate values are in Hz.
 1540 
	/*
1080 
		* Divide by MHz to match bsepc
 1541 
	 * gcc incorrectly analyses that these can be used without being
1081 
		*/
 1542 
	 * initialized. To be fair, it's hard to guess.
1082 
		 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
 1543 
	 */
- 
 
 1544 
	p0 = p1 = p2 = 0;
Line 1083... Line 1545...
1083 
		 wrpll_params->dco_fraction =
 1545 
	skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1084 
			 div_u64(((div_u64(dco_freq, 24) -
 1546 
	skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1085 
				   wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
 1547 
				  p0, p1, p2);
1086 
 
 1548 
 
Line 1106... Line 1568...
1106 
	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 1568 
	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1107 
		struct skl_wrpll_params wrpll_params = { 0, };
 1569 
		struct skl_wrpll_params wrpll_params = { 0, };
Line 1108... Line 1570...
1108 
 
 1570 
 
Line 1109... Line 1571...
1109 
		ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
 1571 
		ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
- 
 
 1572 
 
Line 1110... Line 1573...
1110 
 
 1573 
		if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1111 
		skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
 1574 
			return false;
1112 
 
 1575 
 
Line 1118... Line 1581...
1118 
			 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
 1581 
			 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1119 
			 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
 1582 
			 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1120 
			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
 1583 
			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1121 
			 wrpll_params.central_freq;
 1584 
			 wrpll_params.central_freq;
1122 
	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 1585 
	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1123 
		struct drm_encoder *encoder = &intel_encoder->base;
 - 
 
1124 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 - 
 
1125 
 
 - 
 
1126 
		switch (intel_dp->link_bw) {
 1586 
		switch (crtc_state->port_clock / 2) {
1127 
		case DP_LINK_BW_1_62:
 1587 
		case 81000:
1128 
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
 1588 
			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1129 
			break;
 1589 
			break;
1130 
		case DP_LINK_BW_2_7:
 1590 
		case 135000:
1131 
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
 1591 
			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1132 
			break;
 1592 
			break;
1133 
		case DP_LINK_BW_5_4:
 1593 
		case 270000:
1134 
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
 1594 
			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1135 
			break;
 1595 
			break;
1136 
		}
 1596 
		}
Line 1137... Line 1597...
1137 
 
 1597 
 
1138 
		cfgcr1 = cfgcr2 = 0;
 1598 
		cfgcr1 = cfgcr2 = 0;
1139 
	} else /* eDP */
 1599 
	} else /* eDP */
Line -... Line 1600...
- 
 
 1600 
		return true;
- 
 
 1601 
 
- 
 
 1602 
	memset(&crtc_state->dpll_hw_state, 0,
1140 
		return true;
 1603 
	       sizeof(crtc_state->dpll_hw_state));
1141 
 
 1604 
 
1142 
	intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
 1605 
	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
Line 1143... Line 1606...
1143 
	intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
 1606 
	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1144 
	intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
 1607 
	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1145 
 
 1608 
 
1146 
	pll = intel_get_shared_dpll(intel_crtc);
 1609 
	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1147 
	if (pll == NULL) {
 1610 
	if (pll == NULL) {
1148 
		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 1611 
		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Line 1149... Line 1612...
1149 
				 pipe_name(intel_crtc->pipe));
 1612 
				 pipe_name(intel_crtc->pipe));
1150 
		return false;
 1613 
		return false;
- 
 
 1614 
	}
- 
 
 1615 
 
- 
 
 1616 
	/* shared DPLL id 0 is DPLL 1 */
- 
 
 1617 
	crtc_state->ddi_pll_sel = pll->id + 1;
- 
 
 1618 
 
- 
 
 1619 
	return true;
- 
 
 1620 
}
- 
 
 1621 
 
- 
 
 1622 
/* bxt clock parameters */
- 
 
 1623 
struct bxt_clk_div {
- 
 
 1624 
	int clock;
- 
 
 1625 
	uint32_t p1;
- 
 
 1626 
	uint32_t p2;
- 
 
 1627 
	uint32_t m2_int;
- 
 
 1628 
	uint32_t m2_frac;
- 
 
 1629 
	bool m2_frac_en;
- 
 
 1630 
	uint32_t n;
- 
 
 1631 
};
- 
 
 1632 
 
- 
 
 1633 
/* pre-calculated values for DP linkrates */
- 
 
 1634 
static const struct bxt_clk_div bxt_dp_clk_val[] = {
- 
 
 1635 
	{162000, 4, 2, 32, 1677722, 1, 1},
- 
 
 1636 
	{270000, 4, 1, 27,       0, 0, 1},
- 
 
 1637 
	{540000, 2, 1, 27,       0, 0, 1},
- 
 
 1638 
	{216000, 3, 2, 32, 1677722, 1, 1},
- 
 
 1639 
	{243000, 4, 1, 24, 1258291, 1, 1},
- 
 
 1640 
	{324000, 4, 1, 32, 1677722, 1, 1},
- 
 
 1641 
	{432000, 3, 1, 32, 1677722, 1, 1}
- 
 
 1642 
};
- 
 
 1643 
 
- 
 
 1644 
static bool
- 
 
 1645 
bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
- 
 
 1646 
		   struct intel_crtc_state *crtc_state,
- 
 
 1647 
		   struct intel_encoder *intel_encoder)
- 
 
 1648 
{
- 
 
 1649 
	struct intel_shared_dpll *pll;
- 
 
 1650 
	struct bxt_clk_div clk_div = {0};
- 
 
 1651 
	int vco = 0;
- 
 
 1652 
	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
- 
 
 1653 
	uint32_t lanestagger;
- 
 
 1654 
	int clock = crtc_state->port_clock;
- 
 
 1655 
 
- 
 
 1656 
	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
- 
 
 1657 
		intel_clock_t best_clock;
- 
 
 1658 
 
- 
 
 1659 
		/* Calculate HDMI div */
- 
 
 1660 
		/*
- 
 
 1661 
		 * FIXME: tie the following calculation into
- 
 
 1662 
		 * i9xx_crtc_compute_clock
- 
 
 1663 
		 */
- 
 
 1664 
		if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
- 
 
 1665 
			DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
- 
 
 1666 
					 clock, pipe_name(intel_crtc->pipe));
- 
 
 1667 
			return false;
- 
 
 1668 
		}
- 
 
 1669 
 
- 
 
 1670 
		clk_div.p1 = best_clock.p1;
- 
 
 1671 
		clk_div.p2 = best_clock.p2;
- 
 
 1672 
		WARN_ON(best_clock.m1 != 2);
- 
 
 1673 
		clk_div.n = best_clock.n;
- 
 
 1674 
		clk_div.m2_int = best_clock.m2 >> 22;
- 
 
 1675 
		clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
- 
 
 1676 
		clk_div.m2_frac_en = clk_div.m2_frac != 0;
- 
 
 1677 
 
- 
 
 1678 
		vco = best_clock.vco;
- 
 
 1679 
	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
- 
 
 1680 
			intel_encoder->type == INTEL_OUTPUT_EDP) {
- 
 
 1681 
		int i;
- 
 
 1682 
 
- 
 
 1683 
		clk_div = bxt_dp_clk_val[0];
- 
 
 1684 
		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
- 
 
 1685 
			if (bxt_dp_clk_val[i].clock == clock) {
- 
 
 1686 
				clk_div = bxt_dp_clk_val[i];
- 
 
 1687 
				break;
- 
 
 1688 
			}
- 
 
 1689 
		}
- 
 
 1690 
		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
- 
 
 1691 
	}
- 
 
 1692 
 
- 
 
 1693 
	if (vco >= 6200000 && vco <= 6700000) {
- 
 
 1694 
		prop_coef = 4;
- 
 
 1695 
		int_coef = 9;
- 
 
 1696 
		gain_ctl = 3;
- 
 
 1697 
		targ_cnt = 8;
- 
 
 1698 
	} else if ((vco > 5400000 && vco < 6200000) ||
- 
 
 1699 
			(vco >= 4800000 && vco < 5400000)) {
- 
 
 1700 
		prop_coef = 5;
- 
 
 1701 
		int_coef = 11;
- 
 
 1702 
		gain_ctl = 3;
- 
 
 1703 
		targ_cnt = 9;
- 
 
 1704 
	} else if (vco == 5400000) {
- 
 
 1705 
		prop_coef = 3;
- 
 
 1706 
		int_coef = 8;
- 
 
 1707 
		gain_ctl = 1;
- 
 
 1708 
		targ_cnt = 9;
- 
 
 1709 
	} else {
- 
 
 1710 
		DRM_ERROR("Invalid VCO\n");
- 
 
 1711 
		return false;
- 
 
 1712 
	}
- 
 
 1713 
 
- 
 
 1714 
	memset(&crtc_state->dpll_hw_state, 0,
- 
 
 1715 
	       sizeof(crtc_state->dpll_hw_state));
- 
 
 1716 
 
- 
 
 1717 
	if (clock > 270000)
- 
 
 1718 
		lanestagger = 0x18;
- 
 
 1719 
	else if (clock > 135000)
- 
 
 1720 
		lanestagger = 0x0d;
- 
 
 1721 
	else if (clock > 67000)
- 
 
 1722 
		lanestagger = 0x07;
- 
 
 1723 
	else if (clock > 33000)
- 
 
 1724 
		lanestagger = 0x04;
- 
 
 1725 
	else
- 
 
 1726 
		lanestagger = 0x02;
- 
 
 1727 
 
- 
 
 1728 
	crtc_state->dpll_hw_state.ebb0 =
- 
 
 1729 
		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
- 
 
 1730 
	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
- 
 
 1731 
	crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
- 
 
 1732 
	crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
- 
 
 1733 
 
- 
 
 1734 
	if (clk_div.m2_frac_en)
- 
 
 1735 
		crtc_state->dpll_hw_state.pll3 =
- 
 
 1736 
			PORT_PLL_M2_FRAC_ENABLE;
- 
 
 1737 
 
- 
 
 1738 
	crtc_state->dpll_hw_state.pll6 =
- 
 
 1739 
		prop_coef | PORT_PLL_INT_COEFF(int_coef);
- 
 
 1740 
	crtc_state->dpll_hw_state.pll6 |=
- 
 
 1741 
		PORT_PLL_GAIN_CTL(gain_ctl);
- 
 
 1742 
 
- 
 
 1743 
	crtc_state->dpll_hw_state.pll8 = targ_cnt;
- 
 
 1744 
 
- 
 
 1745 
	crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
- 
 
 1746 
 
- 
 
 1747 
	crtc_state->dpll_hw_state.pll10 =
- 
 
 1748 
		PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
- 
 
 1749 
		| PORT_PLL_DCO_AMP_OVR_EN_H;
- 
 
 1750 
 
- 
 
 1751 
	crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
- 
 
 1752 
 
- 
 
 1753 
	crtc_state->dpll_hw_state.pcsdw12 =
- 
 
 1754 
		LANESTAGGER_STRAP_OVRD | lanestagger;
- 
 
 1755 
 
- 
 
 1756 
	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
- 
 
 1757 
	if (pll == NULL) {
- 
 
 1758 
		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
- 
 
 1759 
			pipe_name(intel_crtc->pipe));
- 
 
 1760 
		return false;
Line 1151... Line 1761...
1151 
	}
 1761 
	}
1152 
 
 1762 
 
Line 1153... Line 1763...
1153 
	/* shared DPLL id 0 is DPLL 1 */
 1763 
	/* shared DPLL id 0 is DPLL A */
Line 1161... Line 1771...
1161 
 * intel_crtc->ddi_pll_sel.
 1771 
 * intel_crtc->ddi_pll_sel.
1162 
 *
 1772 
 *
1163 
 * For private DPLLs, compute_config() should do the selection for us. This
 1773 
 * For private DPLLs, compute_config() should do the selection for us. This
1164 
 * function should be folded into compute_config() eventually.
 1774 
 * function should be folded into compute_config() eventually.
1165 
 */
 1775 
 */
1166 
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 1776 
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
- 
 
 1777 
			  struct intel_crtc_state *crtc_state)
1167 
{
 1778 
{
1168 
	struct drm_device *dev = intel_crtc->base.dev;
 1779 
	struct drm_device *dev = intel_crtc->base.dev;
1169 
	struct intel_encoder *intel_encoder =
 1780 
	struct intel_encoder *intel_encoder =
1170 
		intel_ddi_get_crtc_new_encoder(intel_crtc);
 1781 
		intel_ddi_get_crtc_new_encoder(crtc_state);
1171 
	int clock = intel_crtc->new_config->port_clock;
 - 
 
Line 1172... Line 1782...
1172 
 
 1782 
 
1173 
	if (IS_SKYLAKE(dev))
 1783 
	if (IS_SKYLAKE(dev))
- 
 
 1784 
		return skl_ddi_pll_select(intel_crtc, crtc_state,
- 
 
 1785 
					  intel_encoder);
- 
 
 1786 
	else if (IS_BROXTON(dev))
- 
 
 1787 
		return bxt_ddi_pll_select(intel_crtc, crtc_state,
1174 
		return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
 1788 
					  intel_encoder);
1175 
	else
 1789 
	else
- 
 
 1790 
		return hsw_ddi_pll_select(intel_crtc, crtc_state,
1176 
		return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
 1791 
					  intel_encoder);
Line 1177... Line 1792...
1177 
}
 1792 
}
1178 
 
 1793 
 
1179 
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 1794 
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1180 
{
 1795 
{
1181 
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 1796 
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1182 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 1797 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1183 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 1798 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1184 
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 1799 
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Line 1185... Line 1800...
1185 
	int type = intel_encoder->type;
 1800 
	int type = intel_encoder->type;
1186 
	uint32_t temp;
 1801 
	uint32_t temp;
1187 
 
 1802 
 
1188 
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
 1803 
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1189 
		temp = TRANS_MSA_SYNC_CLK;
 1804 
		temp = TRANS_MSA_SYNC_CLK;
1190 
		switch (intel_crtc->config.pipe_bpp) {
 1805 
		switch (intel_crtc->config->pipe_bpp) {
1191 
	case 18:
 1806 
		case 18:
1192 
			temp |= TRANS_MSA_6_BPC;
 1807 
			temp |= TRANS_MSA_6_BPC;
Line 1210... Line 1825...
1210 
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
 1825 
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1211 
{
 1826 
{
1212 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 1827 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1213 
	struct drm_device *dev = crtc->dev;
 1828 
	struct drm_device *dev = crtc->dev;
1214 
	struct drm_i915_private *dev_priv = dev->dev_private;
 1829 
	struct drm_i915_private *dev_priv = dev->dev_private;
1215 
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 1830 
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1216 
	uint32_t temp;
 1831 
	uint32_t temp;
1217 
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 1832 
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1218 
	if (state == true)
 1833 
	if (state == true)
1219 
		temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 1834 
		temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1220 
	else
 1835 
	else
Line 1228... Line 1843...
1228 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 1843 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1229 
	struct drm_encoder *encoder = &intel_encoder->base;
 1844 
	struct drm_encoder *encoder = &intel_encoder->base;
1230 
	struct drm_device *dev = crtc->dev;
 1845 
	struct drm_device *dev = crtc->dev;
1231 
	struct drm_i915_private *dev_priv = dev->dev_private;
 1846 
	struct drm_i915_private *dev_priv = dev->dev_private;
1232 
	enum pipe pipe = intel_crtc->pipe;
 1847 
	enum pipe pipe = intel_crtc->pipe;
1233 
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 1848 
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1234 
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 1849 
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1235 
	int type = intel_encoder->type;
 1850 
	int type = intel_encoder->type;
1236 
	uint32_t temp;
 1851 
	uint32_t temp;
Line 1237... Line 1852...
1237 
 
 1852 
 
1238 
	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 1853 
	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1239 
	temp = TRANS_DDI_FUNC_ENABLE;
 1854 
	temp = TRANS_DDI_FUNC_ENABLE;
Line 1240... Line 1855...
1240 
	temp |= TRANS_DDI_SELECT_PORT(port);
 1855 
	temp |= TRANS_DDI_SELECT_PORT(port);
1241 
 
 1856 
 
1242 
	switch (intel_crtc->config.pipe_bpp) {
 1857 
	switch (intel_crtc->config->pipe_bpp) {
1243 
	case 18:
 1858 
	case 18:
1244 
		temp |= TRANS_DDI_BPC_6;
 1859 
		temp |= TRANS_DDI_BPC_6;
1245 
		break;
 1860 
		break;
Line 1254... Line 1869...
1254 
		break;
 1869 
		break;
1255 
	default:
 1870 
	default:
1256 
		BUG();
 1871 
		BUG();
1257 
	}
 1872 
	}
Line 1258... Line 1873...
1258 
 
 1873 
 
1259 
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 1874 
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1260 
		temp |= TRANS_DDI_PVSYNC;
 1875 
		temp |= TRANS_DDI_PVSYNC;
1261 
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 1876 
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
Line 1262... Line 1877...
1262 
		temp |= TRANS_DDI_PHSYNC;
 1877 
		temp |= TRANS_DDI_PHSYNC;
1263 
 
 1878 
 
1264 
	if (cpu_transcoder == TRANSCODER_EDP) {
 1879 
	if (cpu_transcoder == TRANSCODER_EDP) {
1265 
		switch (pipe) {
 1880 
		switch (pipe) {
1266 
		case PIPE_A:
 1881 
		case PIPE_A:
1267 
			/* On Haswell, can only use the always-on power well for
 1882 
			/* On Haswell, can only use the always-on power well for
1268 
			 * eDP when not using the panel fitter, and when not
 1883 
			 * eDP when not using the panel fitter, and when not
1269 
			 * using motion blur mitigation (which we don't
 1884 
			 * using motion blur mitigation (which we don't
1270 
			 * support). */
 1885 
			 * support). */
1271 
			if (IS_HASWELL(dev) &&
 1886 
			if (IS_HASWELL(dev) &&
1272 
			    (intel_crtc->config.pch_pfit.enabled ||
 1887 
			    (intel_crtc->config->pch_pfit.enabled ||
1273 
			     intel_crtc->config.pch_pfit.force_thru))
 1888 
			     intel_crtc->config->pch_pfit.force_thru))
1274 
			temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 1889 
				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1275 
			else
 1890 
			else
1276 
				temp |= TRANS_DDI_EDP_INPUT_A_ON;
 1891 
				temp |= TRANS_DDI_EDP_INPUT_A_ON;
Line 1286... Line 1901...
1286 
			break;
 1901 
			break;
1287 
		}
 1902 
		}
1288 
	}
 1903 
	}
Line 1289... Line 1904...
1289 
 
 1904 
 
1290 
	if (type == INTEL_OUTPUT_HDMI) {
 1905 
	if (type == INTEL_OUTPUT_HDMI) {
1291 
		if (intel_crtc->config.has_hdmi_sink)
 1906 
		if (intel_crtc->config->has_hdmi_sink)
1292 
			temp |= TRANS_DDI_MODE_SELECT_HDMI;
 1907 
			temp |= TRANS_DDI_MODE_SELECT_HDMI;
1293 
	else
 1908 
		else
Line 1294... Line 1909...
1294 
			temp |= TRANS_DDI_MODE_SELECT_DVI;
 1909 
			temp |= TRANS_DDI_MODE_SELECT_DVI;
1295 
 
 1910 
 
1296 
	} else if (type == INTEL_OUTPUT_ANALOG) {
 1911 
	} else if (type == INTEL_OUTPUT_ANALOG) {
Line 1297... Line 1912...
1297 
		temp |= TRANS_DDI_MODE_SELECT_FDI;
 1912 
		temp |= TRANS_DDI_MODE_SELECT_FDI;
1298 
		temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 1913 
		temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1299 
 
 1914 
 
Line 1300... Line 1915...
1300 
	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 1915 
	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1301 
		   type == INTEL_OUTPUT_EDP) {
 1916 
		   type == INTEL_OUTPUT_EDP) {
1302 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 1917 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1303 
 
 1918 
 
Line 1304... Line 1919...
1304 
		if (intel_dp->is_mst) {
 1919 
		if (intel_dp->is_mst) {
1305 
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 1920 
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1306 
		} else
 1921 
		} else
Line 1307... Line 1922...
1307 
			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 1922 
			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1308 
 
 1923 
 
1309 
		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 1924 
		temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1310 
	} else if (type == INTEL_OUTPUT_DP_MST) {
 1925 
	} else if (type == INTEL_OUTPUT_DP_MST) {
Line 1311... Line 1926...
1311 
		struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
 1926 
		struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1312 
 
 1927 
 
1313 
		if (intel_dp->is_mst) {
 1928 
		if (intel_dp->is_mst) {
1314 
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 1929 
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1315 
		} else
 1930 
		} else
Line 1440... Line 2055...
1440 
}
 2055 
}
Line 1441... Line 2056...
1441 
 
 2056 
 
1442 
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
 2057 
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1443 
{
 2058 
{
- 
 
 2059 
	struct drm_crtc *crtc = &intel_crtc->base;
1444 
	struct drm_crtc *crtc = &intel_crtc->base;
 2060 
	struct drm_device *dev = crtc->dev;
1445 
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 2061 
	struct drm_i915_private *dev_priv = dev->dev_private;
1446 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 2062 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1447 
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 2063 
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
Line 1448... Line 2064...
1448 
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 2064 
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1449 
 
 2065 
 
1450 
	if (cpu_transcoder != TRANSCODER_EDP)
 2066 
	if (cpu_transcoder != TRANSCODER_EDP)
1451 
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
 2067 
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
Line 1452... Line 2068...
1452 
			   TRANS_CLK_SEL_PORT(port));
 2068 
			   TRANS_CLK_SEL_PORT(port));
1453 
}
 2069 
}
1454 
 
 2070 
 
1455 
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
 2071 
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
Line 1456... Line 2072...
1456 
{
 2072 
{
1457 
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
 2073 
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1458 
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 2074 
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1459 
 
 2075 
 
Line -... Line 2076...
- 
 
 2076 
	if (cpu_transcoder != TRANSCODER_EDP)
- 
 
 2077 
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- 
 
 2078 
			   TRANS_CLK_SEL_DISABLED);
- 
 
 2079 
}
- 
 
 2080 
 
- 
 
 2081 
static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
- 
 
 2082 
			       enum port port, int type)
- 
 
 2083 
{
- 
 
 2084 
	struct drm_i915_private *dev_priv = dev->dev_private;
- 
 
 2085 
	const struct ddi_buf_trans *ddi_translations;
- 
 
 2086 
	uint8_t iboost;
- 
 
 2087 
	uint8_t dp_iboost, hdmi_iboost;
- 
 
 2088 
	int n_entries;
- 
 
 2089 
	u32 reg;
- 
 
 2090 
 
- 
 
 2091 
	/* VBT may override standard boost values */
- 
 
 2092 
	dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
- 
 
 2093 
	hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
- 
 
 2094 
 
- 
 
 2095 
	if (type == INTEL_OUTPUT_DISPLAYPORT) {
- 
 
 2096 
		if (dp_iboost) {
- 
 
 2097 
			iboost = dp_iboost;
- 
 
 2098 
		} else {
- 
 
 2099 
			ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
- 
 
 2100 
			iboost = ddi_translations[port].i_boost;
- 
 
 2101 
		}
- 
 
 2102 
	} else if (type == INTEL_OUTPUT_EDP) {
- 
 
 2103 
		if (dp_iboost) {
- 
 
 2104 
			iboost = dp_iboost;
- 
 
 2105 
		} else {
- 
 
 2106 
			ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
- 
 
 2107 
			iboost = ddi_translations[port].i_boost;
- 
 
 2108 
		}
- 
 
 2109 
	} else if (type == INTEL_OUTPUT_HDMI) {
- 
 
 2110 
		if (hdmi_iboost) {
- 
 
 2111 
			iboost = hdmi_iboost;
- 
 
 2112 
		} else {
- 
 
 2113 
			ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
- 
 
 2114 
			iboost = ddi_translations[port].i_boost;
- 
 
 2115 
		}
- 
 
 2116 
	} else {
- 
 
 2117 
		return;
- 
 
 2118 
	}
- 
 
 2119 
 
- 
 
 2120 
	/* Make sure that the requested I_boost is valid */
- 
 
 2121 
	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
- 
 
 2122 
		DRM_ERROR("Invalid I_boost value %u\n", iboost);
- 
 
 2123 
		return;
- 
 
 2124 
	}
- 
 
 2125 
 
- 
 
 2126 
	reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
- 
 
 2127 
	reg &= ~BALANCE_LEG_MASK(port);
- 
 
 2128 
	reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
- 
 
 2129 
 
- 
 
 2130 
	if (iboost)
- 
 
 2131 
		reg |= iboost << BALANCE_LEG_SHIFT(port);
- 
 
 2132 
	else
- 
 
 2133 
		reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
- 
 
 2134 
 
- 
 
 2135 
	I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
- 
 
 2136 
}
- 
 
 2137 
 
- 
 
 2138 
static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
- 
 
 2139 
				    enum port port, int type)
- 
 
 2140 
{
- 
 
 2141 
	struct drm_i915_private *dev_priv = dev->dev_private;
- 
 
 2142 
	const struct bxt_ddi_buf_trans *ddi_translations;
- 
 
 2143 
	u32 n_entries, i;
- 
 
 2144 
	uint32_t val;
- 
 
 2145 
 
- 
 
 2146 
	if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
- 
 
 2147 
		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
- 
 
 2148 
		ddi_translations = bxt_ddi_translations_edp;
- 
 
 2149 
	} else if (type == INTEL_OUTPUT_DISPLAYPORT
- 
 
 2150 
			|| type == INTEL_OUTPUT_EDP) {
- 
 
 2151 
		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
- 
 
 2152 
		ddi_translations = bxt_ddi_translations_dp;
- 
 
 2153 
	} else if (type == INTEL_OUTPUT_HDMI) {
- 
 
 2154 
		n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
- 
 
 2155 
		ddi_translations = bxt_ddi_translations_hdmi;
- 
 
 2156 
	} else {
- 
 
 2157 
		DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
- 
 
 2158 
				type);
- 
 
 2159 
		return;
- 
 
 2160 
	}
- 
 
 2161 
 
- 
 
 2162 
	/* Check if default value has to be used */
- 
 
 2163 
	if (level >= n_entries ||
- 
 
 2164 
	    (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
- 
 
 2165 
		for (i = 0; i < n_entries; i++) {
- 
 
 2166 
			if (ddi_translations[i].default_index) {
- 
 
 2167 
				level = i;
- 
 
 2168 
				break;
- 
 
 2169 
			}
- 
 
 2170 
		}
- 
 
 2171 
	}
- 
 
 2172 
 
- 
 
 2173 
	/*
- 
 
 2174 
	 * While we write to the group register to program all lanes at once we
- 
 
 2175 
	 * can read only lane registers and we pick lanes 0/1 for that.
- 
 
 2176 
	 */
- 
 
 2177 
	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
- 
 
 2178 
	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
- 
 
 2179 
	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
- 
 
 2180 
 
- 
 
 2181 
	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
- 
 
 2182 
	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
- 
 
 2183 
	val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
- 
 
 2184 
	       ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
- 
 
 2185 
	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
- 
 
 2186 
 
- 
 
 2187 
	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
- 
 
 2188 
	val &= ~SCALE_DCOMP_METHOD;
- 
 
 2189 
	if (ddi_translations[level].enable)
- 
 
 2190 
		val |= SCALE_DCOMP_METHOD;
- 
 
 2191 
 
- 
 
 2192 
	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
- 
 
 2193 
		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
- 
 
 2194 
 
- 
 
 2195 
	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
- 
 
 2196 
 
- 
 
 2197 
	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
- 
 
 2198 
	val &= ~DE_EMPHASIS;
- 
 
 2199 
	val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
- 
 
 2200 
	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
- 
 
 2201 
 
- 
 
 2202 
	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
- 
 
 2203 
	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
- 
 
 2204 
	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
- 
 
 2205 
}
- 
 
 2206 
 
- 
 
 2207 
static uint32_t translate_signal_level(int signal_levels)
- 
 
 2208 
{
- 
 
 2209 
	uint32_t level;
- 
 
 2210 
 
- 
 
 2211 
	switch (signal_levels) {
- 
 
 2212 
	default:
- 
 
 2213 
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
- 
 
 2214 
			      signal_levels);
- 
 
 2215 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- 
 
 2216 
		level = 0;
- 
 
 2217 
		break;
- 
 
 2218 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
- 
 
 2219 
		level = 1;
- 
 
 2220 
		break;
- 
 
 2221 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
- 
 
 2222 
		level = 2;
- 
 
 2223 
		break;
- 
 
 2224 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
- 
 
 2225 
		level = 3;
- 
 
 2226 
		break;
- 
 
 2227 
 
- 
 
 2228 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- 
 
 2229 
		level = 4;
- 
 
 2230 
		break;
- 
 
 2231 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
- 
 
 2232 
		level = 5;
- 
 
 2233 
		break;
- 
 
 2234 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
- 
 
 2235 
		level = 6;
- 
 
 2236 
		break;
- 
 
 2237 
 
- 
 
 2238 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- 
 
 2239 
		level = 7;
- 
 
 2240 
		break;
- 
 
 2241 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
- 
 
 2242 
		level = 8;
- 
 
 2243 
		break;
- 
 
 2244 
 
- 
 
 2245 
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- 
 
 2246 
		level = 9;
- 
 
 2247 
		break;
- 
 
 2248 
	}
- 
 
 2249 
 
- 
 
 2250 
	return level;
- 
 
 2251 
}
- 
 
 2252 
 
- 
 
 2253 
uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
- 
 
 2254 
{
- 
 
 2255 
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
- 
 
 2256 
	struct drm_device *dev = dport->base.base.dev;
- 
 
 2257 
	struct intel_encoder *encoder = &dport->base;
- 
 
 2258 
	uint8_t train_set = intel_dp->train_set[0];
- 
 
 2259 
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
- 
 
 2260 
					 DP_TRAIN_PRE_EMPHASIS_MASK);
- 
 
 2261 
	enum port port = dport->port;
- 
 
 2262 
	uint32_t level;
- 
 
 2263 
 
- 
 
 2264 
	level = translate_signal_level(signal_levels);
- 
 
 2265 
 
- 
 
 2266 
	if (IS_SKYLAKE(dev))
- 
 
 2267 
		skl_ddi_set_iboost(dev, level, port, encoder->type);
- 
 
 2268 
	else if (IS_BROXTON(dev))
1460 
	if (cpu_transcoder != TRANSCODER_EDP)
 2269 
		bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
1461 
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
 2270 
 
1462 
			   TRANS_CLK_SEL_DISABLED);
 2271 
	return DDI_BUF_TRANS_SELECT(level);
1463 
}
 2272 
}
1464 
 
 2273 
 
1465 
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 2274 
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1466 
{
 2275 
{
1467 
	struct drm_encoder *encoder = &intel_encoder->base;
 2276 
	struct drm_encoder *encoder = &intel_encoder->base;
- 
 
 2277 
	struct drm_device *dev = encoder->dev;
Line 1468... Line 2278...
1468 
	struct drm_device *dev = encoder->dev;
 2278 
	struct drm_i915_private *dev_priv = dev->dev_private;
1469 
	struct drm_i915_private *dev_priv = dev->dev_private;
 2279 
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1470 
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 2280 
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1471 
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 2281 
	int type = intel_encoder->type;
Line 1472... Line 2282...
1472 
	int type = intel_encoder->type;
 2282 
	int hdmi_level;
1473 
 
 2283 
 
1474 
	if (type == INTEL_OUTPUT_EDP) {
 2284 
	if (type == INTEL_OUTPUT_EDP) {
Line 1475... Line 2285...
1475 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 2285 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1476 
		intel_edp_panel_on(intel_dp);
 2286 
		intel_edp_panel_on(intel_dp);
1477 
	}
 2287 
	}
Line 1489... Line 2299...
1489 
 
 2299 
 
Line 1490... Line 2300...
1490 
			val = I915_READ(DPLL_CTRL1);
 2300 
			val = I915_READ(DPLL_CTRL1);
1491 
 
 2301 
 
1492 
			val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
 2302 
			val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1493 
				 DPLL_CTRL1_SSC(dpll) |
 2303 
				 DPLL_CTRL1_SSC(dpll) |
Line 1494... Line 2304...
1494 
				 DPLL_CRTL1_LINK_RATE_MASK(dpll));
 2304 
				 DPLL_CTRL1_LINK_RATE_MASK(dpll));
1495 
			val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6);
 2305 
			val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
1496 
 
 2306 
 
Line 1506... Line 2316...
1506 
		val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
 2316 
		val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1507 
			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
 2317 
			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
Line 1508... Line 2318...
1508 
 
 2318 
 
Line 1509... Line 2319...
1509 
		I915_WRITE(DPLL_CTRL2, val);
 2319 
		I915_WRITE(DPLL_CTRL2, val);
1510 
 
 2320 
 
1511 
	} else {
 2321 
	} else if (INTEL_INFO(dev)->gen < 9) {
1512 
	WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
 2322 
		WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
Line 1513... Line 2323...
1513 
	I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
 2323 
		I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
1514 
	}
 2324 
	}
Line -... Line 2325...
- 
 
 2325 
 
- 
 
 2326 
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1515 
 
 2327 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Line 1516... Line 2328...
1516 
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 2328 
 
1517 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 2329 
		intel_dp_set_link_params(intel_dp, crtc->config);
1518 
 
 - 
 
1519 
		intel_ddi_init_dp_buf_reg(intel_encoder);
 2330 
 
1520 
 
 2331 
		intel_ddi_init_dp_buf_reg(intel_encoder);
1521 
		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 2332 
 
1522 
		intel_dp_start_link_train(intel_dp);
 2333 
		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
Line -... Line 2334...
- 
 
 2334 
		intel_dp_start_link_train(intel_dp);
- 
 
 2335 
		if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
- 
 
 2336 
			intel_dp_stop_link_train(intel_dp);
- 
 
 2337 
	} else if (type == INTEL_OUTPUT_HDMI) {
- 
 
 2338 
		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- 
 
 2339 
 
1523 
		intel_dp_complete_link_train(intel_dp);
 2340 
		if (IS_BROXTON(dev)) {
1524 
		if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
 2341 
			hdmi_level = dev_priv->vbt.
1525 
			intel_dp_stop_link_train(intel_dp);
 2342 
				ddi_port_info[port].hdmi_level_shift;
1526 
	} else if (type == INTEL_OUTPUT_HDMI) {
 2343 
			bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1527 
		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 2344 
					INTEL_OUTPUT_HDMI);
Line 1528... Line 2345...
1528 
 
 2345 
		}
1529 
		intel_hdmi->set_infoframes(encoder,
 2346 
		intel_hdmi->set_infoframes(encoder,
Line 1565... Line 2382...
1565 
	}
 2382 
	}
Line 1566... Line 2383...
1566 
 
 2383 
 
1567 
	if (IS_SKYLAKE(dev))
 2384 
	if (IS_SKYLAKE(dev))
1568 
		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
 2385 
		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1569 
					DPLL_CTRL2_DDI_CLK_OFF(port)));
 2386 
					DPLL_CTRL2_DDI_CLK_OFF(port)));
1570 
	else
 2387 
	else if (INTEL_INFO(dev)->gen < 9)
1571 
	I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 2388 
		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
Line 1572... Line 2389...
1572 
}
 2389 
}
1573 
 
 2390 
 
Line 1598... Line 2415...
1598 
		if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
 2415 
		if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1599 
			intel_dp_stop_link_train(intel_dp);
 2416 
			intel_dp_stop_link_train(intel_dp);
Line 1600... Line 2417...
1600 
 
 2417 
 
1601 
		intel_edp_backlight_on(intel_dp);
 2418 
		intel_edp_backlight_on(intel_dp);
- 
 
 2419 
		intel_psr_enable(intel_dp);
1602 
		intel_psr_enable(intel_dp);
 2420 
		intel_edp_drrs_enable(intel_dp);
Line 1603... Line 2421...
1603 
	}
 2421 
	}
1604 
 
 2422 
 
1605 
	if (intel_crtc->config.has_audio) {
 2423 
	if (intel_crtc->config->has_audio) {
1606 
		intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
 2424 
		intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1607 
		intel_audio_codec_enable(intel_encoder);
 2425 
		intel_audio_codec_enable(intel_encoder);
Line 1615... Line 2433...
1615 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 2433 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1616 
	int type = intel_encoder->type;
 2434 
	int type = intel_encoder->type;
1617 
	struct drm_device *dev = encoder->dev;
 2435 
	struct drm_device *dev = encoder->dev;
1618 
	struct drm_i915_private *dev_priv = dev->dev_private;
 2436 
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 1619... Line 2437...
1619 
 
 2437 
 
1620 
	if (intel_crtc->config.has_audio) {
 2438 
	if (intel_crtc->config->has_audio) {
1621 
		intel_audio_codec_disable(intel_encoder);
 2439 
		intel_audio_codec_disable(intel_encoder);
1622 
		intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
 2440 
		intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
Line 1623... Line 2441...
1623 
	}
 2441 
	}
1624 
 
 2442 
 
Line -... Line 2443...
- 
 
 2443 
	if (type == INTEL_OUTPUT_EDP) {
1625 
	if (type == INTEL_OUTPUT_EDP) {
 2444 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1626 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 2445 
 
1627 
 
 2446 
		intel_edp_drrs_disable(intel_dp);
1628 
		intel_psr_disable(intel_dp);
 2447 
		intel_psr_disable(intel_dp);
Line 1629... Line -...
1629 
		intel_edp_backlight_off(intel_dp);
 - 
 
1630 
	}
 - 
 
1631 
}
 - 
 
1632 
 
 - 
 
1633 
static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
 - 
 
1634 
{
 - 
 
1635 
	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
 - 
 
1636 
	uint32_t cdctl = I915_READ(CDCLK_CTL);
 - 
 
1637 
	uint32_t linkrate;
 - 
 
1638 
 
 - 
 
1639 
	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
 - 
 
1640 
		WARN(1, "LCPLL1 not enabled\n");
 - 
 
1641 
		return 24000; /* 24MHz is the cd freq with NSSC ref */
 - 
 
1642 
	}
 - 
 
1643 
 
 - 
 
1644 
	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
 - 
 
1645 
		return 540000;
 - 
 
1646 
 
 - 
 
1647 
	linkrate = (I915_READ(DPLL_CTRL1) &
 - 
 
1648 
		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
 - 
 
1649 
 
 - 
 
1650 
	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
 - 
 
1651 
	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
 - 
 
1652 
		/* vco 8640 */
 - 
 
1653 
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 - 
 
1654 
		case CDCLK_FREQ_450_432:
 - 
 
1655 
			return 432000;
 - 
 
1656 
		case CDCLK_FREQ_337_308:
 - 
 
1657 
			return 308570;
 - 
 
1658 
		case CDCLK_FREQ_675_617:
 - 
 
1659 
			return 617140;
 - 
 
1660 
		default:
 - 
 
1661 
			WARN(1, "Unknown cd freq selection\n");
 - 
 
1662 
		}
 - 
 
1663 
	} else {
 - 
 
1664 
		/* vco 8100 */
 - 
 
1665 
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 - 
 
1666 
		case CDCLK_FREQ_450_432:
 - 
 
1667 
			return 450000;
 - 
 
1668 
		case CDCLK_FREQ_337_308:
 - 
 
1669 
			return 337500;
 - 
 
1670 
		case CDCLK_FREQ_675_617:
 - 
 
1671 
			return 675000;
 - 
 
1672 
		default:
 - 
 
1673 
			WARN(1, "Unknown cd freq selection\n");
 - 
 
1674 
		}
 - 
 
1675 
	}
 - 
 
1676 
 
 - 
 
1677 
	/* error case, do as if DPLL0 isn't enabled */
 - 
 
1678 
	return 24000;
 - 
 
1679 
}
 - 
 
1680 
 
 - 
 
1681 
static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
 - 
 
1682 
{
 - 
 
1683 
	uint32_t lcpll = I915_READ(LCPLL_CTL);
 - 
 
1684 
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 - 
 
1685 
 
 - 
 
1686 
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
 - 
 
1687 
		return 800000;
 - 
 
1688 
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 - 
 
1689 
		return 450000;
 - 
 
1690 
	else if (freq == LCPLL_CLK_FREQ_450)
 - 
 
1691 
		return 450000;
 - 
 
1692 
	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 - 
 
1693 
			return 540000;
 - 
 
1694 
		else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 - 
 
1695 
			return 337500;
 - 
 
1696 
		else
 2448 
		intel_edp_backlight_off(intel_dp);
1697 
			return 675000;
 - 
 
1698 
}
 - 
 
1699 
 
 - 
 
1700 
static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
 - 
 
1701 
{
 - 
 
1702 
	struct drm_device *dev = dev_priv->dev;
 - 
 
1703 
	uint32_t lcpll = I915_READ(LCPLL_CTL);
 - 
 
1704 
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 - 
 
1705 
 
 - 
 
1706 
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
 2449 
	}
1707 
		return 800000;
 - 
 
1708 
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 - 
 
1709 
		return 450000;
 - 
 
1710 
	else if (freq == LCPLL_CLK_FREQ_450)
 - 
 
1711 
		return 450000;
 - 
 
1712 
	else if (IS_HSW_ULT(dev))
 - 
 
1713 
		return 337500;
 - 
 
1714 
	else
 - 
 
1715 
		return 540000;
 2450 
}
1716 
}
 2451 
 
1717 
 
 - 
 
1718 
int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 - 
 
1719 
{
 - 
 
1720 
	struct drm_device *dev = dev_priv->dev;
 - 
 
1721 
 
 2452 
static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
1722 
	if (IS_SKYLAKE(dev))
 - 
 
1723 
		return skl_get_cdclk_freq(dev_priv);
 - 
 
1724 
 
 2453 
			       struct intel_shared_dpll *pll)
1725 
	if (IS_BROADWELL(dev))
 - 
 
1726 
		return bdw_get_cdclk_freq(dev_priv);
 2454 
{
Line 1727... Line 2455...
1727 
 
 2455 
	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1728 
	/* Haswell */
 2456 
	POSTING_READ(WRPLL_CTL(pll->id));
1729 
	return hsw_get_cdclk_freq(dev_priv);
 2457 
	udelay(20);
1730 
}
 2458 
}
1731 
 
 2459 
 
1732 
static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
 2460 
static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
1733 
			       struct intel_shared_dpll *pll)
 2461 
				struct intel_shared_dpll *pll)
Line 1734... Line 2462...
1734 
{
 2462 
{
1735 
	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
 2463 
	I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
1736 
	POSTING_READ(WRPLL_CTL(pll->id));
 2464 
	POSTING_READ(SPLL_CTL);
1737 
	udelay(20);
 2465 
	udelay(20);
Line 1738... Line 2466...
1738 
}
 2466 
}
1739 
 
 2467 
 
1740 
static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
 2468 
static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
1741 
				struct intel_shared_dpll *pll)
 2469 
				  struct intel_shared_dpll *pll)
Line -... Line 2470...
- 
 
 2470 
{
- 
 
 2471 
	uint32_t val;
- 
 
 2472 
 
- 
 
 2473 
	val = I915_READ(WRPLL_CTL(pll->id));
- 
 
 2474 
	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
- 
 
 2475 
	POSTING_READ(WRPLL_CTL(pll->id));
- 
 
 2476 
}
- 
 
 2477 
 
- 
 
 2478 
static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
- 
 
 2479 
				 struct intel_shared_dpll *pll)
1742 
{
 2480 
{
1743 
	uint32_t val;
 2481 
	uint32_t val;
1744 
 
 2482 
 
1745 
	val = I915_READ(WRPLL_CTL(pll->id));
 2483 
	val = I915_READ(SPLL_CTL);
1746 
	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
 2484 
	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
Line 1760... Line 2498...
1760 
	hw_state->wrpll = val;
 2498 
	hw_state->wrpll = val;
Line 1761... Line 2499...
1761 
 
 2499 
 
1762 
	return val & WRPLL_PLL_ENABLE;
 2500 
	return val & WRPLL_PLL_ENABLE;
Line -... Line 2501...
- 
 
 2501 
}
- 
 
 2502 
 
- 
 
 2503 
static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
- 
 
 2504 
				      struct intel_shared_dpll *pll,
- 
 
 2505 
				      struct intel_dpll_hw_state *hw_state)
- 
 
 2506 
{
- 
 
 2507 
	uint32_t val;
- 
 
 2508 
 
- 
 
 2509 
	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
- 
 
 2510 
		return false;
- 
 
 2511 
 
- 
 
 2512 
	val = I915_READ(SPLL_CTL);
- 
 
 2513 
	hw_state->spll = val;
- 
 
 2514 
 
- 
 
 2515 
	return val & SPLL_PLL_ENABLE;
- 
 
 2516 
}
1763 
}
 2517 
 
1764 
 
 2518 
 
1765 
static const char * const hsw_ddi_pll_names[] = {
 2519 
static const char * const hsw_ddi_pll_names[] = {
- 
 
 2520 
	"WRPLL 1",
1766 
	"WRPLL 1",
 2521 
	"WRPLL 2",
Line 1767... Line 2522...
1767 
	"WRPLL 2",
 2522 
	"SPLL"
1768 
};
 2523 
};
1769 
 
 2524 
 
Line 1770... Line 2525...
1770 
static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
 2525 
static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
Line 1771... Line 2526...
1771 
{
 2526 
{
1772 
	int i;
 2527 
	int i;
1773 
 
 2528 
 
1774 
	dev_priv->num_shared_dpll = 2;
 2529 
	dev_priv->num_shared_dpll = 3;
1775 
 
 2530 
 
1776 
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 2531 
	for (i = 0; i < 2; i++) {
1777 
		dev_priv->shared_dplls[i].id = i;
 2532 
		dev_priv->shared_dplls[i].id = i;
1778 
		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
 2533 
		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
- 
 
 2534 
		dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
- 
 
 2535 
		dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
- 
 
 2536 
		dev_priv->shared_dplls[i].get_hw_state =
- 
 
 2537 
			hsw_ddi_wrpll_get_hw_state;
- 
 
 2538 
	}
- 
 
 2539 
 
- 
 
 2540 
	/* SPLL is special, but needs to be initialized anyway.. */
- 
 
 2541 
	dev_priv->shared_dplls[i].id = i;
1779 
		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
 2542 
	dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
Line 1780... Line 2543...
1780 
		dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
 2543 
	dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
1781 
		dev_priv->shared_dplls[i].get_hw_state =
 2544 
	dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
1782 
			hsw_ddi_pll_get_hw_state;
 2545 
	dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
Line 1796... Line 2559...
1796 
/* this array is indexed by the *shared* pll id */
 2559 
/* this array is indexed by the *shared* pll id */
1797 
static const struct skl_dpll_regs skl_dpll_regs[3] = {
 2560 
static const struct skl_dpll_regs skl_dpll_regs[3] = {
1798 
	{
 2561 
	{
1799 
		/* DPLL 1 */
 2562 
		/* DPLL 1 */
1800 
		.ctl = LCPLL2_CTL,
 2563 
		.ctl = LCPLL2_CTL,
1801 
		.cfgcr1 = DPLL1_CFGCR1,
 2564 
		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1802 
		.cfgcr2 = DPLL1_CFGCR2,
 2565 
		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
1803 
	},
 2566 
	},
1804 
	{
 2567 
	{
1805 
		/* DPLL 2 */
 2568 
		/* DPLL 2 */
1806 
		.ctl = WRPLL_CTL1,
 2569 
		.ctl = WRPLL_CTL1,
1807 
		.cfgcr1 = DPLL2_CFGCR1,
 2570 
		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1808 
		.cfgcr2 = DPLL2_CFGCR2,
 2571 
		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
1809 
	},
 2572 
	},
1810 
	{
 2573 
	{
1811 
		/* DPLL 3 */
 2574 
		/* DPLL 3 */
1812 
		.ctl = WRPLL_CTL2,
 2575 
		.ctl = WRPLL_CTL2,
1813 
		.cfgcr1 = DPLL3_CFGCR1,
 2576 
		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1814 
		.cfgcr2 = DPLL3_CFGCR2,
 2577 
		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1815 
	},
 2578 
	},
1816 
};
 2579 
};
Line 1817... Line 2580...
1817 
 
 2580 
 
1818 
static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 2581 
static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
Line 1826... Line 2589...
1826 
	dpll = pll->id + 1;
 2589 
	dpll = pll->id + 1;
Line 1827... Line 2590...
1827 
 
 2590 
 
Line 1828... Line 2591...
1828 
	val = I915_READ(DPLL_CTRL1);
 2591 
	val = I915_READ(DPLL_CTRL1);
1829 
 
 2592 
 
1830 
	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
 2593 
	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
Line 1831... Line 2594...
1831 
		 DPLL_CRTL1_LINK_RATE_MASK(dpll));
 2594 
		 DPLL_CTRL1_LINK_RATE_MASK(dpll));
1832 
	val |= pll->config.hw_state.ctrl1 << (dpll * 6);
 2595 
	val |= pll->config.hw_state.ctrl1 << (dpll * 6);
Line 1902... Line 2665...
1902 
		dev_priv->shared_dplls[i].get_hw_state =
 2665 
		dev_priv->shared_dplls[i].get_hw_state =
1903 
			skl_ddi_pll_get_hw_state;
 2666 
			skl_ddi_pll_get_hw_state;
1904 
	}
 2667 
	}
1905 
}
 2668 
}
Line -... Line 2669...
- 
 
 2669 
 
- 
 
 2670 
static void broxton_phy_init(struct drm_i915_private *dev_priv,
- 
 
 2671 
			     enum dpio_phy phy)
- 
 
 2672 
{
- 
 
 2673 
	enum port port;
- 
 
 2674 
	uint32_t val;
- 
 
 2675 
 
- 
 
 2676 
	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
- 
 
 2677 
	val |= GT_DISPLAY_POWER_ON(phy);
- 
 
 2678 
	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
- 
 
 2679 
 
- 
 
 2680 
	/* Considering 10ms timeout until BSpec is updated */
- 
 
 2681 
	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
- 
 
 2682 
		DRM_ERROR("timeout during PHY%d power on\n", phy);
- 
 
 2683 
 
- 
 
 2684 
	for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
- 
 
 2685 
	     port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
- 
 
 2686 
		int lane;
- 
 
 2687 
 
- 
 
 2688 
		for (lane = 0; lane < 4; lane++) {
- 
 
 2689 
			val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
- 
 
 2690 
			/*
- 
 
 2691 
			 * Note that on CHV this flag is called UPAR, but has
- 
 
 2692 
			 * the same function.
- 
 
 2693 
			 */
- 
 
 2694 
			val &= ~LATENCY_OPTIM;
- 
 
 2695 
			if (lane != 1)
- 
 
 2696 
				val |= LATENCY_OPTIM;
- 
 
 2697 
 
- 
 
 2698 
			I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
- 
 
 2699 
		}
- 
 
 2700 
	}
- 
 
 2701 
 
- 
 
 2702 
	/* Program PLL Rcomp code offset */
- 
 
 2703 
	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
- 
 
 2704 
	val &= ~IREF0RC_OFFSET_MASK;
- 
 
 2705 
	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
- 
 
 2706 
	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
- 
 
 2707 
 
- 
 
 2708 
	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
- 
 
 2709 
	val &= ~IREF1RC_OFFSET_MASK;
- 
 
 2710 
	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
- 
 
 2711 
	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
- 
 
 2712 
 
- 
 
 2713 
	/* Program power gating */
- 
 
 2714 
	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
- 
 
 2715 
	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
- 
 
 2716 
		SUS_CLK_CONFIG;
- 
 
 2717 
	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
- 
 
 2718 
 
- 
 
 2719 
	if (phy == DPIO_PHY0) {
- 
 
 2720 
		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
- 
 
 2721 
		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
- 
 
 2722 
		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
- 
 
 2723 
	}
- 
 
 2724 
 
- 
 
 2725 
	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
- 
 
 2726 
	val &= ~OCL2_LDOFUSE_PWR_DIS;
- 
 
 2727 
	/*
- 
 
 2728 
	 * On PHY1 disable power on the second channel, since no port is
- 
 
 2729 
	 * connected there. On PHY0 both channels have a port, so leave it
- 
 
 2730 
	 * enabled.
- 
 
 2731 
	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
- 
 
 2732 
	 * power down the second channel on PHY0 as well.
- 
 
 2733 
	 */
- 
 
 2734 
	if (phy == DPIO_PHY1)
- 
 
 2735 
		val |= OCL2_LDOFUSE_PWR_DIS;
- 
 
 2736 
	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
- 
 
 2737 
 
- 
 
 2738 
	if (phy == DPIO_PHY0) {
- 
 
 2739 
		uint32_t grc_code;
- 
 
 2740 
		/*
- 
 
 2741 
		 * PHY0 isn't connected to an RCOMP resistor so copy over
- 
 
 2742 
		 * the corresponding calibrated value from PHY1, and disable
- 
 
 2743 
		 * the automatic calibration on PHY0.
- 
 
 2744 
		 */
- 
 
 2745 
		if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
- 
 
 2746 
			     10))
- 
 
 2747 
			DRM_ERROR("timeout waiting for PHY1 GRC\n");
- 
 
 2748 
 
- 
 
 2749 
		val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
- 
 
 2750 
		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
- 
 
 2751 
		grc_code = val << GRC_CODE_FAST_SHIFT |
- 
 
 2752 
			   val << GRC_CODE_SLOW_SHIFT |
- 
 
 2753 
			   val;
- 
 
 2754 
		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
- 
 
 2755 
 
- 
 
 2756 
		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
- 
 
 2757 
		val |= GRC_DIS | GRC_RDY_OVRD;
- 
 
 2758 
		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
- 
 
 2759 
	}
- 
 
 2760 
 
- 
 
 2761 
	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
- 
 
 2762 
	val |= COMMON_RESET_DIS;
- 
 
 2763 
	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
- 
 
 2764 
}
- 
 
 2765 
 
- 
 
 2766 
void broxton_ddi_phy_init(struct drm_device *dev)
- 
 
 2767 
{
- 
 
 2768 
	/* Enable PHY1 first since it provides Rcomp for PHY0 */
- 
 
 2769 
	broxton_phy_init(dev->dev_private, DPIO_PHY1);
- 
 
 2770 
	broxton_phy_init(dev->dev_private, DPIO_PHY0);
- 
 
 2771 
}
- 
 
 2772 
 
- 
 
 2773 
static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
- 
 
 2774 
			       enum dpio_phy phy)
- 
 
 2775 
{
- 
 
 2776 
	uint32_t val;
- 
 
 2777 
 
- 
 
 2778 
	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
- 
 
 2779 
	val &= ~COMMON_RESET_DIS;
- 
 
 2780 
	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
- 
 
 2781 
}
- 
 
 2782 
 
- 
 
 2783 
void broxton_ddi_phy_uninit(struct drm_device *dev)
- 
 
 2784 
{
- 
 
 2785 
	struct drm_i915_private *dev_priv = dev->dev_private;
- 
 
 2786 
 
- 
 
 2787 
	broxton_phy_uninit(dev_priv, DPIO_PHY1);
- 
 
 2788 
	broxton_phy_uninit(dev_priv, DPIO_PHY0);
- 
 
 2789 
 
- 
 
 2790 
	/* FIXME: do this in broxton_phy_uninit per phy */
- 
 
 2791 
	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
- 
 
 2792 
}
- 
 
 2793 
 
- 
 
 2794 
static const char * const bxt_ddi_pll_names[] = {
- 
 
 2795 
	"PORT PLL A",
- 
 
 2796 
	"PORT PLL B",
- 
 
 2797 
	"PORT PLL C",
- 
 
 2798 
};
- 
 
 2799 
 
- 
 
 2800 
static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
- 
 
 2801 
				struct intel_shared_dpll *pll)
- 
 
 2802 
{
- 
 
 2803 
	uint32_t temp;
- 
 
 2804 
	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
- 
 
 2805 
 
- 
 
 2806 
	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
- 
 
 2807 
	temp &= ~PORT_PLL_REF_SEL;
- 
 
 2808 
	/* Non-SSC reference */
- 
 
 2809 
	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
- 
 
 2810 
 
- 
 
 2811 
	/* Disable 10 bit clock */
- 
 
 2812 
	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
- 
 
 2813 
	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
- 
 
 2814 
	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
- 
 
 2815 
 
- 
 
 2816 
	/* Write P1 & P2 */
- 
 
 2817 
	temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
- 
 
 2818 
	temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
- 
 
 2819 
	temp |= pll->config.hw_state.ebb0;
- 
 
 2820 
	I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
- 
 
 2821 
 
- 
 
 2822 
	/* Write M2 integer */
- 
 
 2823 
	temp = I915_READ(BXT_PORT_PLL(port, 0));
- 
 
 2824 
	temp &= ~PORT_PLL_M2_MASK;
- 
 
 2825 
	temp |= pll->config.hw_state.pll0;
- 
 
 2826 
	I915_WRITE(BXT_PORT_PLL(port, 0), temp);
- 
 
 2827 
 
- 
 
 2828 
	/* Write N */
- 
 
 2829 
	temp = I915_READ(BXT_PORT_PLL(port, 1));
- 
 
 2830 
	temp &= ~PORT_PLL_N_MASK;
- 
 
 2831 
	temp |= pll->config.hw_state.pll1;
- 
 
 2832 
	I915_WRITE(BXT_PORT_PLL(port, 1), temp);
- 
 
 2833 
 
- 
 
 2834 
	/* Write M2 fraction */
- 
 
 2835 
	temp = I915_READ(BXT_PORT_PLL(port, 2));
- 
 
 2836 
	temp &= ~PORT_PLL_M2_FRAC_MASK;
- 
 
 2837 
	temp |= pll->config.hw_state.pll2;
- 
 
 2838 
	I915_WRITE(BXT_PORT_PLL(port, 2), temp);
- 
 
 2839 
 
- 
 
 2840 
	/* Write M2 fraction enable */
- 
 
 2841 
	temp = I915_READ(BXT_PORT_PLL(port, 3));
- 
 
 2842 
	temp &= ~PORT_PLL_M2_FRAC_ENABLE;
- 
 
 2843 
	temp |= pll->config.hw_state.pll3;
- 
 
 2844 
	I915_WRITE(BXT_PORT_PLL(port, 3), temp);
- 
 
 2845 
 
- 
 
 2846 
	/* Write coeff */
- 
 
 2847 
	temp = I915_READ(BXT_PORT_PLL(port, 6));
- 
 
 2848 
	temp &= ~PORT_PLL_PROP_COEFF_MASK;
- 
 
 2849 
	temp &= ~PORT_PLL_INT_COEFF_MASK;
- 
 
 2850 
	temp &= ~PORT_PLL_GAIN_CTL_MASK;
- 
 
 2851 
	temp |= pll->config.hw_state.pll6;
- 
 
 2852 
	I915_WRITE(BXT_PORT_PLL(port, 6), temp);
- 
 
 2853 
 
- 
 
 2854 
	/* Write calibration val */
- 
 
 2855 
	temp = I915_READ(BXT_PORT_PLL(port, 8));
- 
 
 2856 
	temp &= ~PORT_PLL_TARGET_CNT_MASK;
- 
 
 2857 
	temp |= pll->config.hw_state.pll8;
- 
 
 2858 
	I915_WRITE(BXT_PORT_PLL(port, 8), temp);
- 
 
 2859 
 
- 
 
 2860 
	temp = I915_READ(BXT_PORT_PLL(port, 9));
- 
 
 2861 
	temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
- 
 
 2862 
	temp |= pll->config.hw_state.pll9;
- 
 
 2863 
	I915_WRITE(BXT_PORT_PLL(port, 9), temp);
- 
 
 2864 
 
- 
 
 2865 
	temp = I915_READ(BXT_PORT_PLL(port, 10));
- 
 
 2866 
	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
- 
 
 2867 
	temp &= ~PORT_PLL_DCO_AMP_MASK;
- 
 
 2868 
	temp |= pll->config.hw_state.pll10;
- 
 
 2869 
	I915_WRITE(BXT_PORT_PLL(port, 10), temp);
- 
 
 2870 
 
- 
 
 2871 
	/* Recalibrate with new settings */
- 
 
 2872 
	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
- 
 
 2873 
	temp |= PORT_PLL_RECALIBRATE;
- 
 
 2874 
	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
- 
 
 2875 
	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
- 
 
 2876 
	temp |= pll->config.hw_state.ebb4;
- 
 
 2877 
	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
- 
 
 2878 
 
- 
 
 2879 
	/* Enable PLL */
- 
 
 2880 
	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
- 
 
 2881 
	temp |= PORT_PLL_ENABLE;
- 
 
 2882 
	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
- 
 
 2883 
	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
- 
 
 2884 
 
- 
 
 2885 
	if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
- 
 
 2886 
			PORT_PLL_LOCK), 200))
- 
 
 2887 
		DRM_ERROR("PLL %d not locked\n", port);
- 
 
 2888 
 
- 
 
 2889 
	/*
- 
 
 2890 
	 * While we write to the group register to program all lanes at once we
- 
 
 2891 
	 * can read only lane registers and we pick lanes 0/1 for that.
- 
 
 2892 
	 */
- 
 
 2893 
	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
- 
 
 2894 
	temp &= ~LANE_STAGGER_MASK;
- 
 
 2895 
	temp &= ~LANESTAGGER_STRAP_OVRD;
- 
 
 2896 
	temp |= pll->config.hw_state.pcsdw12;
- 
 
 2897 
	I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
- 
 
 2898 
}
- 
 
 2899 
 
- 
 
 2900 
static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
- 
 
 2901 
					struct intel_shared_dpll *pll)
- 
 
 2902 
{
- 
 
 2903 
	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
- 
 
 2904 
	uint32_t temp;
- 
 
 2905 
 
- 
 
 2906 
	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
- 
 
 2907 
	temp &= ~PORT_PLL_ENABLE;
- 
 
 2908 
	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
- 
 
 2909 
	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
- 
 
 2910 
}
- 
 
 2911 
 
- 
 
 2912 
static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
- 
 
 2913 
					struct intel_shared_dpll *pll,
- 
 
 2914 
					struct intel_dpll_hw_state *hw_state)
- 
 
 2915 
{
- 
 
 2916 
	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
- 
 
 2917 
	uint32_t val;
- 
 
 2918 
 
- 
 
 2919 
	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
- 
 
 2920 
		return false;
- 
 
 2921 
 
- 
 
 2922 
	val = I915_READ(BXT_PORT_PLL_ENABLE(port));
- 
 
 2923 
	if (!(val & PORT_PLL_ENABLE))
- 
 
 2924 
		return false;
- 
 
 2925 
 
- 
 
 2926 
	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
- 
 
 2927 
	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
- 
 
 2928 
 
- 
 
 2929 
	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
- 
 
 2930 
	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
- 
 
 2931 
 
- 
 
 2932 
	hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
- 
 
 2933 
	hw_state->pll0 &= PORT_PLL_M2_MASK;
- 
 
 2934 
 
- 
 
 2935 
	hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
- 
 
 2936 
	hw_state->pll1 &= PORT_PLL_N_MASK;
- 
 
 2937 
 
- 
 
 2938 
	hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
- 
 
 2939 
	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
- 
 
 2940 
 
- 
 
 2941 
	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
- 
 
 2942 
	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
- 
 
 2943 
 
- 
 
 2944 
	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
- 
 
 2945 
	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
- 
 
 2946 
			  PORT_PLL_INT_COEFF_MASK |
- 
 
 2947 
			  PORT_PLL_GAIN_CTL_MASK;
- 
 
 2948 
 
- 
 
 2949 
	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
- 
 
 2950 
	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
- 
 
 2951 
 
- 
 
 2952 
	hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
- 
 
 2953 
	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
- 
 
 2954 
 
- 
 
 2955 
	hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
- 
 
 2956 
	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
- 
 
 2957 
			   PORT_PLL_DCO_AMP_MASK;
- 
 
 2958 
 
- 
 
 2959 
	/*
- 
 
 2960 
	 * While we write to the group register to program all lanes at once we
- 
 
 2961 
	 * can read only lane registers. We configure all lanes the same way, so
- 
 
 2962 
	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
- 
 
 2963 
	 */
- 
 
 2964 
	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
- 
 
 2965 
	if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
- 
 
 2966 
		DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
- 
 
 2967 
				 hw_state->pcsdw12,
- 
 
 2968 
				 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
- 
 
 2969 
	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
- 
 
 2970 
 
- 
 
 2971 
	return true;
- 
 
 2972 
}
- 
 
 2973 
 
- 
 
 2974 
static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
- 
 
 2975 
{
- 
 
 2976 
	int i;
- 
 
 2977 
 
- 
 
 2978 
	dev_priv->num_shared_dpll = 3;
- 
 
 2979 
 
- 
 
 2980 
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
- 
 
 2981 
		dev_priv->shared_dplls[i].id = i;
- 
 
 2982 
		dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
- 
 
 2983 
		dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
- 
 
 2984 
		dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
- 
 
 2985 
		dev_priv->shared_dplls[i].get_hw_state =
- 
 
 2986 
			bxt_ddi_pll_get_hw_state;
- 
 
 2987 
	}
- 
 
 2988 
}
1906 
 
 2989 
 
1907 
void intel_ddi_pll_init(struct drm_device *dev)
 2990 
void intel_ddi_pll_init(struct drm_device *dev)
1908 
{
 2991 
{
1909 
	struct drm_i915_private *dev_priv = dev->dev_private;
 2992 
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 1910... Line 2993...
1910 
	uint32_t val = I915_READ(LCPLL_CTL);
 2993 
	uint32_t val = I915_READ(LCPLL_CTL);
1911 
 
 2994 
 
- 
 
 2995 
	if (IS_SKYLAKE(dev))
- 
 
 2996 
		skl_shared_dplls_init(dev_priv);
1912 
	if (IS_SKYLAKE(dev))
 2997 
	else if (IS_BROXTON(dev))
1913 
		skl_shared_dplls_init(dev_priv);
 2998 
		bxt_shared_dplls_init(dev_priv);
Line 1914... Line -...
1914 
	else
 - 
 
1915 
		hsw_shared_dplls_init(dev_priv);
 - 
 
1916 
 
 - 
 
1917 
	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
 2999 
	else
- 
 
 3000 
		hsw_shared_dplls_init(dev_priv);
- 
 
 3001 
 
- 
 
 3002 
	if (IS_SKYLAKE(dev)) {
- 
 
 3003 
		int cdclk_freq;
1918 
		      intel_ddi_get_cdclk_freq(dev_priv));
 3004 
 
1919 
 
 3005 
		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
- 
 
 3006 
		dev_priv->skl_boot_cdclk = cdclk_freq;
- 
 
 3007 
		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
- 
 
 3008 
			DRM_ERROR("LCPLL1 is disabled\n");
- 
 
 3009 
		else
- 
 
 3010 
			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1920 
	if (IS_SKYLAKE(dev)) {
 3011 
	} else if (IS_BROXTON(dev)) {
1921 
		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
 3012 
		broxton_init_cdclk(dev);
1922 
			DRM_ERROR("LCPLL1 is disabled\n");
 3013 
		broxton_ddi_phy_init(dev);
1923 
	} else {
 3014 
	} else {
1924 
		/*
 3015 
		/*
Line 1987... Line 3078...
1987 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 3078 
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1988 
	uint32_t val;
 3079 
	uint32_t val;
Line 1989... Line 3080...
1989 
 
 3080 
 
Line 1990... Line 3081...
1990 
	intel_ddi_post_disable(intel_encoder);
 3081 
	intel_ddi_post_disable(intel_encoder);
1991 
 
 3082 
 
1992 
	val = I915_READ(_FDI_RXA_CTL);
 3083 
	val = I915_READ(FDI_RX_CTL(PIPE_A));
Line 1993... Line 3084...
1993 
	val &= ~FDI_RX_ENABLE;
 3084 
	val &= ~FDI_RX_ENABLE;
1994 
	I915_WRITE(_FDI_RXA_CTL, val);
 3085 
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1995 
 
 3086 
 
1996 
	val = I915_READ(_FDI_RXA_MISC);
 3087 
	val = I915_READ(FDI_RX_MISC(PIPE_A));
Line 1997... Line 3088...
1997 
	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 3088 
	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1998 
	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 3089 
	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1999 
	I915_WRITE(_FDI_RXA_MISC, val);
 3090 
	I915_WRITE(FDI_RX_MISC(PIPE_A), val);
Line 2000... Line 3091...
2000 
 
 3091 
 
2001 
	val = I915_READ(_FDI_RXA_CTL);
 3092 
	val = I915_READ(FDI_RX_CTL(PIPE_A));
2002 
	val &= ~FDI_PCDCLK;
 3093 
	val &= ~FDI_PCDCLK;
2003 
	I915_WRITE(_FDI_RXA_CTL, val);
 - 
 
2004 
 
 - 
 
2005 
	val = I915_READ(_FDI_RXA_CTL);
 - 
 
2006 
	val &= ~FDI_RX_PLL_ENABLE;
 - 
 
2007 
	I915_WRITE(_FDI_RXA_CTL, val);
 - 
 
2008 
}
 - 
 
2009 
 
 - 
 
2010 
static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
 - 
 
2011 
{
 - 
 
2012 
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
 - 
 
2013 
	int type = intel_dig_port->base.type;
 - 
 
2014 
 
 - 
 
2015 
	if (type != INTEL_OUTPUT_DISPLAYPORT &&
 - 
 
2016 
	    type != INTEL_OUTPUT_EDP &&
 - 
 
2017 
	    type != INTEL_OUTPUT_UNKNOWN) {
 3094 
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
Line 2018... Line 3095...
2018 
		return;
 3095 
 
2019 
	}
 3096 
	val = I915_READ(FDI_RX_CTL(PIPE_A));
2020 
 
 3097 
	val &= ~FDI_RX_PLL_ENABLE;
2021 
	intel_dp_hot_plug(intel_encoder);
 3098 
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2022 
}
 3099 
}
2023 
 
 3100 
 
2024 
void intel_ddi_get_config(struct intel_encoder *encoder,
 3101 
void intel_ddi_get_config(struct intel_encoder *encoder,
2025 
				 struct intel_crtc_config *pipe_config)
 3102 
			  struct intel_crtc_state *pipe_config)
2026 
{
 - 
 
Line 2027... Line 3103...
2027 
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 3103 
{
2028 
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 3104 
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2029 
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 3105 
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2030 
	struct intel_hdmi *intel_hdmi;
 3106 
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
Line 2039... Line 3115...
2039 
	if (temp & TRANS_DDI_PVSYNC)
 3115 
	if (temp & TRANS_DDI_PVSYNC)
2040 
		flags |= DRM_MODE_FLAG_PVSYNC;
 3116 
		flags |= DRM_MODE_FLAG_PVSYNC;
2041 
	else
 3117 
	else
2042 
		flags |= DRM_MODE_FLAG_NVSYNC;
 3118 
		flags |= DRM_MODE_FLAG_NVSYNC;
Line 2043... Line 3119...
2043 
 
 3119 
 
Line 2044... Line 3120...
2044 
	pipe_config->adjusted_mode.flags |= flags;
 3120 
	pipe_config->base.adjusted_mode.flags |= flags;
2045 
 
 3121 
 
2046 
	switch (temp & TRANS_DDI_BPC_MASK) {
 3122 
	switch (temp & TRANS_DDI_BPC_MASK) {
2047 
	case TRANS_DDI_BPC_6:
 3123 
	case TRANS_DDI_BPC_6:
Line 2072... Line 3148...
2072 
	case TRANS_DDI_MODE_SELECT_FDI:
 3148 
	case TRANS_DDI_MODE_SELECT_FDI:
2073 
		break;
 3149 
		break;
2074 
	case TRANS_DDI_MODE_SELECT_DP_SST:
 3150 
	case TRANS_DDI_MODE_SELECT_DP_SST:
2075 
	case TRANS_DDI_MODE_SELECT_DP_MST:
 3151 
	case TRANS_DDI_MODE_SELECT_DP_MST:
2076 
		pipe_config->has_dp_encoder = true;
 3152 
		pipe_config->has_dp_encoder = true;
- 
 
 3153 
		pipe_config->lane_count =
- 
 
 3154 
			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2077 
		intel_dp_get_m_n(intel_crtc, pipe_config);
 3155 
		intel_dp_get_m_n(intel_crtc, pipe_config);
2078 
		break;
 3156 
		break;
2079 
	default:
 3157 
	default:
2080 
		break;
 3158 
		break;
2081 
	}
 3159 
	}
Line 2104... Line 3182...
2104 
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
 3182 
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2105 
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
 3183 
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2106 
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
 3184 
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2107 
	}
 3185 
	}
Line 2108... Line -...
2108 
 
 - 
 
2109 
	if (INTEL_INFO(dev)->gen <= 8)
 - 
 
2110 
		hsw_ddi_clock_get(encoder, pipe_config);
 - 
 
2111 
	else
 3186 
 
2112 
		skl_ddi_clock_get(encoder, pipe_config);
 3187 
	intel_ddi_clock_get(encoder, pipe_config);
Line 2113... Line 3188...
2113 
}
 3188 
}
2114 
 
 3189 
 
2115 
static void intel_ddi_destroy(struct drm_encoder *encoder)
 3190 
static void intel_ddi_destroy(struct drm_encoder *encoder)
2116 
{
 3191 
{
2117 
	/* HDMI has nothing special to destroy, so we can go with this. */
 3192 
	/* HDMI has nothing special to destroy, so we can go with this. */
Line 2118... Line 3193...
2118 
	intel_dp_encoder_destroy(encoder);
 3193 
	intel_dp_encoder_destroy(encoder);
2119 
}
 3194 
}
2120 
 
 3195 
 
2121 
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
 3196 
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2122 
				     struct intel_crtc_config *pipe_config)
 3197 
				     struct intel_crtc_state *pipe_config)
Line 2123... Line 3198...
2123 
{
 3198 
{
Line 2143... Line 3218...
2143 
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
 3218 
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2144 
{
 3219 
{
2145 
	struct intel_connector *connector;
 3220 
	struct intel_connector *connector;
2146 
	enum port port = intel_dig_port->port;
 3221 
	enum port port = intel_dig_port->port;
Line 2147... Line 3222...
2147 
 
 3222 
 
2148 
	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
 3223 
	connector = intel_connector_alloc();
2149 
	if (!connector)
 3224 
	if (!connector)
Line 2150... Line 3225...
2150 
		return NULL;
 3225 
		return NULL;
2151 
 
 3226 
 
Line 2162... Line 3237...
2162 
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
 3237 
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2163 
{
 3238 
{
2164 
	struct intel_connector *connector;
 3239 
	struct intel_connector *connector;
2165 
	enum port port = intel_dig_port->port;
 3240 
	enum port port = intel_dig_port->port;
Line 2166... Line 3241...
2166 
 
 3241 
 
2167 
	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
 3242 
	connector = intel_connector_alloc();
2168 
	if (!connector)
 3243 
	if (!connector)
Line 2169... Line 3244...
2169 
		return NULL;
 3244 
		return NULL;
2170 
 
 3245 
 
Line 2184... Line 3259...
2184 
 
 3259 
 
2185 
	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
 3260 
	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2186 
		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
 3261 
		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2187 
	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
 3262 
	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2188 
	if (!init_dp && !init_hdmi) {
 3263 
	if (!init_dp && !init_hdmi) {
2189 
		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
 3264 
		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2190 
			      port_name(port));
 - 
 
2191 
		init_hdmi = true;
 3265 
			      port_name(port));
2192 
		init_dp = true;
 3266 
		return;
Line 2193... Line 3267...
2193 
	}
 3267 
	}
2194 
 
 3268 
 
2195 
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
 3269 
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Line 2216... Line 3290...
2216 
					   DDI_A_4_LANES);
 3290 
					   DDI_A_4_LANES);
Line 2217... Line 3291...
2217 
 
 3291 
 
2218 
	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
 3292 
	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2219 
	intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
 3293 
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2220 
	intel_encoder->cloneable = 0;
 - 
 
Line 2221... Line 3294...
2221 
	intel_encoder->hot_plug = intel_ddi_hot_plug;
 3294 
	intel_encoder->cloneable = 0;
2222 
 
 3295 
 
2223 
	if (init_dp) {
 3296 
	if (init_dp) {
Line 2224... Line 3297...
2224 
		if (!intel_ddi_init_dp_connector(intel_dig_port))
 3297 
		if (!intel_ddi_init_dp_connector(intel_dig_port))
- 
 
 3298 
			goto err;
- 
 
 3299 
 
- 
 
 3300 
		intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
- 
 
 3301 
		/*
- 
 
 3302 
		 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
- 
 
 3303 
		 * interrupts to check the external panel connection.
- 
 
 3304 
		 */
- 
 
 3305 
		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
2225 
			goto err;
 3306 
					 && port == PORT_B)
2226 
 
 3307 
			dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
Line 2227... Line 3308...
2227 
		intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
 3308 
		else
2228 
		dev_priv->hpd_irq_port[port] = intel_dig_port;
 3309 
			dev_priv->hotplug.irq_port[port] = intel_dig_port;
2229 
	}
 3310 
	}