WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_ddi.c

 x00FFFFFF, 0x0005000A,
 x00D75FFF, 0x000C0004,
 x80C30FFF, 0x000B0000,
 x00FFFFFF, 0x00040006,
 x80D75FFF, 0x000B0000,
-x00FFFFFF, 0x00040006		/* HDMI parameters */
 };
 static const u32 hsw_ddi_translations_fdi[] = {
 x00FFFFFF, 0x0007000E,		/* FDI parameters */
 x00FFFFFF, 0x000F000A,
 x00D75FFF, 0x00160004,
 x00C30FFF, 0x001E0000,
 x00FFFFFF, 0x00060006,
 x00D75FFF, 0x001E0000,
-x00FFFFFF, 0x00040006		/* HDMI parameters */
 };
+static const u32 hsw_ddi_translations_hdmi[] = {
+				/* Idx	NT mV diff	T mV diff	db  */
+x00FFFFFF, 0x0006000E, /* 0:	400		400		0   */
+x00E79FFF, 0x000E000C, /* 1:	400		500		2   */
+x00D75FFF, 0x0005000A, /* 2:	400		600		3.5 */
+x00FFFFFF, 0x0005000A, /* 3:	600		600		0   */
+x00E79FFF, 0x001D0007, /* 4:	600		750		2   */
+x00D75FFF, 0x000C0004, /* 5:	600		900		3.5 */
+x00FFFFFF, 0x00040006, /* 6:	800		800		0   */
+x80E79FFF, 0x00030002, /* 7:	800		1000		2   */
+x00FFFFFF, 0x00140005, /* 8:	850		850		0   */
+x00FFFFFF, 0x000C0004, /* 9:	900		900		0   */
+x00FFFFFF, 0x001C0003, /* 10:	950		950		0   */
+x80FFFFFF, 0x00030002, /* 11:	1000		1000		0   */
+};
+static const u32 bdw_ddi_translations_edp[] = {
+x00FFFFFF, 0x00000012,		/* eDP parameters */
+x00EBAFFF, 0x00020011,
+x00C71FFF, 0x0006000F,
+x00FFFFFF, 0x00020011,
+x00DB6FFF, 0x0005000F,
+x00BEEFFF, 0x000A000C,
+x00FFFFFF, 0x0005000F,
+x00DB6FFF, 0x000A000C,
+x00FFFFFF, 0x000A000C,
+x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
+};
+static const u32 bdw_ddi_translations_dp[] = {
+x00FFFFFF, 0x0007000E,		/* DP parameters */
+x00D75FFF, 0x000E000A,
+x00BEFFFF, 0x00140006,
+x00FFFFFF, 0x000E000A,
+x00D75FFF, 0x00180004,
+x80CB2FFF, 0x001B0002,
+x00F7DFFF, 0x00180004,
+x80D75FFF, 0x001B0002,
+x80FFFFFF, 0x001B0002,
+x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
+};
+static const u32 bdw_ddi_translations_fdi[] = {
+x00FFFFFF, 0x0001000E,		/* FDI parameters */
+x00D75FFF, 0x0004000A,
+x00C30FFF, 0x00070006,
+x00AAAFFF, 0x000C0000,
+x00FFFFFF, 0x0004000A,
+x00D75FFF, 0x00090004,
+x00C30FFF, 0x000C0000,
+x00FFFFFF, 0x00070006,
+x00D75FFF, 0x000C0000,
+x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
+};
-static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
+enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
+{
 	struct drm_encoder *encoder = &intel_encoder->base;
 	int type = intel_encoder->type;
 		DRM_ERROR("Invalid DDI encoder type %d\n", type);
 		BUG();
+	}
+}
+/*
-/* On Haswell, DDI port buffers must be programmed with correct values
+ * Starting with Haswell, DDI port buffers must be programmed with correct
- * in advance. The buffer values are different for FDI and DP modes,
+ * values in advance. The buffer values are different for FDI and DP modes,
  * but the HDMI/DVI fields are shared among those. So we program the DDI
  * in either FDI or DP modes only, as HDMI connections will work with both
  * of those
  */
 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg;
+	int i;
-	int i;
+	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
-	const u32 *ddi_translations = (port == PORT_E) ?
+	const u32 *ddi_translations_fdi;
-		hsw_ddi_translations_fdi :
+	const u32 *ddi_translations_dp;
+	const u32 *ddi_translations_edp;
+	const u32 *ddi_translations;
+	if (IS_BROADWELL(dev)) {
+		ddi_translations_fdi = bdw_ddi_translations_fdi;
+		ddi_translations_dp = bdw_ddi_translations_dp;
+		ddi_translations_edp = bdw_ddi_translations_edp;
+	} else if (IS_HASWELL(dev)) {
+		ddi_translations_fdi = hsw_ddi_translations_fdi;
+		ddi_translations_dp = hsw_ddi_translations_dp;
+		ddi_translations_edp = hsw_ddi_translations_dp;
+	} else {
+		WARN(1, "ddi translation table missing\n");
+		ddi_translations_edp = bdw_ddi_translations_dp;
+		ddi_translations_fdi = bdw_ddi_translations_fdi;
+		ddi_translations_dp = bdw_ddi_translations_dp;
+	}
+	switch (port) {
+	case PORT_A:
+		ddi_translations = ddi_translations_edp;
+		break;
+	case PORT_B:
+	case PORT_C:
+		ddi_translations = ddi_translations_dp;
+		break;
+	case PORT_D:
+		if (intel_dp_is_edp(dev, PORT_D))
+			ddi_translations = ddi_translations_edp;
+		else
+			ddi_translations = ddi_translations_dp;
+		break;
+	case PORT_E:
+		ddi_translations = ddi_translations_fdi;
+		break;
+	default:
+		BUG();
 		hsw_ddi_translations_dp;
 	for (i = 0, reg = DDI_BUF_TRANS(port);
 	     i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 		I915_WRITE(reg, ddi_translations[i]);
+		reg += 4;
+	}
+	/* Entry 9 is for HDMI: */
+	for (i = 0; i < 2; i++) {
+		I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
 		reg += 4;
+	}
+}
 			/* write eld */
 			DRM_DEBUG_DRIVER("DP audio: write eld information\n");
 			intel_write_eld(&encoder->base, adjusted_mode);
-		}
-		intel_dp_init_link_config(intel_dp);
+		}
 	} else if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+	}
 	*n2_out = best.n2;
 	*p_out = best.p;
-	*r2_out = best.r2;
-	DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
-		      clock, *p_out, *n2_out, *r2_out);
+	*r2_out = best.r2;
+}
+/*
+ * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
+ * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
+ * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
-}
+ * enable the PLL.
  */
-bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
+bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
+{
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct drm_crtc *crtc = &intel_crtc->base;
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
-	int type = intel_encoder->type;
-	enum pipe pipe = intel_crtc->pipe;
+	int type = intel_encoder->type;
-	uint32_t reg, val;
-	int clock = intel_crtc->config.port_clock;
 	enum pipe pipe = intel_crtc->pipe;
-	/* TODO: reuse PLLs when possible (compare values) */
+	int clock = intel_crtc->config.port_clock;
 			DRM_ERROR("Link bandwidth %d unsupported\n",
 				  intel_dp->link_bw);
 			return false;
+		}
-		/* We don't need to turn any PLL on because we'll use LCPLL. */
-		return true;
+	} else if (type == INTEL_OUTPUT_HDMI) {
-	} else if (type == INTEL_OUTPUT_HDMI) {
+		uint32_t reg, val;
+		unsigned p, n2, r2;
+		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
+		val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
+		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+		      WRPLL_DIVIDER_POST(p);
+		if (val == I915_READ(WRPLL_CTL1)) {
+			DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
+				      pipe_name(pipe));
+			reg = WRPLL_CTL1;
+		} else if (val == I915_READ(WRPLL_CTL2)) {
+			DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
-		unsigned p, n2, r2;
+				      pipe_name(pipe));
 			reg = WRPLL_CTL2;
-		if (plls->wrpll1_refcount == 0) {
+		} else if (plls->wrpll1_refcount == 0) {
-			DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
-				      pipe_name(pipe));
+			DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
-			plls->wrpll1_refcount++;
-			reg = WRPLL_CTL1;
+				      pipe_name(pipe));
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
+			reg = WRPLL_CTL1;
 		} else if (plls->wrpll2_refcount == 0) {
-			DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
-				      pipe_name(pipe));
+			DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
-			plls->wrpll2_refcount++;
-			reg = WRPLL_CTL2;
+				      pipe_name(pipe));
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
+			reg = WRPLL_CTL2;
 		} else {
 			DRM_ERROR("No WRPLLs available!\n");
 			return false;
 		}
+		DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
-		WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
-		     "WRPLL already enabled\n");
+			      clock, p, n2, r2);
+		if (reg == WRPLL_CTL1) {
-		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
+			plls->wrpll1_refcount++;
+			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 		} else {
-		val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
+			plls->wrpll2_refcount++;
-		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 		      WRPLL_DIVIDER_POST(p);
-	} else if (type == INTEL_OUTPUT_ANALOG) {
-		if (plls->spll_refcount == 0) {
+	} else if (type == INTEL_OUTPUT_ANALOG) {
-			DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
+		if (plls->spll_refcount == 0) {
-				      pipe_name(pipe));
+			DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
-			plls->spll_refcount++;
+				      pipe_name(pipe));
-			reg = SPLL_CTL;
+			plls->spll_refcount++;
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
-		} else {
-			DRM_ERROR("SPLL already in use\n");
-			return false;
-		}
 			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
-		WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
+		} else {
-		     "SPLL already enabled\n");
+			DRM_ERROR("SPLL already in use\n");
 			return false;
-		val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
-	} else {
 		WARN(1, "Invalid DDI encoder type %d\n", type);
 		return false;
+	} else {
+		WARN(1, "Invalid DDI encoder type %d\n", type);
+		return false;
+	}
+	return true;
+}
+/*
+ * To be called after intel_ddi_pll_select(). That one selects the PLL to be
+ * used, this one actually enables the PLL.
+ */
+void intel_ddi_pll_enable(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
+	int clock = crtc->config.port_clock;
+	uint32_t reg, cur_val, new_val;
+	int refcount;
+	const char *pll_name;
+	uint32_t enable_bit = (1 << 31);
+	unsigned int p, n2, r2;
+	BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
+	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
+	switch (crtc->ddi_pll_sel) {
+	case PORT_CLK_SEL_LCPLL_2700:
+	case PORT_CLK_SEL_LCPLL_1350:
+	case PORT_CLK_SEL_LCPLL_810:
+		/*
+		 * LCPLL should always be enabled at this point of the mode set
+		 * sequence, so nothing to do.
+		 */
+		return;
+	case PORT_CLK_SEL_SPLL:
+		pll_name = "SPLL";
+		reg = SPLL_CTL;
+		refcount = plls->spll_refcount;
+		new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
+			  SPLL_PLL_SSC;
+		break;
+	case PORT_CLK_SEL_WRPLL1:
+	case PORT_CLK_SEL_WRPLL2:
+		if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
+			pll_name = "WRPLL1";
+			reg = WRPLL_CTL1;
+			refcount = plls->wrpll1_refcount;
+	} else {
+			pll_name = "WRPLL2";
+			reg = WRPLL_CTL2;
+			refcount = plls->wrpll2_refcount;
+		}
+		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
+		new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
+			  WRPLL_DIVIDER_REFERENCE(r2) |
+			  WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
+		break;
+	case PORT_CLK_SEL_NONE:
+		WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
+		return;
+	default:
+		WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
+		return;
+	}
+	cur_val = I915_READ(reg);
+	WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
+	if (refcount == 1) {
+		WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
 		I915_WRITE(reg, new_val);
 		POSTING_READ(reg);
-	I915_WRITE(reg, val);
+	udelay(20);
-	udelay(20);
+	} else {
 		WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
+{
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 	struct drm_encoder *encoder = &intel_encoder->base;
+	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum pipe pipe = intel_crtc->pipe;
 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 	int type = intel_encoder->type;
 	uint32_t temp;
 		break;
 	default:
 		BUG();
+	}
-	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
+	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 		temp |= TRANS_DDI_PVSYNC;
-	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
+	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 		temp |= TRANS_DDI_PHSYNC;
 	if (cpu_transcoder == TRANSCODER_EDP) {
 		switch (pipe) {
 		case PIPE_A:
-			/* Can only use the always-on power well for eDP when
+			/* On Haswell, can only use the always-on power well for
+			 * eDP when not using the panel fitter, and when not
-			 * not using the panel fitter, and when not using motion
+			 * using motion blur mitigation (which we don't
-			  * blur mitigation (which we don't support). */
+			 * support). */
-			if (intel_crtc->config.pch_pfit.enabled)
+			if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
 			temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 			else
 				temp |= TRANS_DDI_EDP_INPUT_A_ON;
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 	int type = intel_encoder->type;
 	if (type == INTEL_OUTPUT_EDP) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-		ironlake_edp_panel_vdd_on(intel_dp);
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-		ironlake_edp_panel_on(intel_dp);
-		ironlake_edp_panel_vdd_off(intel_dp, true);
+		ironlake_edp_panel_on(intel_dp);
+	}
 	I915_WRITE(DP_TP_CTL(port), val);
 	if (wait)
 		intel_wait_ddi_buf_idle(dev_priv, port);
-	if (type == INTEL_OUTPUT_EDP) {
+	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-		ironlake_edp_panel_vdd_on(intel_dp);
+		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		ironlake_edp_panel_off(intel_dp);
+	}
+	}
+}
 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
+	uint32_t lcpll = I915_READ(LCPLL_CTL);
-	uint32_t lcpll = I915_READ(LCPLL_CTL);
+	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
-	if (lcpll & LCPLL_CD_SOURCE_FCLK)
+	if (lcpll & LCPLL_CD_SOURCE_FCLK) {
 		return 800000;
-	else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
+	} else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
 		return 450000;
-	else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)
+	} else if (freq == LCPLL_CLK_FREQ_450) {
+		return 450000;
-		return 450000;
+	} else if (IS_HASWELL(dev)) {
-	else if (IS_ULT(dev_priv->dev))
+		if (IS_ULT(dev))
 		return 337500;
+	else
+		return 540000;
+	} else {
+		if (freq == LCPLL_CLK_FREQ_54O_BDW)
+			return 540000;
+		else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
+			return 337500;
+		else
-	else
+			return 675000;
 		return 540000;
+}
 			intel_wait_ddi_buf_idle(dev_priv, port);
+	}
 	val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
 	      DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
-	if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
 	I915_WRITE(DP_TP_CTL(port), val);
 	POSTING_READ(DP_TP_CTL(port));
 		break;
 	default:
 		break;
+	}
+	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
+	case TRANS_DDI_MODE_SELECT_HDMI:
+	case TRANS_DDI_MODE_SELECT_DVI:
+	case TRANS_DDI_MODE_SELECT_FDI:
+		break;
+	case TRANS_DDI_MODE_SELECT_DP_SST:
+	case TRANS_DDI_MODE_SELECT_DP_MST:
+		pipe_config->has_dp_encoder = true;
+		intel_dp_get_m_n(intel_crtc, pipe_config);
+		break;
+	default:
+		break;
+	}
 	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
 		/*
 		 * This is a big fat ugly hack.
 static const struct drm_encoder_funcs intel_ddi_funcs = {
 	.destroy = intel_ddi_destroy,
+};
+static struct intel_connector *
+intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
+{
+	struct intel_connector *connector;
+	enum port port = intel_dig_port->port;
+	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
+	if (!connector)
+		return NULL;
+	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
+	if (!intel_dp_init_connector(intel_dig_port, connector)) {
+		kfree(connector);
+		return NULL;
+	}
+	return connector;
+}
+static struct intel_connector *
+intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
+{
+	struct intel_connector *connector;
+	enum port port = intel_dig_port->port;
+	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
+	if (!connector)
+		return NULL;
+	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
+	intel_hdmi_init_connector(intel_dig_port, connector);
+	return connector;
 };
 void intel_ddi_init(struct drm_device *dev, enum port port)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port;
 	struct intel_encoder *intel_encoder;
 	struct drm_encoder *encoder;
+	struct intel_connector *hdmi_connector = NULL;
+	struct intel_connector *dp_connector = NULL;
+	bool init_hdmi, init_dp;
-	struct intel_connector *hdmi_connector = NULL;
-	struct intel_connector *dp_connector = NULL;
+	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
+		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
+	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
+	if (!init_dp && !init_hdmi) {
+		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
+			      port_name(port));
-	intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
+		init_hdmi = true;
-	if (!intel_dig_port)
-		return;
+		init_dp = true;
+	}
-	dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 	if (!dp_connector) {
-		kfree(intel_dig_port);
+	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
-		return;
+	if (!intel_dig_port)
 	intel_dig_port->port = port;
 	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
 					  (DDI_BUF_PORT_REVERSAL |
-					   DDI_A_4_LANES);
-	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
+					   DDI_A_4_LANES);
 	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
 	intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
-	intel_encoder->cloneable = false;
-	intel_encoder->hot_plug = intel_ddi_hot_plug;
+	intel_encoder->cloneable = false;
-	if (!intel_dp_init_connector(intel_dig_port, dp_connector)) {
+	intel_encoder->hot_plug = intel_ddi_hot_plug;
-		drm_encoder_cleanup(encoder);
-		kfree(intel_dig_port);
+	if (init_dp)
-		kfree(dp_connector);
+		dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
-		return;
-	}
-	if (intel_encoder->type != INTEL_OUTPUT_EDP) {
-		hdmi_connector = kzalloc(sizeof(struct intel_connector),
-					 GFP_KERNEL);
+	/* In theory we don't need the encoder->type check, but leave it just in
+	 * case we have some really bad VBTs... */
-		if (!hdmi_connector) {
+	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
-			return;
+		hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ddi.c – Rev 4539 → 4560