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Rev 6937 | Rev 7144 | ||
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Line 131... | Line 131... | ||
131 | /* Skylake H and S */ |
131 | /* Skylake H and S */ |
132 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
132 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
133 | { 0x00002016, 0x000000A0, 0x0 }, |
133 | { 0x00002016, 0x000000A0, 0x0 }, |
134 | { 0x00005012, 0x0000009B, 0x0 }, |
134 | { 0x00005012, 0x0000009B, 0x0 }, |
135 | { 0x00007011, 0x00000088, 0x0 }, |
135 | { 0x00007011, 0x00000088, 0x0 }, |
136 | { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
136 | { 0x80009010, 0x000000C0, 0x1 }, |
137 | { 0x00002016, 0x0000009B, 0x0 }, |
137 | { 0x00002016, 0x0000009B, 0x0 }, |
138 | { 0x00005012, 0x00000088, 0x0 }, |
138 | { 0x00005012, 0x00000088, 0x0 }, |
139 | { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
139 | { 0x80007011, 0x000000C0, 0x1 }, |
140 | { 0x00002016, 0x000000DF, 0x0 }, |
140 | { 0x00002016, 0x000000DF, 0x0 }, |
141 | { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
141 | { 0x80005012, 0x000000C0, 0x1 }, |
142 | }; |
142 | }; |
Line 143... | Line 143... | ||
143 | 143 | ||
144 | /* Skylake U */ |
144 | /* Skylake U */ |
145 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { |
145 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { |
146 | { 0x0000201B, 0x000000A2, 0x0 }, |
146 | { 0x0000201B, 0x000000A2, 0x0 }, |
147 | { 0x00005012, 0x00000088, 0x0 }, |
147 | { 0x00005012, 0x00000088, 0x0 }, |
148 | { 0x00007011, 0x00000087, 0x0 }, |
148 | { 0x80007011, 0x000000CD, 0x0 }, |
149 | { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
149 | { 0x80009010, 0x000000C0, 0x1 }, |
150 | { 0x0000201B, 0x0000009D, 0x0 }, |
150 | { 0x0000201B, 0x0000009D, 0x0 }, |
151 | { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
151 | { 0x80005012, 0x000000C0, 0x1 }, |
152 | { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
152 | { 0x80007011, 0x000000C0, 0x1 }, |
153 | { 0x00002016, 0x00000088, 0x0 }, |
153 | { 0x00002016, 0x00000088, 0x0 }, |
154 | { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
154 | { 0x80005012, 0x000000C0, 0x1 }, |
Line 155... | Line 155... | ||
155 | }; |
155 | }; |
156 | 156 | ||
157 | /* Skylake Y */ |
157 | /* Skylake Y */ |
158 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { |
158 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { |
159 | { 0x00000018, 0x000000A2, 0x0 }, |
159 | { 0x00000018, 0x000000A2, 0x0 }, |
160 | { 0x00005012, 0x00000088, 0x0 }, |
160 | { 0x00005012, 0x00000088, 0x0 }, |
161 | { 0x00007011, 0x00000087, 0x0 }, |
161 | { 0x80007011, 0x000000CD, 0x0 }, |
162 | { 0x80009010, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
162 | { 0x80009010, 0x000000C0, 0x3 }, |
163 | { 0x00000018, 0x0000009D, 0x0 }, |
163 | { 0x00000018, 0x0000009D, 0x0 }, |
164 | { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
164 | { 0x80005012, 0x000000C0, 0x3 }, |
165 | { 0x80007011, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
165 | { 0x80007011, 0x000000C0, 0x3 }, |
166 | { 0x00000018, 0x00000088, 0x0 }, |
166 | { 0x00000018, 0x00000088, 0x0 }, |
Line 167... | Line 167... | ||
167 | { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
167 | { 0x80005012, 0x000000C0, 0x3 }, |
168 | }; |
168 | }; |
169 | 169 | ||
Line 224... | Line 224... | ||
224 | { 0x00005012, 0x0000009D, 0x0 }, |
224 | { 0x00005012, 0x0000009D, 0x0 }, |
225 | { 0x00007011, 0x00000088, 0x0 }, |
225 | { 0x00007011, 0x00000088, 0x0 }, |
226 | { 0x00000018, 0x000000A1, 0x0 }, |
226 | { 0x00000018, 0x000000A1, 0x0 }, |
227 | { 0x00000018, 0x00000098, 0x0 }, |
227 | { 0x00000018, 0x00000098, 0x0 }, |
228 | { 0x00004013, 0x00000088, 0x0 }, |
228 | { 0x00004013, 0x00000088, 0x0 }, |
229 | { 0x00006012, 0x00000087, 0x0 }, |
229 | { 0x80006012, 0x000000CD, 0x1 }, |
230 | { 0x00000018, 0x000000DF, 0x0 }, |
230 | { 0x00000018, 0x000000DF, 0x0 }, |
231 | { 0x00003015, 0x00000087, 0x0 }, /* Default */ |
231 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
232 | { 0x00003015, 0x000000C7, 0x0 }, |
232 | { 0x80003015, 0x000000C0, 0x1 }, |
233 | { 0x00000018, 0x000000C7, 0x0 }, |
233 | { 0x80000018, 0x000000C0, 0x1 }, |
234 | }; |
234 | }; |
Line 235... | Line 235... | ||
235 | 235 | ||
236 | /* Skylake Y */ |
236 | /* Skylake Y */ |
237 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
237 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
238 | { 0x00000018, 0x000000A1, 0x0 }, |
238 | { 0x00000018, 0x000000A1, 0x0 }, |
239 | { 0x00005012, 0x000000DF, 0x0 }, |
239 | { 0x00005012, 0x000000DF, 0x0 }, |
240 | { 0x00007011, 0x00000084, 0x0 }, |
240 | { 0x80007011, 0x000000CB, 0x3 }, |
241 | { 0x00000018, 0x000000A4, 0x0 }, |
241 | { 0x00000018, 0x000000A4, 0x0 }, |
242 | { 0x00000018, 0x0000009D, 0x0 }, |
242 | { 0x00000018, 0x0000009D, 0x0 }, |
243 | { 0x00004013, 0x00000080, 0x0 }, |
243 | { 0x00004013, 0x00000080, 0x0 }, |
244 | { 0x00006013, 0x000000C7, 0x0 }, |
244 | { 0x80006013, 0x000000C0, 0x3 }, |
245 | { 0x00000018, 0x0000008A, 0x0 }, |
245 | { 0x00000018, 0x0000008A, 0x0 }, |
246 | { 0x00003015, 0x000000C7, 0x0 }, /* Default */ |
246 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
247 | { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */ |
247 | { 0x80003015, 0x000000C0, 0x3 }, |
248 | { 0x00000018, 0x000000C7, 0x0 }, |
248 | { 0x80000018, 0x000000C0, 0x3 }, |
Line 249... | Line 249... | ||
249 | }; |
249 | }; |
250 | 250 | ||
251 | struct bxt_ddi_buf_trans { |
251 | struct bxt_ddi_buf_trans { |
Line 299... | Line 299... | ||
299 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
299 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ |
300 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
300 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ |
301 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
301 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
302 | }; |
302 | }; |
Line 303... | Line 303... | ||
303 | 303 | ||
304 | static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, |
304 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
Line 305... | Line 305... | ||
305 | enum port port, int type); |
305 | u32 level, enum port port, int type); |
306 | 306 | ||
307 | static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, |
307 | static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, |
308 | struct intel_digital_port **dig_port, |
308 | struct intel_digital_port **dig_port, |
Line 340... | Line 340... | ||
340 | ddi_get_encoder_port(intel_encoder, &dig_port, &port); |
340 | ddi_get_encoder_port(intel_encoder, &dig_port, &port); |
Line 341... | Line 341... | ||
341 | 341 | ||
342 | return port; |
342 | return port; |
Line 343... | Line -... | ||
343 | } |
- | |
344 | 343 | } |
|
345 | static bool |
- | |
346 | intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) |
- | |
347 | { |
- | |
348 | return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg); |
- | |
349 | } |
344 | |
350 | - | ||
351 | static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, |
345 | static const struct ddi_buf_trans * |
352 | int *n_entries) |
- | |
353 | { |
- | |
354 | const struct ddi_buf_trans *ddi_translations; |
346 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
355 | - | ||
356 | if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
347 | { |
- | 348 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
|
357 | ddi_translations = skl_y_ddi_translations_dp; |
349 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
358 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
- | |
359 | } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { |
350 | return skl_y_ddi_translations_dp; |
- | 351 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
|
360 | ddi_translations = skl_u_ddi_translations_dp; |
352 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
361 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
- | |
362 | } else { |
353 | return skl_u_ddi_translations_dp; |
- | 354 | } else { |
|
363 | ddi_translations = skl_ddi_translations_dp; |
355 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
364 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
- | |
365 | } |
- | |
366 | 356 | return skl_ddi_translations_dp; |
|
Line 367... | Line 357... | ||
367 | return ddi_translations; |
357 | } |
368 | } |
358 | } |
369 | 359 | ||
370 | static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, |
- | |
371 | int *n_entries) |
- | |
372 | { |
- | |
373 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
374 | const struct ddi_buf_trans *ddi_translations; |
360 | static const struct ddi_buf_trans * |
375 | 361 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
|
376 | if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
362 | { |
377 | if (dev_priv->edp_low_vswing) { |
- | |
378 | ddi_translations = skl_y_ddi_translations_edp; |
363 | if (dev_priv->edp_low_vswing) { |
379 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
- | |
380 | } else { |
- | |
381 | ddi_translations = skl_y_ddi_translations_dp; |
364 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
382 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
- | |
383 | } |
- | |
384 | } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { |
365 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
- | 366 | return skl_y_ddi_translations_edp; |
|
385 | if (dev_priv->edp_low_vswing) { |
367 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
386 | ddi_translations = skl_u_ddi_translations_edp; |
- | |
387 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
- | |
388 | } else { |
- | |
389 | ddi_translations = skl_u_ddi_translations_dp; |
- | |
390 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
- | |
391 | } |
- | |
392 | } else { |
368 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
393 | if (dev_priv->edp_low_vswing) { |
- | |
394 | ddi_translations = skl_ddi_translations_edp; |
369 | return skl_u_ddi_translations_edp; |
395 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
- | |
396 | } else { |
370 | } else { |
397 | ddi_translations = skl_ddi_translations_dp; |
371 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
Line 398... | Line 372... | ||
398 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
372 | return skl_ddi_translations_edp; |
399 | } |
373 | } |
Line 400... | Line 374... | ||
400 | } |
374 | } |
401 | 375 | ||
402 | return ddi_translations; |
- | |
403 | } |
376 | return skl_get_buf_trans_dp(dev_priv, n_entries); |
404 | - | ||
405 | static const struct ddi_buf_trans * |
- | |
406 | skl_get_buf_trans_hdmi(struct drm_device *dev, |
377 | } |
407 | int *n_entries) |
- | |
408 | { |
378 | |
- | 379 | static const struct ddi_buf_trans * |
|
409 | const struct ddi_buf_trans *ddi_translations; |
380 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
410 | - | ||
411 | if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
381 | { |
- | 382 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
|
412 | ddi_translations = skl_y_ddi_translations_hdmi; |
383 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
413 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
- | |
414 | } else { |
- | |
415 | ddi_translations = skl_ddi_translations_hdmi; |
384 | return skl_y_ddi_translations_hdmi; |
Line 416... | Line 385... | ||
416 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
385 | } else { |
417 | } |
386 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
418 | 387 | return skl_ddi_translations_hdmi; |
|
419 | return ddi_translations; |
388 | } |
420 | } |
389 | } |
421 | 390 | ||
422 | /* |
391 | /* |
423 | * Starting with Haswell, DDI port buffers must be programmed with correct |
392 | * Starting with Haswell, DDI port buffers must be programmed with correct |
424 | * values in advance. The buffer values are different for FDI and DP modes, |
- | |
425 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
393 | * values in advance. The buffer values are different for FDI and DP modes, |
426 | * in either FDI or DP modes only, as HDMI connections will work with both |
394 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
427 | * of those |
395 | * in either FDI or DP modes only, as HDMI connections will work with both |
428 | */ |
396 | * of those |
429 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, |
397 | */ |
430 | bool supports_hdmi) |
398 | void intel_prepare_ddi_buffer(struct intel_encoder *encoder) |
- | 399 | { |
|
431 | { |
400 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
432 | struct drm_i915_private *dev_priv = dev->dev_private; |
401 | u32 iboost_bit = 0; |
433 | u32 iboost_bit = 0; |
402 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, |
434 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, |
403 | size; |
435 | size; |
404 | int hdmi_level; |
Line -... | Line 405... | ||
- | 405 | enum port port; |
|
- | 406 | const struct ddi_buf_trans *ddi_translations_fdi; |
|
- | 407 | const struct ddi_buf_trans *ddi_translations_dp; |
|
436 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
408 | const struct ddi_buf_trans *ddi_translations_edp; |
437 | const struct ddi_buf_trans *ddi_translations_fdi; |
409 | const struct ddi_buf_trans *ddi_translations_hdmi; |
438 | const struct ddi_buf_trans *ddi_translations_dp; |
410 | const struct ddi_buf_trans *ddi_translations; |
Line 439... | Line 411... | ||
439 | const struct ddi_buf_trans *ddi_translations_edp; |
411 | |
440 | const struct ddi_buf_trans *ddi_translations_hdmi; |
412 | port = intel_ddi_get_encoder_port(encoder); |
441 | const struct ddi_buf_trans *ddi_translations; |
413 | hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
442 | 414 | ||
- | 415 | if (IS_BROXTON(dev_priv)) { |
|
- | 416 | if (encoder->type != INTEL_OUTPUT_HDMI) |
|
443 | if (IS_BROXTON(dev)) { |
417 | return; |
444 | if (!supports_hdmi) |
418 | |
445 | return; |
419 | /* Vswing programming for HDMI */ |
446 | 420 | bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port, |
|
447 | /* Vswing programming for HDMI */ |
421 | INTEL_OUTPUT_HDMI); |
448 | bxt_ddi_vswing_sequence(dev, hdmi_level, port, |
422 | return; |
449 | INTEL_OUTPUT_HDMI); |
423 | } |
450 | return; |
424 | |
451 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
425 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
452 | ddi_translations_fdi = NULL; |
426 | ddi_translations_fdi = NULL; |
453 | ddi_translations_dp = |
427 | ddi_translations_dp = |
454 | skl_get_buf_trans_dp(dev, &n_dp_entries); |
428 | skl_get_buf_trans_dp(dev_priv, &n_dp_entries); |
455 | ddi_translations_edp = |
429 | ddi_translations_edp = |
- | 430 | skl_get_buf_trans_edp(dev_priv, &n_edp_entries); |
|
- | 431 | ddi_translations_hdmi = |
|
- | 432 | skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); |
|
- | 433 | hdmi_default_entry = 8; |
|
- | 434 | /* If we're boosting the current, set bit 31 of trans1 */ |
|
456 | skl_get_buf_trans_edp(dev, &n_edp_entries); |
435 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || |
457 | ddi_translations_hdmi = |
436 | dev_priv->vbt.ddi_port_info[port].dp_boost_level) |
458 | skl_get_buf_trans_hdmi(dev, &n_hdmi_entries); |
437 | iboost_bit = 1<<31; |
Line 459... | Line 438... | ||
459 | hdmi_default_entry = 8; |
438 | |
460 | /* If we're boosting the current, set bit 31 of trans1 */ |
439 | if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && |
Line 476... | Line 455... | ||
476 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
455 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
Line 477... | Line 456... | ||
477 | 456 | ||
478 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
457 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
479 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
458 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
480 | hdmi_default_entry = 7; |
459 | hdmi_default_entry = 7; |
481 | } else if (IS_HASWELL(dev)) { |
460 | } else if (IS_HASWELL(dev_priv)) { |
482 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
461 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
483 | ddi_translations_dp = hsw_ddi_translations_dp; |
462 | ddi_translations_dp = hsw_ddi_translations_dp; |
484 | ddi_translations_edp = hsw_ddi_translations_dp; |
463 | ddi_translations_edp = hsw_ddi_translations_dp; |
485 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
464 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
Line 496... | Line 475... | ||
496 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
475 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
497 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
476 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
498 | hdmi_default_entry = 7; |
477 | hdmi_default_entry = 7; |
499 | } |
478 | } |
Line 500... | Line 479... | ||
500 | 479 | ||
501 | switch (port) { |
480 | switch (encoder->type) { |
502 | case PORT_A: |
481 | case INTEL_OUTPUT_EDP: |
503 | ddi_translations = ddi_translations_edp; |
482 | ddi_translations = ddi_translations_edp; |
504 | size = n_edp_entries; |
483 | size = n_edp_entries; |
505 | break; |
- | |
506 | case PORT_B: |
484 | break; |
507 | case PORT_C: |
- | |
508 | ddi_translations = ddi_translations_dp; |
- | |
509 | size = n_dp_entries; |
- | |
510 | break; |
485 | case INTEL_OUTPUT_DISPLAYPORT: |
511 | case PORT_D: |
- | |
512 | if (intel_dp_is_edp(dev, PORT_D)) { |
- | |
513 | ddi_translations = ddi_translations_edp; |
- | |
514 | size = n_edp_entries; |
- | |
515 | } else { |
486 | case INTEL_OUTPUT_HDMI: |
516 | ddi_translations = ddi_translations_dp; |
487 | ddi_translations = ddi_translations_dp; |
517 | size = n_dp_entries; |
- | |
518 | } |
488 | size = n_dp_entries; |
519 | break; |
489 | break; |
520 | case PORT_E: |
- | |
521 | if (ddi_translations_fdi) |
490 | case INTEL_OUTPUT_ANALOG: |
522 | ddi_translations = ddi_translations_fdi; |
- | |
523 | else |
- | |
524 | ddi_translations = ddi_translations_dp; |
491 | ddi_translations = ddi_translations_fdi; |
525 | size = n_dp_entries; |
492 | size = n_dp_entries; |
526 | break; |
493 | break; |
527 | default: |
494 | default: |
528 | BUG(); |
495 | BUG(); |
Line 533... | Line 500... | ||
533 | ddi_translations[i].trans1 | iboost_bit); |
500 | ddi_translations[i].trans1 | iboost_bit); |
534 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
501 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
535 | ddi_translations[i].trans2); |
502 | ddi_translations[i].trans2); |
536 | } |
503 | } |
Line 537... | Line 504... | ||
537 | 504 | ||
538 | if (!supports_hdmi) |
505 | if (encoder->type != INTEL_OUTPUT_HDMI) |
Line 539... | Line 506... | ||
539 | return; |
506 | return; |
540 | 507 | ||
541 | /* Choose a good default if VBT is badly populated */ |
508 | /* Choose a good default if VBT is badly populated */ |
Line 548... | Line 515... | ||
548 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
515 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
549 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
516 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), |
550 | ddi_translations_hdmi[hdmi_level].trans2); |
517 | ddi_translations_hdmi[hdmi_level].trans2); |
551 | } |
518 | } |
Line 552... | Line -... | ||
552 | - | ||
553 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP |
- | |
554 | * mode and port E for FDI. |
- | |
555 | */ |
- | |
556 | void intel_prepare_ddi(struct drm_device *dev) |
- | |
557 | { |
- | |
558 | struct intel_encoder *intel_encoder; |
- | |
559 | bool visited[I915_MAX_PORTS] = { 0, }; |
- | |
560 | - | ||
561 | if (!HAS_DDI(dev)) |
- | |
562 | return; |
- | |
563 | - | ||
564 | for_each_intel_encoder(dev, intel_encoder) { |
- | |
565 | struct intel_digital_port *intel_dig_port; |
- | |
566 | enum port port; |
- | |
567 | bool supports_hdmi; |
- | |
568 | - | ||
569 | if (intel_encoder->type == INTEL_OUTPUT_DSI) |
- | |
570 | continue; |
- | |
571 | - | ||
572 | ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); |
- | |
573 | if (visited[port]) |
- | |
574 | continue; |
- | |
575 | - | ||
576 | supports_hdmi = intel_dig_port && |
- | |
577 | intel_dig_port_supports_hdmi(intel_dig_port); |
- | |
578 | - | ||
579 | intel_prepare_ddi_buffers(dev, port, supports_hdmi); |
- | |
580 | visited[port] = true; |
- | |
581 | } |
- | |
582 | } |
- | |
583 | 519 | ||
584 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
520 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
585 | enum port port) |
521 | enum port port) |
586 | { |
522 | { |
587 | i915_reg_t reg = DDI_BUF_CTL(port); |
523 | i915_reg_t reg = DDI_BUF_CTL(port); |
Line 607... | Line 543... | ||
607 | void hsw_fdi_link_train(struct drm_crtc *crtc) |
543 | void hsw_fdi_link_train(struct drm_crtc *crtc) |
608 | { |
544 | { |
609 | struct drm_device *dev = crtc->dev; |
545 | struct drm_device *dev = crtc->dev; |
610 | struct drm_i915_private *dev_priv = dev->dev_private; |
546 | struct drm_i915_private *dev_priv = dev->dev_private; |
611 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 548 | struct intel_encoder *encoder; |
|
612 | u32 temp, i, rx_ctl_val; |
549 | u32 temp, i, rx_ctl_val; |
Line -... | Line 550... | ||
- | 550 | ||
- | 551 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
|
- | 552 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); |
|
- | 553 | intel_prepare_ddi_buffer(encoder); |
|
- | 554 | } |
|
613 | 555 | ||
614 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
556 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
615 | * mode set "sequence for CRT port" document: |
557 | * mode set "sequence for CRT port" document: |
616 | * - TP1 to TP2 time with the default value |
558 | * - TP1 to TP2 time with the default value |
617 | * - FDI delay to 90h |
559 | * - FDI delay to 90h |
Line 1610... | Line 1552... | ||
1610 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); |
1552 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); |
1611 | break; |
1553 | break; |
1612 | } |
1554 | } |
Line 1613... | Line 1555... | ||
1613 | 1555 | ||
1614 | cfgcr1 = cfgcr2 = 0; |
1556 | cfgcr1 = cfgcr2 = 0; |
1615 | } else /* eDP */ |
1557 | } else if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
- | 1558 | return true; |
|
- | 1559 | } else |
|
Line 1616... | Line 1560... | ||
1616 | return true; |
1560 | return false; |
1617 | 1561 | ||
Line 1618... | Line 1562... | ||
1618 | memset(&crtc_state->dpll_hw_state, 0, |
1562 | memset(&crtc_state->dpll_hw_state, 0, |
Line 2115... | Line 2059... | ||
2115 | if (cpu_transcoder != TRANSCODER_EDP) |
2059 | if (cpu_transcoder != TRANSCODER_EDP) |
2116 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
2060 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
2117 | TRANS_CLK_SEL_DISABLED); |
2061 | TRANS_CLK_SEL_DISABLED); |
2118 | } |
2062 | } |
Line 2119... | Line 2063... | ||
2119 | 2063 | ||
2120 | static void skl_ddi_set_iboost(struct drm_device *dev, u32 level, |
2064 | static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
2121 | enum port port, int type) |
2065 | u32 level, enum port port, int type) |
2122 | { |
- | |
2123 | struct drm_i915_private *dev_priv = dev->dev_private; |
2066 | { |
2124 | const struct ddi_buf_trans *ddi_translations; |
2067 | const struct ddi_buf_trans *ddi_translations; |
2125 | uint8_t iboost; |
2068 | uint8_t iboost; |
2126 | uint8_t dp_iboost, hdmi_iboost; |
2069 | uint8_t dp_iboost, hdmi_iboost; |
2127 | int n_entries; |
2070 | int n_entries; |
Line 2133... | Line 2076... | ||
2133 | 2076 | ||
2134 | if (type == INTEL_OUTPUT_DISPLAYPORT) { |
2077 | if (type == INTEL_OUTPUT_DISPLAYPORT) { |
2135 | if (dp_iboost) { |
2078 | if (dp_iboost) { |
2136 | iboost = dp_iboost; |
2079 | iboost = dp_iboost; |
2137 | } else { |
2080 | } else { |
2138 | ddi_translations = skl_get_buf_trans_dp(dev, &n_entries); |
2081 | ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries); |
2139 | iboost = ddi_translations[level].i_boost; |
2082 | iboost = ddi_translations[level].i_boost; |
2140 | } |
2083 | } |
2141 | } else if (type == INTEL_OUTPUT_EDP) { |
2084 | } else if (type == INTEL_OUTPUT_EDP) { |
2142 | if (dp_iboost) { |
2085 | if (dp_iboost) { |
2143 | iboost = dp_iboost; |
2086 | iboost = dp_iboost; |
2144 | } else { |
2087 | } else { |
- | 2088 | ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); |
|
- | 2089 | ||
- | 2090 | if (WARN_ON(port != PORT_A && |
|
- | 2091 | port != PORT_E && n_entries > 9)) |
|
- | 2092 | n_entries = 9; |
|
2145 | ddi_translations = skl_get_buf_trans_edp(dev, &n_entries); |
2093 | |
2146 | iboost = ddi_translations[level].i_boost; |
2094 | iboost = ddi_translations[level].i_boost; |
2147 | } |
2095 | } |
2148 | } else if (type == INTEL_OUTPUT_HDMI) { |
2096 | } else if (type == INTEL_OUTPUT_HDMI) { |
2149 | if (hdmi_iboost) { |
2097 | if (hdmi_iboost) { |
2150 | iboost = hdmi_iboost; |
2098 | iboost = hdmi_iboost; |
2151 | } else { |
2099 | } else { |
2152 | ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries); |
2100 | ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); |
2153 | iboost = ddi_translations[level].i_boost; |
2101 | iboost = ddi_translations[level].i_boost; |
2154 | } |
2102 | } |
2155 | } else { |
2103 | } else { |
2156 | return; |
2104 | return; |
Line 2172... | Line 2120... | ||
2172 | reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); |
2120 | reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); |
Line 2173... | Line 2121... | ||
2173 | 2121 | ||
2174 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); |
2122 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); |
Line 2175... | Line 2123... | ||
2175 | } |
2123 | } |
2176 | 2124 | ||
2177 | static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, |
2125 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
2178 | enum port port, int type) |
- | |
2179 | { |
2126 | u32 level, enum port port, int type) |
2180 | struct drm_i915_private *dev_priv = dev->dev_private; |
2127 | { |
2181 | const struct bxt_ddi_buf_trans *ddi_translations; |
2128 | const struct bxt_ddi_buf_trans *ddi_translations; |
Line 2182... | Line 2129... | ||
2182 | u32 n_entries, i; |
2129 | u32 n_entries, i; |
Line 2290... | Line 2237... | ||
2290 | } |
2237 | } |
Line 2291... | Line 2238... | ||
2291 | 2238 | ||
2292 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) |
2239 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) |
2293 | { |
2240 | { |
2294 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2241 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2295 | struct drm_device *dev = dport->base.base.dev; |
2242 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
2296 | struct intel_encoder *encoder = &dport->base; |
2243 | struct intel_encoder *encoder = &dport->base; |
2297 | uint8_t train_set = intel_dp->train_set[0]; |
2244 | uint8_t train_set = intel_dp->train_set[0]; |
2298 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2245 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2299 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2246 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2300 | enum port port = dport->port; |
2247 | enum port port = dport->port; |
Line 2301... | Line 2248... | ||
2301 | uint32_t level; |
2248 | uint32_t level; |
Line 2302... | Line 2249... | ||
2302 | 2249 | ||
2303 | level = translate_signal_level(signal_levels); |
2250 | level = translate_signal_level(signal_levels); |
2304 | 2251 | ||
2305 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2252 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
Line 2306... | Line 2253... | ||
2306 | skl_ddi_set_iboost(dev, level, port, encoder->type); |
2253 | skl_ddi_set_iboost(dev_priv, level, port, encoder->type); |
2307 | else if (IS_BROXTON(dev)) |
2254 | else if (IS_BROXTON(dev_priv)) |
Line 2308... | Line 2255... | ||
2308 | bxt_ddi_vswing_sequence(dev, level, port, encoder->type); |
2255 | bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); |
Line 2355... | Line 2302... | ||
2355 | } |
2302 | } |
Line 2356... | Line 2303... | ||
2356 | 2303 | ||
2357 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
2304 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
2358 | { |
2305 | { |
2359 | struct drm_encoder *encoder = &intel_encoder->base; |
- | |
2360 | struct drm_device *dev = encoder->dev; |
2306 | struct drm_encoder *encoder = &intel_encoder->base; |
2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
2307 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
2362 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
2308 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
2363 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2309 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
- | 2310 | int type = intel_encoder->type; |
|
- | 2311 | ||
- | 2312 | if (type == INTEL_OUTPUT_HDMI) { |
|
- | 2313 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
|
- | 2314 | ||
- | 2315 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
|
- | 2316 | } |
|
2364 | int type = intel_encoder->type; |
2317 | |
Line 2365... | Line 2318... | ||
2365 | int hdmi_level; |
2318 | intel_prepare_ddi_buffer(intel_encoder); |
2366 | 2319 | ||
2367 | if (type == INTEL_OUTPUT_EDP) { |
2320 | if (type == INTEL_OUTPUT_EDP) { |
2368 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2321 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Line 2378... | Line 2331... | ||
2378 | 2331 | ||
Line 2379... | Line 2332... | ||
2379 | intel_ddi_init_dp_buf_reg(intel_encoder); |
2332 | intel_ddi_init_dp_buf_reg(intel_encoder); |
2380 | 2333 | ||
2381 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2334 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2382 | intel_dp_start_link_train(intel_dp); |
2335 | intel_dp_start_link_train(intel_dp); |
2383 | if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) |
2336 | if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9) |
2384 | intel_dp_stop_link_train(intel_dp); |
2337 | intel_dp_stop_link_train(intel_dp); |
Line 2385... | Line -... | ||
2385 | } else if (type == INTEL_OUTPUT_HDMI) { |
- | |
2386 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
- | |
2387 | - | ||
2388 | if (IS_BROXTON(dev)) { |
- | |
2389 | hdmi_level = dev_priv->vbt. |
- | |
2390 | ddi_port_info[port].hdmi_level_shift; |
- | |
2391 | bxt_ddi_vswing_sequence(dev, hdmi_level, port, |
2338 | } else if (type == INTEL_OUTPUT_HDMI) { |
2392 | INTEL_OUTPUT_HDMI); |
2339 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
2393 | } |
2340 | |
2394 | intel_hdmi->set_infoframes(encoder, |
2341 | intel_hdmi->set_infoframes(encoder, |
2395 | crtc->config->has_hdmi_sink, |
2342 | crtc->config->has_hdmi_sink, |
Line 2432... | Line 2379... | ||
2432 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2379 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2433 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
2380 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
2434 | DPLL_CTRL2_DDI_CLK_OFF(port))); |
2381 | DPLL_CTRL2_DDI_CLK_OFF(port))); |
2435 | else if (INTEL_INFO(dev)->gen < 9) |
2382 | else if (INTEL_INFO(dev)->gen < 9) |
2436 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
2383 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
- | 2384 | ||
- | 2385 | if (type == INTEL_OUTPUT_HDMI) { |
|
- | 2386 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
|
- | 2387 | ||
- | 2388 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); |
|
- | 2389 | } |
|
2437 | } |
2390 | } |
Line 2438... | Line 2391... | ||
2438 | 2391 | ||
2439 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
2392 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
2440 | { |
2393 | { |
Line 3316... | Line 3269... | ||
3316 | struct drm_i915_private *dev_priv = dev->dev_private; |
3269 | struct drm_i915_private *dev_priv = dev->dev_private; |
3317 | struct intel_digital_port *intel_dig_port; |
3270 | struct intel_digital_port *intel_dig_port; |
3318 | struct intel_encoder *intel_encoder; |
3271 | struct intel_encoder *intel_encoder; |
3319 | struct drm_encoder *encoder; |
3272 | struct drm_encoder *encoder; |
3320 | bool init_hdmi, init_dp; |
3273 | bool init_hdmi, init_dp; |
- | 3274 | int max_lanes; |
|
- | 3275 | ||
- | 3276 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { |
|
- | 3277 | switch (port) { |
|
- | 3278 | case PORT_A: |
|
- | 3279 | max_lanes = 4; |
|
- | 3280 | break; |
|
- | 3281 | case PORT_E: |
|
- | 3282 | max_lanes = 0; |
|
- | 3283 | break; |
|
- | 3284 | default: |
|
- | 3285 | max_lanes = 4; |
|
- | 3286 | break; |
|
- | 3287 | } |
|
- | 3288 | } else { |
|
- | 3289 | switch (port) { |
|
- | 3290 | case PORT_A: |
|
- | 3291 | max_lanes = 2; |
|
- | 3292 | break; |
|
- | 3293 | case PORT_E: |
|
- | 3294 | max_lanes = 2; |
|
- | 3295 | break; |
|
- | 3296 | default: |
|
- | 3297 | max_lanes = 4; |
|
- | 3298 | break; |
|
- | 3299 | } |
|
- | 3300 | } |
|
Line 3321... | Line 3301... | ||
3321 | 3301 | ||
3322 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || |
3302 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || |
3323 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); |
3303 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); |
3324 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; |
3304 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; |
Line 3361... | Line 3341... | ||
3361 | */ |
3341 | */ |
3362 | if (IS_BROXTON(dev) && port == PORT_A) { |
3342 | if (IS_BROXTON(dev) && port == PORT_A) { |
3363 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
3343 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
3364 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); |
3344 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); |
3365 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; |
3345 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; |
- | 3346 | max_lanes = 4; |
|
3366 | } |
3347 | } |
3367 | } |
3348 | } |
Line -... | Line 3349... | ||
- | 3349 | ||
- | 3350 | intel_dig_port->max_lanes = max_lanes; |
|
3368 | 3351 | ||
3369 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
3352 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
3370 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3353 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Line 3371... | Line 3354... | ||
3371 | intel_encoder->cloneable = 0; |
3354 | intel_encoder->cloneable = 0; |