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Rev 6660 Rev 6937
Line 45... Line 45...
45
#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
45
#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
Line 46... Line 46...
46
 
46
 
47
MODULE_FIRMWARE(I915_CSR_SKL);
47
MODULE_FIRMWARE(I915_CSR_SKL);
Line 48... Line -...
48
MODULE_FIRMWARE(I915_CSR_BXT);
-
 
49
 
48
MODULE_FIRMWARE(I915_CSR_BXT);
50
/*
49
 
51
* SKL CSR registers for DC5 and DC6
-
 
52
*/
-
 
53
#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
-
 
54
#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
-
 
55
#define CSR_HTP_ADDR_SKL		0x00500034
-
 
56
#define CSR_SSP_BASE			0x8F074
-
 
57
#define CSR_HTP_SKL			0x8F004
-
 
58
#define CSR_LAST_WRITE			0x8F034
-
 
59
#define CSR_LAST_WRITE_VALUE		0xc003b400
50
#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)
60
/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
51
 
61
#define CSR_MAX_FW_SIZE			0x2FFF
-
 
62
#define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
-
 
Line 63... Line 52...
63
#define CSR_MMIO_START_RANGE	0x80000
52
#define CSR_MAX_FW_SIZE			0x2FFF
64
#define CSR_MMIO_END_RANGE		0x8FFFF
53
#define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
65
 
54
 
Line 175... Line 164...
175
struct stepping_info {
164
struct stepping_info {
176
	char stepping;
165
	char stepping;
177
	char substepping;
166
	char substepping;
178
};
167
};
Line -... Line 168...
-
 
168
 
-
 
169
/*
-
 
170
 * Kabylake derivated from Skylake H0, so SKL H0
-
 
171
 * is the right firmware for KBL A0 (revid 0).
-
 
172
 */
-
 
173
static const struct stepping_info kbl_stepping_info[] = {
-
 
174
	{'H', '0'}, {'I', '0'}
-
 
175
};
179
 
176
 
180
static const struct stepping_info skl_stepping_info[] = {
177
static const struct stepping_info skl_stepping_info[] = {
181
		{'A', '0'}, {'B', '0'}, {'C', '0'},
178
		{'A', '0'}, {'B', '0'}, {'C', '0'},
182
		{'D', '0'}, {'E', '0'}, {'F', '0'},
179
		{'D', '0'}, {'E', '0'}, {'F', '0'},
183
		{'G', '0'}, {'H', '0'}, {'I', '0'},
180
		{'G', '0'}, {'H', '0'}, {'I', '0'},
184
		{'J', '0'}, {'K', '0'}
181
		{'J', '0'}, {'K', '0'}
Line 185... Line 182...
185
};
182
};
186
 
183
 
187
static struct stepping_info bxt_stepping_info[] = {
184
static const struct stepping_info bxt_stepping_info[] = {
188
	{'A', '0'}, {'A', '1'}, {'A', '2'},
185
	{'A', '0'}, {'A', '1'}, {'A', '2'},
Line 189... Line 186...
189
	{'B', '0'}, {'B', '1'}, {'B', '2'}
186
	{'B', '0'}, {'B', '1'}, {'B', '2'}
190
};
187
};
191
 
-
 
192
static char intel_get_stepping(struct drm_device *dev)
-
 
193
{
-
 
194
	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
-
 
195
			ARRAY_SIZE(skl_stepping_info)))
188
 
196
		return skl_stepping_info[dev->pdev->revision].stepping;
-
 
197
	else if (IS_BROXTON(dev) && (dev->pdev->revision <
-
 
198
				ARRAY_SIZE(bxt_stepping_info)))
189
static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
199
		return bxt_stepping_info[dev->pdev->revision].stepping;
-
 
Line -... Line 190...
-
 
190
{
200
	else
191
	const struct stepping_info *si;
201
		return -ENODATA;
-
 
-
 
192
	unsigned int size;
202
}
193
 
203
 
194
	if (IS_KABYLAKE(dev)) {
204
static char intel_get_substepping(struct drm_device *dev)
195
		size = ARRAY_SIZE(kbl_stepping_info);
205
{
196
		si = kbl_stepping_info;
206
	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
197
	} else if (IS_SKYLAKE(dev)) {
207
			ARRAY_SIZE(skl_stepping_info)))
198
		size = ARRAY_SIZE(skl_stepping_info);
208
		return skl_stepping_info[dev->pdev->revision].substepping;
199
		si = skl_stepping_info;
209
	else if (IS_BROXTON(dev) && (dev->pdev->revision <
200
	} else if (IS_BROXTON(dev)) {
210
			ARRAY_SIZE(bxt_stepping_info)))
201
		size = ARRAY_SIZE(bxt_stepping_info);
Line 211... Line -...
211
		return bxt_stepping_info[dev->pdev->revision].substepping;
-
 
212
	else
-
 
213
		return -ENODATA;
202
		si = bxt_stepping_info;
214
}
-
 
215
 
-
 
216
/**
-
 
217
 * intel_csr_load_status_get() - to get firmware loading status.
203
	} else {
218
 * @dev_priv: i915 device.
-
 
219
 *
-
 
220
 * This function helps to get the firmware loading status.
-
 
221
 *
-
 
222
 * Return: Firmware loading status.
-
 
223
 */
-
 
224
enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
-
 
225
{
-
 
Line 226... Line 204...
226
	enum csr_state state;
204
		return NULL;
227
 
-
 
228
	mutex_lock(&dev_priv->csr_lock);
-
 
229
	state = dev_priv->csr.state;
-
 
230
	mutex_unlock(&dev_priv->csr_lock);
-
 
231
 
-
 
232
	return state;
-
 
233
}
-
 
234
 
-
 
235
/**
-
 
236
 * intel_csr_load_status_set() - help to set firmware loading status.
-
 
237
 * @dev_priv: i915 device.
-
 
238
 * @state: enumeration of firmware loading status.
-
 
239
 *
-
 
240
 * Set the firmware loading status.
-
 
241
 */
-
 
242
void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
205
	}
Line 243... Line 206...
243
			enum csr_state state)
206
 
244
{
207
	if (INTEL_REVID(dev) < size)
245
	mutex_lock(&dev_priv->csr_lock);
208
		return si + INTEL_REVID(dev);
246
	dev_priv->csr.state = state;
209
 
247
	mutex_unlock(&dev_priv->csr_lock);
210
	return NULL;
248
}
211
}
249
 
212
 
250
/**
213
/**
251
 * intel_csr_load_program() - write the firmware from memory to register.
214
 * intel_csr_load_program() - write the firmware from memory to register.
252
 * @dev: drm device.
215
 * @dev_priv: i915 drm device.
253
 *
-
 
254
 * CSR firmware is read from a .bin file and kept in internal memory one time.
216
 *
255
 * Everytime display comes back from low power state this function is called to
217
 * CSR firmware is read from a .bin file and kept in internal memory one time.
Line 256... Line 218...
256
 * copy the firmware from internal memory to registers.
218
 * Everytime display comes back from low power state this function is called to
257
 */
219
 * copy the firmware from internal memory to registers.
258
void intel_csr_load_program(struct drm_device *dev)
220
 */
259
{
221
void intel_csr_load_program(struct drm_i915_private *dev_priv)
Line 260... Line -...
260
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
261
	u32 *payload = dev_priv->csr.dmc_payload;
-
 
262
	uint32_t i, fw_size;
-
 
263
 
222
{
264
	if (!IS_GEN9(dev)) {
223
	u32 *payload = dev_priv->csr.dmc_payload;
265
		DRM_ERROR("No CSR support available for this platform\n");
-
 
266
		return;
-
 
267
	}
224
	uint32_t i, fw_size;
-
 
225
 
Line 268... Line -...
268
 
-
 
269
	/*
226
	if (!IS_GEN9(dev_priv)) {
270
	 * FIXME: Firmware gets lost on S3/S4, but not when entering system
227
		DRM_ERROR("No CSR support available for this platform\n");
271
	 * standby or suspend-to-idle (which is just like forced runtime pm).
228
		return;
Line 272... Line 229...
272
	 * Unfortunately the ACPI subsystem doesn't yet give us a way to
229
	}
273
	 * differentiate this, hence figure it out with this hack.
230
 
274
	 */
231
	if (!dev_priv->csr.dmc_payload) {
275
	if (I915_READ(CSR_PROGRAM(0)))
232
		DRM_ERROR("Tried to program CSR with empty payload\n");
Line 276... Line 233...
276
		return;
233
		return;
277
 
-
 
278
	mutex_lock(&dev_priv->csr_lock);
234
	}
Line 279... Line 235...
279
	fw_size = dev_priv->csr.dmc_fw_size;
235
 
-
 
236
	fw_size = dev_priv->csr.dmc_fw_size;
280
	for (i = 0; i < fw_size; i++)
237
	for (i = 0; i < fw_size; i++)
281
		I915_WRITE(CSR_PROGRAM(i), payload[i]);
-
 
282
 
238
		I915_WRITE(CSR_PROGRAM(i), payload[i]);
283
	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
239
 
284
		I915_WRITE(dev_priv->csr.mmioaddr[i],
240
	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
285
			dev_priv->csr.mmiodata[i]);
241
		I915_WRITE(dev_priv->csr.mmioaddr[i],
286
	}
242
			dev_priv->csr.mmiodata[i]);
287
 
243
	}
288
	dev_priv->csr.state = FW_LOADED;
244
 
289
	mutex_unlock(&dev_priv->csr_lock);
245
	dev_priv->csr.dc_state = 0;
290
}
246
}
291
 
247
 
292
static void finish_csr_load(const struct firmware *fw, void *context)
-
 
Line 293... Line 248...
293
{
248
static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
294
	struct drm_i915_private *dev_priv = context;
-
 
295
	struct drm_device *dev = dev_priv->dev;
249
			      const struct firmware *fw)
296
	struct intel_css_header *css_header;
-
 
Line 297... Line 250...
297
	struct intel_package_header *package_header;
250
{
298
	struct intel_dmc_header *dmc_header;
251
	struct drm_device *dev = dev_priv->dev;
299
	struct intel_csr *csr = &dev_priv->csr;
252
	struct intel_css_header *css_header;
300
	char stepping = intel_get_stepping(dev);
253
	struct intel_package_header *package_header;
Line -... Line 254...
-
 
254
	struct intel_dmc_header *dmc_header;
-
 
255
	struct intel_csr *csr = &dev_priv->csr;
-
 
256
	const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
301
	char substepping = intel_get_substepping(dev);
257
	char stepping, substepping;
302
	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
258
	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
303
	uint32_t i;
259
	uint32_t i;
304
	uint32_t *dmc_payload;
260
	uint32_t *dmc_payload;
305
	bool fw_loaded = false;
261
 
306
 
262
	if (!fw)
307
	if (!fw) {
263
		return NULL;
-
 
264
 
-
 
265
	if (!stepping_info) {
-
 
266
		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
-
 
267
		return NULL;
-
 
268
	}
-
 
269
 
-
 
270
	stepping = stepping_info->stepping;
-
 
271
	substepping = stepping_info->substepping;
-
 
272
 
-
 
273
	/* Extract CSS Header information*/
-
 
274
	css_header = (struct intel_css_header *)fw->data;
-
 
275
	if (sizeof(struct intel_css_header) !=
-
 
276
		(css_header->header_len * 4)) {
308
		i915_firmware_load_error_print(csr->fw_path, 0);
277
		DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
-
 
278
			(css_header->header_len * 4));
309
		goto out;
279
		return NULL;
Line 310... Line 280...
310
	}
280
	}
311
 
281
 
312
	if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
282
	csr->version = css_header->version;
313
		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
283
 
314
		goto out;
284
	if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
315
	}
285
		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
316
 
286
			 " please upgrade to v%u.%u or later"
317
	/* Extract CSS Header information*/
287
			 " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
318
	css_header = (struct intel_css_header *)fw->data;
288
			 CSR_VERSION_MAJOR(csr->version),
319
	if (sizeof(struct intel_css_header) !=
289
			 CSR_VERSION_MINOR(csr->version),
Line 320... Line 290...
320
		(css_header->header_len * 4)) {
290
			 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
321
		DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
291
			 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
Line 349... Line 319...
349
			package_header->fw_info[i].substepping == '*')
319
			package_header->fw_info[i].substepping == '*')
350
			dmc_offset = package_header->fw_info[i].offset;
320
			dmc_offset = package_header->fw_info[i].offset;
351
	}
321
	}
352
	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
322
	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
353
		DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
323
		DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
354
		goto out;
324
		return NULL;
355
	}
325
	}
356
	readcount += dmc_offset;
326
	readcount += dmc_offset;
Line 357... Line 327...
357
 
327
 
358
	/* Extract dmc_header information. */
328
	/* Extract dmc_header information. */
359
	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
329
	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
360
	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
330
	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
361
		DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
331
		DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
362
				(dmc_header->header_len));
332
				(dmc_header->header_len));
363
		goto out;
333
		return NULL;
364
	}
334
	}
Line 365... Line 335...
365
	readcount += sizeof(struct intel_dmc_header);
335
	readcount += sizeof(struct intel_dmc_header);
366
 
336
 
367
	/* Cache the dmc header info. */
337
	/* Cache the dmc header info. */
368
	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
338
	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
369
		DRM_ERROR("Firmware has wrong mmio count %u\n",
339
		DRM_ERROR("Firmware has wrong mmio count %u\n",
370
						dmc_header->mmio_count);
340
						dmc_header->mmio_count);
371
		goto out;
341
		return NULL;
372
	}
342
	}
373
	csr->mmio_count = dmc_header->mmio_count;
343
	csr->mmio_count = dmc_header->mmio_count;
374
	for (i = 0; i < dmc_header->mmio_count; i++) {
344
	for (i = 0; i < dmc_header->mmio_count; i++) {
375
		if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
345
		if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
376
			dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
346
			dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
377
			DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
347
			DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
378
						dmc_header->mmioaddr[i]);
348
						dmc_header->mmioaddr[i]);
379
			goto out;
349
			return NULL;
380
		}
350
		}
381
		csr->mmioaddr[i] = dmc_header->mmioaddr[i];
351
		csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
Line 382... Line 352...
382
		csr->mmiodata[i] = dmc_header->mmiodata[i];
352
		csr->mmiodata[i] = dmc_header->mmiodata[i];
383
	}
353
	}
384
 
354
 
385
	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
355
	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
386
	nbytes = dmc_header->fw_size * 4;
356
	nbytes = dmc_header->fw_size * 4;
387
	if (nbytes > CSR_MAX_FW_SIZE) {
357
	if (nbytes > CSR_MAX_FW_SIZE) {
388
		DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
358
		DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
Line 389... Line 359...
389
		goto out;
359
		return NULL;
390
	}
360
	}
391
	csr->dmc_fw_size = dmc_header->fw_size;
361
	csr->dmc_fw_size = dmc_header->fw_size;
392
 
362
 
393
	csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL);
363
	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
Line 394... Line -...
394
	if (!csr->dmc_payload) {
-
 
395
		DRM_ERROR("Memory allocation failed for dmc payload\n");
364
	if (!dmc_payload) {
Line -... Line 365...
-
 
365
		DRM_ERROR("Memory allocation failed for dmc payload\n");
-
 
366
		return NULL;
-
 
367
	}
-
 
368
 
-
 
369
	memcpy(dmc_payload, &fw->data[readcount], nbytes);
-
 
370
 
-
 
371
	return dmc_payload;
-
 
372
}
-
 
373
 
-
 
374
static void csr_load_work_fn(struct drm_i915_private *dev_priv)
-
 
375
{
-
 
376
	struct intel_csr *csr;
-
 
377
	const struct firmware *fw;
-
 
378
	int ret;
-
 
379
 
-
 
380
	csr = &dev_priv->csr;
-
 
381
 
-
 
382
	ret = request_firmware(&fw, dev_priv->csr.fw_path,
-
 
383
			       &dev_priv->dev->pdev->dev);
-
 
384
	if (!fw)
396
		goto out;
385
		goto out;
397
	}
386
 
398
 
-
 
Line 399... Line -...
399
	dmc_payload = csr->dmc_payload;
-
 
400
	memcpy(dmc_payload, &fw->data[readcount], nbytes);
387
	dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
401
 
388
	if (!dev_priv->csr.dmc_payload)
402
	/* load csr program during system boot, as needed for DC states */
389
		goto out;
-
 
390
 
-
 
391
	/* load csr program during system boot, as needed for DC states */
-
 
392
	intel_csr_load_program(dev_priv);
-
 
393
 
-
 
394
out:
403
	intel_csr_load_program(dev);
395
	if (dev_priv->csr.dmc_payload) {
404
	fw_loaded = true;
396
		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
-
 
397
 
Line 405... Line 398...
405
 
398
		DRM_INFO("Finished loading %s (v%u.%u)\n",
406
	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
399
			 dev_priv->csr.fw_path,
Line 407... Line 400...
407
out:
400
			 CSR_VERSION_MAJOR(csr->version),
408
	if (fw_loaded)
401
			 CSR_VERSION_MINOR(csr->version));
409
		intel_runtime_pm_put(dev_priv);
402
	} else {
410
	else
403
		DRM_ERROR("Failed to load DMC firmware, disabling rpm\n");
411
		intel_csr_load_status_set(dev_priv, FW_FAILED);
404
    }
412
 
405
 
413
	release_firmware(fw);
406
	release_firmware(fw);
414
}
407
}
415
 
408
 
416
/**
-
 
417
 * intel_csr_ucode_init() - initialize the firmware loading.
409
/**
418
 * @dev: drm device.
-
 
Line 419... Line 410...
419
 *
410
 * intel_csr_ucode_init() - initialize the firmware loading.
420
 * This function is called at the time of loading the display driver to read
411
 * @dev_priv: i915 drm device.
Line 421... Line 412...
421
 * firmware from a .bin file and copied into a internal memory.
412
 *
422
 */
413
 * This function is called at the time of loading the display driver to read
423
void intel_csr_ucode_init(struct drm_device *dev)
414
 * firmware from a .bin file and copied into a internal memory.
424
{
415
 */
425
	struct drm_i915_private *dev_priv = dev->dev_private;
416
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
426
	struct intel_csr *csr = &dev_priv->csr;
417
{
427
	int ret;
-
 
428
 
418
	struct intel_csr *csr = &dev_priv->csr;
429
	if (!HAS_CSR(dev))
419
 
430
		return;
420
	if (!HAS_CSR(dev_priv))
431
 
421
		return;
Line 432... Line 422...
432
	if (IS_SKYLAKE(dev))
422
 
433
		csr->fw_path = I915_CSR_SKL;
423
	if (IS_SKYLAKE(dev_priv))
434
	else if (IS_BROXTON(dev_priv))
424
		csr->fw_path = I915_CSR_SKL;
435
		csr->fw_path = I915_CSR_BXT;
425
	else if (IS_BROXTON(dev_priv))
436
	else {
426
		csr->fw_path = I915_CSR_BXT;
Line 437... Line -...
437
		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
-
 
438
		intel_csr_load_status_set(dev_priv, FW_FAILED);
-
 
439
		return;
-
 
440
	}
427
	else {
441
#if 0
-
 
442
	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
-
 
443
 
-
 
444
	/*
-
 
445
	 * Obtain a runtime pm reference, until CSR is loaded,
-
 
446
	 * to avoid entering runtime-suspend.
-
 
447
	 */
428
		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
Line 448... Line 429...
448
	intel_runtime_pm_get(dev_priv);
429
		return;
449
 
430
	}
450
	/* CSR supported for platform, load firmware */
431
 
451
	ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
432
	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
452
				&dev_priv->dev->pdev->dev,
433
 
453
				GFP_KERNEL, dev_priv,
434
	/*
454
				finish_csr_load);
435
	 * Obtain a runtime pm reference, until CSR is loaded,
455
	if (ret) {
436
	 * to avoid entering runtime-suspend.
456
		i915_firmware_load_error_print(csr->fw_path, ret);
437
	 */
457
		intel_csr_load_status_set(dev_priv, FW_FAILED);
-
 
458
	}
-
 
459
#endif
438
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
460
}
439
 
Line 461... Line -...
461
 
-
 
462
/**
-
 
463
 * intel_csr_ucode_fini() - unload the CSR firmware.
-
 
Line 464... Line -...
464
 * @dev: drm device.
-
 
465
 *
-
 
466
 * Firmmware unloading includes freeing the internal momory and reset the
-
 
467
 * firmware loading status.
440
	csr_load_work_fn(dev_priv);
468
 */
-
 
469
void intel_csr_ucode_fini(struct drm_device *dev)
-
 
470
{
-
 
471
	struct drm_i915_private *dev_priv = dev->dev_private;
-
 
472
 
441
}