WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_crt.c


/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt 
 */
 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include "intel_drv.h"
#include 
#include "i915_drv.h"
 
/* Here's the desired hotplug mode */
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
			   ADPA_CRT_HOTPLUG_VOLREF_325MV |		\
			   ADPA_CRT_HOTPLUG_ENABLE)
 
struct intel_crt {
	struct intel_encoder base;
	/* DPMS state is stored in the connector, which we need in the
	 * encoder's enable/disable callbacks */
	struct intel_connector *connector;
	bool force_hotplug_required;
	u32 adpa_reg;
};
 
static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
{
	return container_of(encoder, struct intel_crt, base);
}
 
static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
{
	return intel_encoder_to_crt(intel_attached_encoder(connector));
}
 
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	enum intel_display_power_domain power_domain;
	u32 tmp;
 
	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
		return false;
 
	tmp = I915_READ(crt->adpa_reg);
 
	if (!(tmp & ADPA_DAC_ENABLE))
		return false;
 
	if (HAS_PCH_CPT(dev))
		*pipe = PORT_TO_PIPE_CPT(tmp);
	else
		*pipe = PORT_TO_PIPE(tmp);
 
	return true;
}
 
static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	u32 tmp, flags = 0;
 
	tmp = I915_READ(crt->adpa_reg);
 
	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
 
	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;
 
	return flags;
}
 
static void intel_crt_get_config(struct intel_encoder *encoder,
				 struct intel_crtc_state *pipe_config)
{
	struct drm_device *dev = encoder->base.dev;
	int dotclock;
 
	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 
	dotclock = pipe_config->port_clock;
 
	if (HAS_PCH_SPLIT(dev))
		ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
 
static void hsw_crt_get_config(struct intel_encoder *encoder,
			       struct intel_crtc_state *pipe_config)
{
	intel_ddi_get_config(encoder, pipe_config);
 
	pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
					      DRM_MODE_FLAG_NHSYNC |
					      DRM_MODE_FLAG_PVSYNC |
					      DRM_MODE_FLAG_NVSYNC);
	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 
 
 
 
 
 
 
 
 
 
 
 
}
 
/* Note: The caller is required to filter out dpms modes not supported by the
 * platform. */
static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
	u32 adpa;
 
	if (INTEL_INFO(dev)->gen >= 5)
		adpa = ADPA_HOTPLUG_BITS;
	else
		adpa = 0;
 
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 
	/* For CPT allow 3 pipe config, for others just use A or B */
	if (HAS_PCH_LPT(dev))
		; /* Those bits don't exist here */
	else if (HAS_PCH_CPT(dev))
		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
	else if (crtc->pipe == 0)
		adpa |= ADPA_PIPE_A_SELECT;
	else
		adpa |= ADPA_PIPE_B_SELECT;
 
	if (!HAS_PCH_SPLIT(dev))
		I915_WRITE(BCLRPAT(crtc->pipe), 0);
 
	switch (mode) {
	case DRM_MODE_DPMS_ON:
		adpa |= ADPA_DAC_ENABLE;
		break;
	case DRM_MODE_DPMS_STANDBY:
		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_SUSPEND:
		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_OFF:
		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	}
 
	I915_WRITE(crt->adpa_reg, adpa);
}
 
static void intel_disable_crt(struct intel_encoder *encoder)
{
	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
}
 
 
static void pch_disable_crt(struct intel_encoder *encoder)
 
 
{
}
 
static void pch_post_disable_crt(struct intel_encoder *encoder)
 
 
 
{
	intel_disable_crt(encoder);
}
 
static void intel_enable_crt(struct intel_encoder *encoder)
{
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
 
	intel_crt_set_dpms(encoder, crt->connector->base.dpms);
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
{
	struct drm_device *dev = connector->dev;
 
	int max_clock = 0;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;
 
	if (mode->clock < 25000)
		return MODE_CLOCK_LOW;
 
	if (IS_GEN2(dev))
		max_clock = 350000;
	else
		max_clock = 400000;
	if (mode->clock > max_clock)
		return MODE_CLOCK_HIGH;
 
	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
	if (HAS_PCH_LPT(dev) &&
	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
		return MODE_CLOCK_HIGH;
 
	return MODE_OK;
}
 
static bool intel_crt_compute_config(struct intel_encoder *encoder,
				     struct intel_crtc_state *pipe_config)
{
	struct drm_device *dev = encoder->base.dev;
 
	if (HAS_PCH_SPLIT(dev))
		pipe_config->has_pch_encoder = true;
 
	/* LPT FDI RX only supports 8bpc. */
	if (HAS_PCH_LPT(dev))
		pipe_config->pipe_bpp = 24;
 
	/* FDI must always be 2.7 GHz */
	if (HAS_DDI(dev)) {
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
		pipe_config->port_clock = 135000 * 2;
 
		pipe_config->dpll_hw_state.wrpll = 0;
		pipe_config->dpll_hw_state.spll =
			SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
	}
 
	return true;
}
 
static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa;
	bool ret;
 
	/* The first time through, trigger an explicit detection cycle */
	if (crt->force_hotplug_required) {
		bool turn_off_dac = HAS_PCH_SPLIT(dev);
		u32 save_adpa;
 
		crt->force_hotplug_required = 0;
 
		save_adpa = adpa = I915_READ(crt->adpa_reg);
		DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 
		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
		if (turn_off_dac)
			adpa &= ~ADPA_DAC_ENABLE;
 
		I915_WRITE(crt->adpa_reg, adpa);
 
		if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 
		if (turn_off_dac) {
			I915_WRITE(crt->adpa_reg, save_adpa);
			POSTING_READ(crt->adpa_reg);
		}
	}
 
	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(crt->adpa_reg);
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
		ret = true;
	else
		ret = false;
	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 
	return ret;
}
 
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa;
	bool ret;
	u32 save_adpa;
 
	save_adpa = adpa = I915_READ(crt->adpa_reg);
	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 
	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 
	I915_WRITE(crt->adpa_reg, adpa);
 
	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
		     1000)) {
		DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
		I915_WRITE(crt->adpa_reg, save_adpa);
	}
 
	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(crt->adpa_reg);
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
		ret = true;
	else
		ret = false;
 
	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 
	return ret;
}
 
/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 *
 * Not for i915G/i915GM
 *
 * \return true if CRT is connected.
 * \return false if CRT is disconnected.
 */
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 stat;
	bool ret = false;
	int i, tries = 0;
 
	if (HAS_PCH_SPLIT(dev))
		return intel_ironlake_crt_detect_hotplug(connector);
 
	if (IS_VALLEYVIEW(dev))
		return valleyview_crt_detect_hotplug(connector);
 
	/*
	 * On 4 series desktop, CRT detect sequence need to be done twice
	 * to get a reliable result.
	 */
 
	if (IS_G4X(dev) && !IS_GM45(dev))
		tries = 2;
	else
		tries = 1;
 
 
 
	for (i = 0; i < tries ; i++) {
		/* turn on the FORCE_DETECT */
		i915_hotplug_interrupt_update(dev_priv,
					      CRT_HOTPLUG_FORCE_DETECT,
					      CRT_HOTPLUG_FORCE_DETECT);
		/* wait for FORCE_DETECT to go off */
		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
			      CRT_HOTPLUG_FORCE_DETECT) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
	}
 
	stat = I915_READ(PORT_HOTPLUG_STAT);
	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
		ret = true;
 
	/* clear the interrupt we just generated, if any */
	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 
 
	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 
	return ret;
}
 
static struct edid *intel_crt_get_edid(struct drm_connector *connector,
				struct i2c_adapter *i2c)
{
	struct edid *edid;
 
	edid = drm_get_edid(connector, i2c);
 
	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
		DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
		intel_gmbus_force_bit(i2c, true);
		edid = drm_get_edid(connector, i2c);
		intel_gmbus_force_bit(i2c, false);
	}
 
	return edid;
}
 
/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
static int intel_crt_ddc_get_modes(struct drm_connector *connector,
				struct i2c_adapter *adapter)
{
	struct edid *edid;
	int ret;
 
	edid = intel_crt_get_edid(connector, adapter);
	if (!edid)
		return 0;
 
	ret = intel_connector_update_modes(connector, edid);
	kfree(edid);
 
	return ret;
}
 
static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
	struct edid *edid;
	struct i2c_adapter *i2c;
 
	BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 
	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
	edid = intel_crt_get_edid(connector, i2c);
 
	if (edid) {
		bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 
		/*
		 * This may be a DVI-I connector with a shared DDC
		 * link between analog and digital outputs, so we
		 * have to check the EDID input spec of the attached device.
		 */
		if (!is_digital) {
			DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
			return true;
		}
 
		DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
	} else {
		DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
	}
 
	kfree(edid);
 
	return false;
}
 
static enum drm_connector_status
intel_crt_load_detect(struct intel_crt *crt)
{
	struct drm_device *dev = crt->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
	uint32_t save_bclrpat;
	uint32_t save_vtotal;
	uint32_t vtotal, vactive;
	uint32_t vsample;
	uint32_t vblank, vblank_start, vblank_end;
	uint32_t dsl;
	uint32_t bclrpat_reg;
	uint32_t vtotal_reg;
	uint32_t vblank_reg;
	uint32_t vsync_reg;
	uint32_t pipeconf_reg;
	uint32_t pipe_dsl_reg;
	uint8_t	st00;
	enum drm_connector_status status;
 
	DRM_DEBUG_KMS("starting load-detect on CRT\n");
 
	bclrpat_reg = BCLRPAT(pipe);
	vtotal_reg = VTOTAL(pipe);
	vblank_reg = VBLANK(pipe);
	vsync_reg = VSYNC(pipe);
	pipeconf_reg = PIPECONF(pipe);
	pipe_dsl_reg = PIPEDSL(pipe);
 
	save_bclrpat = I915_READ(bclrpat_reg);
	save_vtotal = I915_READ(vtotal_reg);
	vblank = I915_READ(vblank_reg);
 
	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	vactive = (save_vtotal & 0x7ff) + 1;
 
	vblank_start = (vblank & 0xfff) + 1;
	vblank_end = ((vblank >> 16) & 0xfff) + 1;
 
	/* Set the border color to purple. */
	I915_WRITE(bclrpat_reg, 0x500050);
 
	if (!IS_GEN2(dev)) {
		uint32_t pipeconf = I915_READ(pipeconf_reg);
		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
		POSTING_READ(pipeconf_reg);
		/* Wait for next Vblank to substitue
		 * border color for Color info */
		intel_wait_for_vblank(dev, pipe);
		st00 = I915_READ8(VGA_MSR_WRITE);
		status = ((st00 & (1 << 4)) != 0) ?
			connector_status_connected :
			connector_status_disconnected;
 
		I915_WRITE(pipeconf_reg, pipeconf);
	} else {
		bool restore_vblank = false;
		int count, detect;
 
		/*
		* If there isn't any border, add some.
		* Yes, this will flicker
		*/
		if (vblank_start <= vactive && vblank_end >= vtotal) {
			uint32_t vsync = I915_READ(vsync_reg);
			uint32_t vsync_start = (vsync & 0xffff) + 1;
 
			vblank_start = vsync_start;
			I915_WRITE(vblank_reg,
				   (vblank_start - 1) |
				   ((vblank_end - 1) << 16));
			restore_vblank = true;
		}
		/* sample in the vertical border, selecting the larger one */
		if (vblank_start - vactive >= vtotal - vblank_end)
			vsample = (vblank_start + vactive) >> 1;
		else
			vsample = (vtotal + vblank_end) >> 1;
 
		/*
		 * Wait for the border to be displayed
		 */
		while (I915_READ(pipe_dsl_reg) >= vactive)
			;
		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
			;
		/*
		 * Watch ST00 for an entire scanline
		 */
		detect = 0;
		count = 0;
		do {
			count++;
			/* Read the ST00 VGA status register */
			st00 = I915_READ8(VGA_MSR_WRITE);
			if (st00 & (1 << 4))
				detect++;
		} while ((I915_READ(pipe_dsl_reg) == dsl));
 
		/* restore vblank if necessary */
		if (restore_vblank)
			I915_WRITE(vblank_reg, vblank);
		/*
		 * If more than 3/4 of the scanline detected a monitor,
		 * then it is assumed to be present. This works even on i830,
		 * where there isn't any way to force the border color across
		 * the screen
		 */
		status = detect * 4 > count * 3 ?
			 connector_status_connected :
			 connector_status_disconnected;
	}
 
	/* Restore previous settings */
	I915_WRITE(bclrpat_reg, save_bclrpat);
 
	return status;
}
 
static enum drm_connector_status
intel_crt_detect(struct drm_connector *connector, bool force)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct intel_encoder *intel_encoder = &crt->base;
	enum intel_display_power_domain power_domain;
	enum drm_connector_status status;
	struct intel_load_detect_pipe tmp;
	struct drm_modeset_acquire_ctx ctx;
 
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
		      connector->base.id, connector->name,
		      force);
 
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
 
	if (I915_HAS_HOTPLUG(dev)) {
		/* We can not rely on the HPD pin always being correctly wired
		 * up, for example many KVM do not pass it through, and so
		 * only trust an assertion that the monitor is connected.
		 */
		if (intel_crt_detect_hotplug(connector)) {
			DRM_DEBUG_KMS("CRT detected via hotplug\n");
			status = connector_status_connected;
			goto out;
		} else
			DRM_DEBUG_KMS("CRT not detected via hotplug\n");
	}
 
	if (intel_crt_detect_ddc(connector)) {
		status = connector_status_connected;
		goto out;
	}
 
	/* Load detection is broken on HPD capable machines. Whoever wants a
	 * broken monitor (without edid) to work behind a broken kvm (that fails
	 * to have the right resistors for HP detection) needs to fix this up.
	 * For now just bail out. */
	if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
		status = connector_status_disconnected;
		goto out;
	}
 
	if (!force) {
		status = connector->status;
		goto out;
	}
 
	drm_modeset_acquire_init(&ctx, 0);
 
	/* for pre-945g platforms use load detect */
	if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
		if (intel_crt_detect_ddc(connector))
			status = connector_status_connected;
		else if (INTEL_INFO(dev)->gen < 4)
			status = intel_crt_load_detect(crt);
		else
			status = connector_status_unknown;
		intel_release_load_detect_pipe(connector, &tmp, &ctx);
	} else
		status = connector_status_unknown;
 
	drm_modeset_drop_locks(&ctx);
	drm_modeset_acquire_fini(&ctx);
 
out:
	intel_display_power_put(dev_priv, power_domain);
	return status;
}
 
static void intel_crt_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	kfree(connector);
}
 
static int intel_crt_get_modes(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct intel_encoder *intel_encoder = &crt->base;
	enum intel_display_power_domain power_domain;
	int ret;
	struct i2c_adapter *i2c;
 
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
 
	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
	ret = intel_crt_ddc_get_modes(connector, i2c);
	if (ret || !IS_G4X(dev))
		goto out;
 
	/* Try to probe digital port for output in DVI-I -> VGA mode. */
	i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
	ret = intel_crt_ddc_get_modes(connector, i2c);
 
out:
	intel_display_power_put(dev_priv, power_domain);
 
	return ret;
}
 
static int intel_crt_set_property(struct drm_connector *connector,
				  struct drm_property *property,
				  uint64_t value)
{
	return 0;
}
 
static void intel_crt_reset(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_attached_crt(connector);
 
	if (INTEL_INFO(dev)->gen >= 5) {
		u32 adpa;
 
		adpa = I915_READ(crt->adpa_reg);
		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
		adpa |= ADPA_HOTPLUG_BITS;
		I915_WRITE(crt->adpa_reg, adpa);
		POSTING_READ(crt->adpa_reg);
 
		DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
		crt->force_hotplug_required = 1;
	}
 
}
 
/*
 * Routines for controlling stuff on the analog port
 */
 
static const struct drm_connector_funcs intel_crt_connector_funcs = {
	.reset = intel_crt_reset,
	.dpms = drm_atomic_helper_connector_dpms,
	.detect = intel_crt_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = intel_crt_destroy,
	.set_property = intel_crt_set_property,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	.atomic_get_property = intel_connector_atomic_get_property,
};
 
static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	.mode_valid = intel_crt_mode_valid,
	.get_modes = intel_crt_get_modes,
	.best_encoder = intel_best_encoder,
};
 
static const struct drm_encoder_funcs intel_crt_enc_funcs = {
	.destroy = intel_encoder_destroy,
};
 
static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
{
	DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
	return 1;
}
 
static const struct dmi_system_id intel_no_crt[] = {
	{
		.callback = intel_no_crt_dmi_callback,
		.ident = "ACER ZGB",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
		},
	},
	{
		.callback = intel_no_crt_dmi_callback,
		.ident = "DELL XPS 8700",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
			DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
		},
	},
	{ }
};
 
void intel_crt_init(struct drm_device *dev)
{
	struct drm_connector *connector;
	struct intel_crt *crt;
	struct intel_connector *intel_connector;
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	/* Skip machines without VGA that falsely report hotplug events */
	if (dmi_check_system(intel_no_crt))
		return;
 
	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
	if (!crt)
		return;
 
	intel_connector = intel_connector_alloc();
	if (!intel_connector) {
		kfree(crt);
		return;
	}
 
	connector = &intel_connector->base;
	crt->connector = intel_connector;
	drm_connector_init(dev, &intel_connector->base,
			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 
	drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
			 DRM_MODE_ENCODER_DAC);
 
	intel_connector_attach_encoder(intel_connector, &crt->base);
 
	crt->base.type = INTEL_OUTPUT_ANALOG;
	crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
	if (IS_I830(dev))
		crt->base.crtc_mask = (1 << 0);
	else
		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
	if (IS_GEN2(dev))
		connector->interlace_allowed = 0;
	else
		connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;
 
	if (HAS_PCH_SPLIT(dev))
		crt->adpa_reg = PCH_ADPA;
	else if (IS_VALLEYVIEW(dev))
		crt->adpa_reg = VLV_ADPA;
	else
		crt->adpa_reg = ADPA;
 
	crt->base.compute_config = intel_crt_compute_config;
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {
		crt->base.disable = pch_disable_crt;
		crt->base.post_disable = pch_post_disable_crt;
	} else {
		crt->base.disable = intel_disable_crt;
	}
	crt->base.enable = intel_enable_crt;
	if (I915_HAS_HOTPLUG(dev))
		crt->base.hpd_pin = HPD_CRT;
	if (HAS_DDI(dev)) {
		crt->base.get_config = hsw_crt_get_config;
		crt->base.get_hw_state = intel_ddi_get_hw_state;
 
 
	} else {
		crt->base.get_config = intel_crt_get_config;
		crt->base.get_hw_state = intel_crt_get_hw_state;
	}
	intel_connector->get_hw_state = intel_connector_get_hw_state;
	intel_connector->unregister = intel_connector_unregister;
 
	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 
	drm_connector_register(connector);
 
	if (!I915_HAS_HOTPLUG(dev))
		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 
	/*
	 * Configure the automatic hotplug detection stuff
	 */
	crt->force_hotplug_required = 0;
 
	/*
	 * TODO: find a proper way to discover whether we need to set the the
	 * polarity and link reversal bits or not, instead of relying on the
	 * BIOS.
	 */
	if (HAS_PCH_LPT(dev)) {
		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
				 FDI_RX_LINK_REVERSAL_OVERRIDE;
 
		dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
	}
 
	intel_crt_reset(connector);
}

Rev 5354	Rev 6084
1	/*	1	/*
2	* Copyright © 2006-2007 Intel Corporation	2	* Copyright © 2006-2007 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.	21	* DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	*/	25	*/
26		26
27	#include	27	#include
28	#include	28	#include
29	#include	29	#include
30	#include	30	#include
-		31	#include
31	#include	32	#include
32	#include	33	#include
33	#include	34	#include
34	#include "intel_drv.h"	35	#include "intel_drv.h"
35	#include	36	#include
36	#include "i915_drv.h"	37	#include "i915_drv.h"
37		38
38	/* Here's the desired hotplug mode */	39	/* Here's the desired hotplug mode */
39	#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 \| \	40	#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 \| \
40	ADPA_CRT_HOTPLUG_WARMUP_10MS \| \	41	ADPA_CRT_HOTPLUG_WARMUP_10MS \| \
41	ADPA_CRT_HOTPLUG_SAMPLE_4S \| \	42	ADPA_CRT_HOTPLUG_SAMPLE_4S \| \
42	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| \	43	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| \
43	ADPA_CRT_HOTPLUG_VOLREF_325MV \| \	44	ADPA_CRT_HOTPLUG_VOLREF_325MV \| \
44	ADPA_CRT_HOTPLUG_ENABLE)	45	ADPA_CRT_HOTPLUG_ENABLE)
45		46
46	struct intel_crt {	47	struct intel_crt {
47	struct intel_encoder base;	48	struct intel_encoder base;
48	/* DPMS state is stored in the connector, which we need in the	49	/* DPMS state is stored in the connector, which we need in the
49	* encoder's enable/disable callbacks */	50	* encoder's enable/disable callbacks */
50	struct intel_connector *connector;	51	struct intel_connector *connector;
51	bool force_hotplug_required;	52	bool force_hotplug_required;
52	u32 adpa_reg;	53	u32 adpa_reg;
53	};	54	};
54		55
55	static struct intel_crt intel_encoder_to_crt(struct intel_encoder encoder)	56	static struct intel_crt intel_encoder_to_crt(struct intel_encoder encoder)
56	{	57	{
57	return container_of(encoder, struct intel_crt, base);	58	return container_of(encoder, struct intel_crt, base);
58	}	59	}
59		60
60	static struct intel_crt intel_attached_crt(struct drm_connector connector)	61	static struct intel_crt intel_attached_crt(struct drm_connector connector)
61	{	62	{
62	return intel_encoder_to_crt(intel_attached_encoder(connector));	63	return intel_encoder_to_crt(intel_attached_encoder(connector));
63	}	64	}
64		65
65	static bool intel_crt_get_hw_state(struct intel_encoder *encoder,	66	static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
66	enum pipe *pipe)	67	enum pipe *pipe)
67	{	68	{
68	struct drm_device *dev = encoder->base.dev;	69	struct drm_device *dev = encoder->base.dev;
69	struct drm_i915_private *dev_priv = dev->dev_private;	70	struct drm_i915_private *dev_priv = dev->dev_private;
70	struct intel_crt *crt = intel_encoder_to_crt(encoder);	71	struct intel_crt *crt = intel_encoder_to_crt(encoder);
71	enum intel_display_power_domain power_domain;	72	enum intel_display_power_domain power_domain;
72	u32 tmp;	73	u32 tmp;
73		74
74	power_domain = intel_display_port_power_domain(encoder);	75	power_domain = intel_display_port_power_domain(encoder);
75	if (!intel_display_power_is_enabled(dev_priv, power_domain))	76	if (!intel_display_power_is_enabled(dev_priv, power_domain))
76	return false;	77	return false;
77		78
78	tmp = I915_READ(crt->adpa_reg);	79	tmp = I915_READ(crt->adpa_reg);
79		80
80	if (!(tmp & ADPA_DAC_ENABLE))	81	if (!(tmp & ADPA_DAC_ENABLE))
81	return false;	82	return false;
82		83
83	if (HAS_PCH_CPT(dev))	84	if (HAS_PCH_CPT(dev))
84	*pipe = PORT_TO_PIPE_CPT(tmp);	85	*pipe = PORT_TO_PIPE_CPT(tmp);
85	else	86	else
86	*pipe = PORT_TO_PIPE(tmp);	87	*pipe = PORT_TO_PIPE(tmp);
87		88
88	return true;	89	return true;
89	}	90	}
90		91
91	static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)	92	static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
92	{	93	{
93	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;	94	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
94	struct intel_crt *crt = intel_encoder_to_crt(encoder);	95	struct intel_crt *crt = intel_encoder_to_crt(encoder);
95	u32 tmp, flags = 0;	96	u32 tmp, flags = 0;
96		97
97	tmp = I915_READ(crt->adpa_reg);	98	tmp = I915_READ(crt->adpa_reg);
98		99
99	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)	100	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
100	flags \|= DRM_MODE_FLAG_PHSYNC;	101	flags \|= DRM_MODE_FLAG_PHSYNC;
101	else	102	else
102	flags \|= DRM_MODE_FLAG_NHSYNC;	103	flags \|= DRM_MODE_FLAG_NHSYNC;
103		104
104	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)	105	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
105	flags \|= DRM_MODE_FLAG_PVSYNC;	106	flags \|= DRM_MODE_FLAG_PVSYNC;
106	else	107	else
107	flags \|= DRM_MODE_FLAG_NVSYNC;	108	flags \|= DRM_MODE_FLAG_NVSYNC;
108		109
109	return flags;	110	return flags;
110	}	111	}
111		112
112	static void intel_crt_get_config(struct intel_encoder *encoder,	113	static void intel_crt_get_config(struct intel_encoder *encoder,
113	struct intel_crtc_config *pipe_config)	114	struct intel_crtc_state *pipe_config)
114	{	115	{
115	struct drm_device *dev = encoder->base.dev;	116	struct drm_device *dev = encoder->base.dev;
116	int dotclock;	117	int dotclock;
117		118
118	pipe_config->adjusted_mode.flags \|= intel_crt_get_flags(encoder);	119	pipe_config->base.adjusted_mode.flags \|= intel_crt_get_flags(encoder);
119		120
120	dotclock = pipe_config->port_clock;	121	dotclock = pipe_config->port_clock;
121		122
122	if (HAS_PCH_SPLIT(dev))	123	if (HAS_PCH_SPLIT(dev))
123	ironlake_check_encoder_dotclock(pipe_config, dotclock);	124	ironlake_check_encoder_dotclock(pipe_config, dotclock);
124		125
125	pipe_config->adjusted_mode.crtc_clock = dotclock;	126	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
126	}	127	}
127		128
128	static void hsw_crt_get_config(struct intel_encoder *encoder,	129	static void hsw_crt_get_config(struct intel_encoder *encoder,
129	struct intel_crtc_config *pipe_config)	130	struct intel_crtc_state *pipe_config)
130	{	131	{
131	intel_ddi_get_config(encoder, pipe_config);	132	intel_ddi_get_config(encoder, pipe_config);
132		133
133	pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC \|	134	pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC \|
134	DRM_MODE_FLAG_NHSYNC \|	135	DRM_MODE_FLAG_NHSYNC \|
135	DRM_MODE_FLAG_PVSYNC \|	136	DRM_MODE_FLAG_PVSYNC \|
136	DRM_MODE_FLAG_NVSYNC);	137	DRM_MODE_FLAG_NVSYNC);
137	pipe_config->adjusted_mode.flags \|= intel_crt_get_flags(encoder);	138	pipe_config->base.adjusted_mode.flags \|= intel_crt_get_flags(encoder);
138	}	-
139		-
140	static void hsw_crt_pre_enable(struct intel_encoder *encoder)	-
141	{	-
142	struct drm_device *dev = encoder->base.dev;	-
143	struct drm_i915_private *dev_priv = dev->dev_private;	-
144		-
145	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");	-
146	I915_WRITE(SPLL_CTL,	-
147	SPLL_PLL_ENABLE \| SPLL_PLL_FREQ_1350MHz \| SPLL_PLL_SSC);	-
148	POSTING_READ(SPLL_CTL);	-
149	udelay(20);	-
150	}	139	}
151		140
152	/* Note: The caller is required to filter out dpms modes not supported by the	141	/* Note: The caller is required to filter out dpms modes not supported by the
153	* platform. */	142	* platform. */
154	static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)	143	static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
155	{	144	{
156	struct drm_device *dev = encoder->base.dev;	145	struct drm_device *dev = encoder->base.dev;
157	struct drm_i915_private *dev_priv = dev->dev_private;	146	struct drm_i915_private *dev_priv = dev->dev_private;
158	struct intel_crt *crt = intel_encoder_to_crt(encoder);	147	struct intel_crt *crt = intel_encoder_to_crt(encoder);
159	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);	148	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
160	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;	149	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
161	u32 adpa;	150	u32 adpa;
162		151
163	if (INTEL_INFO(dev)->gen >= 5)	152	if (INTEL_INFO(dev)->gen >= 5)
164	adpa = ADPA_HOTPLUG_BITS;	153	adpa = ADPA_HOTPLUG_BITS;
165	else	154	else
166	adpa = 0;	155	adpa = 0;
167		156
168	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)	157	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
169	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;	158	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;
170	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)	159	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
171	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;	160	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;
172		161
173	/* For CPT allow 3 pipe config, for others just use A or B */	162	/* For CPT allow 3 pipe config, for others just use A or B */
174	if (HAS_PCH_LPT(dev))	163	if (HAS_PCH_LPT(dev))
175	; /* Those bits don't exist here */	164	; /* Those bits don't exist here */
176	else if (HAS_PCH_CPT(dev))	165	else if (HAS_PCH_CPT(dev))
177	adpa \|= PORT_TRANS_SEL_CPT(crtc->pipe);	166	adpa \|= PORT_TRANS_SEL_CPT(crtc->pipe);
178	else if (crtc->pipe == 0)	167	else if (crtc->pipe == 0)
179	adpa \|= ADPA_PIPE_A_SELECT;	168	adpa \|= ADPA_PIPE_A_SELECT;
180	else	169	else
181	adpa \|= ADPA_PIPE_B_SELECT;	170	adpa \|= ADPA_PIPE_B_SELECT;
182		171
183	if (!HAS_PCH_SPLIT(dev))	172	if (!HAS_PCH_SPLIT(dev))
184	I915_WRITE(BCLRPAT(crtc->pipe), 0);	173	I915_WRITE(BCLRPAT(crtc->pipe), 0);
185		174
186	switch (mode) {	175	switch (mode) {
187	case DRM_MODE_DPMS_ON:	176	case DRM_MODE_DPMS_ON:
188	adpa \|= ADPA_DAC_ENABLE;	177	adpa \|= ADPA_DAC_ENABLE;
189	break;	178	break;
190	case DRM_MODE_DPMS_STANDBY:	179	case DRM_MODE_DPMS_STANDBY:
191	adpa \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;	180	adpa \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;
192	break;	181	break;
193	case DRM_MODE_DPMS_SUSPEND:	182	case DRM_MODE_DPMS_SUSPEND:
194	adpa \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;	183	adpa \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;
195	break;	184	break;
196	case DRM_MODE_DPMS_OFF:	185	case DRM_MODE_DPMS_OFF:
197	adpa \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;	186	adpa \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;
198	break;	187	break;
199	}	188	}
200		189
201	I915_WRITE(crt->adpa_reg, adpa);	190	I915_WRITE(crt->adpa_reg, adpa);
202	}	191	}
203		192
204	static void intel_disable_crt(struct intel_encoder *encoder)	193	static void intel_disable_crt(struct intel_encoder *encoder)
205	{	194	{
206	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);	195	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
207	}	196	}
208		-
209		197
210	static void hsw_crt_post_disable(struct intel_encoder *encoder)	198	static void pch_disable_crt(struct intel_encoder *encoder)
211	{	-
212	struct drm_device *dev = encoder->base.dev;	-
213	struct drm_i915_private *dev_priv = dev->dev_private;	199	{
214	uint32_t val;	200	}
-		201
215		202	static void pch_post_disable_crt(struct intel_encoder *encoder)
216	DRM_DEBUG_KMS("Disabling SPLL\n");	-
217	val = I915_READ(SPLL_CTL);	-
218	WARN_ON(!(val & SPLL_PLL_ENABLE));	-
219	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);	203	{
220	POSTING_READ(SPLL_CTL);	204	intel_disable_crt(encoder);
221	}	205	}
222		206
223	static void intel_enable_crt(struct intel_encoder *encoder)	207	static void intel_enable_crt(struct intel_encoder *encoder)
224	{	208	{
225	struct intel_crt *crt = intel_encoder_to_crt(encoder);	209	struct intel_crt *crt = intel_encoder_to_crt(encoder);
226		210
227	intel_crt_set_dpms(encoder, crt->connector->base.dpms);	211	intel_crt_set_dpms(encoder, crt->connector->base.dpms);
228	}	212	}
229		-
230	/* Special dpms function to support cloning between dvo/sdvo/crt. */	-
231	static void intel_crt_dpms(struct drm_connector *connector, int mode)	-
232	{	-
233	struct drm_device *dev = connector->dev;	-
234	struct intel_encoder *encoder = intel_attached_encoder(connector);	-
235	struct drm_crtc *crtc;	-
236	int old_dpms;	-
237		-
238	/* PCH platforms and VLV only support on/off. */	-
239	if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)	-
240	mode = DRM_MODE_DPMS_OFF;	-
241		-
242	if (mode == connector->dpms)	-
243	return;	-
244		-
245	old_dpms = connector->dpms;	-
246	connector->dpms = mode;	-
247		-
248	/* Only need to change hw state when actually enabled */	-
249	crtc = encoder->base.crtc;	-
250	if (!crtc) {	-
251	encoder->connectors_active = false;	-
252	return;	-
253	}	-
254		-
255	/* We need the pipe to run for anything but OFF. */	-
256	if (mode == DRM_MODE_DPMS_OFF)	-
257	encoder->connectors_active = false;	-
258	else	-
259	encoder->connectors_active = true;	-
260		-
261	/* We call connector dpms manually below in case pipe dpms doesn't	-
262	* change due to cloning. */	-
263	if (mode < old_dpms) {	-
264	/* From off to on, enable the pipe first. */	-
265	intel_crtc_update_dpms(crtc);	-
266		-
267	intel_crt_set_dpms(encoder, mode);	-
268	} else {	-
269	intel_crt_set_dpms(encoder, mode);	-
270		-
271	intel_crtc_update_dpms(crtc);	-
272	}	-
273		-
274	intel_modeset_check_state(connector->dev);	-
275	}	-
276		213
277	static enum drm_mode_status	214	static enum drm_mode_status
278	intel_crt_mode_valid(struct drm_connector *connector,	215	intel_crt_mode_valid(struct drm_connector *connector,
279	struct drm_display_mode *mode)	216	struct drm_display_mode *mode)
280	{	217	{
281	struct drm_device *dev = connector->dev;	218	struct drm_device *dev = connector->dev;
282		219
283	int max_clock = 0;	220	int max_clock = 0;
284	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)	221	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
285	return MODE_NO_DBLESCAN;	222	return MODE_NO_DBLESCAN;
286		223
287	if (mode->clock < 25000)	224	if (mode->clock < 25000)
288	return MODE_CLOCK_LOW;	225	return MODE_CLOCK_LOW;
289		226
290	if (IS_GEN2(dev))	227	if (IS_GEN2(dev))
291	max_clock = 350000;	228	max_clock = 350000;
292	else	229	else
293	max_clock = 400000;	230	max_clock = 400000;
294	if (mode->clock > max_clock)	231	if (mode->clock > max_clock)
295	return MODE_CLOCK_HIGH;	232	return MODE_CLOCK_HIGH;
296		233
297	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */	234	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
298	if (HAS_PCH_LPT(dev) &&	235	if (HAS_PCH_LPT(dev) &&
299	(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))	236	(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
300	return MODE_CLOCK_HIGH;	237	return MODE_CLOCK_HIGH;
301		238
302	return MODE_OK;	239	return MODE_OK;
303	}	240	}
304		241
305	static bool intel_crt_compute_config(struct intel_encoder *encoder,	242	static bool intel_crt_compute_config(struct intel_encoder *encoder,
306	struct intel_crtc_config *pipe_config)	243	struct intel_crtc_state *pipe_config)
307	{	244	{
308	struct drm_device *dev = encoder->base.dev;	245	struct drm_device *dev = encoder->base.dev;
309		246
310	if (HAS_PCH_SPLIT(dev))	247	if (HAS_PCH_SPLIT(dev))
311	pipe_config->has_pch_encoder = true;	248	pipe_config->has_pch_encoder = true;
312		249
313	/* LPT FDI RX only supports 8bpc. */	250	/* LPT FDI RX only supports 8bpc. */
314	if (HAS_PCH_LPT(dev))	251	if (HAS_PCH_LPT(dev))
315	pipe_config->pipe_bpp = 24;	252	pipe_config->pipe_bpp = 24;
316		253
317	/* FDI must always be 2.7 GHz */	254	/* FDI must always be 2.7 GHz */
318	if (HAS_DDI(dev)) {	255	if (HAS_DDI(dev)) {
319	pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;	256	pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
320	pipe_config->port_clock = 135000 * 2;	257	pipe_config->port_clock = 135000 * 2;
-		258
-		259	pipe_config->dpll_hw_state.wrpll = 0;
-		260	pipe_config->dpll_hw_state.spll =
-		261	SPLL_PLL_ENABLE \| SPLL_PLL_FREQ_1350MHz \| SPLL_PLL_SSC;
321	}	262	}
322		263
323	return true;	264	return true;
324	}	265	}
325		266
326	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)	267	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
327	{	268	{
328	struct drm_device *dev = connector->dev;	269	struct drm_device *dev = connector->dev;
329	struct intel_crt *crt = intel_attached_crt(connector);	270	struct intel_crt *crt = intel_attached_crt(connector);
330	struct drm_i915_private *dev_priv = dev->dev_private;	271	struct drm_i915_private *dev_priv = dev->dev_private;
331	u32 adpa;	272	u32 adpa;
332	bool ret;	273	bool ret;
333		274
334	/* The first time through, trigger an explicit detection cycle */	275	/* The first time through, trigger an explicit detection cycle */
335	if (crt->force_hotplug_required) {	276	if (crt->force_hotplug_required) {
336	bool turn_off_dac = HAS_PCH_SPLIT(dev);	277	bool turn_off_dac = HAS_PCH_SPLIT(dev);
337	u32 save_adpa;	278	u32 save_adpa;
338		279
339	crt->force_hotplug_required = 0;	280	crt->force_hotplug_required = 0;
340		281
341	save_adpa = adpa = I915_READ(crt->adpa_reg);	282	save_adpa = adpa = I915_READ(crt->adpa_reg);
342	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);	283	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
343		284
344	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;	285	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
345	if (turn_off_dac)	286	if (turn_off_dac)
346	adpa &= ~ADPA_DAC_ENABLE;	287	adpa &= ~ADPA_DAC_ENABLE;
347		288
348	I915_WRITE(crt->adpa_reg, adpa);	289	I915_WRITE(crt->adpa_reg, adpa);
349		290
350	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,	291	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
351	1000))	292	1000))
352	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");	293	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
353		294
354	if (turn_off_dac) {	295	if (turn_off_dac) {
355	I915_WRITE(crt->adpa_reg, save_adpa);	296	I915_WRITE(crt->adpa_reg, save_adpa);
356	POSTING_READ(crt->adpa_reg);	297	POSTING_READ(crt->adpa_reg);
357	}	298	}
358	}	299	}
359		300
360	/* Check the status to see if both blue and green are on now */	301	/* Check the status to see if both blue and green are on now */
361	adpa = I915_READ(crt->adpa_reg);	302	adpa = I915_READ(crt->adpa_reg);
362	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)	303	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
363	ret = true;	304	ret = true;
364	else	305	else
365	ret = false;	306	ret = false;
366	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);	307	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
367		308
368	return ret;	309	return ret;
369	}	310	}
370		311
371	static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)	312	static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
372	{	313	{
373	struct drm_device *dev = connector->dev;	314	struct drm_device *dev = connector->dev;
374	struct intel_crt *crt = intel_attached_crt(connector);	315	struct intel_crt *crt = intel_attached_crt(connector);
375	struct drm_i915_private *dev_priv = dev->dev_private;	316	struct drm_i915_private *dev_priv = dev->dev_private;
376	u32 adpa;	317	u32 adpa;
377	bool ret;	318	bool ret;
378	u32 save_adpa;	319	u32 save_adpa;
379		320
380	save_adpa = adpa = I915_READ(crt->adpa_reg);	321	save_adpa = adpa = I915_READ(crt->adpa_reg);
381	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);	322	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
382		323
383	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;	324	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
384		325
385	I915_WRITE(crt->adpa_reg, adpa);	326	I915_WRITE(crt->adpa_reg, adpa);
386		327
387	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,	328	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
388	1000)) {	329	1000)) {
389	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");	330	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
390	I915_WRITE(crt->adpa_reg, save_adpa);	331	I915_WRITE(crt->adpa_reg, save_adpa);
391	}	332	}
392		333
393	/* Check the status to see if both blue and green are on now */	334	/* Check the status to see if both blue and green are on now */
394	adpa = I915_READ(crt->adpa_reg);	335	adpa = I915_READ(crt->adpa_reg);
395	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)	336	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
396	ret = true;	337	ret = true;
397	else	338	else
398	ret = false;	339	ret = false;
399		340
400	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);	341	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
401		342
402	return ret;	343	return ret;
403	}	344	}
404		345
405	/**	346	/**
406	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.	347	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
407	*	348	*
408	* Not for i915G/i915GM	349	* Not for i915G/i915GM
409	*	350	*
410	* \return true if CRT is connected.	351	* \return true if CRT is connected.
411	* \return false if CRT is disconnected.	352	* \return false if CRT is disconnected.
412	*/	353	*/
413	static bool intel_crt_detect_hotplug(struct drm_connector *connector)	354	static bool intel_crt_detect_hotplug(struct drm_connector *connector)
414	{	355	{
415	struct drm_device *dev = connector->dev;	356	struct drm_device *dev = connector->dev;
416	struct drm_i915_private *dev_priv = dev->dev_private;	357	struct drm_i915_private *dev_priv = dev->dev_private;
417	u32 hotplug_en, orig, stat;	358	u32 stat;
418	bool ret = false;	359	bool ret = false;
419	int i, tries = 0;	360	int i, tries = 0;
420		361
421	if (HAS_PCH_SPLIT(dev))	362	if (HAS_PCH_SPLIT(dev))
422	return intel_ironlake_crt_detect_hotplug(connector);	363	return intel_ironlake_crt_detect_hotplug(connector);
423		364
424	if (IS_VALLEYVIEW(dev))	365	if (IS_VALLEYVIEW(dev))
425	return valleyview_crt_detect_hotplug(connector);	366	return valleyview_crt_detect_hotplug(connector);
426		367
427	/*	368	/*
428	* On 4 series desktop, CRT detect sequence need to be done twice	369	* On 4 series desktop, CRT detect sequence need to be done twice
429	* to get a reliable result.	370	* to get a reliable result.
430	*/	371	*/
431		372
432	if (IS_G4X(dev) && !IS_GM45(dev))	373	if (IS_G4X(dev) && !IS_GM45(dev))
433	tries = 2;	374	tries = 2;
434	else	375	else
435	tries = 1;	376	tries = 1;
436	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);	-
437	hotplug_en \|= CRT_HOTPLUG_FORCE_DETECT;	-
438		377
439	for (i = 0; i < tries ; i++) {	378	for (i = 0; i < tries ; i++) {
440	/* turn on the FORCE_DETECT */	379	/* turn on the FORCE_DETECT */
-		380	i915_hotplug_interrupt_update(dev_priv,
-		381	CRT_HOTPLUG_FORCE_DETECT,
441	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);	382	CRT_HOTPLUG_FORCE_DETECT);
442	/* wait for FORCE_DETECT to go off */	383	/* wait for FORCE_DETECT to go off */
443	if (wait_for((I915_READ(PORT_HOTPLUG_EN) &	384	if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
444	CRT_HOTPLUG_FORCE_DETECT) == 0,	385	CRT_HOTPLUG_FORCE_DETECT) == 0,
445	1000))	386	1000))
446	DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");	387	DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
447	}	388	}
448		389
449	stat = I915_READ(PORT_HOTPLUG_STAT);	390	stat = I915_READ(PORT_HOTPLUG_STAT);
450	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)	391	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
451	ret = true;	392	ret = true;
452		393
453	/* clear the interrupt we just generated, if any */	394	/* clear the interrupt we just generated, if any */
454	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);	395	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
455		-
456	/* and put the bits back */	396
457	I915_WRITE(PORT_HOTPLUG_EN, orig);	397	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
458		398
459	return ret;	399	return ret;
460	}	400	}
461		401
462	static struct edid intel_crt_get_edid(struct drm_connector connector,	402	static struct edid intel_crt_get_edid(struct drm_connector connector,
463	struct i2c_adapter *i2c)	403	struct i2c_adapter *i2c)
464	{	404	{
465	struct edid *edid;	405	struct edid *edid;
466		406
467	edid = drm_get_edid(connector, i2c);	407	edid = drm_get_edid(connector, i2c);
468		408
469	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {	409	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
470	DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");	410	DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
471	intel_gmbus_force_bit(i2c, true);	411	intel_gmbus_force_bit(i2c, true);
472	edid = drm_get_edid(connector, i2c);	412	edid = drm_get_edid(connector, i2c);
473	intel_gmbus_force_bit(i2c, false);	413	intel_gmbus_force_bit(i2c, false);
474	}	414	}
475		415
476	return edid;	416	return edid;
477	}	417	}
478		418
479	/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */	419	/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
480	static int intel_crt_ddc_get_modes(struct drm_connector *connector,	420	static int intel_crt_ddc_get_modes(struct drm_connector *connector,
481	struct i2c_adapter *adapter)	421	struct i2c_adapter *adapter)
482	{	422	{
483	struct edid *edid;	423	struct edid *edid;
484	int ret;	424	int ret;
485		425
486	edid = intel_crt_get_edid(connector, adapter);	426	edid = intel_crt_get_edid(connector, adapter);
487	if (!edid)	427	if (!edid)
488	return 0;	428	return 0;
489		429
490	ret = intel_connector_update_modes(connector, edid);	430	ret = intel_connector_update_modes(connector, edid);
491	kfree(edid);	431	kfree(edid);
492		432

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_crt.c – Rev 5354 → 6084