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Rev 6937 Rev 7144
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 * Authors:
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 * Authors:
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 *    Eric Anholt
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 *    Eric Anholt
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 *
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 *
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 */
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 */
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#ifndef _I830_BIOS_H_
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#ifndef _INTEL_BIOS_H_
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#define _INTEL_BIOS_H_
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- 
 
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/**
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 * struct vbt_header - VBT Header structure
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 33 
 * @signature:		VBT signature, always starts with "$VBT"
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 * @version:		Version of this structure
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 * @header_size:	Size of this structure
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 * @vbt_size:		Size of VBT (VBT Header, BDB Header and data blocks)
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 * @vbt_checksum:	Checksum
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 * @reserved0:		Reserved
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 * @bdb_offset:		Offset of &struct bdb_header from beginning of VBT
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#define _I830_BIOS_H_
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 * @aim_offset:		Offsets of add-in data blocks from beginning of VBT
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 */
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struct vbt_header {
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struct vbt_header {
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	u8 signature[20];		/**< Always starts with 'VBT$' */
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	u8 signature[20];
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	u16 version;			/**< decimal */
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	u16 version;
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	u16 header_size;		/**< in bytes */
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	u16 header_size;
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	u16 vbt_size;			/**< in bytes */
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	u16 vbt_size;
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	u8 vbt_checksum;
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	u8 vbt_checksum;
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	u8 reserved0;
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	u8 reserved0;
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	u32 bdb_offset;			/**< from beginning of VBT */
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	u32 bdb_offset;
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	u32 aim_offset[4];
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} __packed;
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/**
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 * struct bdb_header - BDB Header structure
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 * @signature:		BDB signature "BIOS_DATA_BLOCK"
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 * @version:		Version of the data block definitions
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	u32 aim_offset[4];		/**< from beginning of VBT */
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 * @header_size:	Size of this structure
40 
} __packed;
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 * @bdb_size:		Size of BDB (BDB Header and data blocks)
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 */
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struct bdb_header {
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struct bdb_header {
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	u8 signature[16];		/**< Always 'BIOS_DATA_BLOCK' */
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	u8 signature[16];
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	u16 version;			/**< decimal */
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	u16 version;
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	u16 header_size;		/**< in bytes */
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	u16 header_size;
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	u16 bdb_size;			/**< in bytes */
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	u16 bdb_size;
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} __packed;
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} __packed;
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	u8 data[0];
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	u8 data[0];
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} __packed;
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} __packed;
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/* MIPI Sequnece Block definitions */
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/* MIPI Sequnece Block definitions */
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enum mipi_seq {
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enum mipi_seq {
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	MIPI_SEQ_UNDEFINED = 0,
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	MIPI_SEQ_END = 0,
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	MIPI_SEQ_ASSERT_RESET,
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	MIPI_SEQ_ASSERT_RESET,
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	MIPI_SEQ_INIT_OTP,
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	MIPI_SEQ_INIT_OTP,
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	MIPI_SEQ_DISPLAY_ON,
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	MIPI_SEQ_DISPLAY_ON,
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	MIPI_SEQ_DISPLAY_OFF,
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	MIPI_SEQ_DISPLAY_OFF,
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	MIPI_SEQ_DEASSERT_RESET,
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	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
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	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
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	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
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	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
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	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
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	MIPI_SEQ_DEASSERT_RESET,
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	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
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	MIPI_SEQ_MAX
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	MIPI_SEQ_MAX
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};
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};
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enum mipi_seq_element {
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enum mipi_seq_element {
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	MIPI_SEQ_ELEM_UNDEFINED = 0,
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	MIPI_SEQ_ELEM_END = 0,
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	MIPI_SEQ_ELEM_SEND_PKT,
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	MIPI_SEQ_ELEM_SEND_PKT,
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	MIPI_SEQ_ELEM_DELAY,
951 
	MIPI_SEQ_ELEM_DELAY,
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	MIPI_SEQ_ELEM_GPIO,
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	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
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	MIPI_SEQ_ELEM_GPIO,
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	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
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	MIPI_SEQ_ELEM_STATUS,
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	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
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	MIPI_SEQ_ELEM_MAX
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	MIPI_SEQ_ELEM_MAX
955 
};
 981 
};
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	MIPI_GPIO_PWR_DOWN_R,
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	MIPI_GPIO_PWR_DOWN_R,
964 
	MIPI_GPIO_STDBY_RST_N,
 990 
	MIPI_GPIO_STDBY_RST_N,
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	MIPI_GPIO_MAX
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	MIPI_GPIO_MAX
966 
};
 992 
};
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