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1 | /* |
1 | /* |
2 | * Copyright © 2006 Intel Corporation |
2 | * Copyright © 2006 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
21 | * SOFTWARE. |
21 | * SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #ifndef _I830_BIOS_H_ |
28 | #ifndef _INTEL_BIOS_H_ |
- | 29 | #define _INTEL_BIOS_H_ |
|
- | 30 | ||
- | 31 | /** |
|
- | 32 | * struct vbt_header - VBT Header structure |
|
- | 33 | * @signature: VBT signature, always starts with "$VBT" |
|
- | 34 | * @version: Version of this structure |
|
- | 35 | * @header_size: Size of this structure |
|
- | 36 | * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) |
|
- | 37 | * @vbt_checksum: Checksum |
|
- | 38 | * @reserved0: Reserved |
|
- | 39 | * @bdb_offset: Offset of &struct bdb_header from beginning of VBT |
|
29 | #define _I830_BIOS_H_ |
40 | * @aim_offset: Offsets of add-in data blocks from beginning of VBT |
30 | 41 | */ |
|
31 | struct vbt_header { |
42 | struct vbt_header { |
32 | u8 signature[20]; /**< Always starts with 'VBT$' */ |
43 | u8 signature[20]; |
33 | u16 version; /**< decimal */ |
44 | u16 version; |
34 | u16 header_size; /**< in bytes */ |
45 | u16 header_size; |
35 | u16 vbt_size; /**< in bytes */ |
46 | u16 vbt_size; |
36 | u8 vbt_checksum; |
47 | u8 vbt_checksum; |
37 | u8 reserved0; |
48 | u8 reserved0; |
38 | u32 bdb_offset; /**< from beginning of VBT */ |
49 | u32 bdb_offset; |
- | 50 | u32 aim_offset[4]; |
|
- | 51 | } __packed; |
|
- | 52 | ||
- | 53 | /** |
|
- | 54 | * struct bdb_header - BDB Header structure |
|
- | 55 | * @signature: BDB signature "BIOS_DATA_BLOCK" |
|
- | 56 | * @version: Version of the data block definitions |
|
39 | u32 aim_offset[4]; /**< from beginning of VBT */ |
57 | * @header_size: Size of this structure |
40 | } __packed; |
58 | * @bdb_size: Size of BDB (BDB Header and data blocks) |
41 | 59 | */ |
|
42 | struct bdb_header { |
60 | struct bdb_header { |
43 | u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ |
61 | u8 signature[16]; |
44 | u16 version; /**< decimal */ |
62 | u16 version; |
45 | u16 header_size; /**< in bytes */ |
63 | u16 header_size; |
46 | u16 bdb_size; /**< in bytes */ |
64 | u16 bdb_size; |
47 | } __packed; |
65 | } __packed; |
48 | 66 | ||
49 | /* strictly speaking, this is a "skip" block, but it has interesting info */ |
67 | /* strictly speaking, this is a "skip" block, but it has interesting info */ |
50 | struct vbios_data { |
68 | struct vbios_data { |
51 | u8 type; /* 0 == desktop, 1 == mobile */ |
69 | u8 type; /* 0 == desktop, 1 == mobile */ |
52 | u8 relstage; |
70 | u8 relstage; |
53 | u8 chipset; |
71 | u8 chipset; |
54 | u8 lvds_present:1; |
72 | u8 lvds_present:1; |
55 | u8 tv_present:1; |
73 | u8 tv_present:1; |
56 | u8 rsvd2:6; /* finish byte */ |
74 | u8 rsvd2:6; /* finish byte */ |
57 | u8 rsvd3[4]; |
75 | u8 rsvd3[4]; |
58 | u8 signon[155]; |
76 | u8 signon[155]; |
59 | u8 copyright[61]; |
77 | u8 copyright[61]; |
60 | u16 code_segment; |
78 | u16 code_segment; |
61 | u8 dos_boot_mode; |
79 | u8 dos_boot_mode; |
62 | u8 bandwidth_percent; |
80 | u8 bandwidth_percent; |
63 | u8 rsvd4; /* popup memory size */ |
81 | u8 rsvd4; /* popup memory size */ |
64 | u8 resize_pci_bios; |
82 | u8 resize_pci_bios; |
65 | u8 rsvd5; /* is crt already on ddc2 */ |
83 | u8 rsvd5; /* is crt already on ddc2 */ |
66 | } __packed; |
84 | } __packed; |
67 | 85 | ||
68 | /* |
86 | /* |
69 | * There are several types of BIOS data blocks (BDBs), each block has |
87 | * There are several types of BIOS data blocks (BDBs), each block has |
70 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
88 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
71 | * Known types are listed below. |
89 | * Known types are listed below. |
72 | */ |
90 | */ |
73 | #define BDB_GENERAL_FEATURES 1 |
91 | #define BDB_GENERAL_FEATURES 1 |
74 | #define BDB_GENERAL_DEFINITIONS 2 |
92 | #define BDB_GENERAL_DEFINITIONS 2 |
75 | #define BDB_OLD_TOGGLE_LIST 3 |
93 | #define BDB_OLD_TOGGLE_LIST 3 |
76 | #define BDB_MODE_SUPPORT_LIST 4 |
94 | #define BDB_MODE_SUPPORT_LIST 4 |
77 | #define BDB_GENERIC_MODE_TABLE 5 |
95 | #define BDB_GENERIC_MODE_TABLE 5 |
78 | #define BDB_EXT_MMIO_REGS 6 |
96 | #define BDB_EXT_MMIO_REGS 6 |
79 | #define BDB_SWF_IO 7 |
97 | #define BDB_SWF_IO 7 |
80 | #define BDB_SWF_MMIO 8 |
98 | #define BDB_SWF_MMIO 8 |
81 | #define BDB_PSR 9 |
99 | #define BDB_PSR 9 |
82 | #define BDB_MODE_REMOVAL_TABLE 10 |
100 | #define BDB_MODE_REMOVAL_TABLE 10 |
83 | #define BDB_CHILD_DEVICE_TABLE 11 |
101 | #define BDB_CHILD_DEVICE_TABLE 11 |
84 | #define BDB_DRIVER_FEATURES 12 |
102 | #define BDB_DRIVER_FEATURES 12 |
85 | #define BDB_DRIVER_PERSISTENCE 13 |
103 | #define BDB_DRIVER_PERSISTENCE 13 |
86 | #define BDB_EXT_TABLE_PTRS 14 |
104 | #define BDB_EXT_TABLE_PTRS 14 |
87 | #define BDB_DOT_CLOCK_OVERRIDE 15 |
105 | #define BDB_DOT_CLOCK_OVERRIDE 15 |
88 | #define BDB_DISPLAY_SELECT 16 |
106 | #define BDB_DISPLAY_SELECT 16 |
89 | /* 17 rsvd */ |
107 | /* 17 rsvd */ |
90 | #define BDB_DRIVER_ROTATION 18 |
108 | #define BDB_DRIVER_ROTATION 18 |
91 | #define BDB_DISPLAY_REMOVE 19 |
109 | #define BDB_DISPLAY_REMOVE 19 |
92 | #define BDB_OEM_CUSTOM 20 |
110 | #define BDB_OEM_CUSTOM 20 |
93 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ |
111 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ |
94 | #define BDB_SDVO_LVDS_OPTIONS 22 |
112 | #define BDB_SDVO_LVDS_OPTIONS 22 |
95 | #define BDB_SDVO_PANEL_DTDS 23 |
113 | #define BDB_SDVO_PANEL_DTDS 23 |
96 | #define BDB_SDVO_LVDS_PNP_IDS 24 |
114 | #define BDB_SDVO_LVDS_PNP_IDS 24 |
97 | #define BDB_SDVO_LVDS_POWER_SEQ 25 |
115 | #define BDB_SDVO_LVDS_POWER_SEQ 25 |
98 | #define BDB_TV_OPTIONS 26 |
116 | #define BDB_TV_OPTIONS 26 |
99 | #define BDB_EDP 27 |
117 | #define BDB_EDP 27 |
100 | #define BDB_LVDS_OPTIONS 40 |
118 | #define BDB_LVDS_OPTIONS 40 |
101 | #define BDB_LVDS_LFP_DATA_PTRS 41 |
119 | #define BDB_LVDS_LFP_DATA_PTRS 41 |
102 | #define BDB_LVDS_LFP_DATA 42 |
120 | #define BDB_LVDS_LFP_DATA 42 |
103 | #define BDB_LVDS_BACKLIGHT 43 |
121 | #define BDB_LVDS_BACKLIGHT 43 |
104 | #define BDB_LVDS_POWER 44 |
122 | #define BDB_LVDS_POWER 44 |
105 | #define BDB_MIPI_CONFIG 52 |
123 | #define BDB_MIPI_CONFIG 52 |
106 | #define BDB_MIPI_SEQUENCE 53 |
124 | #define BDB_MIPI_SEQUENCE 53 |
107 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
125 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
108 | 126 | ||
109 | struct bdb_general_features { |
127 | struct bdb_general_features { |
110 | /* bits 1 */ |
128 | /* bits 1 */ |
111 | u8 panel_fitting:2; |
129 | u8 panel_fitting:2; |
112 | u8 flexaim:1; |
130 | u8 flexaim:1; |
113 | u8 msg_enable:1; |
131 | u8 msg_enable:1; |
114 | u8 clear_screen:3; |
132 | u8 clear_screen:3; |
115 | u8 color_flip:1; |
133 | u8 color_flip:1; |
116 | 134 | ||
117 | /* bits 2 */ |
135 | /* bits 2 */ |
118 | u8 download_ext_vbt:1; |
136 | u8 download_ext_vbt:1; |
119 | u8 enable_ssc:1; |
137 | u8 enable_ssc:1; |
120 | u8 ssc_freq:1; |
138 | u8 ssc_freq:1; |
121 | u8 enable_lfp_on_override:1; |
139 | u8 enable_lfp_on_override:1; |
122 | u8 disable_ssc_ddt:1; |
140 | u8 disable_ssc_ddt:1; |
123 | u8 rsvd7:1; |
141 | u8 rsvd7:1; |
124 | u8 display_clock_mode:1; |
142 | u8 display_clock_mode:1; |
125 | u8 rsvd8:1; /* finish byte */ |
143 | u8 rsvd8:1; /* finish byte */ |
126 | 144 | ||
127 | /* bits 3 */ |
145 | /* bits 3 */ |
128 | u8 disable_smooth_vision:1; |
146 | u8 disable_smooth_vision:1; |
129 | u8 single_dvi:1; |
147 | u8 single_dvi:1; |
130 | u8 rsvd9:1; |
148 | u8 rsvd9:1; |
131 | u8 fdi_rx_polarity_inverted:1; |
149 | u8 fdi_rx_polarity_inverted:1; |
132 | u8 rsvd10:4; /* finish byte */ |
150 | u8 rsvd10:4; /* finish byte */ |
133 | 151 | ||
134 | /* bits 4 */ |
152 | /* bits 4 */ |
135 | u8 legacy_monitor_detect; |
153 | u8 legacy_monitor_detect; |
136 | 154 | ||
137 | /* bits 5 */ |
155 | /* bits 5 */ |
138 | u8 int_crt_support:1; |
156 | u8 int_crt_support:1; |
139 | u8 int_tv_support:1; |
157 | u8 int_tv_support:1; |
140 | u8 int_efp_support:1; |
158 | u8 int_efp_support:1; |
141 | u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ |
159 | u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ |
142 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
160 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
143 | u8 rsvd11:3; /* finish byte */ |
161 | u8 rsvd11:3; /* finish byte */ |
144 | } __packed; |
162 | } __packed; |
145 | 163 | ||
146 | /* pre-915 */ |
164 | /* pre-915 */ |
147 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
165 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
148 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
166 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
149 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
167 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
150 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
168 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
151 | 169 | ||
152 | /* Pre 915 */ |
170 | /* Pre 915 */ |
153 | #define DEVICE_TYPE_NONE 0x00 |
171 | #define DEVICE_TYPE_NONE 0x00 |
154 | #define DEVICE_TYPE_CRT 0x01 |
172 | #define DEVICE_TYPE_CRT 0x01 |
155 | #define DEVICE_TYPE_TV 0x09 |
173 | #define DEVICE_TYPE_TV 0x09 |
156 | #define DEVICE_TYPE_EFP 0x12 |
174 | #define DEVICE_TYPE_EFP 0x12 |
157 | #define DEVICE_TYPE_LFP 0x22 |
175 | #define DEVICE_TYPE_LFP 0x22 |
158 | /* On 915+ */ |
176 | /* On 915+ */ |
159 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
177 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
160 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
178 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
161 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
179 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
162 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
180 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
163 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
181 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
164 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
182 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
165 | #define DEVICE_TYPE_TV_SCART 0x0209 |
183 | #define DEVICE_TYPE_TV_SCART 0x0209 |
166 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
184 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
167 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
185 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
168 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
186 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
169 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
187 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
170 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
188 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
171 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
189 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
172 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
190 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
173 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
191 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
174 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
192 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
175 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
193 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
176 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
194 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
177 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
195 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
178 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
196 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
179 | 197 | ||
180 | #define DEVICE_CFG_NONE 0x00 |
198 | #define DEVICE_CFG_NONE 0x00 |
181 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
199 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
182 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
200 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
183 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
201 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
184 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
202 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
185 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
203 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
186 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
204 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
187 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
205 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
188 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
206 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
189 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
207 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
190 | 208 | ||
191 | #define DEVICE_WIRE_NONE 0x00 |
209 | #define DEVICE_WIRE_NONE 0x00 |
192 | #define DEVICE_WIRE_DVOB 0x01 |
210 | #define DEVICE_WIRE_DVOB 0x01 |
193 | #define DEVICE_WIRE_DVOC 0x02 |
211 | #define DEVICE_WIRE_DVOC 0x02 |
194 | #define DEVICE_WIRE_DVOBC 0x03 |
212 | #define DEVICE_WIRE_DVOBC 0x03 |
195 | #define DEVICE_WIRE_DVOBB 0x05 |
213 | #define DEVICE_WIRE_DVOBB 0x05 |
196 | #define DEVICE_WIRE_DVOCC 0x06 |
214 | #define DEVICE_WIRE_DVOCC 0x06 |
197 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
215 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
198 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
216 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
199 | 217 | ||
200 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
218 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
201 | #define DEVICE_PORT_DVOB 0x01 |
219 | #define DEVICE_PORT_DVOB 0x01 |
202 | #define DEVICE_PORT_DVOC 0x02 |
220 | #define DEVICE_PORT_DVOC 0x02 |
203 | 221 | ||
204 | /* |
222 | /* |
205 | * We used to keep this struct but without any version control. We should avoid |
223 | * We used to keep this struct but without any version control. We should avoid |
206 | * using it in the future, but it should be safe to keep using it in the old |
224 | * using it in the future, but it should be safe to keep using it in the old |
207 | * code. Do not change; we rely on its size. |
225 | * code. Do not change; we rely on its size. |
208 | */ |
226 | */ |
209 | struct old_child_dev_config { |
227 | struct old_child_dev_config { |
210 | u16 handle; |
228 | u16 handle; |
211 | u16 device_type; |
229 | u16 device_type; |
212 | u8 device_id[10]; /* ascii string */ |
230 | u8 device_id[10]; /* ascii string */ |
213 | u16 addin_offset; |
231 | u16 addin_offset; |
214 | u8 dvo_port; /* See Device_PORT_* above */ |
232 | u8 dvo_port; /* See Device_PORT_* above */ |
215 | u8 i2c_pin; |
233 | u8 i2c_pin; |
216 | u8 slave_addr; |
234 | u8 slave_addr; |
217 | u8 ddc_pin; |
235 | u8 ddc_pin; |
218 | u16 edid_ptr; |
236 | u16 edid_ptr; |
219 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
237 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
220 | u8 dvo2_port; |
238 | u8 dvo2_port; |
221 | u8 i2c2_pin; |
239 | u8 i2c2_pin; |
222 | u8 slave2_addr; |
240 | u8 slave2_addr; |
223 | u8 ddc2_pin; |
241 | u8 ddc2_pin; |
224 | u8 capabilities; |
242 | u8 capabilities; |
225 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ |
243 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ |
226 | u8 dvo2_wiring; |
244 | u8 dvo2_wiring; |
227 | u16 extended_type; |
245 | u16 extended_type; |
228 | u8 dvo_function; |
246 | u8 dvo_function; |
229 | } __packed; |
247 | } __packed; |
230 | 248 | ||
231 | /* This one contains field offsets that are known to be common for all BDB |
249 | /* This one contains field offsets that are known to be common for all BDB |
232 | * versions. Notice that the meaning of the contents contents may still change, |
250 | * versions. Notice that the meaning of the contents contents may still change, |
233 | * but at least the offsets are consistent. */ |
251 | * but at least the offsets are consistent. */ |
234 | 252 | ||
235 | /* Definitions for flags_1 */ |
253 | /* Definitions for flags_1 */ |
236 | #define IBOOST_ENABLE (1<<3) |
254 | #define IBOOST_ENABLE (1<<3) |
237 | 255 | ||
238 | struct common_child_dev_config { |
256 | struct common_child_dev_config { |
239 | u16 handle; |
257 | u16 handle; |
240 | u16 device_type; |
258 | u16 device_type; |
241 | u8 not_common1[12]; |
259 | u8 not_common1[12]; |
242 | u8 dvo_port; |
260 | u8 dvo_port; |
243 | u8 not_common2[2]; |
261 | u8 not_common2[2]; |
244 | u8 ddc_pin; |
262 | u8 ddc_pin; |
245 | u16 edid_ptr; |
263 | u16 edid_ptr; |
246 | u8 obsolete; |
264 | u8 obsolete; |
247 | u8 flags_1; |
265 | u8 flags_1; |
248 | u8 not_common3[13]; |
266 | u8 not_common3[13]; |
249 | u8 iboost_level; |
267 | u8 iboost_level; |
250 | } __packed; |
268 | } __packed; |
251 | 269 | ||
252 | 270 | ||
253 | /* This field changes depending on the BDB version, so the most reliable way to |
271 | /* This field changes depending on the BDB version, so the most reliable way to |
254 | * read it is by checking the BDB version and reading the raw pointer. */ |
272 | * read it is by checking the BDB version and reading the raw pointer. */ |
255 | union child_device_config { |
273 | union child_device_config { |
256 | /* This one is safe to be used anywhere, but the code should still check |
274 | /* This one is safe to be used anywhere, but the code should still check |
257 | * the BDB version. */ |
275 | * the BDB version. */ |
258 | u8 raw[33]; |
276 | u8 raw[33]; |
259 | /* This one should only be kept for legacy code. */ |
277 | /* This one should only be kept for legacy code. */ |
260 | struct old_child_dev_config old; |
278 | struct old_child_dev_config old; |
261 | /* This one should also be safe to use anywhere, even without version |
279 | /* This one should also be safe to use anywhere, even without version |
262 | * checks. */ |
280 | * checks. */ |
263 | struct common_child_dev_config common; |
281 | struct common_child_dev_config common; |
264 | } __packed; |
282 | } __packed; |
265 | 283 | ||
266 | struct bdb_general_definitions { |
284 | struct bdb_general_definitions { |
267 | /* DDC GPIO */ |
285 | /* DDC GPIO */ |
268 | u8 crt_ddc_gmbus_pin; |
286 | u8 crt_ddc_gmbus_pin; |
269 | 287 | ||
270 | /* DPMS bits */ |
288 | /* DPMS bits */ |
271 | u8 dpms_acpi:1; |
289 | u8 dpms_acpi:1; |
272 | u8 skip_boot_crt_detect:1; |
290 | u8 skip_boot_crt_detect:1; |
273 | u8 dpms_aim:1; |
291 | u8 dpms_aim:1; |
274 | u8 rsvd1:5; /* finish byte */ |
292 | u8 rsvd1:5; /* finish byte */ |
275 | 293 | ||
276 | /* boot device bits */ |
294 | /* boot device bits */ |
277 | u8 boot_display[2]; |
295 | u8 boot_display[2]; |
278 | u8 child_dev_size; |
296 | u8 child_dev_size; |
279 | 297 | ||
280 | /* |
298 | /* |
281 | * Device info: |
299 | * Device info: |
282 | * If TV is present, it'll be at devices[0]. |
300 | * If TV is present, it'll be at devices[0]. |
283 | * LVDS will be next, either devices[0] or [1], if present. |
301 | * LVDS will be next, either devices[0] or [1], if present. |
284 | * On some platforms the number of device is 6. But could be as few as |
302 | * On some platforms the number of device is 6. But could be as few as |
285 | * 4 if both TV and LVDS are missing. |
303 | * 4 if both TV and LVDS are missing. |
286 | * And the device num is related with the size of general definition |
304 | * And the device num is related with the size of general definition |
287 | * block. It is obtained by using the following formula: |
305 | * block. It is obtained by using the following formula: |
288 | * number = (block_size - sizeof(bdb_general_definitions))/ |
306 | * number = (block_size - sizeof(bdb_general_definitions))/ |
289 | * defs->child_dev_size; |
307 | * defs->child_dev_size; |
290 | */ |
308 | */ |
291 | uint8_t devices[0]; |
309 | uint8_t devices[0]; |
292 | } __packed; |
310 | } __packed; |
293 | 311 | ||
294 | /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ |
312 | /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ |
295 | #define MODE_MASK 0x3 |
313 | #define MODE_MASK 0x3 |
296 | 314 | ||
297 | struct bdb_lvds_options { |
315 | struct bdb_lvds_options { |
298 | u8 panel_type; |
316 | u8 panel_type; |
299 | u8 rsvd1; |
317 | u8 rsvd1; |
300 | /* LVDS capabilities, stored in a dword */ |
318 | /* LVDS capabilities, stored in a dword */ |
301 | u8 pfit_mode:2; |
319 | u8 pfit_mode:2; |
302 | u8 pfit_text_mode_enhanced:1; |
320 | u8 pfit_text_mode_enhanced:1; |
303 | u8 pfit_gfx_mode_enhanced:1; |
321 | u8 pfit_gfx_mode_enhanced:1; |
304 | u8 pfit_ratio_auto:1; |
322 | u8 pfit_ratio_auto:1; |
305 | u8 pixel_dither:1; |
323 | u8 pixel_dither:1; |
306 | u8 lvds_edid:1; |
324 | u8 lvds_edid:1; |
307 | u8 rsvd2:1; |
325 | u8 rsvd2:1; |
308 | u8 rsvd4; |
326 | u8 rsvd4; |
309 | /* LVDS Panel channel bits stored here */ |
327 | /* LVDS Panel channel bits stored here */ |
310 | u32 lvds_panel_channel_bits; |
328 | u32 lvds_panel_channel_bits; |
311 | /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ |
329 | /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ |
312 | u16 ssc_bits; |
330 | u16 ssc_bits; |
313 | u16 ssc_freq; |
331 | u16 ssc_freq; |
314 | u16 ssc_ddt; |
332 | u16 ssc_ddt; |
315 | /* Panel color depth defined here */ |
333 | /* Panel color depth defined here */ |
316 | u16 panel_color_depth; |
334 | u16 panel_color_depth; |
317 | /* LVDS panel type bits stored here */ |
335 | /* LVDS panel type bits stored here */ |
318 | u32 dps_panel_type_bits; |
336 | u32 dps_panel_type_bits; |
319 | /* LVDS backlight control type bits stored here */ |
337 | /* LVDS backlight control type bits stored here */ |
320 | u32 blt_control_type_bits; |
338 | u32 blt_control_type_bits; |
321 | } __packed; |
339 | } __packed; |
322 | 340 | ||
323 | /* LFP pointer table contains entries to the struct below */ |
341 | /* LFP pointer table contains entries to the struct below */ |
324 | struct bdb_lvds_lfp_data_ptr { |
342 | struct bdb_lvds_lfp_data_ptr { |
325 | u16 fp_timing_offset; /* offsets are from start of bdb */ |
343 | u16 fp_timing_offset; /* offsets are from start of bdb */ |
326 | u8 fp_table_size; |
344 | u8 fp_table_size; |
327 | u16 dvo_timing_offset; |
345 | u16 dvo_timing_offset; |
328 | u8 dvo_table_size; |
346 | u8 dvo_table_size; |
329 | u16 panel_pnp_id_offset; |
347 | u16 panel_pnp_id_offset; |
330 | u8 pnp_table_size; |
348 | u8 pnp_table_size; |
331 | } __packed; |
349 | } __packed; |
332 | 350 | ||
333 | struct bdb_lvds_lfp_data_ptrs { |
351 | struct bdb_lvds_lfp_data_ptrs { |
334 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ |
352 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ |
335 | struct bdb_lvds_lfp_data_ptr ptr[16]; |
353 | struct bdb_lvds_lfp_data_ptr ptr[16]; |
336 | } __packed; |
354 | } __packed; |
337 | 355 | ||
338 | /* LFP data has 3 blocks per entry */ |
356 | /* LFP data has 3 blocks per entry */ |
339 | struct lvds_fp_timing { |
357 | struct lvds_fp_timing { |
340 | u16 x_res; |
358 | u16 x_res; |
341 | u16 y_res; |
359 | u16 y_res; |
342 | u32 lvds_reg; |
360 | u32 lvds_reg; |
343 | u32 lvds_reg_val; |
361 | u32 lvds_reg_val; |
344 | u32 pp_on_reg; |
362 | u32 pp_on_reg; |
345 | u32 pp_on_reg_val; |
363 | u32 pp_on_reg_val; |
346 | u32 pp_off_reg; |
364 | u32 pp_off_reg; |
347 | u32 pp_off_reg_val; |
365 | u32 pp_off_reg_val; |
348 | u32 pp_cycle_reg; |
366 | u32 pp_cycle_reg; |
349 | u32 pp_cycle_reg_val; |
367 | u32 pp_cycle_reg_val; |
350 | u32 pfit_reg; |
368 | u32 pfit_reg; |
351 | u32 pfit_reg_val; |
369 | u32 pfit_reg_val; |
352 | u16 terminator; |
370 | u16 terminator; |
353 | } __packed; |
371 | } __packed; |
354 | 372 | ||
355 | struct lvds_dvo_timing { |
373 | struct lvds_dvo_timing { |
356 | u16 clock; /**< In 10khz */ |
374 | u16 clock; /**< In 10khz */ |
357 | u8 hactive_lo; |
375 | u8 hactive_lo; |
358 | u8 hblank_lo; |
376 | u8 hblank_lo; |
359 | u8 hblank_hi:4; |
377 | u8 hblank_hi:4; |
360 | u8 hactive_hi:4; |
378 | u8 hactive_hi:4; |
361 | u8 vactive_lo; |
379 | u8 vactive_lo; |
362 | u8 vblank_lo; |
380 | u8 vblank_lo; |
363 | u8 vblank_hi:4; |
381 | u8 vblank_hi:4; |
364 | u8 vactive_hi:4; |
382 | u8 vactive_hi:4; |
365 | u8 hsync_off_lo; |
383 | u8 hsync_off_lo; |
366 | u8 hsync_pulse_width; |
384 | u8 hsync_pulse_width; |
367 | u8 vsync_pulse_width:4; |
385 | u8 vsync_pulse_width:4; |
368 | u8 vsync_off:4; |
386 | u8 vsync_off:4; |
369 | u8 rsvd0:6; |
387 | u8 rsvd0:6; |
370 | u8 hsync_off_hi:2; |
388 | u8 hsync_off_hi:2; |
371 | u8 h_image; |
389 | u8 h_image; |
372 | u8 v_image; |
390 | u8 v_image; |
373 | u8 max_hv; |
391 | u8 max_hv; |
374 | u8 h_border; |
392 | u8 h_border; |
375 | u8 v_border; |
393 | u8 v_border; |
376 | u8 rsvd1:3; |
394 | u8 rsvd1:3; |
377 | u8 digital:2; |
395 | u8 digital:2; |
378 | u8 vsync_positive:1; |
396 | u8 vsync_positive:1; |
379 | u8 hsync_positive:1; |
397 | u8 hsync_positive:1; |
380 | u8 rsvd2:1; |
398 | u8 rsvd2:1; |
381 | } __packed; |
399 | } __packed; |
382 | 400 | ||
383 | struct lvds_pnp_id { |
401 | struct lvds_pnp_id { |
384 | u16 mfg_name; |
402 | u16 mfg_name; |
385 | u16 product_code; |
403 | u16 product_code; |
386 | u32 serial; |
404 | u32 serial; |
387 | u8 mfg_week; |
405 | u8 mfg_week; |
388 | u8 mfg_year; |
406 | u8 mfg_year; |
389 | } __packed; |
407 | } __packed; |
390 | 408 | ||
391 | struct bdb_lvds_lfp_data_entry { |
409 | struct bdb_lvds_lfp_data_entry { |
392 | struct lvds_fp_timing fp_timing; |
410 | struct lvds_fp_timing fp_timing; |
393 | struct lvds_dvo_timing dvo_timing; |
411 | struct lvds_dvo_timing dvo_timing; |
394 | struct lvds_pnp_id pnp_id; |
412 | struct lvds_pnp_id pnp_id; |
395 | } __packed; |
413 | } __packed; |
396 | 414 | ||
397 | struct bdb_lvds_lfp_data { |
415 | struct bdb_lvds_lfp_data { |
398 | struct bdb_lvds_lfp_data_entry data[16]; |
416 | struct bdb_lvds_lfp_data_entry data[16]; |
399 | } __packed; |
417 | } __packed; |
400 | 418 | ||
401 | #define BDB_BACKLIGHT_TYPE_NONE 0 |
419 | #define BDB_BACKLIGHT_TYPE_NONE 0 |
402 | #define BDB_BACKLIGHT_TYPE_PWM 2 |
420 | #define BDB_BACKLIGHT_TYPE_PWM 2 |
403 | 421 | ||
404 | struct bdb_lfp_backlight_data_entry { |
422 | struct bdb_lfp_backlight_data_entry { |
405 | u8 type:2; |
423 | u8 type:2; |
406 | u8 active_low_pwm:1; |
424 | u8 active_low_pwm:1; |
407 | u8 obsolete1:5; |
425 | u8 obsolete1:5; |
408 | u16 pwm_freq_hz; |
426 | u16 pwm_freq_hz; |
409 | u8 min_brightness; |
427 | u8 min_brightness; |
410 | u8 obsolete2; |
428 | u8 obsolete2; |
411 | u8 obsolete3; |
429 | u8 obsolete3; |
412 | } __packed; |
430 | } __packed; |
413 | 431 | ||
414 | struct bdb_lfp_backlight_data { |
432 | struct bdb_lfp_backlight_data { |
415 | u8 entry_size; |
433 | u8 entry_size; |
416 | struct bdb_lfp_backlight_data_entry data[16]; |
434 | struct bdb_lfp_backlight_data_entry data[16]; |
417 | u8 level[16]; |
435 | u8 level[16]; |
418 | } __packed; |
436 | } __packed; |
419 | 437 | ||
420 | struct aimdb_header { |
438 | struct aimdb_header { |
421 | char signature[16]; |
439 | char signature[16]; |
422 | char oem_device[20]; |
440 | char oem_device[20]; |
423 | u16 aimdb_version; |
441 | u16 aimdb_version; |
424 | u16 aimdb_header_size; |
442 | u16 aimdb_header_size; |
425 | u16 aimdb_size; |
443 | u16 aimdb_size; |
426 | } __packed; |
444 | } __packed; |
427 | 445 | ||
428 | struct aimdb_block { |
446 | struct aimdb_block { |
429 | u8 aimdb_id; |
447 | u8 aimdb_id; |
430 | u16 aimdb_size; |
448 | u16 aimdb_size; |
431 | } __packed; |
449 | } __packed; |
432 | 450 | ||
433 | struct vch_panel_data { |
451 | struct vch_panel_data { |
434 | u16 fp_timing_offset; |
452 | u16 fp_timing_offset; |
435 | u8 fp_timing_size; |
453 | u8 fp_timing_size; |
436 | u16 dvo_timing_offset; |
454 | u16 dvo_timing_offset; |
437 | u8 dvo_timing_size; |
455 | u8 dvo_timing_size; |
438 | u16 text_fitting_offset; |
456 | u16 text_fitting_offset; |
439 | u8 text_fitting_size; |
457 | u8 text_fitting_size; |
440 | u16 graphics_fitting_offset; |
458 | u16 graphics_fitting_offset; |
441 | u8 graphics_fitting_size; |
459 | u8 graphics_fitting_size; |
442 | } __packed; |
460 | } __packed; |
443 | 461 | ||
444 | struct vch_bdb_22 { |
462 | struct vch_bdb_22 { |
445 | struct aimdb_block aimdb_block; |
463 | struct aimdb_block aimdb_block; |
446 | struct vch_panel_data panels[16]; |
464 | struct vch_panel_data panels[16]; |
447 | } __packed; |
465 | } __packed; |
448 | 466 | ||
449 | struct bdb_sdvo_lvds_options { |
467 | struct bdb_sdvo_lvds_options { |
450 | u8 panel_backlight; |
468 | u8 panel_backlight; |
451 | u8 h40_set_panel_type; |
469 | u8 h40_set_panel_type; |
452 | u8 panel_type; |
470 | u8 panel_type; |
453 | u8 ssc_clk_freq; |
471 | u8 ssc_clk_freq; |
454 | u16 als_low_trip; |
472 | u16 als_low_trip; |
455 | u16 als_high_trip; |
473 | u16 als_high_trip; |
456 | u8 sclalarcoeff_tab_row_num; |
474 | u8 sclalarcoeff_tab_row_num; |
457 | u8 sclalarcoeff_tab_row_size; |
475 | u8 sclalarcoeff_tab_row_size; |
458 | u8 coefficient[8]; |
476 | u8 coefficient[8]; |
459 | u8 panel_misc_bits_1; |
477 | u8 panel_misc_bits_1; |
460 | u8 panel_misc_bits_2; |
478 | u8 panel_misc_bits_2; |
461 | u8 panel_misc_bits_3; |
479 | u8 panel_misc_bits_3; |
462 | u8 panel_misc_bits_4; |
480 | u8 panel_misc_bits_4; |
463 | } __packed; |
481 | } __packed; |
464 | 482 | ||
465 | 483 | ||
466 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
484 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
467 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
485 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
468 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
486 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
469 | #define BDB_DRIVER_FEATURE_EDP 3 |
487 | #define BDB_DRIVER_FEATURE_EDP 3 |
470 | 488 | ||
471 | struct bdb_driver_features { |
489 | struct bdb_driver_features { |
472 | u8 boot_dev_algorithm:1; |
490 | u8 boot_dev_algorithm:1; |
473 | u8 block_display_switch:1; |
491 | u8 block_display_switch:1; |
474 | u8 allow_display_switch:1; |
492 | u8 allow_display_switch:1; |
475 | u8 hotplug_dvo:1; |
493 | u8 hotplug_dvo:1; |
476 | u8 dual_view_zoom:1; |
494 | u8 dual_view_zoom:1; |
477 | u8 int15h_hook:1; |
495 | u8 int15h_hook:1; |
478 | u8 sprite_in_clone:1; |
496 | u8 sprite_in_clone:1; |
479 | u8 primary_lfp_id:1; |
497 | u8 primary_lfp_id:1; |
480 | 498 | ||
481 | u16 boot_mode_x; |
499 | u16 boot_mode_x; |
482 | u16 boot_mode_y; |
500 | u16 boot_mode_y; |
483 | u8 boot_mode_bpp; |
501 | u8 boot_mode_bpp; |
484 | u8 boot_mode_refresh; |
502 | u8 boot_mode_refresh; |
485 | 503 | ||
486 | u16 enable_lfp_primary:1; |
504 | u16 enable_lfp_primary:1; |
487 | u16 selective_mode_pruning:1; |
505 | u16 selective_mode_pruning:1; |
488 | u16 dual_frequency:1; |
506 | u16 dual_frequency:1; |
489 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
507 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
490 | u16 nt_clone_support:1; |
508 | u16 nt_clone_support:1; |
491 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
509 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
492 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
510 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
493 | u16 cui_aspect_scaling:1; |
511 | u16 cui_aspect_scaling:1; |
494 | u16 preserve_aspect_ratio:1; |
512 | u16 preserve_aspect_ratio:1; |
495 | u16 sdvo_device_power_down:1; |
513 | u16 sdvo_device_power_down:1; |
496 | u16 crt_hotplug:1; |
514 | u16 crt_hotplug:1; |
497 | u16 lvds_config:2; |
515 | u16 lvds_config:2; |
498 | u16 tv_hotplug:1; |
516 | u16 tv_hotplug:1; |
499 | u16 hdmi_config:2; |
517 | u16 hdmi_config:2; |
500 | 518 | ||
501 | u8 static_display:1; |
519 | u8 static_display:1; |
502 | u8 reserved2:7; |
520 | u8 reserved2:7; |
503 | u16 legacy_crt_max_x; |
521 | u16 legacy_crt_max_x; |
504 | u16 legacy_crt_max_y; |
522 | u16 legacy_crt_max_y; |
505 | u8 legacy_crt_max_refresh; |
523 | u8 legacy_crt_max_refresh; |
506 | 524 | ||
507 | u8 hdmi_termination; |
525 | u8 hdmi_termination; |
508 | u8 custom_vbt_version; |
526 | u8 custom_vbt_version; |
509 | /* Driver features data block */ |
527 | /* Driver features data block */ |
510 | u16 rmpm_enabled:1; |
528 | u16 rmpm_enabled:1; |
511 | u16 s2ddt_enabled:1; |
529 | u16 s2ddt_enabled:1; |
512 | u16 dpst_enabled:1; |
530 | u16 dpst_enabled:1; |
513 | u16 bltclt_enabled:1; |
531 | u16 bltclt_enabled:1; |
514 | u16 adb_enabled:1; |
532 | u16 adb_enabled:1; |
515 | u16 drrs_enabled:1; |
533 | u16 drrs_enabled:1; |
516 | u16 grs_enabled:1; |
534 | u16 grs_enabled:1; |
517 | u16 gpmt_enabled:1; |
535 | u16 gpmt_enabled:1; |
518 | u16 tbt_enabled:1; |
536 | u16 tbt_enabled:1; |
519 | u16 psr_enabled:1; |
537 | u16 psr_enabled:1; |
520 | u16 ips_enabled:1; |
538 | u16 ips_enabled:1; |
521 | u16 reserved3:4; |
539 | u16 reserved3:4; |
522 | u16 pc_feature_valid:1; |
540 | u16 pc_feature_valid:1; |
523 | } __packed; |
541 | } __packed; |
524 | 542 | ||
525 | #define EDP_18BPP 0 |
543 | #define EDP_18BPP 0 |
526 | #define EDP_24BPP 1 |
544 | #define EDP_24BPP 1 |
527 | #define EDP_30BPP 2 |
545 | #define EDP_30BPP 2 |
528 | #define EDP_RATE_1_62 0 |
546 | #define EDP_RATE_1_62 0 |
529 | #define EDP_RATE_2_7 1 |
547 | #define EDP_RATE_2_7 1 |
530 | #define EDP_LANE_1 0 |
548 | #define EDP_LANE_1 0 |
531 | #define EDP_LANE_2 1 |
549 | #define EDP_LANE_2 1 |
532 | #define EDP_LANE_4 3 |
550 | #define EDP_LANE_4 3 |
533 | #define EDP_PREEMPHASIS_NONE 0 |
551 | #define EDP_PREEMPHASIS_NONE 0 |
534 | #define EDP_PREEMPHASIS_3_5dB 1 |
552 | #define EDP_PREEMPHASIS_3_5dB 1 |
535 | #define EDP_PREEMPHASIS_6dB 2 |
553 | #define EDP_PREEMPHASIS_6dB 2 |
536 | #define EDP_PREEMPHASIS_9_5dB 3 |
554 | #define EDP_PREEMPHASIS_9_5dB 3 |
537 | #define EDP_VSWING_0_4V 0 |
555 | #define EDP_VSWING_0_4V 0 |
538 | #define EDP_VSWING_0_6V 1 |
556 | #define EDP_VSWING_0_6V 1 |
539 | #define EDP_VSWING_0_8V 2 |
557 | #define EDP_VSWING_0_8V 2 |
540 | #define EDP_VSWING_1_2V 3 |
558 | #define EDP_VSWING_1_2V 3 |
541 | 559 | ||
542 | struct edp_power_seq { |
560 | struct edp_power_seq { |
543 | u16 t1_t3; |
561 | u16 t1_t3; |
544 | u16 t8; |
562 | u16 t8; |
545 | u16 t9; |
563 | u16 t9; |
546 | u16 t10; |
564 | u16 t10; |
547 | u16 t11_t12; |
565 | u16 t11_t12; |
548 | } __packed; |
566 | } __packed; |
549 | 567 | ||
550 | struct edp_link_params { |
568 | struct edp_link_params { |
551 | u8 rate:4; |
569 | u8 rate:4; |
552 | u8 lanes:4; |
570 | u8 lanes:4; |
553 | u8 preemphasis:4; |
571 | u8 preemphasis:4; |
554 | u8 vswing:4; |
572 | u8 vswing:4; |
555 | } __packed; |
573 | } __packed; |
556 | 574 | ||
557 | struct bdb_edp { |
575 | struct bdb_edp { |
558 | struct edp_power_seq power_seqs[16]; |
576 | struct edp_power_seq power_seqs[16]; |
559 | u32 color_depth; |
577 | u32 color_depth; |
560 | struct edp_link_params link_params[16]; |
578 | struct edp_link_params link_params[16]; |
561 | u32 sdrrs_msa_timing_delay; |
579 | u32 sdrrs_msa_timing_delay; |
562 | 580 | ||
563 | /* ith bit indicates enabled/disabled for (i+1)th panel */ |
581 | /* ith bit indicates enabled/disabled for (i+1)th panel */ |
564 | u16 edp_s3d_feature; |
582 | u16 edp_s3d_feature; |
565 | u16 edp_t3_optimization; |
583 | u16 edp_t3_optimization; |
566 | u64 edp_vswing_preemph; /* v173 */ |
584 | u64 edp_vswing_preemph; /* v173 */ |
567 | } __packed; |
585 | } __packed; |
568 | 586 | ||
569 | struct psr_table { |
587 | struct psr_table { |
570 | /* Feature bits */ |
588 | /* Feature bits */ |
571 | u8 full_link:1; |
589 | u8 full_link:1; |
572 | u8 require_aux_to_wakeup:1; |
590 | u8 require_aux_to_wakeup:1; |
573 | u8 feature_bits_rsvd:6; |
591 | u8 feature_bits_rsvd:6; |
574 | 592 | ||
575 | /* Wait times */ |
593 | /* Wait times */ |
576 | u8 idle_frames:4; |
594 | u8 idle_frames:4; |
577 | u8 lines_to_wait:3; |
595 | u8 lines_to_wait:3; |
578 | u8 wait_times_rsvd:1; |
596 | u8 wait_times_rsvd:1; |
579 | 597 | ||
580 | /* TP wake up time in multiple of 100 */ |
598 | /* TP wake up time in multiple of 100 */ |
581 | u16 tp1_wakeup_time; |
599 | u16 tp1_wakeup_time; |
582 | u16 tp2_tp3_wakeup_time; |
600 | u16 tp2_tp3_wakeup_time; |
583 | } __packed; |
601 | } __packed; |
584 | 602 | ||
585 | struct bdb_psr { |
603 | struct bdb_psr { |
586 | struct psr_table psr_table[16]; |
604 | struct psr_table psr_table[16]; |
587 | } __packed; |
605 | } __packed; |
588 | 606 | ||
589 | /* |
607 | /* |
590 | * Driver<->VBIOS interaction occurs through scratch bits in |
608 | * Driver<->VBIOS interaction occurs through scratch bits in |
591 | * GR18 & SWF*. |
609 | * GR18 & SWF*. |
592 | */ |
610 | */ |
593 | 611 | ||
594 | /* GR18 bits are set on display switch and hotkey events */ |
612 | /* GR18 bits are set on display switch and hotkey events */ |
595 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ |
613 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ |
596 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ |
614 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ |
597 | #define GR18_HK_NONE (0x0<<3) |
615 | #define GR18_HK_NONE (0x0<<3) |
598 | #define GR18_HK_LFP_STRETCH (0x1<<3) |
616 | #define GR18_HK_LFP_STRETCH (0x1<<3) |
599 | #define GR18_HK_TOGGLE_DISP (0x2<<3) |
617 | #define GR18_HK_TOGGLE_DISP (0x2<<3) |
600 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ |
618 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ |
601 | #define GR18_HK_POPUP_DISABLED (0x6<<3) |
619 | #define GR18_HK_POPUP_DISABLED (0x6<<3) |
602 | #define GR18_HK_POPUP_ENABLED (0x7<<3) |
620 | #define GR18_HK_POPUP_ENABLED (0x7<<3) |
603 | #define GR18_HK_PFIT (0x8<<3) |
621 | #define GR18_HK_PFIT (0x8<<3) |
604 | #define GR18_HK_APM_CHANGE (0xa<<3) |
622 | #define GR18_HK_APM_CHANGE (0xa<<3) |
605 | #define GR18_HK_MULTIPLE (0xc<<3) |
623 | #define GR18_HK_MULTIPLE (0xc<<3) |
606 | #define GR18_USER_INT_EN (1<<2) |
624 | #define GR18_USER_INT_EN (1<<2) |
607 | #define GR18_A0000_FLUSH_EN (1<<1) |
625 | #define GR18_A0000_FLUSH_EN (1<<1) |
608 | #define GR18_SMM_EN (1<<0) |
626 | #define GR18_SMM_EN (1<<0) |
609 | 627 | ||
610 | /* Set by driver, cleared by VBIOS */ |
628 | /* Set by driver, cleared by VBIOS */ |
611 | #define SWF00_YRES_SHIFT 16 |
629 | #define SWF00_YRES_SHIFT 16 |
612 | #define SWF00_XRES_SHIFT 0 |
630 | #define SWF00_XRES_SHIFT 0 |
613 | #define SWF00_RES_MASK 0xffff |
631 | #define SWF00_RES_MASK 0xffff |
614 | 632 | ||
615 | /* Set by VBIOS at boot time and driver at runtime */ |
633 | /* Set by VBIOS at boot time and driver at runtime */ |
616 | #define SWF01_TV2_FORMAT_SHIFT 8 |
634 | #define SWF01_TV2_FORMAT_SHIFT 8 |
617 | #define SWF01_TV1_FORMAT_SHIFT 0 |
635 | #define SWF01_TV1_FORMAT_SHIFT 0 |
618 | #define SWF01_TV_FORMAT_MASK 0xffff |
636 | #define SWF01_TV_FORMAT_MASK 0xffff |
619 | 637 | ||
620 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) |
638 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) |
621 | #define SWF10_GTT_OVERRIDE_EN (1<<28) |
639 | #define SWF10_GTT_OVERRIDE_EN (1<<28) |
622 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ |
640 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ |
623 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) |
641 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) |
624 | #define SWF10_OLD_TOGGLE 0x0 |
642 | #define SWF10_OLD_TOGGLE 0x0 |
625 | #define SWF10_TOGGLE_LIST_1 0x1 |
643 | #define SWF10_TOGGLE_LIST_1 0x1 |
626 | #define SWF10_TOGGLE_LIST_2 0x2 |
644 | #define SWF10_TOGGLE_LIST_2 0x2 |
627 | #define SWF10_TOGGLE_LIST_3 0x3 |
645 | #define SWF10_TOGGLE_LIST_3 0x3 |
628 | #define SWF10_TOGGLE_LIST_4 0x4 |
646 | #define SWF10_TOGGLE_LIST_4 0x4 |
629 | #define SWF10_PANNING_EN (1<<23) |
647 | #define SWF10_PANNING_EN (1<<23) |
630 | #define SWF10_DRIVER_LOADED (1<<22) |
648 | #define SWF10_DRIVER_LOADED (1<<22) |
631 | #define SWF10_EXTENDED_DESKTOP (1<<21) |
649 | #define SWF10_EXTENDED_DESKTOP (1<<21) |
632 | #define SWF10_EXCLUSIVE_MODE (1<<20) |
650 | #define SWF10_EXCLUSIVE_MODE (1<<20) |
633 | #define SWF10_OVERLAY_EN (1<<19) |
651 | #define SWF10_OVERLAY_EN (1<<19) |
634 | #define SWF10_PLANEB_HOLDOFF (1<<18) |
652 | #define SWF10_PLANEB_HOLDOFF (1<<18) |
635 | #define SWF10_PLANEA_HOLDOFF (1<<17) |
653 | #define SWF10_PLANEA_HOLDOFF (1<<17) |
636 | #define SWF10_VGA_HOLDOFF (1<<16) |
654 | #define SWF10_VGA_HOLDOFF (1<<16) |
637 | #define SWF10_ACTIVE_DISP_MASK 0xffff |
655 | #define SWF10_ACTIVE_DISP_MASK 0xffff |
638 | #define SWF10_PIPEB_LFP2 (1<<15) |
656 | #define SWF10_PIPEB_LFP2 (1<<15) |
639 | #define SWF10_PIPEB_EFP2 (1<<14) |
657 | #define SWF10_PIPEB_EFP2 (1<<14) |
640 | #define SWF10_PIPEB_TV2 (1<<13) |
658 | #define SWF10_PIPEB_TV2 (1<<13) |
641 | #define SWF10_PIPEB_CRT2 (1<<12) |
659 | #define SWF10_PIPEB_CRT2 (1<<12) |
642 | #define SWF10_PIPEB_LFP (1<<11) |
660 | #define SWF10_PIPEB_LFP (1<<11) |
643 | #define SWF10_PIPEB_EFP (1<<10) |
661 | #define SWF10_PIPEB_EFP (1<<10) |
644 | #define SWF10_PIPEB_TV (1<<9) |
662 | #define SWF10_PIPEB_TV (1<<9) |
645 | #define SWF10_PIPEB_CRT (1<<8) |
663 | #define SWF10_PIPEB_CRT (1<<8) |
646 | #define SWF10_PIPEA_LFP2 (1<<7) |
664 | #define SWF10_PIPEA_LFP2 (1<<7) |
647 | #define SWF10_PIPEA_EFP2 (1<<6) |
665 | #define SWF10_PIPEA_EFP2 (1<<6) |
648 | #define SWF10_PIPEA_TV2 (1<<5) |
666 | #define SWF10_PIPEA_TV2 (1<<5) |
649 | #define SWF10_PIPEA_CRT2 (1<<4) |
667 | #define SWF10_PIPEA_CRT2 (1<<4) |
650 | #define SWF10_PIPEA_LFP (1<<3) |
668 | #define SWF10_PIPEA_LFP (1<<3) |
651 | #define SWF10_PIPEA_EFP (1<<2) |
669 | #define SWF10_PIPEA_EFP (1<<2) |
652 | #define SWF10_PIPEA_TV (1<<1) |
670 | #define SWF10_PIPEA_TV (1<<1) |
653 | #define SWF10_PIPEA_CRT (1<<0) |
671 | #define SWF10_PIPEA_CRT (1<<0) |
654 | 672 | ||
655 | #define SWF11_MEMORY_SIZE_SHIFT 16 |
673 | #define SWF11_MEMORY_SIZE_SHIFT 16 |
656 | #define SWF11_SV_TEST_EN (1<<15) |
674 | #define SWF11_SV_TEST_EN (1<<15) |
657 | #define SWF11_IS_AGP (1<<14) |
675 | #define SWF11_IS_AGP (1<<14) |
658 | #define SWF11_DISPLAY_HOLDOFF (1<<13) |
676 | #define SWF11_DISPLAY_HOLDOFF (1<<13) |
659 | #define SWF11_DPMS_REDUCED (1<<12) |
677 | #define SWF11_DPMS_REDUCED (1<<12) |
660 | #define SWF11_IS_VBE_MODE (1<<11) |
678 | #define SWF11_IS_VBE_MODE (1<<11) |
661 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ |
679 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ |
662 | #define SWF11_DPMS_MASK 0x07 |
680 | #define SWF11_DPMS_MASK 0x07 |
663 | #define SWF11_DPMS_OFF (1<<2) |
681 | #define SWF11_DPMS_OFF (1<<2) |
664 | #define SWF11_DPMS_SUSPEND (1<<1) |
682 | #define SWF11_DPMS_SUSPEND (1<<1) |
665 | #define SWF11_DPMS_STANDBY (1<<0) |
683 | #define SWF11_DPMS_STANDBY (1<<0) |
666 | #define SWF11_DPMS_ON 0 |
684 | #define SWF11_DPMS_ON 0 |
667 | 685 | ||
668 | #define SWF14_GFX_PFIT_EN (1<<31) |
686 | #define SWF14_GFX_PFIT_EN (1<<31) |
669 | #define SWF14_TEXT_PFIT_EN (1<<30) |
687 | #define SWF14_TEXT_PFIT_EN (1<<30) |
670 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ |
688 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ |
671 | #define SWF14_POPUP_EN (1<<28) |
689 | #define SWF14_POPUP_EN (1<<28) |
672 | #define SWF14_DISPLAY_HOLDOFF (1<<27) |
690 | #define SWF14_DISPLAY_HOLDOFF (1<<27) |
673 | #define SWF14_DISP_DETECT_EN (1<<26) |
691 | #define SWF14_DISP_DETECT_EN (1<<26) |
674 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ |
692 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ |
675 | #define SWF14_DRIVER_STATUS (1<<24) |
693 | #define SWF14_DRIVER_STATUS (1<<24) |
676 | #define SWF14_OS_TYPE_WIN9X (1<<23) |
694 | #define SWF14_OS_TYPE_WIN9X (1<<23) |
677 | #define SWF14_OS_TYPE_WINNT (1<<22) |
695 | #define SWF14_OS_TYPE_WINNT (1<<22) |
678 | /* 21:19 rsvd */ |
696 | /* 21:19 rsvd */ |
679 | #define SWF14_PM_TYPE_MASK 0x00070000 |
697 | #define SWF14_PM_TYPE_MASK 0x00070000 |
680 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) |
698 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) |
681 | #define SWF14_PM_ACPI (0x3 << 16) |
699 | #define SWF14_PM_ACPI (0x3 << 16) |
682 | #define SWF14_PM_APM_12 (0x2 << 16) |
700 | #define SWF14_PM_APM_12 (0x2 << 16) |
683 | #define SWF14_PM_APM_11 (0x1 << 16) |
701 | #define SWF14_PM_APM_11 (0x1 << 16) |
684 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ |
702 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ |
685 | /* if GR18 indicates a display switch */ |
703 | /* if GR18 indicates a display switch */ |
686 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) |
704 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) |
687 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) |
705 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) |
688 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) |
706 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) |
689 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) |
707 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) |
690 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) |
708 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) |
691 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) |
709 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) |
692 | #define SWF14_DS_PIPEB_TV_EN (1<<9) |
710 | #define SWF14_DS_PIPEB_TV_EN (1<<9) |
693 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) |
711 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) |
694 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) |
712 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) |
695 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) |
713 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) |
696 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) |
714 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) |
697 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) |
715 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) |
698 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) |
716 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) |
699 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) |
717 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) |
700 | #define SWF14_DS_PIPEA_TV_EN (1<<1) |
718 | #define SWF14_DS_PIPEA_TV_EN (1<<1) |
701 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) |
719 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) |
702 | /* if GR18 indicates a panel fitting request */ |
720 | /* if GR18 indicates a panel fitting request */ |
703 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ |
721 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ |
704 | /* if GR18 indicates an APM change request */ |
722 | /* if GR18 indicates an APM change request */ |
705 | #define SWF14_APM_HIBERNATE 0x4 |
723 | #define SWF14_APM_HIBERNATE 0x4 |
706 | #define SWF14_APM_SUSPEND 0x3 |
724 | #define SWF14_APM_SUSPEND 0x3 |
707 | #define SWF14_APM_STANDBY 0x1 |
725 | #define SWF14_APM_STANDBY 0x1 |
708 | #define SWF14_APM_RESTORE 0x0 |
726 | #define SWF14_APM_RESTORE 0x0 |
709 | 727 | ||
710 | /* Add the device class for LFP, TV, HDMI */ |
728 | /* Add the device class for LFP, TV, HDMI */ |
711 | #define DEVICE_TYPE_INT_LFP 0x1022 |
729 | #define DEVICE_TYPE_INT_LFP 0x1022 |
712 | #define DEVICE_TYPE_INT_TV 0x1009 |
730 | #define DEVICE_TYPE_INT_TV 0x1009 |
713 | #define DEVICE_TYPE_HDMI 0x60D2 |
731 | #define DEVICE_TYPE_HDMI 0x60D2 |
714 | #define DEVICE_TYPE_DP 0x68C6 |
732 | #define DEVICE_TYPE_DP 0x68C6 |
715 | #define DEVICE_TYPE_eDP 0x78C6 |
733 | #define DEVICE_TYPE_eDP 0x78C6 |
716 | 734 | ||
717 | #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) |
735 | #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) |
718 | #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) |
736 | #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) |
719 | #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) |
737 | #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) |
720 | #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) |
738 | #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) |
721 | #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) |
739 | #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) |
722 | #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) |
740 | #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) |
723 | #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) |
741 | #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) |
724 | #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) |
742 | #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) |
725 | #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) |
743 | #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) |
726 | #define DEVICE_TYPE_LVDS_SINGALING (1 << 5) |
744 | #define DEVICE_TYPE_LVDS_SINGALING (1 << 5) |
727 | #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) |
745 | #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) |
728 | #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) |
746 | #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) |
729 | #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) |
747 | #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) |
730 | #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) |
748 | #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) |
731 | #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) |
749 | #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) |
732 | 750 | ||
733 | /* |
751 | /* |
734 | * Bits we care about when checking for DEVICE_TYPE_eDP |
752 | * Bits we care about when checking for DEVICE_TYPE_eDP |
735 | * Depending on the system, the other bits may or may not |
753 | * Depending on the system, the other bits may or may not |
736 | * be set for eDP outputs. |
754 | * be set for eDP outputs. |
737 | */ |
755 | */ |
738 | #define DEVICE_TYPE_eDP_BITS \ |
756 | #define DEVICE_TYPE_eDP_BITS \ |
739 | (DEVICE_TYPE_INTERNAL_CONNECTOR | \ |
757 | (DEVICE_TYPE_INTERNAL_CONNECTOR | \ |
740 | DEVICE_TYPE_MIPI_OUTPUT | \ |
758 | DEVICE_TYPE_MIPI_OUTPUT | \ |
741 | DEVICE_TYPE_COMPOSITE_OUTPUT | \ |
759 | DEVICE_TYPE_COMPOSITE_OUTPUT | \ |
742 | DEVICE_TYPE_DUAL_CHANNEL | \ |
760 | DEVICE_TYPE_DUAL_CHANNEL | \ |
743 | DEVICE_TYPE_LVDS_SINGALING | \ |
761 | DEVICE_TYPE_LVDS_SINGALING | \ |
744 | DEVICE_TYPE_TMDS_DVI_SIGNALING | \ |
762 | DEVICE_TYPE_TMDS_DVI_SIGNALING | \ |
745 | DEVICE_TYPE_VIDEO_SIGNALING | \ |
763 | DEVICE_TYPE_VIDEO_SIGNALING | \ |
746 | DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ |
764 | DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ |
747 | DEVICE_TYPE_ANALOG_OUTPUT) |
765 | DEVICE_TYPE_ANALOG_OUTPUT) |
748 | 766 | ||
749 | /* define the DVO port for HDMI output type */ |
767 | /* define the DVO port for HDMI output type */ |
750 | #define DVO_B 1 |
768 | #define DVO_B 1 |
751 | #define DVO_C 2 |
769 | #define DVO_C 2 |
752 | #define DVO_D 3 |
770 | #define DVO_D 3 |
753 | 771 | ||
754 | /* Possible values for the "DVO Port" field for versions >= 155: */ |
772 | /* Possible values for the "DVO Port" field for versions >= 155: */ |
755 | #define DVO_PORT_HDMIA 0 |
773 | #define DVO_PORT_HDMIA 0 |
756 | #define DVO_PORT_HDMIB 1 |
774 | #define DVO_PORT_HDMIB 1 |
757 | #define DVO_PORT_HDMIC 2 |
775 | #define DVO_PORT_HDMIC 2 |
758 | #define DVO_PORT_HDMID 3 |
776 | #define DVO_PORT_HDMID 3 |
759 | #define DVO_PORT_LVDS 4 |
777 | #define DVO_PORT_LVDS 4 |
760 | #define DVO_PORT_TV 5 |
778 | #define DVO_PORT_TV 5 |
761 | #define DVO_PORT_CRT 6 |
779 | #define DVO_PORT_CRT 6 |
762 | #define DVO_PORT_DPB 7 |
780 | #define DVO_PORT_DPB 7 |
763 | #define DVO_PORT_DPC 8 |
781 | #define DVO_PORT_DPC 8 |
764 | #define DVO_PORT_DPD 9 |
782 | #define DVO_PORT_DPD 9 |
765 | #define DVO_PORT_DPA 10 |
783 | #define DVO_PORT_DPA 10 |
766 | #define DVO_PORT_DPE 11 |
784 | #define DVO_PORT_DPE 11 |
767 | #define DVO_PORT_HDMIE 12 |
785 | #define DVO_PORT_HDMIE 12 |
768 | #define DVO_PORT_MIPIA 21 |
786 | #define DVO_PORT_MIPIA 21 |
769 | #define DVO_PORT_MIPIB 22 |
787 | #define DVO_PORT_MIPIB 22 |
770 | #define DVO_PORT_MIPIC 23 |
788 | #define DVO_PORT_MIPIC 23 |
771 | #define DVO_PORT_MIPID 24 |
789 | #define DVO_PORT_MIPID 24 |
772 | 790 | ||
773 | /* Block 52 contains MIPI Panel info |
791 | /* Block 52 contains MIPI Panel info |
774 | * 6 such enteries will there. Index into correct |
792 | * 6 such enteries will there. Index into correct |
775 | * entery is based on the panel_index in #40 LFP |
793 | * entery is based on the panel_index in #40 LFP |
776 | */ |
794 | */ |
777 | #define MAX_MIPI_CONFIGURATIONS 6 |
795 | #define MAX_MIPI_CONFIGURATIONS 6 |
778 | 796 | ||
779 | #define MIPI_DSI_UNDEFINED_PANEL_ID 0 |
797 | #define MIPI_DSI_UNDEFINED_PANEL_ID 0 |
780 | #define MIPI_DSI_GENERIC_PANEL_ID 1 |
798 | #define MIPI_DSI_GENERIC_PANEL_ID 1 |
781 | 799 | ||
782 | /* |
800 | /* |
783 | * PMIC vs SoC Backlight support specified in pwm_blc |
801 | * PMIC vs SoC Backlight support specified in pwm_blc |
784 | * field in mipi_config block below. |
802 | * field in mipi_config block below. |
785 | */ |
803 | */ |
786 | #define PPS_BLC_PMIC 0 |
804 | #define PPS_BLC_PMIC 0 |
787 | #define PPS_BLC_SOC 1 |
805 | #define PPS_BLC_SOC 1 |
788 | 806 | ||
789 | struct mipi_config { |
807 | struct mipi_config { |
790 | u16 panel_id; |
808 | u16 panel_id; |
791 | 809 | ||
792 | /* General Params */ |
810 | /* General Params */ |
793 | u32 enable_dithering:1; |
811 | u32 enable_dithering:1; |
794 | u32 rsvd1:1; |
812 | u32 rsvd1:1; |
795 | u32 is_bridge:1; |
813 | u32 is_bridge:1; |
796 | 814 | ||
797 | u32 panel_arch_type:2; |
815 | u32 panel_arch_type:2; |
798 | u32 is_cmd_mode:1; |
816 | u32 is_cmd_mode:1; |
799 | 817 | ||
800 | #define NON_BURST_SYNC_PULSE 0x1 |
818 | #define NON_BURST_SYNC_PULSE 0x1 |
801 | #define NON_BURST_SYNC_EVENTS 0x2 |
819 | #define NON_BURST_SYNC_EVENTS 0x2 |
802 | #define BURST_MODE 0x3 |
820 | #define BURST_MODE 0x3 |
803 | u32 video_transfer_mode:2; |
821 | u32 video_transfer_mode:2; |
804 | 822 | ||
805 | u32 cabc_supported:1; |
823 | u32 cabc_supported:1; |
806 | u32 pwm_blc:1; |
824 | u32 pwm_blc:1; |
807 | 825 | ||
808 | /* Bit 13:10 */ |
826 | /* Bit 13:10 */ |
809 | #define PIXEL_FORMAT_RGB565 0x1 |
827 | #define PIXEL_FORMAT_RGB565 0x1 |
810 | #define PIXEL_FORMAT_RGB666 0x2 |
828 | #define PIXEL_FORMAT_RGB666 0x2 |
811 | #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 |
829 | #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 |
812 | #define PIXEL_FORMAT_RGB888 0x4 |
830 | #define PIXEL_FORMAT_RGB888 0x4 |
813 | u32 videomode_color_format:4; |
831 | u32 videomode_color_format:4; |
814 | 832 | ||
815 | /* Bit 15:14 */ |
833 | /* Bit 15:14 */ |
816 | #define ENABLE_ROTATION_0 0x0 |
834 | #define ENABLE_ROTATION_0 0x0 |
817 | #define ENABLE_ROTATION_90 0x1 |
835 | #define ENABLE_ROTATION_90 0x1 |
818 | #define ENABLE_ROTATION_180 0x2 |
836 | #define ENABLE_ROTATION_180 0x2 |
819 | #define ENABLE_ROTATION_270 0x3 |
837 | #define ENABLE_ROTATION_270 0x3 |
820 | u32 rotation:2; |
838 | u32 rotation:2; |
821 | u32 bta_enabled:1; |
839 | u32 bta_enabled:1; |
822 | u32 rsvd2:15; |
840 | u32 rsvd2:15; |
823 | 841 | ||
824 | /* 2 byte Port Description */ |
842 | /* 2 byte Port Description */ |
825 | #define DUAL_LINK_NOT_SUPPORTED 0 |
843 | #define DUAL_LINK_NOT_SUPPORTED 0 |
826 | #define DUAL_LINK_FRONT_BACK 1 |
844 | #define DUAL_LINK_FRONT_BACK 1 |
827 | #define DUAL_LINK_PIXEL_ALT 2 |
845 | #define DUAL_LINK_PIXEL_ALT 2 |
828 | u16 dual_link:2; |
846 | u16 dual_link:2; |
829 | u16 lane_cnt:2; |
847 | u16 lane_cnt:2; |
830 | u16 pixel_overlap:3; |
848 | u16 pixel_overlap:3; |
831 | u16 rsvd3:9; |
849 | u16 rsvd3:9; |
832 | 850 | ||
833 | u16 rsvd4; |
851 | u16 rsvd4; |
834 | 852 | ||
835 | u8 rsvd5; |
853 | u8 rsvd5; |
836 | u32 target_burst_mode_freq; |
854 | u32 target_burst_mode_freq; |
837 | u32 dsi_ddr_clk; |
855 | u32 dsi_ddr_clk; |
838 | u32 bridge_ref_clk; |
856 | u32 bridge_ref_clk; |
839 | 857 | ||
840 | #define BYTE_CLK_SEL_20MHZ 0 |
858 | #define BYTE_CLK_SEL_20MHZ 0 |
841 | #define BYTE_CLK_SEL_10MHZ 1 |
859 | #define BYTE_CLK_SEL_10MHZ 1 |
842 | #define BYTE_CLK_SEL_5MHZ 2 |
860 | #define BYTE_CLK_SEL_5MHZ 2 |
843 | u8 byte_clk_sel:2; |
861 | u8 byte_clk_sel:2; |
844 | 862 | ||
845 | u8 rsvd6:6; |
863 | u8 rsvd6:6; |
846 | 864 | ||
847 | /* DPHY Flags */ |
865 | /* DPHY Flags */ |
848 | u16 dphy_param_valid:1; |
866 | u16 dphy_param_valid:1; |
849 | u16 eot_pkt_disabled:1; |
867 | u16 eot_pkt_disabled:1; |
850 | u16 enable_clk_stop:1; |
868 | u16 enable_clk_stop:1; |
851 | u16 rsvd7:13; |
869 | u16 rsvd7:13; |
852 | 870 | ||
853 | u32 hs_tx_timeout; |
871 | u32 hs_tx_timeout; |
854 | u32 lp_rx_timeout; |
872 | u32 lp_rx_timeout; |
855 | u32 turn_around_timeout; |
873 | u32 turn_around_timeout; |
856 | u32 device_reset_timer; |
874 | u32 device_reset_timer; |
857 | u32 master_init_timer; |
875 | u32 master_init_timer; |
858 | u32 dbi_bw_timer; |
876 | u32 dbi_bw_timer; |
859 | u32 lp_byte_clk_val; |
877 | u32 lp_byte_clk_val; |
860 | 878 | ||
861 | /* 4 byte Dphy Params */ |
879 | /* 4 byte Dphy Params */ |
862 | u32 prepare_cnt:6; |
880 | u32 prepare_cnt:6; |
863 | u32 rsvd8:2; |
881 | u32 rsvd8:2; |
864 | u32 clk_zero_cnt:8; |
882 | u32 clk_zero_cnt:8; |
865 | u32 trail_cnt:5; |
883 | u32 trail_cnt:5; |
866 | u32 rsvd9:3; |
884 | u32 rsvd9:3; |
867 | u32 exit_zero_cnt:6; |
885 | u32 exit_zero_cnt:6; |
868 | u32 rsvd10:2; |
886 | u32 rsvd10:2; |
869 | 887 | ||
870 | u32 clk_lane_switch_cnt; |
888 | u32 clk_lane_switch_cnt; |
871 | u32 hl_switch_cnt; |
889 | u32 hl_switch_cnt; |
872 | 890 | ||
873 | u32 rsvd11[6]; |
891 | u32 rsvd11[6]; |
874 | 892 | ||
875 | /* timings based on dphy spec */ |
893 | /* timings based on dphy spec */ |
876 | u8 tclk_miss; |
894 | u8 tclk_miss; |
877 | u8 tclk_post; |
895 | u8 tclk_post; |
878 | u8 rsvd12; |
896 | u8 rsvd12; |
879 | u8 tclk_pre; |
897 | u8 tclk_pre; |
880 | u8 tclk_prepare; |
898 | u8 tclk_prepare; |
881 | u8 tclk_settle; |
899 | u8 tclk_settle; |
882 | u8 tclk_term_enable; |
900 | u8 tclk_term_enable; |
883 | u8 tclk_trail; |
901 | u8 tclk_trail; |
884 | u16 tclk_prepare_clkzero; |
902 | u16 tclk_prepare_clkzero; |
885 | u8 rsvd13; |
903 | u8 rsvd13; |
886 | u8 td_term_enable; |
904 | u8 td_term_enable; |
887 | u8 teot; |
905 | u8 teot; |
888 | u8 ths_exit; |
906 | u8 ths_exit; |
889 | u8 ths_prepare; |
907 | u8 ths_prepare; |
890 | u16 ths_prepare_hszero; |
908 | u16 ths_prepare_hszero; |
891 | u8 rsvd14; |
909 | u8 rsvd14; |
892 | u8 ths_settle; |
910 | u8 ths_settle; |
893 | u8 ths_skip; |
911 | u8 ths_skip; |
894 | u8 ths_trail; |
912 | u8 ths_trail; |
895 | u8 tinit; |
913 | u8 tinit; |
896 | u8 tlpx; |
914 | u8 tlpx; |
897 | u8 rsvd15[3]; |
915 | u8 rsvd15[3]; |
898 | 916 | ||
899 | /* GPIOs */ |
917 | /* GPIOs */ |
900 | u8 panel_enable; |
918 | u8 panel_enable; |
901 | u8 bl_enable; |
919 | u8 bl_enable; |
902 | u8 pwm_enable; |
920 | u8 pwm_enable; |
903 | u8 reset_r_n; |
921 | u8 reset_r_n; |
904 | u8 pwr_down_r; |
922 | u8 pwr_down_r; |
905 | u8 stdby_r_n; |
923 | u8 stdby_r_n; |
906 | 924 | ||
907 | } __packed; |
925 | } __packed; |
908 | 926 | ||
909 | /* Block 52 contains MIPI configuration block |
927 | /* Block 52 contains MIPI configuration block |
910 | * 6 * bdb_mipi_config, followed by 6 pps data |
928 | * 6 * bdb_mipi_config, followed by 6 pps data |
911 | * block below |
929 | * block below |
912 | * |
930 | * |
913 | * all delays has a unit of 100us |
931 | * all delays has a unit of 100us |
914 | */ |
932 | */ |
915 | struct mipi_pps_data { |
933 | struct mipi_pps_data { |
916 | u16 panel_on_delay; |
934 | u16 panel_on_delay; |
917 | u16 bl_enable_delay; |
935 | u16 bl_enable_delay; |
918 | u16 bl_disable_delay; |
936 | u16 bl_disable_delay; |
919 | u16 panel_off_delay; |
937 | u16 panel_off_delay; |
920 | u16 panel_power_cycle_delay; |
938 | u16 panel_power_cycle_delay; |
921 | } __packed; |
939 | } __packed; |
922 | 940 | ||
923 | struct bdb_mipi_config { |
941 | struct bdb_mipi_config { |
924 | struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; |
942 | struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; |
925 | struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; |
943 | struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; |
926 | } __packed; |
944 | } __packed; |
927 | 945 | ||
928 | /* Block 53 contains MIPI sequences as needed by the panel |
946 | /* Block 53 contains MIPI sequences as needed by the panel |
929 | * for enabling it. This block can be variable in size and |
947 | * for enabling it. This block can be variable in size and |
930 | * can be maximum of 6 blocks |
948 | * can be maximum of 6 blocks |
931 | */ |
949 | */ |
932 | struct bdb_mipi_sequence { |
950 | struct bdb_mipi_sequence { |
933 | u8 version; |
951 | u8 version; |
934 | u8 data[0]; |
952 | u8 data[0]; |
935 | } __packed; |
953 | } __packed; |
936 | 954 | ||
937 | /* MIPI Sequnece Block definitions */ |
955 | /* MIPI Sequnece Block definitions */ |
938 | enum mipi_seq { |
956 | enum mipi_seq { |
939 | MIPI_SEQ_UNDEFINED = 0, |
957 | MIPI_SEQ_END = 0, |
940 | MIPI_SEQ_ASSERT_RESET, |
958 | MIPI_SEQ_ASSERT_RESET, |
941 | MIPI_SEQ_INIT_OTP, |
959 | MIPI_SEQ_INIT_OTP, |
942 | MIPI_SEQ_DISPLAY_ON, |
960 | MIPI_SEQ_DISPLAY_ON, |
943 | MIPI_SEQ_DISPLAY_OFF, |
961 | MIPI_SEQ_DISPLAY_OFF, |
944 | MIPI_SEQ_DEASSERT_RESET, |
962 | MIPI_SEQ_DEASSERT_RESET, |
- | 963 | MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ |
|
- | 964 | MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ |
|
- | 965 | MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ |
|
- | 966 | MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */ |
|
- | 967 | MIPI_SEQ_POWER_ON, /* sequence block v3+ */ |
|
- | 968 | MIPI_SEQ_POWER_OFF, /* sequence block v3+ */ |
|
945 | MIPI_SEQ_MAX |
969 | MIPI_SEQ_MAX |
946 | }; |
970 | }; |
947 | 971 | ||
948 | enum mipi_seq_element { |
972 | enum mipi_seq_element { |
949 | MIPI_SEQ_ELEM_UNDEFINED = 0, |
973 | MIPI_SEQ_ELEM_END = 0, |
950 | MIPI_SEQ_ELEM_SEND_PKT, |
974 | MIPI_SEQ_ELEM_SEND_PKT, |
951 | MIPI_SEQ_ELEM_DELAY, |
975 | MIPI_SEQ_ELEM_DELAY, |
952 | MIPI_SEQ_ELEM_GPIO, |
976 | MIPI_SEQ_ELEM_GPIO, |
- | 977 | MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */ |
|
953 | MIPI_SEQ_ELEM_STATUS, |
978 | MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */ |
- | 979 | MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */ |
|
954 | MIPI_SEQ_ELEM_MAX |
980 | MIPI_SEQ_ELEM_MAX |
955 | }; |
981 | }; |
956 | 982 | ||
957 | enum mipi_gpio_pin_index { |
983 | enum mipi_gpio_pin_index { |
958 | MIPI_GPIO_UNDEFINED = 0, |
984 | MIPI_GPIO_UNDEFINED = 0, |
959 | MIPI_GPIO_PANEL_ENABLE, |
985 | MIPI_GPIO_PANEL_ENABLE, |
960 | MIPI_GPIO_BL_ENABLE, |
986 | MIPI_GPIO_BL_ENABLE, |
961 | MIPI_GPIO_PWM_ENABLE, |
987 | MIPI_GPIO_PWM_ENABLE, |
962 | MIPI_GPIO_RESET_N, |
988 | MIPI_GPIO_RESET_N, |
963 | MIPI_GPIO_PWR_DOWN_R, |
989 | MIPI_GPIO_PWR_DOWN_R, |
964 | MIPI_GPIO_STDBY_RST_N, |
990 | MIPI_GPIO_STDBY_RST_N, |
965 | MIPI_GPIO_MAX |
991 | MIPI_GPIO_MAX |
966 | }; |
992 | }; |
967 | 993 | ||
968 | #endif /* _I830_BIOS_H_ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0)><0)>0) |
994 | #endif /* _INTEL_BIOS_H_ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0)><0)>0) |
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1131 | #define><3) |
1106 | #define>3)><3)>3) |
1132 | #define>3)><3)>3) |
1107 | #define><3) |
1133 | #define><3) |
1108 | #define>3) |
1134 | #define>3) |
1109 | #define><3) |
1135 | #define><3) |
1110 | #define>3) |
1136 | #define>3) |
1111 | #define><3) |
1137 | #define><3) |
1112 | #define>7)><7)>->>3) |
1138 | #define>7)><7)>->>3) |
1113 | 1139 | ||
1114 | struct><3) |
1140 | struct><3) |
1115 | 1141 | ||
1116 | struct>>>>>>>>>>> |
1142 | struct> |