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#define BDB_MIPI_SEQUENCE	 53

/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */

#define MODE_MASK		0x3

	/* LVDS Panel channel bits stored here */

	u32 lvds_panel_channel_bits;

	/* LVDS SSC (Spread Spectrum Clock) bits stored here. */

	u16 ssc_bits;

	u16 ssc_freq;

	u16 ssc_ddt;

	/* Panel color depth defined here */

	u16 panel_color_depth;

	/* LVDS panel type bits stored here */

	u32 dps_panel_type_bits;

	/* LVDS backlight control type bits stored here */

	u32 blt_control_type_bits;

} __packed;

#define BDB_BACKLIGHT_TYPE_NONE	0

	u8 custom_vbt_version;

	/* Driver features data block */

	u16 rmpm_enabled:1;

	u16 s2ddt_enabled:1;

	u16 dpst_enabled:1;

	u16 bltclt_enabled:1;

	u16 adb_enabled:1;

	u16 drrs_enabled:1;

	u16 grs_enabled:1;

	u16 gpmt_enabled:1;

	u16 tbt_enabled:1;

	u16 psr_enabled:1;

	u16 ips_enabled:1;

	u16 reserved3:4;

#define DVO_PORT_MIPIA	21

#define DVO_PORT_MIPIB	22

#define DVO_PORT_MIPIC	23

#define DVO_PORT_MIPID	24

/* Block 52 contains MIPI Panel info

 * 6 such enteries will there. Index into correct

 * entery is based on the panel_index in #40 LFP

 */

#define MAX_MIPI_CONFIGURATIONS	6

#define MIPI_DSI_UNDEFINED_PANEL_ID	0

#define MIPI_DSI_GENERIC_PANEL_ID	1

	u32 panel_arch_type:2;

	u32 is_cmd_mode:1;

#define NON_BURST_SYNC_PULSE	0x1

#define NON_BURST_SYNC_EVENTS	0x2

#define BURST_MODE		0x3

	u32 video_transfer_mode:2;

	u32 cabc_supported:1;

	u32 pwm_blc:1;

	/* Bit 13:10 */

#define PIXEL_FORMAT_RGB565			0x1

#define PIXEL_FORMAT_RGB666			0x2

#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3

#define PIXEL_FORMAT_RGB888			0x4

	u32 videomode_color_format:4;

	/* Bit 15:14 */

#define ENABLE_ROTATION_0	0x0

#define ENABLE_ROTATION_90	0x1

#define ENABLE_ROTATION_180	0x2

#define ENABLE_ROTATION_270	0x3

	u32 rotation:2;

	u32 bta_enabled:1;

	u32 rsvd2:15;

	/* 2 byte Port Description */

#define DUAL_LINK_NOT_SUPPORTED	0

#define DUAL_LINK_FRONT_BACK	1

#define DUAL_LINK_PIXEL_ALT	2

	u16 dual_link:2;

	u16 lane_cnt:2;

	u16 rsvd3:12;

	u8 rsvd5[5];

	u32 dsi_ddr_clk;

	u32 bridge_ref_clk;

#define  BYTE_CLK_SEL_20MHZ		0

#define  BYTE_CLK_SEL_10MHZ		1

#define  BYTE_CLK_SEL_5MHZ		2

	u8 byte_clk_sel:2;

	u8 rsvd6:6;

	/* DPHY Flags */

	u16 dphy_param_valid:1;

	u16 eot_pkt_disabled:1;

	u16 enable_clk_stop:1;

	u16 rsvd7:13;

	u32 hs_tx_timeout;

	u32 lp_rx_timeout;

	u32 turn_around_timeout;

	u32 trail_cnt:5;

	u32 rsvd9:3;

	u32 exit_zero_cnt:6;

	u32 rsvd10:2;

	u32 clk_lane_switch_cnt;

	u32 hl_switch_cnt;

	u32 rsvd11[6];

	/* timings based on dphy spec */

	u8 tclk_miss;

	u8 tclk_post;

	u8 rsvd12;

	u8 tclk_pre;

	u8 tclk_prepare;

	u8 tclk_settle;

	u8 tclk_term_enable;

	u8 tclk_trail;

	u16 tclk_prepare_clkzero;

	u8 rsvd13;

	u8 td_term_enable;

	u8 teot;

	u8 ths_exit;

	u8 ths_prepare;

	u16 ths_prepare_hszero;

	u8 rsvd14;

	u8 ths_settle;

	u8 ths_skip;

	u8 ths_trail;

	u8 tinit;

	u8 tlpx;

	u8 rsvd15[3];

	/* GPIOs */

	u8 panel_enable;

	u8 pwm_enable;

	u8 reset_r_n;

	u8 pwr_down_r;

	u8 stdby_r_n;

} __packed;

/* Block 52 contains MIPI configuration block

 * 6 * bdb_mipi_config, followed by 6 pps data

 * block below

 *

 * all delays has a unit of 100us

 */

struct mipi_pps_data {

	u16 panel_on_delay;

	u16 bl_enable_delay;

	u16 bl_disable_delay;

	u16 panel_off_delay;

	u16 panel_power_cycle_delay;

};

struct bdb_mipi_config {

	struct mipi_config config[MAX_MIPI_CONFIGURATIONS];

	struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];

};

/* Block 53 contains MIPI sequences as needed by the panel

 * for enabling it. This block can be variable in size and

 * can be maximum of 6 blocks

 */

struct bdb_mipi_sequence {

	u8 version;

	u8 data[0];

};

/* MIPI Sequnece Block definitions */

enum mipi_seq {

	MIPI_SEQ_UNDEFINED = 0,

	MIPI_SEQ_ASSERT_RESET,

	MIPI_SEQ_INIT_OTP,

	MIPI_SEQ_DISPLAY_ON,

	MIPI_SEQ_DISPLAY_OFF,

	MIPI_SEQ_DEASSERT_RESET,

	MIPI_SEQ_MAX

};

enum mipi_seq_element {

	MIPI_SEQ_ELEM_UNDEFINED = 0,

	MIPI_SEQ_ELEM_SEND_PKT,

	MIPI_SEQ_ELEM_DELAY,

	MIPI_SEQ_ELEM_GPIO,

	MIPI_SEQ_ELEM_STATUS,

	MIPI_SEQ_ELEM_MAX

};

enum mipi_gpio_pin_index {

	MIPI_GPIO_UNDEFINED = 0,

	MIPI_GPIO_PANEL_ENABLE,

	MIPI_GPIO_BL_ENABLE,