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1 | /* |
1 | /* |
2 | * Copyright © 2006 Intel Corporation |
2 | * Copyright © 2006 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
21 | * SOFTWARE. |
21 | * SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #ifndef _I830_BIOS_H_ |
28 | #ifndef _I830_BIOS_H_ |
29 | #define _I830_BIOS_H_ |
29 | #define _I830_BIOS_H_ |
30 | 30 | ||
31 | #include "drmP.h" |
31 | #include "drmP.h" |
32 | 32 | ||
33 | struct vbt_header { |
33 | struct vbt_header { |
34 | u8 signature[20]; /**< Always starts with 'VBT$' */ |
34 | u8 signature[20]; /**< Always starts with 'VBT$' */ |
35 | u16 version; /**< decimal */ |
35 | u16 version; /**< decimal */ |
36 | u16 header_size; /**< in bytes */ |
36 | u16 header_size; /**< in bytes */ |
37 | u16 vbt_size; /**< in bytes */ |
37 | u16 vbt_size; /**< in bytes */ |
38 | u8 vbt_checksum; |
38 | u8 vbt_checksum; |
39 | u8 reserved0; |
39 | u8 reserved0; |
40 | u32 bdb_offset; /**< from beginning of VBT */ |
40 | u32 bdb_offset; /**< from beginning of VBT */ |
41 | u32 aim_offset[4]; /**< from beginning of VBT */ |
41 | u32 aim_offset[4]; /**< from beginning of VBT */ |
42 | } __attribute__((packed)); |
42 | } __attribute__((packed)); |
43 | 43 | ||
44 | struct bdb_header { |
44 | struct bdb_header { |
45 | u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ |
45 | u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ |
46 | u16 version; /**< decimal */ |
46 | u16 version; /**< decimal */ |
47 | u16 header_size; /**< in bytes */ |
47 | u16 header_size; /**< in bytes */ |
48 | u16 bdb_size; /**< in bytes */ |
48 | u16 bdb_size; /**< in bytes */ |
49 | }; |
49 | }; |
50 | 50 | ||
51 | /* strictly speaking, this is a "skip" block, but it has interesting info */ |
51 | /* strictly speaking, this is a "skip" block, but it has interesting info */ |
52 | struct vbios_data { |
52 | struct vbios_data { |
53 | u8 type; /* 0 == desktop, 1 == mobile */ |
53 | u8 type; /* 0 == desktop, 1 == mobile */ |
54 | u8 relstage; |
54 | u8 relstage; |
55 | u8 chipset; |
55 | u8 chipset; |
56 | u8 lvds_present:1; |
56 | u8 lvds_present:1; |
57 | u8 tv_present:1; |
57 | u8 tv_present:1; |
58 | u8 rsvd2:6; /* finish byte */ |
58 | u8 rsvd2:6; /* finish byte */ |
59 | u8 rsvd3[4]; |
59 | u8 rsvd3[4]; |
60 | u8 signon[155]; |
60 | u8 signon[155]; |
61 | u8 copyright[61]; |
61 | u8 copyright[61]; |
62 | u16 code_segment; |
62 | u16 code_segment; |
63 | u8 dos_boot_mode; |
63 | u8 dos_boot_mode; |
64 | u8 bandwidth_percent; |
64 | u8 bandwidth_percent; |
65 | u8 rsvd4; /* popup memory size */ |
65 | u8 rsvd4; /* popup memory size */ |
66 | u8 resize_pci_bios; |
66 | u8 resize_pci_bios; |
67 | u8 rsvd5; /* is crt already on ddc2 */ |
67 | u8 rsvd5; /* is crt already on ddc2 */ |
68 | } __attribute__((packed)); |
68 | } __attribute__((packed)); |
69 | 69 | ||
70 | /* |
70 | /* |
71 | * There are several types of BIOS data blocks (BDBs), each block has |
71 | * There are several types of BIOS data blocks (BDBs), each block has |
72 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
72 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
73 | * Known types are listed below. |
73 | * Known types are listed below. |
74 | */ |
74 | */ |
75 | #define BDB_GENERAL_FEATURES 1 |
75 | #define BDB_GENERAL_FEATURES 1 |
76 | #define BDB_GENERAL_DEFINITIONS 2 |
76 | #define BDB_GENERAL_DEFINITIONS 2 |
77 | #define BDB_OLD_TOGGLE_LIST 3 |
77 | #define BDB_OLD_TOGGLE_LIST 3 |
78 | #define BDB_MODE_SUPPORT_LIST 4 |
78 | #define BDB_MODE_SUPPORT_LIST 4 |
79 | #define BDB_GENERIC_MODE_TABLE 5 |
79 | #define BDB_GENERIC_MODE_TABLE 5 |
80 | #define BDB_EXT_MMIO_REGS 6 |
80 | #define BDB_EXT_MMIO_REGS 6 |
81 | #define BDB_SWF_IO 7 |
81 | #define BDB_SWF_IO 7 |
82 | #define BDB_SWF_MMIO 8 |
82 | #define BDB_SWF_MMIO 8 |
83 | #define BDB_DOT_CLOCK_TABLE 9 |
83 | #define BDB_DOT_CLOCK_TABLE 9 |
84 | #define BDB_MODE_REMOVAL_TABLE 10 |
84 | #define BDB_MODE_REMOVAL_TABLE 10 |
85 | #define BDB_CHILD_DEVICE_TABLE 11 |
85 | #define BDB_CHILD_DEVICE_TABLE 11 |
86 | #define BDB_DRIVER_FEATURES 12 |
86 | #define BDB_DRIVER_FEATURES 12 |
87 | #define BDB_DRIVER_PERSISTENCE 13 |
87 | #define BDB_DRIVER_PERSISTENCE 13 |
88 | #define BDB_EXT_TABLE_PTRS 14 |
88 | #define BDB_EXT_TABLE_PTRS 14 |
89 | #define BDB_DOT_CLOCK_OVERRIDE 15 |
89 | #define BDB_DOT_CLOCK_OVERRIDE 15 |
90 | #define BDB_DISPLAY_SELECT 16 |
90 | #define BDB_DISPLAY_SELECT 16 |
91 | /* 17 rsvd */ |
91 | /* 17 rsvd */ |
92 | #define BDB_DRIVER_ROTATION 18 |
92 | #define BDB_DRIVER_ROTATION 18 |
93 | #define BDB_DISPLAY_REMOVE 19 |
93 | #define BDB_DISPLAY_REMOVE 19 |
94 | #define BDB_OEM_CUSTOM 20 |
94 | #define BDB_OEM_CUSTOM 20 |
95 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ |
95 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ |
96 | #define BDB_SDVO_LVDS_OPTIONS 22 |
96 | #define BDB_SDVO_LVDS_OPTIONS 22 |
97 | #define BDB_SDVO_PANEL_DTDS 23 |
97 | #define BDB_SDVO_PANEL_DTDS 23 |
98 | #define BDB_SDVO_LVDS_PNP_IDS 24 |
98 | #define BDB_SDVO_LVDS_PNP_IDS 24 |
99 | #define BDB_SDVO_LVDS_POWER_SEQ 25 |
99 | #define BDB_SDVO_LVDS_POWER_SEQ 25 |
100 | #define BDB_TV_OPTIONS 26 |
100 | #define BDB_TV_OPTIONS 26 |
101 | #define BDB_EDP 27 |
101 | #define BDB_EDP 27 |
102 | #define BDB_LVDS_OPTIONS 40 |
102 | #define BDB_LVDS_OPTIONS 40 |
103 | #define BDB_LVDS_LFP_DATA_PTRS 41 |
103 | #define BDB_LVDS_LFP_DATA_PTRS 41 |
104 | #define BDB_LVDS_LFP_DATA 42 |
104 | #define BDB_LVDS_LFP_DATA 42 |
105 | #define BDB_LVDS_BACKLIGHT 43 |
105 | #define BDB_LVDS_BACKLIGHT 43 |
106 | #define BDB_LVDS_POWER 44 |
106 | #define BDB_LVDS_POWER 44 |
107 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
107 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
108 | 108 | ||
109 | struct bdb_general_features { |
109 | struct bdb_general_features { |
110 | /* bits 1 */ |
110 | /* bits 1 */ |
111 | u8 panel_fitting:2; |
111 | u8 panel_fitting:2; |
112 | u8 flexaim:1; |
112 | u8 flexaim:1; |
113 | u8 msg_enable:1; |
113 | u8 msg_enable:1; |
114 | u8 clear_screen:3; |
114 | u8 clear_screen:3; |
115 | u8 color_flip:1; |
115 | u8 color_flip:1; |
116 | 116 | ||
117 | /* bits 2 */ |
117 | /* bits 2 */ |
118 | u8 download_ext_vbt:1; |
118 | u8 download_ext_vbt:1; |
119 | u8 enable_ssc:1; |
119 | u8 enable_ssc:1; |
120 | u8 ssc_freq:1; |
120 | u8 ssc_freq:1; |
121 | u8 enable_lfp_on_override:1; |
121 | u8 enable_lfp_on_override:1; |
122 | u8 disable_ssc_ddt:1; |
122 | u8 disable_ssc_ddt:1; |
- | 123 | u8 rsvd7:1; |
|
- | 124 | u8 display_clock_mode:1; |
|
123 | u8 rsvd8:3; /* finish byte */ |
125 | u8 rsvd8:1; /* finish byte */ |
124 | 126 | ||
125 | /* bits 3 */ |
127 | /* bits 3 */ |
126 | u8 disable_smooth_vision:1; |
128 | u8 disable_smooth_vision:1; |
127 | u8 single_dvi:1; |
129 | u8 single_dvi:1; |
128 | u8 rsvd9:6; /* finish byte */ |
130 | u8 rsvd9:6; /* finish byte */ |
129 | 131 | ||
130 | /* bits 4 */ |
132 | /* bits 4 */ |
131 | u8 legacy_monitor_detect; |
133 | u8 legacy_monitor_detect; |
132 | 134 | ||
133 | /* bits 5 */ |
135 | /* bits 5 */ |
134 | u8 int_crt_support:1; |
136 | u8 int_crt_support:1; |
135 | u8 int_tv_support:1; |
137 | u8 int_tv_support:1; |
- | 138 | u8 int_efp_support:1; |
|
- | 139 | u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ |
|
- | 140 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
|
136 | u8 rsvd11:6; /* finish byte */ |
141 | u8 rsvd11:3; /* finish byte */ |
137 | } __attribute__((packed)); |
142 | } __attribute__((packed)); |
138 | 143 | ||
139 | /* pre-915 */ |
144 | /* pre-915 */ |
140 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
145 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
141 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
146 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
142 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
147 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
143 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
148 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
144 | 149 | ||
145 | /* Pre 915 */ |
150 | /* Pre 915 */ |
146 | #define DEVICE_TYPE_NONE 0x00 |
151 | #define DEVICE_TYPE_NONE 0x00 |
147 | #define DEVICE_TYPE_CRT 0x01 |
152 | #define DEVICE_TYPE_CRT 0x01 |
148 | #define DEVICE_TYPE_TV 0x09 |
153 | #define DEVICE_TYPE_TV 0x09 |
149 | #define DEVICE_TYPE_EFP 0x12 |
154 | #define DEVICE_TYPE_EFP 0x12 |
150 | #define DEVICE_TYPE_LFP 0x22 |
155 | #define DEVICE_TYPE_LFP 0x22 |
151 | /* On 915+ */ |
156 | /* On 915+ */ |
152 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
157 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
153 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
158 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
154 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
159 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
155 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
160 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
156 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
161 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
157 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
162 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
158 | #define DEVICE_TYPE_TV_SCART 0x0209 |
163 | #define DEVICE_TYPE_TV_SCART 0x0209 |
159 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
164 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
160 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
165 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
161 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
166 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
162 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
167 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
163 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
168 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
164 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
169 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
165 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
170 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
166 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
171 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
167 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
172 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
168 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
173 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
169 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
174 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
170 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
175 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
171 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
176 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
172 | 177 | ||
173 | #define DEVICE_CFG_NONE 0x00 |
178 | #define DEVICE_CFG_NONE 0x00 |
174 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
179 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
175 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
180 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
176 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
181 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
177 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
182 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
178 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
183 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
179 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
184 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
180 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
185 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
181 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
186 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
182 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
187 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
183 | 188 | ||
184 | #define DEVICE_WIRE_NONE 0x00 |
189 | #define DEVICE_WIRE_NONE 0x00 |
185 | #define DEVICE_WIRE_DVOB 0x01 |
190 | #define DEVICE_WIRE_DVOB 0x01 |
186 | #define DEVICE_WIRE_DVOC 0x02 |
191 | #define DEVICE_WIRE_DVOC 0x02 |
187 | #define DEVICE_WIRE_DVOBC 0x03 |
192 | #define DEVICE_WIRE_DVOBC 0x03 |
188 | #define DEVICE_WIRE_DVOBB 0x05 |
193 | #define DEVICE_WIRE_DVOBB 0x05 |
189 | #define DEVICE_WIRE_DVOCC 0x06 |
194 | #define DEVICE_WIRE_DVOCC 0x06 |
190 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
195 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
191 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
196 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
192 | 197 | ||
193 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
198 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
194 | #define DEVICE_PORT_DVOB 0x01 |
199 | #define DEVICE_PORT_DVOB 0x01 |
195 | #define DEVICE_PORT_DVOC 0x02 |
200 | #define DEVICE_PORT_DVOC 0x02 |
196 | 201 | ||
197 | struct child_device_config { |
202 | struct child_device_config { |
198 | u16 handle; |
203 | u16 handle; |
199 | u16 device_type; |
204 | u16 device_type; |
200 | u8 i2c_speed; |
- | |
201 | u8 rsvd[9]; |
205 | u8 device_id[10]; /* ascii string */ |
202 | u16 addin_offset; |
206 | u16 addin_offset; |
203 | u8 dvo_port; /* See Device_PORT_* above */ |
207 | u8 dvo_port; /* See Device_PORT_* above */ |
204 | u8 i2c_pin; |
208 | u8 i2c_pin; |
205 | u8 slave_addr; |
209 | u8 slave_addr; |
206 | u8 ddc_pin; |
210 | u8 ddc_pin; |
207 | u16 edid_ptr; |
211 | u16 edid_ptr; |
208 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
212 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
209 | u8 dvo2_port; |
213 | u8 dvo2_port; |
210 | u8 i2c2_pin; |
214 | u8 i2c2_pin; |
211 | u8 slave2_addr; |
215 | u8 slave2_addr; |
212 | u8 ddc2_pin; |
216 | u8 ddc2_pin; |
213 | u8 capabilities; |
217 | u8 capabilities; |
214 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ |
218 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ |
215 | u8 dvo2_wiring; |
219 | u8 dvo2_wiring; |
216 | u16 extended_type; |
220 | u16 extended_type; |
217 | u8 dvo_function; |
221 | u8 dvo_function; |
218 | } __attribute__((packed)); |
222 | } __attribute__((packed)); |
219 | 223 | ||
220 | struct bdb_general_definitions { |
224 | struct bdb_general_definitions { |
221 | /* DDC GPIO */ |
225 | /* DDC GPIO */ |
222 | u8 crt_ddc_gmbus_pin; |
226 | u8 crt_ddc_gmbus_pin; |
223 | 227 | ||
224 | /* DPMS bits */ |
228 | /* DPMS bits */ |
225 | u8 dpms_acpi:1; |
229 | u8 dpms_acpi:1; |
226 | u8 skip_boot_crt_detect:1; |
230 | u8 skip_boot_crt_detect:1; |
227 | u8 dpms_aim:1; |
231 | u8 dpms_aim:1; |
228 | u8 rsvd1:5; /* finish byte */ |
232 | u8 rsvd1:5; /* finish byte */ |
229 | 233 | ||
230 | /* boot device bits */ |
234 | /* boot device bits */ |
231 | u8 boot_display[2]; |
235 | u8 boot_display[2]; |
232 | u8 child_dev_size; |
236 | u8 child_dev_size; |
233 | 237 | ||
234 | /* |
238 | /* |
235 | * Device info: |
239 | * Device info: |
236 | * If TV is present, it'll be at devices[0]. |
240 | * If TV is present, it'll be at devices[0]. |
237 | * LVDS will be next, either devices[0] or [1], if present. |
241 | * LVDS will be next, either devices[0] or [1], if present. |
238 | * On some platforms the number of device is 6. But could be as few as |
242 | * On some platforms the number of device is 6. But could be as few as |
239 | * 4 if both TV and LVDS are missing. |
243 | * 4 if both TV and LVDS are missing. |
240 | * And the device num is related with the size of general definition |
244 | * And the device num is related with the size of general definition |
241 | * block. It is obtained by using the following formula: |
245 | * block. It is obtained by using the following formula: |
242 | * number = (block_size - sizeof(bdb_general_definitions))/ |
246 | * number = (block_size - sizeof(bdb_general_definitions))/ |
243 | * sizeof(child_device_config); |
247 | * sizeof(child_device_config); |
244 | */ |
248 | */ |
245 | struct child_device_config devices[0]; |
249 | struct child_device_config devices[0]; |
246 | } __attribute__((packed)); |
250 | } __attribute__((packed)); |
247 | 251 | ||
248 | struct bdb_lvds_options { |
252 | struct bdb_lvds_options { |
249 | u8 panel_type; |
253 | u8 panel_type; |
250 | u8 rsvd1; |
254 | u8 rsvd1; |
251 | /* LVDS capabilities, stored in a dword */ |
255 | /* LVDS capabilities, stored in a dword */ |
252 | u8 pfit_mode:2; |
256 | u8 pfit_mode:2; |
253 | u8 pfit_text_mode_enhanced:1; |
257 | u8 pfit_text_mode_enhanced:1; |
254 | u8 pfit_gfx_mode_enhanced:1; |
258 | u8 pfit_gfx_mode_enhanced:1; |
255 | u8 pfit_ratio_auto:1; |
259 | u8 pfit_ratio_auto:1; |
256 | u8 pixel_dither:1; |
260 | u8 pixel_dither:1; |
257 | u8 lvds_edid:1; |
261 | u8 lvds_edid:1; |
258 | u8 rsvd2:1; |
262 | u8 rsvd2:1; |
259 | u8 rsvd4; |
263 | u8 rsvd4; |
260 | } __attribute__((packed)); |
264 | } __attribute__((packed)); |
261 | 265 | ||
262 | /* LFP pointer table contains entries to the struct below */ |
266 | /* LFP pointer table contains entries to the struct below */ |
263 | struct bdb_lvds_lfp_data_ptr { |
267 | struct bdb_lvds_lfp_data_ptr { |
264 | u16 fp_timing_offset; /* offsets are from start of bdb */ |
268 | u16 fp_timing_offset; /* offsets are from start of bdb */ |
265 | u8 fp_table_size; |
269 | u8 fp_table_size; |
266 | u16 dvo_timing_offset; |
270 | u16 dvo_timing_offset; |
267 | u8 dvo_table_size; |
271 | u8 dvo_table_size; |
268 | u16 panel_pnp_id_offset; |
272 | u16 panel_pnp_id_offset; |
269 | u8 pnp_table_size; |
273 | u8 pnp_table_size; |
270 | } __attribute__((packed)); |
274 | } __attribute__((packed)); |
271 | 275 | ||
272 | struct bdb_lvds_lfp_data_ptrs { |
276 | struct bdb_lvds_lfp_data_ptrs { |
273 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ |
277 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ |
274 | struct bdb_lvds_lfp_data_ptr ptr[16]; |
278 | struct bdb_lvds_lfp_data_ptr ptr[16]; |
275 | } __attribute__((packed)); |
279 | } __attribute__((packed)); |
276 | 280 | ||
277 | /* LFP data has 3 blocks per entry */ |
281 | /* LFP data has 3 blocks per entry */ |
278 | struct lvds_fp_timing { |
282 | struct lvds_fp_timing { |
279 | u16 x_res; |
283 | u16 x_res; |
280 | u16 y_res; |
284 | u16 y_res; |
281 | u32 lvds_reg; |
285 | u32 lvds_reg; |
282 | u32 lvds_reg_val; |
286 | u32 lvds_reg_val; |
283 | u32 pp_on_reg; |
287 | u32 pp_on_reg; |
284 | u32 pp_on_reg_val; |
288 | u32 pp_on_reg_val; |
285 | u32 pp_off_reg; |
289 | u32 pp_off_reg; |
286 | u32 pp_off_reg_val; |
290 | u32 pp_off_reg_val; |
287 | u32 pp_cycle_reg; |
291 | u32 pp_cycle_reg; |
288 | u32 pp_cycle_reg_val; |
292 | u32 pp_cycle_reg_val; |
289 | u32 pfit_reg; |
293 | u32 pfit_reg; |
290 | u32 pfit_reg_val; |
294 | u32 pfit_reg_val; |
291 | u16 terminator; |
295 | u16 terminator; |
292 | } __attribute__((packed)); |
296 | } __attribute__((packed)); |
293 | 297 | ||
294 | struct lvds_dvo_timing { |
298 | struct lvds_dvo_timing { |
295 | u16 clock; /**< In 10khz */ |
299 | u16 clock; /**< In 10khz */ |
296 | u8 hactive_lo; |
300 | u8 hactive_lo; |
297 | u8 hblank_lo; |
301 | u8 hblank_lo; |
298 | u8 hblank_hi:4; |
302 | u8 hblank_hi:4; |
299 | u8 hactive_hi:4; |
303 | u8 hactive_hi:4; |
300 | u8 vactive_lo; |
304 | u8 vactive_lo; |
301 | u8 vblank_lo; |
305 | u8 vblank_lo; |
302 | u8 vblank_hi:4; |
306 | u8 vblank_hi:4; |
303 | u8 vactive_hi:4; |
307 | u8 vactive_hi:4; |
304 | u8 hsync_off_lo; |
308 | u8 hsync_off_lo; |
305 | u8 hsync_pulse_width; |
309 | u8 hsync_pulse_width; |
306 | u8 vsync_pulse_width:4; |
310 | u8 vsync_pulse_width:4; |
307 | u8 vsync_off:4; |
311 | u8 vsync_off:4; |
308 | u8 rsvd0:6; |
312 | u8 rsvd0:6; |
309 | u8 hsync_off_hi:2; |
313 | u8 hsync_off_hi:2; |
310 | u8 h_image; |
314 | u8 h_image; |
311 | u8 v_image; |
315 | u8 v_image; |
312 | u8 max_hv; |
316 | u8 max_hv; |
313 | u8 h_border; |
317 | u8 h_border; |
314 | u8 v_border; |
318 | u8 v_border; |
315 | u8 rsvd1:3; |
319 | u8 rsvd1:3; |
316 | u8 digital:2; |
320 | u8 digital:2; |
317 | u8 vsync_positive:1; |
321 | u8 vsync_positive:1; |
318 | u8 hsync_positive:1; |
322 | u8 hsync_positive:1; |
319 | u8 rsvd2:1; |
323 | u8 rsvd2:1; |
320 | } __attribute__((packed)); |
324 | } __attribute__((packed)); |
321 | 325 | ||
322 | struct lvds_pnp_id { |
326 | struct lvds_pnp_id { |
323 | u16 mfg_name; |
327 | u16 mfg_name; |
324 | u16 product_code; |
328 | u16 product_code; |
325 | u32 serial; |
329 | u32 serial; |
326 | u8 mfg_week; |
330 | u8 mfg_week; |
327 | u8 mfg_year; |
331 | u8 mfg_year; |
328 | } __attribute__((packed)); |
332 | } __attribute__((packed)); |
329 | 333 | ||
330 | struct bdb_lvds_lfp_data_entry { |
334 | struct bdb_lvds_lfp_data_entry { |
331 | struct lvds_fp_timing fp_timing; |
335 | struct lvds_fp_timing fp_timing; |
332 | struct lvds_dvo_timing dvo_timing; |
336 | struct lvds_dvo_timing dvo_timing; |
333 | struct lvds_pnp_id pnp_id; |
337 | struct lvds_pnp_id pnp_id; |
334 | } __attribute__((packed)); |
338 | } __attribute__((packed)); |
335 | 339 | ||
336 | struct bdb_lvds_lfp_data { |
340 | struct bdb_lvds_lfp_data { |
337 | struct bdb_lvds_lfp_data_entry data[16]; |
341 | struct bdb_lvds_lfp_data_entry data[16]; |
338 | } __attribute__((packed)); |
342 | } __attribute__((packed)); |
339 | 343 | ||
340 | struct aimdb_header { |
344 | struct aimdb_header { |
341 | char signature[16]; |
345 | char signature[16]; |
342 | char oem_device[20]; |
346 | char oem_device[20]; |
343 | u16 aimdb_version; |
347 | u16 aimdb_version; |
344 | u16 aimdb_header_size; |
348 | u16 aimdb_header_size; |
345 | u16 aimdb_size; |
349 | u16 aimdb_size; |
346 | } __attribute__((packed)); |
350 | } __attribute__((packed)); |
347 | 351 | ||
348 | struct aimdb_block { |
352 | struct aimdb_block { |
349 | u8 aimdb_id; |
353 | u8 aimdb_id; |
350 | u16 aimdb_size; |
354 | u16 aimdb_size; |
351 | } __attribute__((packed)); |
355 | } __attribute__((packed)); |
352 | 356 | ||
353 | struct vch_panel_data { |
357 | struct vch_panel_data { |
354 | u16 fp_timing_offset; |
358 | u16 fp_timing_offset; |
355 | u8 fp_timing_size; |
359 | u8 fp_timing_size; |
356 | u16 dvo_timing_offset; |
360 | u16 dvo_timing_offset; |
357 | u8 dvo_timing_size; |
361 | u8 dvo_timing_size; |
358 | u16 text_fitting_offset; |
362 | u16 text_fitting_offset; |
359 | u8 text_fitting_size; |
363 | u8 text_fitting_size; |
360 | u16 graphics_fitting_offset; |
364 | u16 graphics_fitting_offset; |
361 | u8 graphics_fitting_size; |
365 | u8 graphics_fitting_size; |
362 | } __attribute__((packed)); |
366 | } __attribute__((packed)); |
363 | 367 | ||
364 | struct vch_bdb_22 { |
368 | struct vch_bdb_22 { |
365 | struct aimdb_block aimdb_block; |
369 | struct aimdb_block aimdb_block; |
366 | struct vch_panel_data panels[16]; |
370 | struct vch_panel_data panels[16]; |
367 | } __attribute__((packed)); |
371 | } __attribute__((packed)); |
368 | 372 | ||
369 | struct bdb_sdvo_lvds_options { |
373 | struct bdb_sdvo_lvds_options { |
370 | u8 panel_backlight; |
374 | u8 panel_backlight; |
371 | u8 h40_set_panel_type; |
375 | u8 h40_set_panel_type; |
372 | u8 panel_type; |
376 | u8 panel_type; |
373 | u8 ssc_clk_freq; |
377 | u8 ssc_clk_freq; |
374 | u16 als_low_trip; |
378 | u16 als_low_trip; |
375 | u16 als_high_trip; |
379 | u16 als_high_trip; |
376 | u8 sclalarcoeff_tab_row_num; |
380 | u8 sclalarcoeff_tab_row_num; |
377 | u8 sclalarcoeff_tab_row_size; |
381 | u8 sclalarcoeff_tab_row_size; |
378 | u8 coefficient[8]; |
382 | u8 coefficient[8]; |
379 | u8 panel_misc_bits_1; |
383 | u8 panel_misc_bits_1; |
380 | u8 panel_misc_bits_2; |
384 | u8 panel_misc_bits_2; |
381 | u8 panel_misc_bits_3; |
385 | u8 panel_misc_bits_3; |
382 | u8 panel_misc_bits_4; |
386 | u8 panel_misc_bits_4; |
383 | } __attribute__((packed)); |
387 | } __attribute__((packed)); |
384 | 388 | ||
385 | 389 | ||
386 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
390 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
387 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
391 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
388 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
392 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
389 | #define BDB_DRIVER_FEATURE_EDP 3 |
393 | #define BDB_DRIVER_FEATURE_EDP 3 |
390 | 394 | ||
391 | struct bdb_driver_features { |
395 | struct bdb_driver_features { |
392 | u8 boot_dev_algorithm:1; |
396 | u8 boot_dev_algorithm:1; |
393 | u8 block_display_switch:1; |
397 | u8 block_display_switch:1; |
394 | u8 allow_display_switch:1; |
398 | u8 allow_display_switch:1; |
395 | u8 hotplug_dvo:1; |
399 | u8 hotplug_dvo:1; |
396 | u8 dual_view_zoom:1; |
400 | u8 dual_view_zoom:1; |
397 | u8 int15h_hook:1; |
401 | u8 int15h_hook:1; |
398 | u8 sprite_in_clone:1; |
402 | u8 sprite_in_clone:1; |
399 | u8 primary_lfp_id:1; |
403 | u8 primary_lfp_id:1; |
400 | 404 | ||
401 | u16 boot_mode_x; |
405 | u16 boot_mode_x; |
402 | u16 boot_mode_y; |
406 | u16 boot_mode_y; |
403 | u8 boot_mode_bpp; |
407 | u8 boot_mode_bpp; |
404 | u8 boot_mode_refresh; |
408 | u8 boot_mode_refresh; |
405 | 409 | ||
406 | u16 enable_lfp_primary:1; |
410 | u16 enable_lfp_primary:1; |
407 | u16 selective_mode_pruning:1; |
411 | u16 selective_mode_pruning:1; |
408 | u16 dual_frequency:1; |
412 | u16 dual_frequency:1; |
409 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
413 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
410 | u16 nt_clone_support:1; |
414 | u16 nt_clone_support:1; |
411 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
415 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
412 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
416 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
413 | u16 cui_aspect_scaling:1; |
417 | u16 cui_aspect_scaling:1; |
414 | u16 preserve_aspect_ratio:1; |
418 | u16 preserve_aspect_ratio:1; |
415 | u16 sdvo_device_power_down:1; |
419 | u16 sdvo_device_power_down:1; |
416 | u16 crt_hotplug:1; |
420 | u16 crt_hotplug:1; |
417 | u16 lvds_config:2; |
421 | u16 lvds_config:2; |
418 | u16 tv_hotplug:1; |
422 | u16 tv_hotplug:1; |
419 | u16 hdmi_config:2; |
423 | u16 hdmi_config:2; |
420 | 424 | ||
421 | u8 static_display:1; |
425 | u8 static_display:1; |
422 | u8 reserved2:7; |
426 | u8 reserved2:7; |
423 | u16 legacy_crt_max_x; |
427 | u16 legacy_crt_max_x; |
424 | u16 legacy_crt_max_y; |
428 | u16 legacy_crt_max_y; |
425 | u8 legacy_crt_max_refresh; |
429 | u8 legacy_crt_max_refresh; |
426 | 430 | ||
427 | u8 hdmi_termination; |
431 | u8 hdmi_termination; |
428 | u8 custom_vbt_version; |
432 | u8 custom_vbt_version; |
429 | } __attribute__((packed)); |
433 | } __attribute__((packed)); |
430 | 434 | ||
431 | #define EDP_18BPP 0 |
435 | #define EDP_18BPP 0 |
432 | #define EDP_24BPP 1 |
436 | #define EDP_24BPP 1 |
433 | #define EDP_30BPP 2 |
437 | #define EDP_30BPP 2 |
434 | #define EDP_RATE_1_62 0 |
438 | #define EDP_RATE_1_62 0 |
435 | #define EDP_RATE_2_7 1 |
439 | #define EDP_RATE_2_7 1 |
436 | #define EDP_LANE_1 0 |
440 | #define EDP_LANE_1 0 |
437 | #define EDP_LANE_2 1 |
441 | #define EDP_LANE_2 1 |
438 | #define EDP_LANE_4 3 |
442 | #define EDP_LANE_4 3 |
439 | #define EDP_PREEMPHASIS_NONE 0 |
443 | #define EDP_PREEMPHASIS_NONE 0 |
440 | #define EDP_PREEMPHASIS_3_5dB 1 |
444 | #define EDP_PREEMPHASIS_3_5dB 1 |
441 | #define EDP_PREEMPHASIS_6dB 2 |
445 | #define EDP_PREEMPHASIS_6dB 2 |
442 | #define EDP_PREEMPHASIS_9_5dB 3 |
446 | #define EDP_PREEMPHASIS_9_5dB 3 |
443 | #define EDP_VSWING_0_4V 0 |
447 | #define EDP_VSWING_0_4V 0 |
444 | #define EDP_VSWING_0_6V 1 |
448 | #define EDP_VSWING_0_6V 1 |
445 | #define EDP_VSWING_0_8V 2 |
449 | #define EDP_VSWING_0_8V 2 |
446 | #define EDP_VSWING_1_2V 3 |
450 | #define EDP_VSWING_1_2V 3 |
447 | 451 | ||
448 | struct edp_power_seq { |
452 | struct edp_power_seq { |
449 | u16 t3; |
453 | u16 t1_t3; |
450 | u16 t7; |
454 | u16 t8; |
451 | u16 t9; |
455 | u16 t9; |
452 | u16 t10; |
456 | u16 t10; |
453 | u16 t12; |
457 | u16 t11_t12; |
454 | } __attribute__ ((packed)); |
458 | } __attribute__ ((packed)); |
455 | 459 | ||
456 | struct edp_link_params { |
460 | struct edp_link_params { |
457 | u8 rate:4; |
461 | u8 rate:4; |
458 | u8 lanes:4; |
462 | u8 lanes:4; |
459 | u8 preemphasis:4; |
463 | u8 preemphasis:4; |
460 | u8 vswing:4; |
464 | u8 vswing:4; |
461 | } __attribute__ ((packed)); |
465 | } __attribute__ ((packed)); |
462 | 466 | ||
463 | struct bdb_edp { |
467 | struct bdb_edp { |
464 | struct edp_power_seq power_seqs[16]; |
468 | struct edp_power_seq power_seqs[16]; |
465 | u32 color_depth; |
469 | u32 color_depth; |
466 | u32 sdrrs_msa_timing_delay; |
- | |
467 | struct edp_link_params link_params[16]; |
470 | struct edp_link_params link_params[16]; |
- | 471 | u32 sdrrs_msa_timing_delay; |
|
- | 472 | ||
- | 473 | /* ith bit indicates enabled/disabled for (i+1)th panel */ |
|
- | 474 | u16 edp_s3d_feature; |
|
- | 475 | u16 edp_t3_optimization; |
|
468 | } __attribute__ ((packed)); |
476 | } __attribute__ ((packed)); |
469 | 477 | ||
470 | void intel_setup_bios(struct drm_device *dev); |
478 | void intel_setup_bios(struct drm_device *dev); |
471 | bool intel_parse_bios(struct drm_device *dev); |
479 | bool intel_parse_bios(struct drm_device *dev); |
472 | 480 | ||
473 | /* |
481 | /* |
474 | * Driver<->VBIOS interaction occurs through scratch bits in |
482 | * Driver<->VBIOS interaction occurs through scratch bits in |
475 | * GR18 & SWF*. |
483 | * GR18 & SWF*. |
476 | */ |
484 | */ |
477 | 485 | ||
478 | /* GR18 bits are set on display switch and hotkey events */ |
486 | /* GR18 bits are set on display switch and hotkey events */ |
479 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ |
487 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ |
480 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ |
488 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ |
481 | #define GR18_HK_NONE (0x0<<3) |
489 | #define GR18_HK_NONE (0x0<<3) |
482 | #define GR18_HK_LFP_STRETCH (0x1<<3) |
490 | #define GR18_HK_LFP_STRETCH (0x1<<3) |
483 | #define GR18_HK_TOGGLE_DISP (0x2<<3) |
491 | #define GR18_HK_TOGGLE_DISP (0x2<<3) |
484 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ |
492 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ |
485 | #define GR18_HK_POPUP_DISABLED (0x6<<3) |
493 | #define GR18_HK_POPUP_DISABLED (0x6<<3) |
486 | #define GR18_HK_POPUP_ENABLED (0x7<<3) |
494 | #define GR18_HK_POPUP_ENABLED (0x7<<3) |
487 | #define GR18_HK_PFIT (0x8<<3) |
495 | #define GR18_HK_PFIT (0x8<<3) |
488 | #define GR18_HK_APM_CHANGE (0xa<<3) |
496 | #define GR18_HK_APM_CHANGE (0xa<<3) |
489 | #define GR18_HK_MULTIPLE (0xc<<3) |
497 | #define GR18_HK_MULTIPLE (0xc<<3) |
490 | #define GR18_USER_INT_EN (1<<2) |
498 | #define GR18_USER_INT_EN (1<<2) |
491 | #define GR18_A0000_FLUSH_EN (1<<1) |
499 | #define GR18_A0000_FLUSH_EN (1<<1) |
492 | #define GR18_SMM_EN (1<<0) |
500 | #define GR18_SMM_EN (1<<0) |
493 | 501 | ||
494 | /* Set by driver, cleared by VBIOS */ |
502 | /* Set by driver, cleared by VBIOS */ |
495 | #define SWF00_YRES_SHIFT 16 |
503 | #define SWF00_YRES_SHIFT 16 |
496 | #define SWF00_XRES_SHIFT 0 |
504 | #define SWF00_XRES_SHIFT 0 |
497 | #define SWF00_RES_MASK 0xffff |
505 | #define SWF00_RES_MASK 0xffff |
498 | 506 | ||
499 | /* Set by VBIOS at boot time and driver at runtime */ |
507 | /* Set by VBIOS at boot time and driver at runtime */ |
500 | #define SWF01_TV2_FORMAT_SHIFT 8 |
508 | #define SWF01_TV2_FORMAT_SHIFT 8 |
501 | #define SWF01_TV1_FORMAT_SHIFT 0 |
509 | #define SWF01_TV1_FORMAT_SHIFT 0 |
502 | #define SWF01_TV_FORMAT_MASK 0xffff |
510 | #define SWF01_TV_FORMAT_MASK 0xffff |
503 | 511 | ||
504 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) |
512 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) |
505 | #define SWF10_GTT_OVERRIDE_EN (1<<28) |
513 | #define SWF10_GTT_OVERRIDE_EN (1<<28) |
506 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ |
514 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ |
507 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) |
515 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) |
508 | #define SWF10_OLD_TOGGLE 0x0 |
516 | #define SWF10_OLD_TOGGLE 0x0 |
509 | #define SWF10_TOGGLE_LIST_1 0x1 |
517 | #define SWF10_TOGGLE_LIST_1 0x1 |
510 | #define SWF10_TOGGLE_LIST_2 0x2 |
518 | #define SWF10_TOGGLE_LIST_2 0x2 |
511 | #define SWF10_TOGGLE_LIST_3 0x3 |
519 | #define SWF10_TOGGLE_LIST_3 0x3 |
512 | #define SWF10_TOGGLE_LIST_4 0x4 |
520 | #define SWF10_TOGGLE_LIST_4 0x4 |
513 | #define SWF10_PANNING_EN (1<<23) |
521 | #define SWF10_PANNING_EN (1<<23) |
514 | #define SWF10_DRIVER_LOADED (1<<22) |
522 | #define SWF10_DRIVER_LOADED (1<<22) |
515 | #define SWF10_EXTENDED_DESKTOP (1<<21) |
523 | #define SWF10_EXTENDED_DESKTOP (1<<21) |
516 | #define SWF10_EXCLUSIVE_MODE (1<<20) |
524 | #define SWF10_EXCLUSIVE_MODE (1<<20) |
517 | #define SWF10_OVERLAY_EN (1<<19) |
525 | #define SWF10_OVERLAY_EN (1<<19) |
518 | #define SWF10_PLANEB_HOLDOFF (1<<18) |
526 | #define SWF10_PLANEB_HOLDOFF (1<<18) |
519 | #define SWF10_PLANEA_HOLDOFF (1<<17) |
527 | #define SWF10_PLANEA_HOLDOFF (1<<17) |
520 | #define SWF10_VGA_HOLDOFF (1<<16) |
528 | #define SWF10_VGA_HOLDOFF (1<<16) |
521 | #define SWF10_ACTIVE_DISP_MASK 0xffff |
529 | #define SWF10_ACTIVE_DISP_MASK 0xffff |
522 | #define SWF10_PIPEB_LFP2 (1<<15) |
530 | #define SWF10_PIPEB_LFP2 (1<<15) |
523 | #define SWF10_PIPEB_EFP2 (1<<14) |
531 | #define SWF10_PIPEB_EFP2 (1<<14) |
524 | #define SWF10_PIPEB_TV2 (1<<13) |
532 | #define SWF10_PIPEB_TV2 (1<<13) |
525 | #define SWF10_PIPEB_CRT2 (1<<12) |
533 | #define SWF10_PIPEB_CRT2 (1<<12) |
526 | #define SWF10_PIPEB_LFP (1<<11) |
534 | #define SWF10_PIPEB_LFP (1<<11) |
527 | #define SWF10_PIPEB_EFP (1<<10) |
535 | #define SWF10_PIPEB_EFP (1<<10) |
528 | #define SWF10_PIPEB_TV (1<<9) |
536 | #define SWF10_PIPEB_TV (1<<9) |
529 | #define SWF10_PIPEB_CRT (1<<8) |
537 | #define SWF10_PIPEB_CRT (1<<8) |
530 | #define SWF10_PIPEA_LFP2 (1<<7) |
538 | #define SWF10_PIPEA_LFP2 (1<<7) |
531 | #define SWF10_PIPEA_EFP2 (1<<6) |
539 | #define SWF10_PIPEA_EFP2 (1<<6) |
532 | #define SWF10_PIPEA_TV2 (1<<5) |
540 | #define SWF10_PIPEA_TV2 (1<<5) |
533 | #define SWF10_PIPEA_CRT2 (1<<4) |
541 | #define SWF10_PIPEA_CRT2 (1<<4) |
534 | #define SWF10_PIPEA_LFP (1<<3) |
542 | #define SWF10_PIPEA_LFP (1<<3) |
535 | #define SWF10_PIPEA_EFP (1<<2) |
543 | #define SWF10_PIPEA_EFP (1<<2) |
536 | #define SWF10_PIPEA_TV (1<<1) |
544 | #define SWF10_PIPEA_TV (1<<1) |
537 | #define SWF10_PIPEA_CRT (1<<0) |
545 | #define SWF10_PIPEA_CRT (1<<0) |
538 | 546 | ||
539 | #define SWF11_MEMORY_SIZE_SHIFT 16 |
547 | #define SWF11_MEMORY_SIZE_SHIFT 16 |
540 | #define SWF11_SV_TEST_EN (1<<15) |
548 | #define SWF11_SV_TEST_EN (1<<15) |
541 | #define SWF11_IS_AGP (1<<14) |
549 | #define SWF11_IS_AGP (1<<14) |
542 | #define SWF11_DISPLAY_HOLDOFF (1<<13) |
550 | #define SWF11_DISPLAY_HOLDOFF (1<<13) |
543 | #define SWF11_DPMS_REDUCED (1<<12) |
551 | #define SWF11_DPMS_REDUCED (1<<12) |
544 | #define SWF11_IS_VBE_MODE (1<<11) |
552 | #define SWF11_IS_VBE_MODE (1<<11) |
545 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ |
553 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ |
546 | #define SWF11_DPMS_MASK 0x07 |
554 | #define SWF11_DPMS_MASK 0x07 |
547 | #define SWF11_DPMS_OFF (1<<2) |
555 | #define SWF11_DPMS_OFF (1<<2) |
548 | #define SWF11_DPMS_SUSPEND (1<<1) |
556 | #define SWF11_DPMS_SUSPEND (1<<1) |
549 | #define SWF11_DPMS_STANDBY (1<<0) |
557 | #define SWF11_DPMS_STANDBY (1<<0) |
550 | #define SWF11_DPMS_ON 0 |
558 | #define SWF11_DPMS_ON 0 |
551 | 559 | ||
552 | #define SWF14_GFX_PFIT_EN (1<<31) |
560 | #define SWF14_GFX_PFIT_EN (1<<31) |
553 | #define SWF14_TEXT_PFIT_EN (1<<30) |
561 | #define SWF14_TEXT_PFIT_EN (1<<30) |
554 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ |
562 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ |
555 | #define SWF14_POPUP_EN (1<<28) |
563 | #define SWF14_POPUP_EN (1<<28) |
556 | #define SWF14_DISPLAY_HOLDOFF (1<<27) |
564 | #define SWF14_DISPLAY_HOLDOFF (1<<27) |
557 | #define SWF14_DISP_DETECT_EN (1<<26) |
565 | #define SWF14_DISP_DETECT_EN (1<<26) |
558 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ |
566 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ |
559 | #define SWF14_DRIVER_STATUS (1<<24) |
567 | #define SWF14_DRIVER_STATUS (1<<24) |
560 | #define SWF14_OS_TYPE_WIN9X (1<<23) |
568 | #define SWF14_OS_TYPE_WIN9X (1<<23) |
561 | #define SWF14_OS_TYPE_WINNT (1<<22) |
569 | #define SWF14_OS_TYPE_WINNT (1<<22) |
562 | /* 21:19 rsvd */ |
570 | /* 21:19 rsvd */ |
563 | #define SWF14_PM_TYPE_MASK 0x00070000 |
571 | #define SWF14_PM_TYPE_MASK 0x00070000 |
564 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) |
572 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) |
565 | #define SWF14_PM_ACPI (0x3 << 16) |
573 | #define SWF14_PM_ACPI (0x3 << 16) |
566 | #define SWF14_PM_APM_12 (0x2 << 16) |
574 | #define SWF14_PM_APM_12 (0x2 << 16) |
567 | #define SWF14_PM_APM_11 (0x1 << 16) |
575 | #define SWF14_PM_APM_11 (0x1 << 16) |
568 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ |
576 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ |
569 | /* if GR18 indicates a display switch */ |
577 | /* if GR18 indicates a display switch */ |
570 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) |
578 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) |
571 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) |
579 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) |
572 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) |
580 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) |
573 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) |
581 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) |
574 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) |
582 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) |
575 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) |
583 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) |
576 | #define SWF14_DS_PIPEB_TV_EN (1<<9) |
584 | #define SWF14_DS_PIPEB_TV_EN (1<<9) |
577 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) |
585 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) |
578 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) |
586 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) |
579 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) |
587 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) |
580 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) |
588 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) |
581 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) |
589 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) |
582 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) |
590 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) |
583 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) |
591 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) |
584 | #define SWF14_DS_PIPEA_TV_EN (1<<1) |
592 | #define SWF14_DS_PIPEA_TV_EN (1<<1) |
585 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) |
593 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) |
586 | /* if GR18 indicates a panel fitting request */ |
594 | /* if GR18 indicates a panel fitting request */ |
587 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ |
595 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ |
588 | /* if GR18 indicates an APM change request */ |
596 | /* if GR18 indicates an APM change request */ |
589 | #define SWF14_APM_HIBERNATE 0x4 |
597 | #define SWF14_APM_HIBERNATE 0x4 |
590 | #define SWF14_APM_SUSPEND 0x3 |
598 | #define SWF14_APM_SUSPEND 0x3 |
591 | #define SWF14_APM_STANDBY 0x1 |
599 | #define SWF14_APM_STANDBY 0x1 |
592 | #define SWF14_APM_RESTORE 0x0 |
600 | #define SWF14_APM_RESTORE 0x0 |
593 | 601 | ||
594 | /* Add the device class for LFP, TV, HDMI */ |
602 | /* Add the device class for LFP, TV, HDMI */ |
595 | #define DEVICE_TYPE_INT_LFP 0x1022 |
603 | #define DEVICE_TYPE_INT_LFP 0x1022 |
596 | #define DEVICE_TYPE_INT_TV 0x1009 |
604 | #define DEVICE_TYPE_INT_TV 0x1009 |
597 | #define DEVICE_TYPE_HDMI 0x60D2 |
605 | #define DEVICE_TYPE_HDMI 0x60D2 |
598 | #define DEVICE_TYPE_DP 0x68C6 |
606 | #define DEVICE_TYPE_DP 0x68C6 |
599 | #define DEVICE_TYPE_eDP 0x78C6 |
607 | #define DEVICE_TYPE_eDP 0x78C6 |
600 | 608 | ||
601 | /* define the DVO port for HDMI output type */ |
609 | /* define the DVO port for HDMI output type */ |
602 | #define DVO_B 1 |
610 | #define DVO_B 1 |
603 | #define DVO_C 2 |
611 | #define DVO_C 2 |
604 | #define DVO_D 3 |
612 | #define DVO_D 3 |
605 | 613 | ||
606 | /* define the PORT for DP output type */ |
614 | /* define the PORT for DP output type */ |
607 | #define PORT_IDPB 7 |
615 | #define PORT_IDPB 7 |
608 | #define PORT_IDPC 8 |
616 | #define PORT_IDPC 8 |
609 | #define PORT_IDPD 9 |
617 | #define PORT_IDPD 9 |
610 | 618 | ||
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