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Rev 6937 | Rev 7144 | ||
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Line 608... | Line 608... | ||
608 | #define IOSF_OPCODE_SHIFT 16 |
608 | #define IOSF_OPCODE_SHIFT 16 |
609 | #define IOSF_PORT_SHIFT 8 |
609 | #define IOSF_PORT_SHIFT 8 |
610 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
610 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
611 | #define IOSF_BAR_SHIFT 1 |
611 | #define IOSF_BAR_SHIFT 1 |
612 | #define IOSF_SB_BUSY (1<<0) |
612 | #define IOSF_SB_BUSY (1<<0) |
613 | #define IOSF_PORT_BUNIT 0x3 |
613 | #define IOSF_PORT_BUNIT 0x03 |
614 | #define IOSF_PORT_PUNIT 0x4 |
614 | #define IOSF_PORT_PUNIT 0x04 |
615 | #define IOSF_PORT_NC 0x11 |
615 | #define IOSF_PORT_NC 0x11 |
616 | #define IOSF_PORT_DPIO 0x12 |
616 | #define IOSF_PORT_DPIO 0x12 |
617 | #define IOSF_PORT_DPIO_2 0x1a |
- | |
618 | #define IOSF_PORT_GPIO_NC 0x13 |
617 | #define IOSF_PORT_GPIO_NC 0x13 |
619 | #define IOSF_PORT_CCK 0x14 |
618 | #define IOSF_PORT_CCK 0x14 |
620 | #define IOSF_PORT_CCU 0xA9 |
619 | #define IOSF_PORT_DPIO_2 0x1a |
- | 620 | #define IOSF_PORT_FLISDSI 0x1b |
|
621 | #define IOSF_PORT_GPS_CORE 0x48 |
621 | #define IOSF_PORT_GPIO_SC 0x48 |
622 | #define IOSF_PORT_FLISDSI 0x1B |
622 | #define IOSF_PORT_GPIO_SUS 0xa8 |
- | 623 | #define IOSF_PORT_CCU 0xa9 |
|
623 | #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
624 | #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
624 | #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) |
625 | #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) |
Line 625... | Line 626... | ||
625 | 626 | ||
626 | /* See configdb bunit SB addr map */ |
627 | /* See configdb bunit SB addr map */ |
Line 1633... | Line 1634... | ||
1633 | #define RING_INVALID 0x00000000 |
1634 | #define RING_INVALID 0x00000000 |
1634 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
1635 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
1635 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
1636 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
1636 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
1637 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
Line -... | Line 1638... | ||
- | 1638 | ||
- | 1639 | #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4) |
|
- | 1640 | #define RING_MAX_NONPRIV_SLOTS 12 |
|
1637 | 1641 | ||
Line 1638... | Line 1642... | ||
1638 | #define GEN7_TLB_RD_ADDR _MMIO(0x4700) |
1642 | #define GEN7_TLB_RD_ADDR _MMIO(0x4700) |
1639 | 1643 | ||
1640 | #if 0 |
1644 | #if 0 |
Line 1709... | Line 1713... | ||
1709 | #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) |
1713 | #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) |
Line 1710... | Line 1714... | ||
1710 | 1714 | ||
1711 | #define FPGA_DBG _MMIO(0x42300) |
1715 | #define FPGA_DBG _MMIO(0x42300) |
Line -... | Line 1716... | ||
- | 1716 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
|
- | 1717 | ||
- | 1718 | #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) |
|
- | 1719 | #define CLAIM_ER_CLR (1 << 31) |
|
- | 1720 | #define CLAIM_ER_OVERFLOW (1 << 16) |
|
1712 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
1721 | #define CLAIM_ER_CTR_MASK 0xffff |
1713 | 1722 | ||
1714 | #define DERRMR _MMIO(0x44050) |
1723 | #define DERRMR _MMIO(0x44050) |
1715 | /* Note that HBLANK events are reserved on bdw+ */ |
1724 | /* Note that HBLANK events are reserved on bdw+ */ |
1716 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
1725 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
Line 5946... | Line 5955... | ||
5946 | #define ILK_VSDPFD_FULL (1<<21) |
5955 | #define ILK_VSDPFD_FULL (1<<21) |
5947 | #define FUSE_STRAP _MMIO(0x42014) |
5956 | #define FUSE_STRAP _MMIO(0x42014) |
5948 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) |
5957 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) |
5949 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) |
5958 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) |
5950 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) |
5959 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) |
- | 5960 | #define IVB_PIPE_C_DISABLE (1 << 28) |
|
5951 | #define ILK_HDCP_DISABLE (1 << 25) |
5961 | #define ILK_HDCP_DISABLE (1 << 25) |
5952 | #define ILK_eDP_A_DISABLE (1 << 24) |
5962 | #define ILK_eDP_A_DISABLE (1 << 24) |
5953 | #define HSW_CDCLK_LIMIT (1 << 24) |
5963 | #define HSW_CDCLK_LIMIT (1 << 24) |
5954 | #define ILK_DESKTOP (1 << 23) |
5964 | #define ILK_DESKTOP (1 << 23) |
Line 5992... | Line 6002... | ||
5992 | #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) |
6002 | #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) |
5993 | #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) |
6003 | #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) |
5994 | #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) |
6004 | #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) |
5995 | #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) |
6005 | #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) |
5996 | #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) |
6006 | #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) |
- | 6007 | #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) |
|
- | 6008 | #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) |
|
- | 6009 | #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) |
|
- | 6010 | ||
- | 6011 | #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) |
|
- | 6012 | #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14) |
|
Line 5997... | Line 6013... | ||
5997 | 6013 | ||
5998 | #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) |
6014 | #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) |
Line -... | Line 6015... | ||
- | 6015 | #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) |
|
- | 6016 | ||
- | 6017 | #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) |
|
5999 | #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) |
6018 | #define GEN8_CS_CHICKEN1 _MMIO(0x2580) |
6000 | 6019 | ||
6001 | /* GEN7 chicken */ |
6020 | /* GEN7 chicken */ |
6002 | #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) |
6021 | #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) |
6003 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
6022 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
Line 6041... | Line 6060... | ||
6041 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
6060 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
6042 | #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) |
6061 | #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) |
6043 | #define HDC_FORCE_NON_COHERENT (1<<4) |
6062 | #define HDC_FORCE_NON_COHERENT (1<<4) |
6044 | #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) |
6063 | #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) |
Line -... | Line 6064... | ||
- | 6064 | ||
- | 6065 | #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) |
|
6045 | 6066 | ||
6046 | /* GEN9 chicken */ |
6067 | /* GEN9 chicken */ |
6047 | #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) |
6068 | #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) |
Line 6048... | Line 6069... | ||
6048 | #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) |
6069 | #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) |
Line 6771... | Line 6792... | ||
6771 | 6792 | ||
Line 6772... | Line 6793... | ||
6772 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
6793 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
Line -... | Line 6794... | ||
- | 6794 | ||
- | 6795 | #define VLV_PMWGICZ _MMIO(0x1300a4) |
|
- | 6796 | ||
- | 6797 | #define RC6_LOCATION _MMIO(0xD40) |
|
- | 6798 | #define RC6_CTX_IN_DRAM (1 << 0) |
|
- | 6799 | #define RC6_CTX_BASE _MMIO(0xD48) |
|
- | 6800 | #define RC6_CTX_BASE_MASK 0xFFFFFFF0 |
|
- | 6801 | #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) |
|
- | 6802 | #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) |
|
- | 6803 | #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) |
|
6773 | 6804 | #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) |
|
6774 | #define VLV_PMWGICZ _MMIO(0x1300a4) |
6805 | #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) |
6775 | 6806 | #define IDLE_TIME_MASK 0xFFFFF |
|
6776 | #define FORCEWAKE _MMIO(0xA18C) |
6807 | #define FORCEWAKE _MMIO(0xA18C) |
6777 | #define FORCEWAKE_VLV _MMIO(0x1300b0) |
6808 | #define FORCEWAKE_VLV _MMIO(0x1300b0) |
Line 6909... | Line 6940... | ||
6909 | #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) |
6940 | #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) |
6910 | #define GEN6_RPDEUHWTC _MMIO(0xA080) |
6941 | #define GEN6_RPDEUHWTC _MMIO(0xA080) |
6911 | #define GEN6_RPDEUC _MMIO(0xA084) |
6942 | #define GEN6_RPDEUC _MMIO(0xA084) |
6912 | #define GEN6_RPDEUCSW _MMIO(0xA088) |
6943 | #define GEN6_RPDEUCSW _MMIO(0xA088) |
6913 | #define GEN6_RC_STATE _MMIO(0xA094) |
6944 | #define GEN6_RC_STATE _MMIO(0xA094) |
- | 6945 | #define RC6_STATE (1 << 18) |
|
6914 | #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) |
6946 | #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) |
6915 | #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) |
6947 | #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) |
6916 | #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) |
6948 | #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) |
6917 | #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) |
6949 | #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) |
6918 | #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) |
6950 | #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) |
Line 7543... | Line 7575... | ||
7543 | #define DC_STATE_EN_DC9 (1<<3) |
7575 | #define DC_STATE_EN_DC9 (1<<3) |
7544 | #define DC_STATE_EN_UPTO_DC6 (2<<0) |
7576 | #define DC_STATE_EN_UPTO_DC6 (2<<0) |
7545 | #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 |
7577 | #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 |
Line 7546... | Line 7578... | ||
7546 | 7578 | ||
- | 7579 | #define DC_STATE_DEBUG _MMIO(0x45520) |
|
7547 | #define DC_STATE_DEBUG _MMIO(0x45520) |
7580 | #define DC_STATE_DEBUG_MASK_CORES (1<<0) |
Line 7548... | Line 7581... | ||
7548 | #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) |
7581 | #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) |
7549 | 7582 | ||
7550 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
7583 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
Line 8162... | Line 8195... | ||
8162 | #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ |
8195 | #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ |
8163 | #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ |
8196 | #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ |
8164 | #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ |
8197 | #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ |
8165 | #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ |
8198 | #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ |
Line -... | Line 8199... | ||
- | 8199 | ||
- | 8200 | /* gamt regs */ |
|
- | 8201 | #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) |
|
- | 8202 | #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ |
|
- | 8203 | #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ |
|
- | 8204 | #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ |
|
- | 8205 | #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ |
|
8166 | 8206 |