Rev 4280 | Rev 5060 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 4280 | Rev 4560 | ||
---|---|---|---|
Line 24... | Line 24... | ||
24 | 24 | ||
25 | #ifndef _I915_REG_H_ |
25 | #ifndef _I915_REG_H_ |
Line 26... | Line 26... | ||
26 | #define _I915_REG_H_ |
26 | #define _I915_REG_H_ |
- | 27 | ||
27 | 28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
|
Line 28... | Line 29... | ||
28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
29 | #define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc)) |
Line 29... | Line 30... | ||
29 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
30 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
Line 107... | Line 108... | ||
107 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
108 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
108 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) |
109 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) |
109 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) |
110 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) |
110 | #define PP_DIR_DCLV_2G 0xffffffff |
111 | #define PP_DIR_DCLV_2G 0xffffffff |
Line -... | Line 112... | ||
- | 112 | ||
- | 113 | #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) |
|
- | 114 | #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) |
|
111 | 115 | ||
112 | #define GAM_ECOCHK 0x4090 |
116 | #define GAM_ECOCHK 0x4090 |
113 | #define ECOCHK_SNB_BIT (1<<10) |
117 | #define ECOCHK_SNB_BIT (1<<10) |
114 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
118 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
115 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
119 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
Line 187... | Line 191... | ||
187 | #define MI_EXE_FLUSH (1 << 1) |
191 | #define MI_EXE_FLUSH (1 << 1) |
188 | #define MI_NO_WRITE_FLUSH (1 << 2) |
192 | #define MI_NO_WRITE_FLUSH (1 << 2) |
189 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
193 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
190 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
194 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
191 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
195 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
- | 196 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
|
- | 197 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
|
- | 198 | #define MI_ARB_ENABLE (1<<0) |
|
- | 199 | #define MI_ARB_DISABLE (0<<0) |
|
192 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
200 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
193 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
201 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
194 | #define MI_SUSPEND_FLUSH_EN (1<<0) |
202 | #define MI_SUSPEND_FLUSH_EN (1<<0) |
195 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
- | |
196 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
203 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
197 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
204 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
198 | #define MI_OVERLAY_ON (0x1<<21) |
205 | #define MI_OVERLAY_ON (0x1<<21) |
199 | #define MI_OVERLAY_OFF (0x2<<21) |
206 | #define MI_OVERLAY_OFF (0x2<<21) |
200 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
207 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
Line 206... | Line 213... | ||
206 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) |
213 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) |
207 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) |
214 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) |
208 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
215 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
209 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
216 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
210 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
217 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
211 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
218 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
- | 219 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
|
212 | #define MI_ARB_ENABLE (1<<0) |
220 | #define MI_SEMAPHORE_UPDATE (1<<21) |
213 | #define MI_ARB_DISABLE (0<<0) |
221 | #define MI_SEMAPHORE_COMPARE (1<<20) |
214 | - | ||
- | 222 | #define MI_SEMAPHORE_REGISTER (1<<18) |
|
- | 223 | #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ |
|
- | 224 | #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ |
|
- | 225 | #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ |
|
- | 226 | #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ |
|
- | 227 | #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ |
|
- | 228 | #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ |
|
- | 229 | #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ |
|
- | 230 | #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ |
|
- | 231 | #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ |
|
- | 232 | #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ |
|
- | 233 | #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ |
|
- | 234 | #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ |
|
- | 235 | #define MI_SEMAPHORE_SYNC_INVALID (3<<16) |
|
215 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
236 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
216 | #define MI_MM_SPACE_GTT (1<<8) |
237 | #define MI_MM_SPACE_GTT (1<<8) |
217 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
238 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
218 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
239 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
219 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
240 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
Line 229... | Line 250... | ||
229 | * - One can actually load arbitrary many arbitrary registers: Simply issue x |
250 | * - One can actually load arbitrary many arbitrary registers: Simply issue x |
230 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
251 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
231 | */ |
252 | */ |
232 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) |
253 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) |
233 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) |
254 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) |
- | 255 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
|
234 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
256 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
235 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
257 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
236 | #define MI_INVALIDATE_TLB (1<<18) |
258 | #define MI_INVALIDATE_TLB (1<<18) |
237 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) |
259 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) |
238 | #define MI_INVALIDATE_BSD (1<<7) |
260 | #define MI_INVALIDATE_BSD (1<<7) |
Line 244... | Line 266... | ||
244 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
266 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
245 | #define MI_BATCH_PPGTT_HSW (1<<8) |
267 | #define MI_BATCH_PPGTT_HSW (1<<8) |
246 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
268 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
247 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
269 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
248 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
270 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
249 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
271 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
250 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
- | |
- | 272 | ||
- | 273 | ||
251 | #define MI_SEMAPHORE_UPDATE (1<<21) |
274 | #define MI_PREDICATE_RESULT_2 (0x2214) |
252 | #define MI_SEMAPHORE_COMPARE (1<<20) |
- | |
253 | #define MI_SEMAPHORE_REGISTER (1<<18) |
275 | #define LOWER_SLICE_ENABLED (1<<0) |
254 | #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ |
- | |
255 | #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ |
- | |
256 | #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ |
- | |
257 | #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ |
- | |
258 | #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ |
- | |
259 | #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ |
- | |
260 | #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ |
- | |
261 | #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ |
- | |
262 | #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ |
- | |
263 | #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ |
- | |
264 | #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ |
- | |
265 | #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ |
- | |
266 | #define MI_SEMAPHORE_SYNC_INVALID (3<<16) |
276 | #define LOWER_SLICE_DISABLED (0<<0) |
- | 277 | ||
267 | /* |
278 | /* |
268 | * 3D instructions used by the kernel |
279 | * 3D instructions used by the kernel |
269 | */ |
280 | */ |
270 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) |
281 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) |
Line 341... | Line 352... | ||
341 | #define IOSF_OPCODE_SHIFT 16 |
352 | #define IOSF_OPCODE_SHIFT 16 |
342 | #define IOSF_PORT_SHIFT 8 |
353 | #define IOSF_PORT_SHIFT 8 |
343 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
354 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
344 | #define IOSF_BAR_SHIFT 1 |
355 | #define IOSF_BAR_SHIFT 1 |
345 | #define IOSF_SB_BUSY (1<<0) |
356 | #define IOSF_SB_BUSY (1<<0) |
- | 357 | #define IOSF_PORT_BUNIT 0x3 |
|
346 | #define IOSF_PORT_PUNIT 0x4 |
358 | #define IOSF_PORT_PUNIT 0x4 |
347 | #define IOSF_PORT_NC 0x11 |
359 | #define IOSF_PORT_NC 0x11 |
348 | #define IOSF_PORT_DPIO 0x12 |
360 | #define IOSF_PORT_DPIO 0x12 |
- | 361 | #define IOSF_PORT_GPIO_NC 0x13 |
|
- | 362 | #define IOSF_PORT_CCK 0x14 |
|
- | 363 | #define IOSF_PORT_CCU 0xA9 |
|
- | 364 | #define IOSF_PORT_GPS_CORE 0x48 |
|
- | 365 | #define IOSF_PORT_FLISDSI 0x1B |
|
349 | #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) |
366 | #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) |
350 | #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) |
367 | #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) |
Line -... | Line 368... | ||
- | 368 | ||
- | 369 | /* See configdb bunit SB addr map */ |
|
- | 370 | #define BUNIT_REG_BISOC 0x11 |
|
351 | 371 | ||
352 | #define PUNIT_OPCODE_REG_READ 6 |
372 | #define PUNIT_OPCODE_REG_READ 6 |
Line -... | Line 373... | ||
- | 373 | #define PUNIT_OPCODE_REG_WRITE 7 |
|
- | 374 | ||
- | 375 | #define PUNIT_REG_DSPFREQ 0x36 |
|
- | 376 | #define DSPFREQSTAT_SHIFT 30 |
|
- | 377 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
|
- | 378 | #define DSPFREQGUAR_SHIFT 14 |
|
- | 379 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
|
- | 380 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
|
- | 381 | #define PUNIT_REG_PWRGT_STATUS 0x61 |
|
- | 382 | #define PUNIT_CLK_GATE 1 |
|
- | 383 | #define PUNIT_PWR_RESET 2 |
|
- | 384 | #define PUNIT_PWR_GATE 3 |
|
- | 385 | #define RENDER_PWRGT (PUNIT_PWR_GATE << 0) |
|
- | 386 | #define MEDIA_PWRGT (PUNIT_PWR_GATE << 2) |
|
353 | #define PUNIT_OPCODE_REG_WRITE 7 |
387 | #define DISP2D_PWRGT (PUNIT_PWR_GATE << 6) |
354 | 388 | ||
355 | #define PUNIT_REG_GPU_LFM 0xd3 |
389 | #define PUNIT_REG_GPU_LFM 0xd3 |
356 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 |
390 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 |
357 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 |
391 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 |
Line 370... | Line 404... | ||
370 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 |
404 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 |
371 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 |
405 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 |
372 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
406 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
373 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
407 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
Line -... | Line 408... | ||
- | 408 | ||
- | 409 | /* vlv2 north clock has */ |
|
- | 410 | #define CCK_FUSE_REG 0x8 |
|
- | 411 | #define CCK_FUSE_HPLL_FREQ_MASK 0x3 |
|
- | 412 | #define CCK_REG_DSI_PLL_FUSE 0x44 |
|
- | 413 | #define CCK_REG_DSI_PLL_CONTROL 0x48 |
|
- | 414 | #define DSI_PLL_VCO_EN (1 << 31) |
|
- | 415 | #define DSI_PLL_LDO_GATE (1 << 30) |
|
- | 416 | #define DSI_PLL_P1_POST_DIV_SHIFT 17 |
|
- | 417 | #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) |
|
- | 418 | #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) |
|
- | 419 | #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) |
|
- | 420 | #define DSI_PLL_MUX_MASK (3 << 9) |
|
- | 421 | #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) |
|
- | 422 | #define DSI_PLL_MUX_DSI0_CCK (1 << 10) |
|
- | 423 | #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) |
|
- | 424 | #define DSI_PLL_MUX_DSI1_CCK (1 << 9) |
|
- | 425 | #define DSI_PLL_CLK_GATE_MASK (0xf << 5) |
|
- | 426 | #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) |
|
- | 427 | #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) |
|
- | 428 | #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) |
|
- | 429 | #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) |
|
- | 430 | #define DSI_PLL_LOCK (1 << 0) |
|
- | 431 | #define CCK_REG_DSI_PLL_DIVIDER 0x4c |
|
- | 432 | #define DSI_PLL_LFSR (1 << 31) |
|
- | 433 | #define DSI_PLL_FRACTION_EN (1 << 30) |
|
- | 434 | #define DSI_PLL_FRAC_COUNTER_SHIFT 27 |
|
- | 435 | #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) |
|
- | 436 | #define DSI_PLL_USYNC_CNT_SHIFT 18 |
|
- | 437 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) |
|
- | 438 | #define DSI_PLL_N1_DIV_SHIFT 16 |
|
- | 439 | #define DSI_PLL_N1_DIV_MASK (3 << 16) |
|
- | 440 | #define DSI_PLL_M1_DIV_SHIFT 0 |
|
- | 441 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) |
|
- | 442 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
|
374 | 443 | ||
375 | /* |
444 | /* |
376 | * DPIO - a special bus for various display related registers to hide behind |
445 | * DPIO - a special bus for various display related registers to hide behind |
377 | * |
446 | * |
378 | * DPIO is VLV only. |
447 | * DPIO is VLV only. |
Line 385... | Line 454... | ||
385 | 454 | ||
386 | #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) |
455 | #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) |
387 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
456 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
388 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ |
457 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ |
389 | #define DPIO_SFR_BYPASS (1<<1) |
458 | #define DPIO_SFR_BYPASS (1<<1) |
Line 390... | Line -... | ||
390 | #define DPIO_RESET (1<<0) |
- | |
391 | 459 | #define DPIO_CMNRST (1<<0) |
|
392 | #define _DPIO_TX3_SWING_CTL4_A 0x690 |
460 | |
393 | #define _DPIO_TX3_SWING_CTL4_B 0x2a90 |
- | |
Line 394... | Line 461... | ||
394 | #define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \ |
461 | #define DPIO_PHY(pipe) ((pipe) >> 1) |
395 | _DPIO_TX3_SWING_CTL4_B) |
462 | #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) |
396 | 463 | ||
397 | /* |
464 | /* |
398 | * Per pipe/PLL DPIO regs |
465 | * Per pipe/PLL DPIO regs |
399 | */ |
466 | */ |
400 | #define _DPIO_DIV_A 0x800c |
467 | #define _VLV_PLL_DW3_CH0 0x800c |
401 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
468 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
402 | #define DPIO_POST_DIV_DAC 0 |
469 | #define DPIO_POST_DIV_DAC 0 |
Line 408... | Line 475... | ||
408 | #define DPIO_P2_SHIFT (16) /* 5 bits */ |
475 | #define DPIO_P2_SHIFT (16) /* 5 bits */ |
409 | #define DPIO_N_SHIFT (12) /* 4 bits */ |
476 | #define DPIO_N_SHIFT (12) /* 4 bits */ |
410 | #define DPIO_ENABLE_CALIBRATION (1<<11) |
477 | #define DPIO_ENABLE_CALIBRATION (1<<11) |
411 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
478 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
412 | #define DPIO_M2DIV_MASK 0xff |
479 | #define DPIO_M2DIV_MASK 0xff |
413 | #define _DPIO_DIV_B 0x802c |
480 | #define _VLV_PLL_DW3_CH1 0x802c |
414 | #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) |
481 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) |
Line 415... | Line 482... | ||
415 | 482 | ||
416 | #define _DPIO_REFSFR_A 0x8014 |
483 | #define _VLV_PLL_DW5_CH0 0x8014 |
417 | #define DPIO_REFSEL_OVERRIDE 27 |
484 | #define DPIO_REFSEL_OVERRIDE 27 |
418 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
485 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
419 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
486 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
420 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
487 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
421 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
488 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
422 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
489 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
423 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
490 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
424 | #define _DPIO_REFSFR_B 0x8034 |
- | |
425 | #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) |
- | |
426 | - | ||
427 | #define _DPIO_CORE_CLK_A 0x801c |
- | |
428 | #define _DPIO_CORE_CLK_B 0x803c |
- | |
429 | #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) |
- | |
430 | - | ||
431 | #define _DPIO_IREF_CTL_A 0x8040 |
- | |
432 | #define _DPIO_IREF_CTL_B 0x8060 |
491 | #define _VLV_PLL_DW5_CH1 0x8034 |
433 | #define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B) |
- | |
434 | - | ||
435 | #define DPIO_IREF_BCAST 0xc044 |
- | |
436 | #define _DPIO_IREF_A 0x8044 |
- | |
437 | #define _DPIO_IREF_B 0x8064 |
- | |
Line -... | Line 492... | ||
- | 492 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) |
|
438 | #define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B) |
493 | |
- | 494 | #define _VLV_PLL_DW7_CH0 0x801c |
|
- | 495 | #define _VLV_PLL_DW7_CH1 0x803c |
|
- | 496 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) |
|
- | 497 | ||
- | 498 | #define _VLV_PLL_DW8_CH0 0x8040 |
|
- | 499 | #define _VLV_PLL_DW8_CH1 0x8060 |
|
- | 500 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) |
|
- | 501 | ||
439 | 502 | #define VLV_PLL_DW9_BCAST 0xc044 |
|
440 | #define _DPIO_PLL_CML_A 0x804c |
503 | #define _VLV_PLL_DW9_CH0 0x8044 |
- | 504 | #define _VLV_PLL_DW9_CH1 0x8064 |
|
- | 505 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) |
|
- | 506 | ||
- | 507 | #define _VLV_PLL_DW10_CH0 0x8048 |
|
- | 508 | #define _VLV_PLL_DW10_CH1 0x8068 |
|
- | 509 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) |
|
- | 510 | ||
- | 511 | #define _VLV_PLL_DW11_CH0 0x804c |
|
Line 441... | Line 512... | ||
441 | #define _DPIO_PLL_CML_B 0x806c |
512 | #define _VLV_PLL_DW11_CH1 0x806c |
442 | #define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) |
513 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) |
443 | - | ||
Line 444... | Line -... | ||
444 | #define _DPIO_LPF_COEFF_A 0x8048 |
- | |
445 | #define _DPIO_LPF_COEFF_B 0x8068 |
- | |
446 | #define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B) |
514 | |
Line 447... | Line 515... | ||
447 | 515 | /* Spec for ref block start counts at DW10 */ |
|
448 | #define DPIO_CALIBRATION 0x80ac |
516 | #define VLV_REF_DW13 0x80ac |
449 | 517 | ||
Line 450... | Line 518... | ||
450 | #define DPIO_FASTCLK_DISABLE 0x8100 |
518 | #define VLV_CMN_DW0 0x8100 |
451 | 519 | ||
452 | /* |
520 | /* |
453 | * Per DDI channel DPIO regs |
521 | * Per DDI channel DPIO regs |
454 | */ |
522 | */ |
Line 455... | Line 523... | ||
455 | 523 | ||
456 | #define _DPIO_PCS_TX_0 0x8200 |
524 | #define _VLV_PCS_DW0_CH0 0x8200 |
457 | #define _DPIO_PCS_TX_1 0x8400 |
525 | #define _VLV_PCS_DW0_CH1 0x8400 |
458 | #define DPIO_PCS_TX_LANE2_RESET (1<<16) |
526 | #define DPIO_PCS_TX_LANE2_RESET (1<<16) |
459 | #define DPIO_PCS_TX_LANE1_RESET (1<<7) |
527 | #define DPIO_PCS_TX_LANE1_RESET (1<<7) |
460 | #define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1) |
528 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
461 | 529 | ||
Line 462... | Line 530... | ||
462 | #define _DPIO_PCS_CLK_0 0x8204 |
530 | #define _VLV_PCS_DW1_CH0 0x8204 |
463 | #define _DPIO_PCS_CLK_1 0x8404 |
531 | #define _VLV_PCS_DW1_CH1 0x8404 |
464 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) |
532 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) |
465 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) |
- | |
466 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
533 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) |
467 | #define DPIO_PCS_CLK_SOFT_RESET (1<<5) |
534 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
468 | #define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1) |
535 | #define DPIO_PCS_CLK_SOFT_RESET (1<<5) |
469 | 536 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
|
470 | #define _DPIO_PCS_CTL_OVR1_A 0x8224 |
537 | |
- | 538 | #define _VLV_PCS_DW8_CH0 0x8220 |
|
- | 539 | #define _VLV_PCS_DW8_CH1 0x8420 |
|
471 | #define _DPIO_PCS_CTL_OVR1_B 0x8424 |
540 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
472 | #define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \ |
541 | |
473 | _DPIO_PCS_CTL_OVR1_B) |
542 | #define _VLV_PCS01_DW8_CH0 0x0220 |
474 | 543 | #define _VLV_PCS23_DW8_CH0 0x0420 |
|
- | 544 | #define _VLV_PCS01_DW8_CH1 0x2620 |
|
- | 545 | #define _VLV_PCS23_DW8_CH1 0x2820 |
|
475 | #define _DPIO_PCS_STAGGER0_A 0x822c |
546 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) |
- | 547 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) |
|
476 | #define _DPIO_PCS_STAGGER0_B 0x842c |
548 | |
477 | #define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \ |
549 | #define _VLV_PCS_DW9_CH0 0x8224 |
478 | _DPIO_PCS_STAGGER0_B) |
550 | #define _VLV_PCS_DW9_CH1 0x8424 |
479 | 551 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
|
- | 552 | ||
- | 553 | #define _VLV_PCS_DW11_CH0 0x822c |
|
480 | #define _DPIO_PCS_STAGGER1_A 0x8230 |
554 | #define _VLV_PCS_DW11_CH1 0x842c |
- | 555 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
|
481 | #define _DPIO_PCS_STAGGER1_B 0x8430 |
556 | |
482 | #define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \ |
557 | #define _VLV_PCS_DW12_CH0 0x8230 |
483 | _DPIO_PCS_STAGGER1_B) |
558 | #define _VLV_PCS_DW12_CH1 0x8430 |
484 | 559 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
|
485 | #define _DPIO_PCS_CLOCKBUF0_A 0x8238 |
- | |
486 | #define _DPIO_PCS_CLOCKBUF0_B 0x8438 |
560 | |
487 | #define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \ |
561 | #define _VLV_PCS_DW14_CH0 0x8238 |
488 | _DPIO_PCS_CLOCKBUF0_B) |
562 | #define _VLV_PCS_DW14_CH1 0x8438 |
489 | 563 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) |
|
490 | #define _DPIO_PCS_CLOCKBUF8_A 0x825c |
- | |
491 | #define _DPIO_PCS_CLOCKBUF8_B 0x845c |
564 | |
492 | #define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \ |
565 | #define _VLV_PCS_DW23_CH0 0x825c |
493 | _DPIO_PCS_CLOCKBUF8_B) |
566 | #define _VLV_PCS_DW23_CH1 0x845c |
494 | 567 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) |
|
495 | #define _DPIO_TX_SWING_CTL2_A 0x8288 |
- | |
496 | #define _DPIO_TX_SWING_CTL2_B 0x8488 |
568 | |
497 | #define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \ |
569 | #define _VLV_TX_DW2_CH0 0x8288 |
498 | _DPIO_TX_SWING_CTL2_B) |
570 | #define _VLV_TX_DW2_CH1 0x8488 |
499 | 571 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
|
- | 572 | ||
500 | #define _DPIO_TX_SWING_CTL3_A 0x828c |
573 | #define _VLV_TX_DW3_CH0 0x828c |
- | 574 | #define _VLV_TX_DW3_CH1 0x848c |
|
- | 575 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
|
Line 501... | Line 576... | ||
501 | #define _DPIO_TX_SWING_CTL3_B 0x848c |
576 | |
502 | #define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \ |
577 | #define _VLV_TX_DW4_CH0 0x8290 |
503 | _DPIO_TX_SWING_CTL3_B) |
578 | #define _VLV_TX_DW4_CH1 0x8490 |
504 | 579 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
|
505 | #define _DPIO_TX_SWING_CTL4_A 0x8290 |
- | |
Line 506... | Line 580... | ||
506 | #define _DPIO_TX_SWING_CTL4_B 0x8490 |
580 | |
507 | #define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \ |
581 | #define _VLV_TX3_DW4_CH0 0x690 |
508 | _DPIO_TX_SWING_CTL4_B) |
582 | #define _VLV_TX3_DW4_CH1 0x2a90 |
509 | 583 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) |
|
510 | #define _DPIO_TX_OCALINIT_0 0x8294 |
584 | |
511 | #define _DPIO_TX_OCALINIT_1 0x8494 |
585 | #define _VLV_TX_DW5_CH0 0x8294 |
512 | #define DPIO_TX_OCALINIT_EN (1<<31) |
586 | #define _VLV_TX_DW5_CH1 0x8494 |
513 | #define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \ |
- | |
514 | _DPIO_TX_OCALINIT_1) |
- | |
515 | - | ||
516 | #define _DPIO_TX_CTL_0 0x82ac |
- | |
517 | #define _DPIO_TX_CTL_1 0x84ac |
- | |
518 | #define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1) |
- | |
519 | - | ||
520 | #define _DPIO_TX_LANE_0 0x82b8 |
- | |
521 | #define _DPIO_TX_LANE_1 0x84b8 |
- | |
522 | #define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1) |
- | |
523 | - | ||
524 | #define _DPIO_DATA_CHANNEL1 0x8220 |
- | |
525 | #define _DPIO_DATA_CHANNEL2 0x8420 |
- | |
Line 526... | Line 587... | ||
526 | #define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2) |
587 | #define DPIO_TX_OCALINIT_EN (1<<31) |
527 | 588 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
|
528 | #define _DPIO_PORT0_PCS0 0x0220 |
589 | |
529 | #define _DPIO_PORT0_PCS1 0x0420 |
590 | #define _VLV_TX_DW11_CH0 0x82ac |
Line 600... | Line 661... | ||
600 | #define RING_HWS_PGA(base) ((base)+0x80) |
661 | #define RING_HWS_PGA(base) ((base)+0x80) |
601 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
662 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
602 | #define ARB_MODE 0x04030 |
663 | #define ARB_MODE 0x04030 |
603 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
664 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
604 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
665 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
- | 666 | #define GAMTARBMODE 0x04a08 |
|
- | 667 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) |
|
- | 668 | #define ARB_MODE_SWIZZLE_BDW (1<<1) |
|
605 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
669 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
606 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
670 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
607 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
671 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
608 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) |
672 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) |
609 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) |
673 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) |
610 | #define RING_FAULT_VALID (1<<0) |
674 | #define RING_FAULT_VALID (1<<0) |
611 | #define DONE_REG 0x40b0 |
675 | #define DONE_REG 0x40b0 |
- | 676 | #define GEN8_PRIVATE_PAT 0x40e0 |
|
612 | #define BSD_HWS_PGA_GEN7 (0x04180) |
677 | #define BSD_HWS_PGA_GEN7 (0x04180) |
613 | #define BLT_HWS_PGA_GEN7 (0x04280) |
678 | #define BLT_HWS_PGA_GEN7 (0x04280) |
614 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
679 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
615 | #define RING_ACTHD(base) ((base)+0x74) |
680 | #define RING_ACTHD(base) ((base)+0x74) |
616 | #define RING_NOPID(base) ((base)+0x94) |
681 | #define RING_NOPID(base) ((base)+0x94) |
Line 667... | Line 732... | ||
667 | #define IPEHR 0x0208c |
732 | #define IPEHR 0x0208c |
668 | #define INSTDONE 0x02090 |
733 | #define INSTDONE 0x02090 |
669 | #define NOPID 0x02094 |
734 | #define NOPID 0x02094 |
670 | #define HWSTAM 0x02098 |
735 | #define HWSTAM 0x02098 |
671 | #define DMA_FADD_I8XX 0x020d0 |
736 | #define DMA_FADD_I8XX 0x020d0 |
- | 737 | #define RING_BBSTATE(base) ((base)+0x110) |
|
- | 738 | #define RING_BBADDR(base) ((base)+0x140) |
|
- | 739 | #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ |
|
Line 672... | Line 740... | ||
672 | 740 | ||
673 | #define ERROR_GEN6 0x040a0 |
741 | #define ERROR_GEN6 0x040a0 |
674 | #define GEN7_ERR_INT 0x44040 |
742 | #define GEN7_ERR_INT 0x44040 |
675 | #define ERR_INT_POISON (1<<31) |
743 | #define ERR_INT_POISON (1<<31) |
- | 744 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
|
676 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
745 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) |
- | 746 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
|
677 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
747 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) |
- | 748 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
|
- | 749 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) |
|
678 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
750 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) |
679 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
751 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
Line 680... | Line 752... | ||
680 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
752 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
681 | 753 | ||
Line 682... | Line 754... | ||
682 | #define FPGA_DBG 0x42300 |
754 | #define FPGA_DBG 0x42300 |
- | 755 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
|
683 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
756 | |
684 | 757 | #define DERRMR 0x44050 |
|
685 | #define DERRMR 0x44050 |
758 | /* Note that HBLANK events are reserved on bdw+ */ |
686 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
759 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
687 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) |
760 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) |
Line 714... | Line 787... | ||
714 | */ |
787 | */ |
715 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
788 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
716 | #define _3D_CHICKEN3 0x02090 |
789 | #define _3D_CHICKEN3 0x02090 |
717 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
790 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
718 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
791 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
- | 792 | #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) |
|
Line 719... | Line 793... | ||
719 | 793 | ||
720 | #define MI_MODE 0x0209c |
794 | #define MI_MODE 0x0209c |
721 | # define VS_TIMER_DISPATCH (1 << 6) |
795 | # define VS_TIMER_DISPATCH (1 << 6) |
722 | # define MI_FLUSH_ENABLE (1 << 12) |
796 | # define MI_FLUSH_ENABLE (1 << 12) |
Line 851... | Line 925... | ||
851 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
925 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
852 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
926 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
853 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
927 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
854 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
928 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
855 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
929 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
856 | #define BB_ADDR 0x02140 /* 8 bytes */ |
- | |
857 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
930 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
858 | #define GFX_FLSH_CNTL_GEN6 0x101008 |
931 | #define GFX_FLSH_CNTL_GEN6 0x101008 |
859 | #define GFX_FLSH_CNTL_EN (1<<0) |
932 | #define GFX_FLSH_CNTL_EN (1<<0) |
860 | #define ECOSKPD 0x021d0 |
933 | #define ECOSKPD 0x021d0 |
861 | #define ECO_GATING_CX_ONLY (1<<3) |
934 | #define ECO_GATING_CX_ONLY (1<<3) |
Line 888... | Line 961... | ||
888 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
961 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
889 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) |
962 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) |
890 | #define GT_BLT_USER_INTERRUPT (1 << 22) |
963 | #define GT_BLT_USER_INTERRUPT (1 << 22) |
891 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) |
964 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) |
892 | #define GT_BSD_USER_INTERRUPT (1 << 12) |
965 | #define GT_BSD_USER_INTERRUPT (1 << 12) |
- | 966 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
|
893 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
967 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
894 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) |
968 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) |
895 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) |
969 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) |
896 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) |
970 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) |
897 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) |
971 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) |
898 | #define GT_RENDER_USER_INTERRUPT (1 << 0) |
972 | #define GT_RENDER_USER_INTERRUPT (1 << 0) |
Line 899... | Line 973... | ||
899 | 973 | ||
900 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
974 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
Line -... | Line 975... | ||
- | 975 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ |
|
- | 976 | ||
- | 977 | #define GT_PARITY_ERROR(dev) \ |
|
- | 978 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ |
|
901 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ |
979 | (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
902 | 980 | ||
903 | /* These are all the "old" interrupts */ |
981 | /* These are all the "old" interrupts */ |
904 | #define ILK_BSD_USER_INTERRUPT (1<<5) |
982 | #define ILK_BSD_USER_INTERRUPT (1<<5) |
905 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
983 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
Line 923... | Line 1001... | ||
923 | 1001 | ||
Line 924... | Line 1002... | ||
924 | #define GEN6_BSD_RNCID 0x12198 |
1002 | #define GEN6_BSD_RNCID 0x12198 |
925 | 1003 | ||
- | 1004 | #define GEN7_FF_THREAD_MODE 0x20a0 |
|
926 | #define GEN7_FF_THREAD_MODE 0x20a0 |
1005 | #define GEN7_FF_SCHED_MASK 0x0077070 |
927 | #define GEN7_FF_SCHED_MASK 0x0077070 |
1006 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
928 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
1007 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
929 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) |
1008 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) |
930 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) |
1009 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) |
Line 950... | Line 1029... | ||
950 | #define FBC_CTL_PERIODIC (1<<30) |
1029 | #define FBC_CTL_PERIODIC (1<<30) |
951 | #define FBC_CTL_INTERVAL_SHIFT (16) |
1030 | #define FBC_CTL_INTERVAL_SHIFT (16) |
952 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
1031 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
953 | #define FBC_CTL_C3_IDLE (1<<13) |
1032 | #define FBC_CTL_C3_IDLE (1<<13) |
954 | #define FBC_CTL_STRIDE_SHIFT (5) |
1033 | #define FBC_CTL_STRIDE_SHIFT (5) |
955 | #define FBC_CTL_FENCENO (1<<0) |
1034 | #define FBC_CTL_FENCENO_SHIFT (0) |
956 | #define FBC_COMMAND 0x0320c |
1035 | #define FBC_COMMAND 0x0320c |
957 | #define FBC_CMD_COMPRESS (1<<0) |
1036 | #define FBC_CMD_COMPRESS (1<<0) |
958 | #define FBC_STATUS 0x03210 |
1037 | #define FBC_STATUS 0x03210 |
959 | #define FBC_STAT_COMPRESSING (1<<31) |
1038 | #define FBC_STAT_COMPRESSING (1<<31) |
960 | #define FBC_STAT_COMPRESSED (1<<30) |
1039 | #define FBC_STAT_COMPRESSED (1<<30) |
961 | #define FBC_STAT_MODIFIED (1<<29) |
1040 | #define FBC_STAT_MODIFIED (1<<29) |
962 | #define FBC_STAT_CURRENT_LINE (1<<0) |
1041 | #define FBC_STAT_CURRENT_LINE_SHIFT (0) |
963 | #define FBC_CONTROL2 0x03214 |
1042 | #define FBC_CONTROL2 0x03214 |
964 | #define FBC_CTL_FENCE_DBL (0<<4) |
1043 | #define FBC_CTL_FENCE_DBL (0<<4) |
965 | #define FBC_CTL_IDLE_IMM (0<<2) |
1044 | #define FBC_CTL_IDLE_IMM (0<<2) |
966 | #define FBC_CTL_IDLE_FULL (1<<2) |
1045 | #define FBC_CTL_IDLE_FULL (1<<2) |
967 | #define FBC_CTL_IDLE_LINE (2<<2) |
1046 | #define FBC_CTL_IDLE_LINE (2<<2) |
Line 1046... | Line 1125... | ||
1046 | #define HSW_BYPASS_FBC_QUEUE (1<<22) |
1125 | #define HSW_BYPASS_FBC_QUEUE (1<<22) |
1047 | #define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ |
1126 | #define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ |
1048 | _HSW_PIPE_SLICE_CHICKEN_1_A, + \ |
1127 | _HSW_PIPE_SLICE_CHICKEN_1_A, + \ |
1049 | _HSW_PIPE_SLICE_CHICKEN_1_B) |
1128 | _HSW_PIPE_SLICE_CHICKEN_1_B) |
Line 1050... | Line -... | ||
1050 | - | ||
1051 | #define HSW_CLKGATE_DISABLE_PART_1 0x46500 |
- | |
1052 | #define HSW_DPFC_GATING_DISABLE (1<<23) |
- | |
1053 | 1129 | ||
1054 | /* |
1130 | /* |
1055 | * GPIO regs |
1131 | * GPIO regs |
1056 | */ |
1132 | */ |
1057 | #define GPIOA 0x5010 |
1133 | #define GPIOA 0x5010 |
Line 1385... | Line 1461... | ||
1385 | #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) |
1461 | #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) |
1386 | #define FW_CSPWRDWNEN (1<<15) |
1462 | #define FW_CSPWRDWNEN (1<<15) |
Line 1387... | Line 1463... | ||
1387 | 1463 | ||
Line -... | Line 1464... | ||
- | 1464 | #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) |
|
- | 1465 | ||
- | 1466 | #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) |
|
- | 1467 | #define CDCLK_FREQ_SHIFT 4 |
|
- | 1468 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) |
|
- | 1469 | #define CZCLK_FREQ_MASK 0xf |
|
1388 | #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) |
1470 | #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) |
1389 | 1471 | ||
1390 | /* |
1472 | /* |
Line 1391... | Line 1473... | ||
1391 | * Palette regs |
1473 | * Palette regs |
Line 1402... | Line 1484... | ||
1402 | * |
1484 | * |
1403 | * This mirrors the MCHBAR MMIO space whose location is determined by |
1485 | * This mirrors the MCHBAR MMIO space whose location is determined by |
1404 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
1486 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
1405 | * every way. It is not accessible from the CP register read instructions. |
1487 | * every way. It is not accessible from the CP register read instructions. |
1406 | * |
1488 | * |
- | 1489 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, |
|
- | 1490 | * just read. |
|
1407 | */ |
1491 | */ |
1408 | #define MCHBAR_MIRROR_BASE 0x10000 |
1492 | #define MCHBAR_MIRROR_BASE 0x10000 |
Line 1409... | Line 1493... | ||
1409 | 1493 | ||
Line 1410... | Line 1494... | ||
1410 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
1494 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
1411 | 1495 | ||
Line 1412... | Line 1496... | ||
1412 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
1496 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
1413 | #define DCLK 0x5e04 |
1497 | #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
1414 | 1498 | ||
1415 | /** 915-945 and GM965 MCH register controlling DRAM channel access */ |
1499 | /** 915-945 and GM965 MCH register controlling DRAM channel access */ |
Line 1703... | Line 1787... | ||
1703 | 1787 | ||
1704 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
1788 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
1705 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
1789 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
Line 1706... | Line 1790... | ||
1706 | #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) |
1790 | #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) |
1707 | 1791 | ||
1708 | #define GEN6_GT_PERF_STATUS 0x145948 |
1792 | #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) |
Line 1709... | Line 1793... | ||
1709 | #define GEN6_RP_STATE_LIMITS 0x145994 |
1793 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
1710 | #define GEN6_RP_STATE_CAP 0x145998 |
1794 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) |
1711 | 1795 | ||
1712 | /* |
1796 | /* |
Line 1750... | Line 1834... | ||
1750 | * size is 70720 bytes, however, the power context and execlist context will |
1834 | * size is 70720 bytes, however, the power context and execlist context will |
1751 | * never be saved (power context is stored elsewhere, and execlists don't work |
1835 | * never be saved (power context is stored elsewhere, and execlists don't work |
1752 | * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. |
1836 | * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. |
1753 | */ |
1837 | */ |
1754 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) |
1838 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) |
- | 1839 | /* Same as Haswell, but 72064 bytes now. */ |
|
- | 1840 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) |
|
- | 1841 | ||
- | 1842 | ||
- | 1843 | #define VLV_CLK_CTL2 0x101104 |
|
- | 1844 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
|
Line 1755... | Line 1845... | ||
1755 | 1845 | ||
1756 | /* |
1846 | /* |
1757 | * Overlay regs |
1847 | * Overlay regs |
Line 1769... | Line 1859... | ||
1769 | 1859 | ||
1770 | /* |
1860 | /* |
1771 | * Display engine regs |
1861 | * Display engine regs |
Line -... | Line 1862... | ||
- | 1862 | */ |
|
- | 1863 | ||
- | 1864 | /* Pipe A CRC regs */ |
|
- | 1865 | #define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050) |
|
- | 1866 | #define PIPE_CRC_ENABLE (1 << 31) |
|
- | 1867 | /* ivb+ source selection */ |
|
- | 1868 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
|
- | 1869 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) |
|
- | 1870 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) |
|
- | 1871 | /* ilk+ source selection */ |
|
- | 1872 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) |
|
- | 1873 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) |
|
- | 1874 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) |
|
- | 1875 | /* embedded DP port on the north display block, reserved on ivb */ |
|
- | 1876 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) |
|
- | 1877 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ |
|
- | 1878 | /* vlv source selection */ |
|
- | 1879 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) |
|
- | 1880 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) |
|
- | 1881 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) |
|
- | 1882 | /* with DP port the pipe source is invalid */ |
|
- | 1883 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) |
|
- | 1884 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) |
|
- | 1885 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) |
|
- | 1886 | /* gen3+ source selection */ |
|
- | 1887 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) |
|
- | 1888 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) |
|
- | 1889 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) |
|
- | 1890 | /* with DP/TV port the pipe source is invalid */ |
|
- | 1891 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) |
|
- | 1892 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) |
|
- | 1893 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) |
|
- | 1894 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) |
|
- | 1895 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) |
|
- | 1896 | /* gen2 doesn't have source selection bits */ |
|
- | 1897 | #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) |
|
- | 1898 | ||
- | 1899 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
|
- | 1900 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 |
|
- | 1901 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c |
|
- | 1902 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 |
|
- | 1903 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 |
|
- | 1904 | ||
- | 1905 | #define _PIPE_CRC_RES_RED_A (dev_priv->info->display_mmio_offset + 0x60060) |
|
- | 1906 | #define _PIPE_CRC_RES_GREEN_A (dev_priv->info->display_mmio_offset + 0x60064) |
|
- | 1907 | #define _PIPE_CRC_RES_BLUE_A (dev_priv->info->display_mmio_offset + 0x60068) |
|
- | 1908 | #define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info->display_mmio_offset + 0x6006c) |
|
- | 1909 | #define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080) |
|
- | 1910 | ||
- | 1911 | /* Pipe B CRC regs */ |
|
- | 1912 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
|
- | 1913 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 |
|
- | 1914 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c |
|
- | 1915 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 |
|
- | 1916 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 |
|
- | 1917 | ||
- | 1918 | #define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000) |
|
- | 1919 | #define PIPE_CRC_RES_1_IVB(pipe) \ |
|
- | 1920 | _PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) |
|
- | 1921 | #define PIPE_CRC_RES_2_IVB(pipe) \ |
|
- | 1922 | _PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) |
|
- | 1923 | #define PIPE_CRC_RES_3_IVB(pipe) \ |
|
- | 1924 | _PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) |
|
- | 1925 | #define PIPE_CRC_RES_4_IVB(pipe) \ |
|
- | 1926 | _PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) |
|
- | 1927 | #define PIPE_CRC_RES_5_IVB(pipe) \ |
|
- | 1928 | _PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) |
|
- | 1929 | ||
- | 1930 | #define PIPE_CRC_RES_RED(pipe) \ |
|
- | 1931 | _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A, 0x01000) |
|
- | 1932 | #define PIPE_CRC_RES_GREEN(pipe) \ |
|
- | 1933 | _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A, 0x01000) |
|
- | 1934 | #define PIPE_CRC_RES_BLUE(pipe) \ |
|
- | 1935 | _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A, 0x01000) |
|
- | 1936 | #define PIPE_CRC_RES_RES1_I915(pipe) \ |
|
- | 1937 | _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_I915, 0x01000) |
|
- | 1938 | #define PIPE_CRC_RES_RES2_G4X(pipe) \ |
|
1772 | */ |
1939 | _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000) |
1773 | 1940 | ||
1774 | /* Pipe A timing regs */ |
1941 | /* Pipe A timing regs */ |
1775 | #define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) |
1942 | #define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) |
1776 | #define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) |
1943 | #define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) |
Line 1791... | Line 1958... | ||
1791 | #define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) |
1958 | #define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) |
1792 | #define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) |
1959 | #define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) |
1793 | #define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) |
1960 | #define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) |
1794 | #define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) |
1961 | #define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) |
Line 1795... | Line -... | ||
1795 | - | ||
1796 | 1962 | ||
1797 | #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) |
1963 | #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) |
1798 | #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) |
1964 | #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) |
1799 | #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) |
1965 | #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) |
1800 | #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) |
1966 | #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) |
1801 | #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) |
1967 | #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) |
1802 | #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) |
1968 | #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) |
1803 | #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
1969 | #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
Line 1804... | Line 1970... | ||
1804 | #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) |
1970 | #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) |
- | 1971 | ||
1805 | 1972 | /* HSW+ eDP PSR registers */ |
|
1806 | /* HSW eDP PSR registers */ |
1973 | #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) |
1807 | #define EDP_PSR_CTL 0x64800 |
1974 | #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) |
1808 | #define EDP_PSR_ENABLE (1<<31) |
1975 | #define EDP_PSR_ENABLE (1<<31) |
1809 | #define EDP_PSR_LINK_DISABLE (0<<27) |
1976 | #define EDP_PSR_LINK_DISABLE (0<<27) |
1810 | #define EDP_PSR_LINK_STANDBY (1<<27) |
1977 | #define EDP_PSR_LINK_STANDBY (1<<27) |
Line 1825... | Line 1992... | ||
1825 | #define EDP_PSR_TP1_TIME_100us (1<<4) |
1992 | #define EDP_PSR_TP1_TIME_100us (1<<4) |
1826 | #define EDP_PSR_TP1_TIME_2500us (2<<4) |
1993 | #define EDP_PSR_TP1_TIME_2500us (2<<4) |
1827 | #define EDP_PSR_TP1_TIME_0us (3<<4) |
1994 | #define EDP_PSR_TP1_TIME_0us (3<<4) |
1828 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 |
1995 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 |
Line 1829... | Line 1996... | ||
1829 | 1996 | ||
1830 | #define EDP_PSR_AUX_CTL 0x64810 |
1997 | #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) |
1831 | #define EDP_PSR_AUX_DATA1 0x64814 |
1998 | #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) |
1832 | #define EDP_PSR_DPCD_COMMAND 0x80060000 |
1999 | #define EDP_PSR_DPCD_COMMAND 0x80060000 |
1833 | #define EDP_PSR_AUX_DATA2 0x64818 |
2000 | #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) |
1834 | #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24) |
2001 | #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24) |
1835 | #define EDP_PSR_AUX_DATA3 0x6481c |
2002 | #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) |
1836 | #define EDP_PSR_AUX_DATA4 0x64820 |
2003 | #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) |
Line 1837... | Line 2004... | ||
1837 | #define EDP_PSR_AUX_DATA5 0x64824 |
2004 | #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) |
1838 | 2005 | ||
1839 | #define EDP_PSR_STATUS_CTL 0x64840 |
2006 | #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) |
1840 | #define EDP_PSR_STATUS_STATE_MASK (7<<29) |
2007 | #define EDP_PSR_STATUS_STATE_MASK (7<<29) |
1841 | #define EDP_PSR_STATUS_STATE_IDLE (0<<29) |
2008 | #define EDP_PSR_STATUS_STATE_IDLE (0<<29) |
1842 | #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) |
2009 | #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) |
Line 1858... | Line 2025... | ||
1858 | #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) |
2025 | #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) |
1859 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) |
2026 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) |
1860 | #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) |
2027 | #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) |
1861 | #define EDP_PSR_STATUS_IDLE_MASK 0xf |
2028 | #define EDP_PSR_STATUS_IDLE_MASK 0xf |
Line 1862... | Line 2029... | ||
1862 | 2029 | ||
1863 | #define EDP_PSR_PERF_CNT 0x64844 |
2030 | #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) |
Line 1864... | Line 2031... | ||
1864 | #define EDP_PSR_PERF_CNT_MASK 0xffffff |
2031 | #define EDP_PSR_PERF_CNT_MASK 0xffffff |
1865 | 2032 | ||
1866 | #define EDP_PSR_DEBUG_CTL 0x64860 |
2033 | #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) |
1867 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
2034 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
Line 1868... | Line 2035... | ||
1868 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) |
2035 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) |
Line 1953... | Line 2120... | ||
1953 | * |
2120 | * |
1954 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. |
2121 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. |
1955 | * Please check the detailed lore in the commit message for for experimental |
2122 | * Please check the detailed lore in the commit message for for experimental |
1956 | * evidence. |
2123 | * evidence. |
1957 | */ |
2124 | */ |
1958 | #define PORTD_HOTPLUG_LIVE_STATUS (1 << 29) |
2125 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
1959 | #define PORTC_HOTPLUG_LIVE_STATUS (1 << 28) |
2126 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
1960 | #define PORTB_HOTPLUG_LIVE_STATUS (1 << 27) |
2127 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) |
- | 2128 | /* VLV DP/HDMI bits again match Bspec */ |
|
- | 2129 | #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) |
|
- | 2130 | #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) |
|
- | 2131 | #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) |
|
1961 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
2132 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
1962 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
2133 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
1963 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
2134 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
1964 | /* CRT/TV common between gen3+ */ |
2135 | /* CRT/TV common between gen3+ */ |
1965 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
2136 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
1966 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
2137 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
1967 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
2138 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
1968 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
2139 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
1969 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
2140 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
1970 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
2141 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
- | 2142 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
|
- | 2143 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) |
|
- | 2144 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) |
|
- | 2145 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
|
- | 2146 | ||
1971 | /* SDVO is different across gen3/4 */ |
2147 | /* SDVO is different across gen3/4 */ |
1972 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
2148 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
1973 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
2149 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
1974 | /* |
2150 | /* |
1975 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, |
2151 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, |
Line 2004... | Line 2180... | ||
2004 | #define PCH_SDVOB 0xe1140 |
2180 | #define PCH_SDVOB 0xe1140 |
2005 | #define PCH_HDMIB PCH_SDVOB |
2181 | #define PCH_HDMIB PCH_SDVOB |
2006 | #define PCH_HDMIC 0xe1150 |
2182 | #define PCH_HDMIC 0xe1150 |
2007 | #define PCH_HDMID 0xe1160 |
2183 | #define PCH_HDMID 0xe1160 |
Line -... | Line 2184... | ||
- | 2184 | ||
- | 2185 | #define PORT_DFT_I9XX 0x61150 |
|
- | 2186 | #define DC_BALANCE_RESET (1 << 25) |
|
- | 2187 | #define PORT_DFT2_G4X 0x61154 |
|
- | 2188 | #define DC_BALANCE_RESET_VLV (1 << 31) |
|
- | 2189 | #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) |
|
- | 2190 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) |
|
- | 2191 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) |
|
2008 | 2192 | ||
2009 | /* Gen 3 SDVO bits: */ |
2193 | /* Gen 3 SDVO bits: */ |
2010 | #define SDVO_ENABLE (1 << 31) |
2194 | #define SDVO_ENABLE (1 << 31) |
2011 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
2195 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
2012 | #define SDVO_PIPE_SEL_MASK (1 << 30) |
2196 | #define SDVO_PIPE_SEL_MASK (1 << 30) |
Line 2032... | Line 2216... | ||
2032 | SDVO_INTERRUPT_ENABLE) |
2216 | SDVO_INTERRUPT_ENABLE) |
2033 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) |
2217 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) |
Line 2034... | Line 2218... | ||
2034 | 2218 | ||
2035 | /* Gen 4 SDVO/HDMI bits: */ |
2219 | /* Gen 4 SDVO/HDMI bits: */ |
- | 2220 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
|
2036 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
2221 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
2037 | #define SDVO_ENCODING_SDVO (0 << 10) |
2222 | #define SDVO_ENCODING_SDVO (0 << 10) |
2038 | #define SDVO_ENCODING_HDMI (2 << 10) |
2223 | #define SDVO_ENCODING_HDMI (2 << 10) |
2039 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
2224 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
2040 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ |
2225 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ |
Line 2236... | Line 2421... | ||
2236 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 |
2421 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 |
2237 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
2422 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
Line 2238... | Line 2423... | ||
2238 | 2423 | ||
Line -... | Line 2424... | ||
- | 2424 | #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238) |
|
- | 2425 | ||
- | 2426 | #define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250) |
|
- | 2427 | #define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350) |
|
- | 2428 | #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ |
|
- | 2429 | _VLV_BLC_PWM_CTL2_B) |
|
- | 2430 | ||
- | 2431 | #define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254) |
|
- | 2432 | #define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354) |
|
- | 2433 | #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ |
|
- | 2434 | _VLV_BLC_PWM_CTL_B) |
|
- | 2435 | ||
- | 2436 | #define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260) |
|
- | 2437 | #define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360) |
|
- | 2438 | #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ |
|
2239 | #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238) |
2439 | _VLV_BLC_HIST_CTL_B) |
2240 | 2440 | ||
2241 | /* Backlight control */ |
2441 | /* Backlight control */ |
2242 | #define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */ |
2442 | #define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */ |
2243 | #define BLM_PWM_ENABLE (1 << 31) |
2443 | #define BLM_PWM_ENABLE (1 << 31) |
Line 2984... | Line 3184... | ||
2984 | #define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) |
3184 | #define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) |
2985 | #define PIPECONF_ENABLE (1<<31) |
3185 | #define PIPECONF_ENABLE (1<<31) |
2986 | #define PIPECONF_DISABLE 0 |
3186 | #define PIPECONF_DISABLE 0 |
2987 | #define PIPECONF_DOUBLE_WIDE (1<<30) |
3187 | #define PIPECONF_DOUBLE_WIDE (1<<30) |
2988 | #define I965_PIPECONF_ACTIVE (1<<30) |
3188 | #define I965_PIPECONF_ACTIVE (1<<30) |
- | 3189 | #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ |
|
2989 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
3190 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
2990 | #define PIPECONF_SINGLE_WIDE 0 |
3191 | #define PIPECONF_SINGLE_WIDE 0 |
2991 | #define PIPECONF_PIPE_UNLOCKED 0 |
3192 | #define PIPECONF_PIPE_UNLOCKED 0 |
2992 | #define PIPECONF_PIPE_LOCKED (1<<25) |
3193 | #define PIPECONF_PIPE_LOCKED (1<<25) |
2993 | #define PIPECONF_PALETTE 0 |
3194 | #define PIPECONF_PALETTE 0 |
Line 3066... | Line 3267... | ||
3066 | #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) |
3267 | #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) |
3067 | #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) |
3268 | #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) |
3068 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
3269 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
3069 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
3270 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
Line -... | Line 3271... | ||
- | 3271 | ||
- | 3272 | #define _PIPE_MISC_A 0x70030 |
|
- | 3273 | #define _PIPE_MISC_B 0x71030 |
|
- | 3274 | #define PIPEMISC_DITHER_BPC_MASK (7<<5) |
|
- | 3275 | #define PIPEMISC_DITHER_8_BPC (0<<5) |
|
- | 3276 | #define PIPEMISC_DITHER_10_BPC (1<<5) |
|
- | 3277 | #define PIPEMISC_DITHER_6_BPC (2<<5) |
|
- | 3278 | #define PIPEMISC_DITHER_12_BPC (3<<5) |
|
- | 3279 | #define PIPEMISC_DITHER_ENABLE (1<<4) |
|
- | 3280 | #define PIPEMISC_DITHER_TYPE_MASK (3<<2) |
|
- | 3281 | #define PIPEMISC_DITHER_TYPE_SP (0<<2) |
|
- | 3282 | #define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) |
|
3070 | 3283 | ||
3071 | #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) |
3284 | #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) |
3072 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
3285 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
3073 | #define PIPEB_HLINE_INT_EN (1<<28) |
3286 | #define PIPEB_HLINE_INT_EN (1<<28) |
3074 | #define PIPEB_VBLANK_INT_EN (1<<27) |
3287 | #define PIPEB_VBLANK_INT_EN (1<<27) |
Line 3182... | Line 3395... | ||
3182 | #define I965_CURSOR_MAX_WM 32 |
3395 | #define I965_CURSOR_MAX_WM 32 |
3183 | #define I965_CURSOR_DFT_WM 8 |
3396 | #define I965_CURSOR_DFT_WM 8 |
Line 3184... | Line 3397... | ||
3184 | 3397 | ||
3185 | /* define the Watermark register on Ironlake */ |
3398 | /* define the Watermark register on Ironlake */ |
3186 | #define WM0_PIPEA_ILK 0x45100 |
3399 | #define WM0_PIPEA_ILK 0x45100 |
3187 | #define WM0_PIPE_PLANE_MASK (0x7f<<16) |
3400 | #define WM0_PIPE_PLANE_MASK (0xffff<<16) |
3188 | #define WM0_PIPE_PLANE_SHIFT 16 |
3401 | #define WM0_PIPE_PLANE_SHIFT 16 |
3189 | #define WM0_PIPE_SPRITE_MASK (0x3f<<8) |
3402 | #define WM0_PIPE_SPRITE_MASK (0xff<<8) |
3190 | #define WM0_PIPE_SPRITE_SHIFT 8 |
3403 | #define WM0_PIPE_SPRITE_SHIFT 8 |
Line 3191... | Line 3404... | ||
3191 | #define WM0_PIPE_CURSOR_MASK (0x1f) |
3404 | #define WM0_PIPE_CURSOR_MASK (0xff) |
3192 | 3405 | ||
3193 | #define WM0_PIPEB_ILK 0x45104 |
3406 | #define WM0_PIPEB_ILK 0x45104 |
3194 | #define WM0_PIPEC_IVB 0x45200 |
3407 | #define WM0_PIPEC_IVB 0x45200 |
3195 | #define WM1_LP_ILK 0x45108 |
3408 | #define WM1_LP_ILK 0x45108 |
3196 | #define WM1_LP_SR_EN (1<<31) |
3409 | #define WM1_LP_SR_EN (1<<31) |
3197 | #define WM1_LP_LATENCY_SHIFT 24 |
3410 | #define WM1_LP_LATENCY_SHIFT 24 |
3198 | #define WM1_LP_LATENCY_MASK (0x7f<<24) |
3411 | #define WM1_LP_LATENCY_MASK (0x7f<<24) |
- | 3412 | #define WM1_LP_FBC_MASK (0xf<<20) |
|
3199 | #define WM1_LP_FBC_MASK (0xf<<20) |
3413 | #define WM1_LP_FBC_SHIFT 20 |
3200 | #define WM1_LP_FBC_SHIFT 20 |
3414 | #define WM1_LP_FBC_SHIFT_BDW 19 |
3201 | #define WM1_LP_SR_MASK (0x1ff<<8) |
3415 | #define WM1_LP_SR_MASK (0x7ff<<8) |
3202 | #define WM1_LP_SR_SHIFT 8 |
3416 | #define WM1_LP_SR_SHIFT 8 |
3203 | #define WM1_LP_CURSOR_MASK (0x3f) |
3417 | #define WM1_LP_CURSOR_MASK (0xff) |
3204 | #define WM2_LP_ILK 0x4510c |
3418 | #define WM2_LP_ILK 0x4510c |
3205 | #define WM2_LP_EN (1<<31) |
3419 | #define WM2_LP_EN (1<<31) |
3206 | #define WM3_LP_ILK 0x45110 |
3420 | #define WM3_LP_ILK 0x45110 |
Line 3219... | Line 3433... | ||
3219 | #define MLTR_WM1_SHIFT 0 |
3433 | #define MLTR_WM1_SHIFT 0 |
3220 | #define MLTR_WM2_SHIFT 8 |
3434 | #define MLTR_WM2_SHIFT 8 |
3221 | /* the unit of memory self-refresh latency time is 0.5us */ |
3435 | /* the unit of memory self-refresh latency time is 0.5us */ |
3222 | #define ILK_SRLT_MASK 0x3f |
3436 | #define ILK_SRLT_MASK 0x3f |
Line 3223... | Line -... | ||
3223 | - | ||
3224 | /* define the fifo size on Ironlake */ |
- | |
3225 | #define ILK_DISPLAY_FIFO 128 |
- | |
3226 | #define ILK_DISPLAY_MAXWM 64 |
- | |
3227 | #define ILK_DISPLAY_DFTWM 8 |
- | |
3228 | #define ILK_CURSOR_FIFO 32 |
- | |
3229 | #define ILK_CURSOR_MAXWM 16 |
- | |
3230 | #define ILK_CURSOR_DFTWM 8 |
- | |
3231 | - | ||
3232 | #define ILK_DISPLAY_SR_FIFO 512 |
- | |
3233 | #define ILK_DISPLAY_MAX_SRWM 0x1ff |
- | |
3234 | #define ILK_DISPLAY_DFT_SRWM 0x3f |
- | |
3235 | #define ILK_CURSOR_SR_FIFO 64 |
- | |
3236 | #define ILK_CURSOR_MAX_SRWM 0x3f |
- | |
3237 | #define ILK_CURSOR_DFT_SRWM 8 |
- | |
3238 | - | ||
3239 | #define ILK_FIFO_LINE_SIZE 64 |
- | |
3240 | - | ||
3241 | /* define the WM info on Sandybridge */ |
- | |
3242 | #define SNB_DISPLAY_FIFO 128 |
- | |
3243 | #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ |
- | |
3244 | #define SNB_DISPLAY_DFTWM 8 |
- | |
3245 | #define SNB_CURSOR_FIFO 32 |
- | |
3246 | #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ |
- | |
3247 | #define SNB_CURSOR_DFTWM 8 |
- | |
3248 | - | ||
3249 | #define SNB_DISPLAY_SR_FIFO 512 |
- | |
3250 | #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ |
- | |
3251 | #define SNB_DISPLAY_DFT_SRWM 0x3f |
- | |
3252 | #define SNB_CURSOR_SR_FIFO 64 |
- | |
3253 | #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ |
- | |
3254 | #define SNB_CURSOR_DFT_SRWM 8 |
- | |
3255 | - | ||
3256 | #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ |
- | |
3257 | - | ||
3258 | #define SNB_FIFO_LINE_SIZE 64 |
- | |
Line 3259... | Line 3437... | ||
3259 | 3437 | ||
3260 | 3438 | ||
3261 | /* the address where we get all kinds of latency value */ |
3439 | /* the address where we get all kinds of latency value */ |
3262 | #define SSKPD 0x5d10 |
3440 | #define SSKPD 0x5d10 |
Line 3279... | Line 3457... | ||
3279 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
3457 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
3280 | * PIPE_FRAME_HIGH_SHIFT); |
3458 | * PIPE_FRAME_HIGH_SHIFT); |
3281 | * } while (high1 != high2); |
3459 | * } while (high1 != high2); |
3282 | * frame = (high1 << 8) | low1; |
3460 | * frame = (high1 << 8) | low1; |
3283 | */ |
3461 | */ |
3284 | #define _PIPEAFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x70040) |
3462 | #define _PIPEAFRAMEHIGH 0x70040 |
3285 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
3463 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
3286 | #define PIPE_FRAME_HIGH_SHIFT 0 |
3464 | #define PIPE_FRAME_HIGH_SHIFT 0 |
3287 | #define _PIPEAFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x70044) |
3465 | #define _PIPEAFRAMEPIXEL 0x70044 |
3288 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
3466 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
3289 | #define PIPE_FRAME_LOW_SHIFT 24 |
3467 | #define PIPE_FRAME_LOW_SHIFT 24 |
3290 | #define PIPE_PIXEL_MASK 0x00ffffff |
3468 | #define PIPE_PIXEL_MASK 0x00ffffff |
3291 | #define PIPE_PIXEL_SHIFT 0 |
3469 | #define PIPE_PIXEL_SHIFT 0 |
3292 | /* GM45+ just has to be different */ |
3470 | /* GM45+ just has to be different */ |
3293 | #define _PIPEA_FRMCOUNT_GM45 0x70040 |
3471 | #define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040) |
3294 | #define _PIPEA_FLIPCOUNT_GM45 0x70044 |
3472 | #define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044) |
3295 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) |
3473 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) |
Line 3296... | Line 3474... | ||
3296 | 3474 | ||
3297 | /* Cursor A & B regs */ |
3475 | /* Cursor A & B regs */ |
3298 | #define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080) |
3476 | #define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080) |
Line 3398... | Line 3576... | ||
3398 | 3576 | ||
3399 | /* Display/Sprite base address macros */ |
3577 | /* Display/Sprite base address macros */ |
3400 | #define DISP_BASEADDR_MASK (0xfffff000) |
3578 | #define DISP_BASEADDR_MASK (0xfffff000) |
3401 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
3579 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
3402 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
- | |
3403 | #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ |
- | |
Line 3404... | Line 3580... | ||
3404 | (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) |
3580 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
3405 | 3581 | ||
3406 | /* VBIOS flags */ |
3582 | /* VBIOS flags */ |
3407 | #define SWF00 (dev_priv->info->display_mmio_offset + 0x71410) |
3583 | #define SWF00 (dev_priv->info->display_mmio_offset + 0x71410) |
Line 3420... | Line 3596... | ||
3420 | 3596 | ||
3421 | /* Pipe B */ |
3597 | /* Pipe B */ |
3422 | #define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000) |
3598 | #define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000) |
3423 | #define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008) |
3599 | #define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008) |
3424 | #define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024) |
3600 | #define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024) |
3425 | #define _PIPEBFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x71040) |
3601 | #define _PIPEBFRAMEHIGH 0x71040 |
3426 | #define _PIPEBFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x71044) |
3602 | #define _PIPEBFRAMEPIXEL 0x71044 |
3427 | #define _PIPEB_FRMCOUNT_GM45 0x71040 |
3603 | #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040) |
Line 3428... | Line 3604... | ||
3428 | #define _PIPEB_FLIPCOUNT_GM45 0x71044 |
3604 | #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044) |
3429 | 3605 | ||
3430 | 3606 | ||
Line 3585... | Line 3761... | ||
3585 | #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) |
3761 | #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) |
3586 | #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
3762 | #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
Line 3587... | Line 3763... | ||
3587 | 3763 | ||
3588 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
3764 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
3589 | #define SP_ENABLE (1<<31) |
3765 | #define SP_ENABLE (1<<31) |
3590 | #define SP_GEAMMA_ENABLE (1<<30) |
3766 | #define SP_GAMMA_ENABLE (1<<30) |
3591 | #define SP_PIXFORMAT_MASK (0xf<<26) |
3767 | #define SP_PIXFORMAT_MASK (0xf<<26) |
3592 | #define SP_FORMAT_YUV422 (0<<26) |
3768 | #define SP_FORMAT_YUV422 (0<<26) |
3593 | #define SP_FORMAT_BGR565 (5<<26) |
3769 | #define SP_FORMAT_BGR565 (5<<26) |
3594 | #define SP_FORMAT_BGRX8888 (6<<26) |
3770 | #define SP_FORMAT_BGRX8888 (6<<26) |
Line 3778... | Line 3954... | ||
3778 | #define DE_MASTER_IRQ_CONTROL (1 << 31) |
3954 | #define DE_MASTER_IRQ_CONTROL (1 << 31) |
3779 | #define DE_SPRITEB_FLIP_DONE (1 << 29) |
3955 | #define DE_SPRITEB_FLIP_DONE (1 << 29) |
3780 | #define DE_SPRITEA_FLIP_DONE (1 << 28) |
3956 | #define DE_SPRITEA_FLIP_DONE (1 << 28) |
3781 | #define DE_PLANEB_FLIP_DONE (1 << 27) |
3957 | #define DE_PLANEB_FLIP_DONE (1 << 27) |
3782 | #define DE_PLANEA_FLIP_DONE (1 << 26) |
3958 | #define DE_PLANEA_FLIP_DONE (1 << 26) |
- | 3959 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
|
3783 | #define DE_PCU_EVENT (1 << 25) |
3960 | #define DE_PCU_EVENT (1 << 25) |
3784 | #define DE_GTT_FAULT (1 << 24) |
3961 | #define DE_GTT_FAULT (1 << 24) |
3785 | #define DE_POISON (1 << 23) |
3962 | #define DE_POISON (1 << 23) |
3786 | #define DE_PERFORM_COUNTER (1 << 22) |
3963 | #define DE_PERFORM_COUNTER (1 << 22) |
3787 | #define DE_PCH_EVENT (1 << 21) |
3964 | #define DE_PCH_EVENT (1 << 21) |
Line 3791... | Line 3968... | ||
3791 | #define DE_PIPEB_VBLANK (1 << 15) |
3968 | #define DE_PIPEB_VBLANK (1 << 15) |
3792 | #define DE_PIPEB_EVEN_FIELD (1 << 14) |
3969 | #define DE_PIPEB_EVEN_FIELD (1 << 14) |
3793 | #define DE_PIPEB_ODD_FIELD (1 << 13) |
3970 | #define DE_PIPEB_ODD_FIELD (1 << 13) |
3794 | #define DE_PIPEB_LINE_COMPARE (1 << 12) |
3971 | #define DE_PIPEB_LINE_COMPARE (1 << 12) |
3795 | #define DE_PIPEB_VSYNC (1 << 11) |
3972 | #define DE_PIPEB_VSYNC (1 << 11) |
- | 3973 | #define DE_PIPEB_CRC_DONE (1 << 10) |
|
3796 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
3974 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
3797 | #define DE_PIPEA_VBLANK (1 << 7) |
3975 | #define DE_PIPEA_VBLANK (1 << 7) |
- | 3976 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) |
|
3798 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
3977 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
3799 | #define DE_PIPEA_ODD_FIELD (1 << 5) |
3978 | #define DE_PIPEA_ODD_FIELD (1 << 5) |
3800 | #define DE_PIPEA_LINE_COMPARE (1 << 4) |
3979 | #define DE_PIPEA_LINE_COMPARE (1 << 4) |
3801 | #define DE_PIPEA_VSYNC (1 << 3) |
3980 | #define DE_PIPEA_VSYNC (1 << 3) |
- | 3981 | #define DE_PIPEA_CRC_DONE (1 << 2) |
|
- | 3982 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) |
|
3802 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
3983 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
- | 3984 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) |
|
Line 3803... | Line 3985... | ||
3803 | 3985 | ||
3804 | /* More Ivybridge lolz */ |
3986 | /* More Ivybridge lolz */ |
3805 | #define DE_ERR_INT_IVB (1<<30) |
3987 | #define DE_ERR_INT_IVB (1<<30) |
3806 | #define DE_GSE_IVB (1<<29) |
3988 | #define DE_GSE_IVB (1<<29) |
Line 3813... | Line 3995... | ||
3813 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
3995 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
3814 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
3996 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
3815 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
3997 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
3816 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
3998 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
3817 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
3999 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
- | 4000 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) |
|
3818 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
4001 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
3819 | - | ||
3820 | #define DE_PIPE_VBLANK_ILK(pipe) (1 << ((pipe * 8) + 7)) |
- | |
3821 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) |
4002 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) |
Line 3822... | Line 4003... | ||
3822 | 4003 | ||
3823 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
4004 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
Line 3831... | Line 4012... | ||
3831 | #define GTISR 0x44010 |
4012 | #define GTISR 0x44010 |
3832 | #define GTIMR 0x44014 |
4013 | #define GTIMR 0x44014 |
3833 | #define GTIIR 0x44018 |
4014 | #define GTIIR 0x44018 |
3834 | #define GTIER 0x4401c |
4015 | #define GTIER 0x4401c |
Line -... | Line 4016... | ||
- | 4016 | ||
- | 4017 | #define GEN8_MASTER_IRQ 0x44200 |
|
- | 4018 | #define GEN8_MASTER_IRQ_CONTROL (1<<31) |
|
- | 4019 | #define GEN8_PCU_IRQ (1<<30) |
|
- | 4020 | #define GEN8_DE_PCH_IRQ (1<<23) |
|
- | 4021 | #define GEN8_DE_MISC_IRQ (1<<22) |
|
- | 4022 | #define GEN8_DE_PORT_IRQ (1<<20) |
|
- | 4023 | #define GEN8_DE_PIPE_C_IRQ (1<<18) |
|
- | 4024 | #define GEN8_DE_PIPE_B_IRQ (1<<17) |
|
- | 4025 | #define GEN8_DE_PIPE_A_IRQ (1<<16) |
|
- | 4026 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) |
|
- | 4027 | #define GEN8_GT_VECS_IRQ (1<<6) |
|
- | 4028 | #define GEN8_GT_VCS2_IRQ (1<<3) |
|
- | 4029 | #define GEN8_GT_VCS1_IRQ (1<<2) |
|
- | 4030 | #define GEN8_GT_BCS_IRQ (1<<1) |
|
- | 4031 | #define GEN8_GT_RCS_IRQ (1<<0) |
|
- | 4032 | ||
- | 4033 | #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) |
|
- | 4034 | #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) |
|
- | 4035 | #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) |
|
- | 4036 | #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) |
|
- | 4037 | ||
- | 4038 | #define GEN8_BCS_IRQ_SHIFT 16 |
|
- | 4039 | #define GEN8_RCS_IRQ_SHIFT 0 |
|
- | 4040 | #define GEN8_VCS2_IRQ_SHIFT 16 |
|
- | 4041 | #define GEN8_VCS1_IRQ_SHIFT 0 |
|
- | 4042 | #define GEN8_VECS_IRQ_SHIFT 0 |
|
- | 4043 | ||
- | 4044 | #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) |
|
- | 4045 | #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) |
|
- | 4046 | #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) |
|
- | 4047 | #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) |
|
- | 4048 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
|
- | 4049 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
|
- | 4050 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) |
|
- | 4051 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) |
|
- | 4052 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) |
|
- | 4053 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) |
|
- | 4054 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) |
|
- | 4055 | #define GEN8_PIPE_FLIP_DONE (1 << 4) |
|
- | 4056 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
|
- | 4057 | #define GEN8_PIPE_VSYNC (1 << 1) |
|
- | 4058 | #define GEN8_PIPE_VBLANK (1 << 0) |
|
- | 4059 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
|
- | 4060 | (GEN8_PIPE_CURSOR_FAULT | \ |
|
- | 4061 | GEN8_PIPE_SPRITE_FAULT | \ |
|
- | 4062 | GEN8_PIPE_PRIMARY_FAULT) |
|
- | 4063 | ||
- | 4064 | #define GEN8_DE_PORT_ISR 0x44440 |
|
- | 4065 | #define GEN8_DE_PORT_IMR 0x44444 |
|
- | 4066 | #define GEN8_DE_PORT_IIR 0x44448 |
|
- | 4067 | #define GEN8_DE_PORT_IER 0x4444c |
|
- | 4068 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) |
|
- | 4069 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
|
- | 4070 | ||
- | 4071 | #define GEN8_DE_MISC_ISR 0x44460 |
|
- | 4072 | #define GEN8_DE_MISC_IMR 0x44464 |
|
- | 4073 | #define GEN8_DE_MISC_IIR 0x44468 |
|
- | 4074 | #define GEN8_DE_MISC_IER 0x4446c |
|
- | 4075 | #define GEN8_DE_MISC_GSE (1 << 27) |
|
- | 4076 | ||
- | 4077 | #define GEN8_PCU_ISR 0x444e0 |
|
- | 4078 | #define GEN8_PCU_IMR 0x444e4 |
|
- | 4079 | #define GEN8_PCU_IIR 0x444e8 |
|
- | 4080 | #define GEN8_PCU_IER 0x444ec |
|
3835 | 4081 | ||
3836 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
4082 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
3837 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
4083 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
3838 | #define ILK_ELPIN_409_SELECT (1 << 25) |
4084 | #define ILK_ELPIN_409_SELECT (1 << 25) |
3839 | #define ILK_DPARB_GATE (1<<22) |
4085 | #define ILK_DPARB_GATE (1<<22) |
Line 3856... | Line 4102... | ||
3856 | #define IVB_CHICKEN3 0x4200c |
4102 | #define IVB_CHICKEN3 0x4200c |
3857 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
4103 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
3858 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) |
4104 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) |
Line 3859... | Line 4105... | ||
3859 | 4105 | ||
- | 4106 | #define CHICKEN_PAR1_1 0x42080 |
|
3860 | #define CHICKEN_PAR1_1 0x42080 |
4107 | #define DPA_MASK_VBLANK_SRD (1 << 15) |
Line -... | Line 4108... | ||
- | 4108 | #define FORCE_ARB_IDLE_PLANES (1 << 14) |
|
- | 4109 | ||
- | 4110 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
|
- | 4111 | #define _CHICKEN_PIPESL_1_B 0x420b4 |
|
- | 4112 | #define DPRS_MASK_VBLANK_SRD (1 << 0) |
|
3861 | #define FORCE_ARB_IDLE_PLANES (1 << 14) |
4113 | #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
3862 | 4114 | ||
3863 | #define DISP_ARB_CTL 0x45000 |
4115 | #define DISP_ARB_CTL 0x45000 |
- | 4116 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
|
- | 4117 | #define DISP_FBC_WM_DIS (1<<15) |
|
3864 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
4118 | #define DISP_ARB_CTL2 0x45004 |
3865 | #define DISP_FBC_WM_DIS (1<<15) |
4119 | #define DISP_DATA_PARTITION_5_6 (1<<6) |
3866 | #define GEN7_MSG_CTL 0x45010 |
4120 | #define GEN7_MSG_CTL 0x45010 |
Line 3867... | Line 4121... | ||
3867 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) |
4121 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) |
3868 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) |
4122 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) |
3869 | 4123 | ||
- | 4124 | /* GEN7 chicken */ |
|
- | 4125 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
|
Line 3870... | Line 4126... | ||
3870 | /* GEN7 chicken */ |
4126 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
3871 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
4127 | #define COMMON_SLICE_CHICKEN2 0x7014 |
3872 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
4128 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) |
Line 3879... | Line 4135... | ||
3879 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
4135 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
Line 3880... | Line 4136... | ||
3880 | 4136 | ||
3881 | #define GEN7_L3SQCREG4 0xb034 |
4137 | #define GEN7_L3SQCREG4 0xb034 |
Line -... | Line 4138... | ||
- | 4138 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
|
- | 4139 | ||
- | 4140 | /* GEN8 chicken */ |
|
- | 4141 | #define HDC_CHICKEN0 0x7300 |
|
3882 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
4142 | #define HDC_FORCE_NON_COHERENT (1<<4) |
3883 | 4143 | ||
3884 | /* WaCatErrorRejectionIssue */ |
4144 | /* WaCatErrorRejectionIssue */ |
Line 3885... | Line 4145... | ||
3885 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
4145 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
Line 4414... | Line 4674... | ||
4414 | 4674 | ||
4415 | /* vlv has 2 sets of panel control regs. */ |
4675 | /* vlv has 2 sets of panel control regs. */ |
4416 | #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
4676 | #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
4417 | #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) |
4677 | #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) |
- | 4678 | #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) |
|
- | 4679 | #define PANEL_PORT_SELECT_DPB_VLV (1 << 30) |
|
4418 | #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) |
4680 | #define PANEL_PORT_SELECT_DPC_VLV (2 << 30) |
4419 | #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) |
4681 | #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) |
Line 4420... | Line 4682... | ||
4420 | #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) |
4682 | #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) |
4421 | 4683 | ||
Line 4445... | Line 4707... | ||
4445 | #define PANEL_POWER_ON (1 << 0) |
4707 | #define PANEL_POWER_ON (1 << 0) |
4446 | #define PCH_PP_ON_DELAYS 0xc7208 |
4708 | #define PCH_PP_ON_DELAYS 0xc7208 |
4447 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
4709 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
4448 | #define PANEL_PORT_SELECT_LVDS (0 << 30) |
4710 | #define PANEL_PORT_SELECT_LVDS (0 << 30) |
4449 | #define PANEL_PORT_SELECT_DPA (1 << 30) |
4711 | #define PANEL_PORT_SELECT_DPA (1 << 30) |
4450 | #define EDP_PANEL (1 << 30) |
- | |
4451 | #define PANEL_PORT_SELECT_DPC (2 << 30) |
4712 | #define PANEL_PORT_SELECT_DPC (2 << 30) |
4452 | #define PANEL_PORT_SELECT_DPD (3 << 30) |
4713 | #define PANEL_PORT_SELECT_DPD (3 << 30) |
4453 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) |
4714 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) |
4454 | #define PANEL_POWER_UP_DELAY_SHIFT 16 |
4715 | #define PANEL_POWER_UP_DELAY_SHIFT 16 |
4455 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) |
4716 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) |
4456 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 |
4717 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 |
Line 4457... | Line 4718... | ||
4457 | 4718 | ||
4458 | #define PCH_PP_OFF_DELAYS 0xc720c |
- | |
4459 | #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) |
- | |
4460 | #define PANEL_POWER_PORT_LVDS (0 << 30) |
- | |
4461 | #define PANEL_POWER_PORT_DP_A (1 << 30) |
- | |
4462 | #define PANEL_POWER_PORT_DP_C (2 << 30) |
- | |
4463 | #define PANEL_POWER_PORT_DP_D (3 << 30) |
4719 | #define PCH_PP_OFF_DELAYS 0xc720c |
4464 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
4720 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
4465 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 |
4721 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 |
4466 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) |
4722 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) |
Line 4567... | Line 4823... | ||
4567 | #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc |
4823 | #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc |
4568 | #define FORCEWAKE_ACK_HSW 0x130044 |
4824 | #define FORCEWAKE_ACK_HSW 0x130044 |
4569 | #define FORCEWAKE_ACK 0x130090 |
4825 | #define FORCEWAKE_ACK 0x130090 |
4570 | #define VLV_GTLC_WAKE_CTRL 0x130090 |
4826 | #define VLV_GTLC_WAKE_CTRL 0x130090 |
4571 | #define VLV_GTLC_PW_STATUS 0x130094 |
4827 | #define VLV_GTLC_PW_STATUS 0x130094 |
- | 4828 | #define VLV_GTLC_PW_RENDER_STATUS_MASK 0x80 |
|
- | 4829 | #define VLV_GTLC_PW_MEDIA_STATUS_MASK 0x20 |
|
4572 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
4830 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
4573 | #define FORCEWAKE_KERNEL 0x1 |
4831 | #define FORCEWAKE_KERNEL 0x1 |
4574 | #define FORCEWAKE_USER 0x2 |
4832 | #define FORCEWAKE_USER 0x2 |
4575 | #define FORCEWAKE_MT_ACK 0x130040 |
4833 | #define FORCEWAKE_MT_ACK 0x130040 |
4576 | #define ECOBUS 0xa180 |
4834 | #define ECOBUS 0xa180 |
4577 | #define FORCEWAKE_MT_ENABLE (1<<5) |
4835 | #define FORCEWAKE_MT_ENABLE (1<<5) |
Line 4578... | Line 4836... | ||
4578 | 4836 | ||
- | 4837 | #define GTFIFODBG 0x120000 |
|
- | 4838 | #define GT_FIFO_SBDROPERR (1<<6) |
|
- | 4839 | #define GT_FIFO_BLOBDROPERR (1<<5) |
|
4579 | #define GTFIFODBG 0x120000 |
4840 | #define GT_FIFO_SB_READ_ABORTERR (1<<4) |
4580 | #define GT_FIFO_CPU_ERROR_MASK 7 |
4841 | #define GT_FIFO_DROPERR (1<<3) |
4581 | #define GT_FIFO_OVFERR (1<<2) |
4842 | #define GT_FIFO_OVFERR (1<<2) |
4582 | #define GT_FIFO_IAWRERR (1<<1) |
4843 | #define GT_FIFO_IAWRERR (1<<1) |
Line -... | Line 4844... | ||
- | 4844 | #define GT_FIFO_IARDERR (1<<0) |
|
4583 | #define GT_FIFO_IARDERR (1<<0) |
4845 | |
4584 | 4846 | #define GTFIFOCTL 0x120008 |
|
Line 4585... | Line 4847... | ||
4585 | #define GT_FIFO_FREE_ENTRIES 0x120008 |
4847 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f |
4586 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
4848 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
4587 | 4849 | ||
Line 4614... | Line 4876... | ||
4614 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) |
4876 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) |
4615 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) |
4877 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) |
4616 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) |
4878 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) |
4617 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) |
4879 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) |
4618 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) |
4880 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) |
- | 4881 | #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) |
|
4619 | #define GEN7_RC_CTL_TO_MODE (1<<28) |
4882 | #define GEN7_RC_CTL_TO_MODE (1<<28) |
4620 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) |
4883 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) |
4621 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) |
4884 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) |
4622 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 |
4885 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 |
4623 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 |
4886 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 |
Line 4636... | Line 4899... | ||
4636 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
4899 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
4637 | #define GEN6_RP_ENABLE (1<<7) |
4900 | #define GEN6_RP_ENABLE (1<<7) |
4638 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
4901 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
4639 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) |
4902 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) |
4640 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) |
4903 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) |
4641 | #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) |
4904 | #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) |
4642 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
4905 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
4643 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
4906 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
4644 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 |
4907 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 |
4645 | #define GEN6_RP_CUR_UP_EI 0xA050 |
4908 | #define GEN6_RP_CUR_UP_EI 0xA050 |
4646 | #define GEN6_CURICONT_MASK 0xffffff |
4909 | #define GEN6_CURICONT_MASK 0xffffff |
Line 4681... | Line 4944... | ||
4681 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
4944 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
4682 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
4945 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
4683 | GEN6_PM_RP_DOWN_TIMEOUT) |
4946 | GEN6_PM_RP_DOWN_TIMEOUT) |
Line 4684... | Line 4947... | ||
4684 | 4947 | ||
- | 4948 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
|
- | 4949 | #define VLV_COUNTER_CONTROL 0x138104 |
|
- | 4950 | #define VLV_COUNT_RANGE_HIGH (1<<15) |
|
- | 4951 | #define VLV_MEDIA_RC6_COUNT_EN (1<<1) |
|
4685 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
4952 | #define VLV_RENDER_RC6_COUNT_EN (1<<0) |
4686 | #define GEN6_GT_GFX_RC6 0x138108 |
4953 | #define GEN6_GT_GFX_RC6 0x138108 |
4687 | #define GEN6_GT_GFX_RC6p 0x13810C |
4954 | #define GEN6_GT_GFX_RC6p 0x13810C |
Line 4688... | Line 4955... | ||
4688 | #define GEN6_GT_GFX_RC6pp 0x138110 |
4955 | #define GEN6_GT_GFX_RC6pp 0x138110 |
Line 4692... | Line 4959... | ||
4692 | #define GEN6_READ_OC_PARAMS 0xc |
4959 | #define GEN6_READ_OC_PARAMS 0xc |
4693 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
4960 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
4694 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
4961 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
4695 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
4962 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
4696 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
4963 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
- | 4964 | #define GEN6_PCODE_READ_D_COMP 0x10 |
|
- | 4965 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
|
4697 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
4966 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
4698 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
4967 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
- | 4968 | #define DISPLAY_IPS_CONTROL 0x19 |
|
4699 | #define GEN6_PCODE_DATA 0x138128 |
4969 | #define GEN6_PCODE_DATA 0x138128 |
4700 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
4970 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
4701 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
4971 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
Line 4702... | Line 4972... | ||
4702 | 4972 | ||
Line 4711... | Line 4981... | ||
4711 | #define GEN7_MISCCPCTL (0x9424) |
4981 | #define GEN7_MISCCPCTL (0x9424) |
4712 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
4982 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
Line 4713... | Line 4983... | ||
4713 | 4983 | ||
4714 | /* IVYBRIDGE DPF */ |
4984 | /* IVYBRIDGE DPF */ |
- | 4985 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ |
|
4715 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ |
4986 | #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ |
4716 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
4987 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
4717 | #define GEN7_PARITY_ERROR_VALID (1<<13) |
4988 | #define GEN7_PARITY_ERROR_VALID (1<<13) |
4718 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) |
4989 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) |
4719 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) |
4990 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) |
Line 4724... | Line 4995... | ||
4724 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
4995 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
4725 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
4996 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
4726 | #define GEN7_L3CDERRST1_ENABLE (1<<7) |
4997 | #define GEN7_L3CDERRST1_ENABLE (1<<7) |
Line 4727... | Line 4998... | ||
4727 | 4998 | ||
- | 4999 | #define GEN7_L3LOG_BASE 0xB070 |
|
4728 | #define GEN7_L3LOG_BASE 0xB070 |
5000 | #define HSW_L3LOG_BASE_SLICE1 0xB270 |
Line 4729... | Line 5001... | ||
4729 | #define GEN7_L3LOG_SIZE 0x80 |
5001 | #define GEN7_L3LOG_SIZE 0x80 |
4730 | 5002 | ||
4731 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
5003 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
- | 5004 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
|
4732 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
5005 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) |
Line 4733... | Line 5006... | ||
4733 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) |
5006 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
4734 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
5007 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
4735 | 5008 | ||
Line 4736... | Line 5009... | ||
4736 | #define GEN7_ROW_CHICKEN2 0xe4f4 |
5009 | #define GEN7_ROW_CHICKEN2 0xe4f4 |
4737 | #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 |
5010 | #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 |
Line -... | Line 5011... | ||
- | 5011 | #define DOP_CLOCK_GATING_DISABLE (1<<0) |
|
- | 5012 | ||
- | 5013 | #define HSW_ROW_CHICKEN3 0xe49c |
|
- | 5014 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
|
4738 | #define DOP_CLOCK_GATING_DISABLE (1<<0) |
5015 | |
4739 | 5016 | #define HALF_SLICE_CHICKEN3 0xe184 |
|
4740 | #define HSW_ROW_CHICKEN3 0xe49c |
5017 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
4741 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
5018 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
Line 4779... | Line 5056... | ||
4779 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
5056 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
4780 | CPT_AUD_CNTL_ST_A, \ |
5057 | CPT_AUD_CNTL_ST_A, \ |
4781 | CPT_AUD_CNTL_ST_B) |
5058 | CPT_AUD_CNTL_ST_B) |
4782 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
5059 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
Line -... | Line 5060... | ||
- | 5060 | ||
- | 5061 | #define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
|
- | 5062 | #define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) |
|
- | 5063 | #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
|
- | 5064 | VLV_HDMIW_HDMIEDID_A, \ |
|
- | 5065 | VLV_HDMIW_HDMIEDID_B) |
|
- | 5066 | #define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
|
- | 5067 | #define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) |
|
- | 5068 | #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
|
- | 5069 | VLV_AUD_CNTL_ST_A, \ |
|
- | 5070 | VLV_AUD_CNTL_ST_B) |
|
- | 5071 | #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) |
|
4783 | 5072 | ||
4784 | /* These are the 4 32-bit write offset registers for each stream |
5073 | /* These are the 4 32-bit write offset registers for each stream |
4785 | * output buffer. It determines the offset from the |
5074 | * output buffer. It determines the offset from the |
4786 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
5075 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
4787 | */ |
5076 | */ |
Line 4795... | Line 5084... | ||
4795 | #define CPT_AUD_CONFIG_A 0xe5000 |
5084 | #define CPT_AUD_CONFIG_A 0xe5000 |
4796 | #define CPT_AUD_CONFIG_B 0xe5100 |
5085 | #define CPT_AUD_CONFIG_B 0xe5100 |
4797 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ |
5086 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ |
4798 | CPT_AUD_CONFIG_A, \ |
5087 | CPT_AUD_CONFIG_A, \ |
4799 | CPT_AUD_CONFIG_B) |
5088 | CPT_AUD_CONFIG_B) |
- | 5089 | #define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
|
- | 5090 | #define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) |
|
- | 5091 | #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ |
|
- | 5092 | VLV_AUD_CONFIG_A, \ |
|
- | 5093 | VLV_AUD_CONFIG_B) |
|
- | 5094 | ||
4800 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
5095 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
4801 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
5096 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
4802 | #define AUD_CONFIG_UPPER_N_SHIFT 20 |
5097 | #define AUD_CONFIG_UPPER_N_SHIFT 20 |
4803 | #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) |
5098 | #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) |
4804 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
5099 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
4805 | #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) |
5100 | #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) |
4806 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
5101 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
4807 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) |
5102 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) |
- | 5103 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) |
|
- | 5104 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) |
|
- | 5105 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) |
|
- | 5106 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) |
|
- | 5107 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) |
|
- | 5108 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) |
|
- | 5109 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) |
|
- | 5110 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) |
|
- | 5111 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) |
|
- | 5112 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) |
|
4808 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
5113 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
Line 4809... | Line 5114... | ||
4809 | 5114 | ||
4810 | /* HSW Audio */ |
5115 | /* HSW Audio */ |
4811 | #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ |
5116 | #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ |
Line 4927... | Line 5232... | ||
4927 | /* DDI Buffer Control */ |
5232 | /* DDI Buffer Control */ |
4928 | #define DDI_BUF_CTL_A 0x64000 |
5233 | #define DDI_BUF_CTL_A 0x64000 |
4929 | #define DDI_BUF_CTL_B 0x64100 |
5234 | #define DDI_BUF_CTL_B 0x64100 |
4930 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
5235 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
4931 | #define DDI_BUF_CTL_ENABLE (1<<31) |
5236 | #define DDI_BUF_CTL_ENABLE (1<<31) |
- | 5237 | /* Haswell */ |
|
4932 | #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
5238 | #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
4933 | #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
5239 | #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
4934 | #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
5240 | #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
4935 | #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
5241 | #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
4936 | #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
5242 | #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
4937 | #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
5243 | #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
4938 | #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
5244 | #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
4939 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
5245 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
4940 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
5246 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
- | 5247 | /* Broadwell */ |
|
- | 5248 | #define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */ |
|
- | 5249 | #define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */ |
|
- | 5250 | #define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */ |
|
- | 5251 | #define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */ |
|
- | 5252 | #define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */ |
|
- | 5253 | #define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */ |
|
- | 5254 | #define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */ |
|
- | 5255 | #define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */ |
|
- | 5256 | #define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */ |
|
4941 | #define DDI_BUF_EMP_MASK (0xf<<24) |
5257 | #define DDI_BUF_EMP_MASK (0xf<<24) |
4942 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
5258 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
4943 | #define DDI_BUF_IS_IDLE (1<<7) |
5259 | #define DDI_BUF_IS_IDLE (1<<7) |
4944 | #define DDI_A_4_LANES (1<<4) |
5260 | #define DDI_A_4_LANES (1<<4) |
4945 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
5261 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
Line 5045... | Line 5361... | ||
5045 | #define LCPLL_CTL 0x130040 |
5361 | #define LCPLL_CTL 0x130040 |
5046 | #define LCPLL_PLL_DISABLE (1<<31) |
5362 | #define LCPLL_PLL_DISABLE (1<<31) |
5047 | #define LCPLL_PLL_LOCK (1<<30) |
5363 | #define LCPLL_PLL_LOCK (1<<30) |
5048 | #define LCPLL_CLK_FREQ_MASK (3<<26) |
5364 | #define LCPLL_CLK_FREQ_MASK (3<<26) |
5049 | #define LCPLL_CLK_FREQ_450 (0<<26) |
5365 | #define LCPLL_CLK_FREQ_450 (0<<26) |
- | 5366 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) |
|
- | 5367 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) |
|
- | 5368 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) |
|
5050 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
5369 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
5051 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
5370 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
5052 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
5371 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
5053 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
5372 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
5054 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
5373 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
Line 5126... | Line 5445... | ||
5126 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) |
5445 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) |
5127 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) |
5446 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) |
5128 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) |
5447 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) |
5129 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) |
5448 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) |
Line -... | Line 5449... | ||
- | 5449 | ||
- | 5450 | /* VLV MIPI registers */ |
|
- | 5451 | ||
- | 5452 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
|
- | 5453 | #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
|
- | 5454 | #define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL) |
|
- | 5455 | #define DPI_ENABLE (1 << 31) /* A + B */ |
|
- | 5456 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
|
- | 5457 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) |
|
- | 5458 | #define DUAL_LINK_MODE_MASK (1 << 26) |
|
- | 5459 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) |
|
- | 5460 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) |
|
- | 5461 | #define DITHERING_ENABLE (1 << 25) /* A + B */ |
|
- | 5462 | #define FLOPPED_HSTX (1 << 23) |
|
- | 5463 | #define DE_INVERT (1 << 19) /* XXX */ |
|
- | 5464 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 |
|
- | 5465 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) |
|
- | 5466 | #define AFE_LATCHOUT (1 << 17) |
|
- | 5467 | #define LP_OUTPUT_HOLD (1 << 16) |
|
- | 5468 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
|
- | 5469 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) |
|
- | 5470 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 |
|
- | 5471 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) |
|
- | 5472 | #define CSB_SHIFT 9 |
|
- | 5473 | #define CSB_MASK (3 << 9) |
|
- | 5474 | #define CSB_20MHZ (0 << 9) |
|
- | 5475 | #define CSB_10MHZ (1 << 9) |
|
- | 5476 | #define CSB_40MHZ (2 << 9) |
|
- | 5477 | #define BANDGAP_MASK (1 << 8) |
|
- | 5478 | #define BANDGAP_PNW_CIRCUIT (0 << 8) |
|
- | 5479 | #define BANDGAP_LNC_CIRCUIT (1 << 8) |
|
- | 5480 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
|
- | 5481 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) |
|
- | 5482 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ |
|
- | 5483 | #define TEARING_EFFECT_SHIFT 2 /* A + B */ |
|
- | 5484 | #define TEARING_EFFECT_MASK (3 << 2) |
|
- | 5485 | #define TEARING_EFFECT_OFF (0 << 2) |
|
- | 5486 | #define TEARING_EFFECT_DSI (1 << 2) |
|
- | 5487 | #define TEARING_EFFECT_GPIO (2 << 2) |
|
- | 5488 | #define LANE_CONFIGURATION_SHIFT 0 |
|
- | 5489 | #define LANE_CONFIGURATION_MASK (3 << 0) |
|
- | 5490 | #define LANE_CONFIGURATION_4LANE (0 << 0) |
|
- | 5491 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) |
|
- | 5492 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) |
|
- | 5493 | ||
- | 5494 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) |
|
- | 5495 | #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
|
- | 5496 | #define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) |
|
- | 5497 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
|
- | 5498 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) |
|
- | 5499 | ||
- | 5500 | /* XXX: all bits reserved */ |
|
- | 5501 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
|
- | 5502 | ||
- | 5503 | /* MIPI DSI Controller and D-PHY registers */ |
|
- | 5504 | ||
- | 5505 | #define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000) |
|
- | 5506 | #define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800) |
|
- | 5507 | #define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY) |
|
- | 5508 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
|
- | 5509 | #define ULPS_STATE_MASK (3 << 1) |
|
- | 5510 | #define ULPS_STATE_ENTER (2 << 1) |
|
- | 5511 | #define ULPS_STATE_EXIT (1 << 1) |
|
- | 5512 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) |
|
- | 5513 | #define DEVICE_READY (1 << 0) |
|
- | 5514 | ||
- | 5515 | #define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004) |
|
- | 5516 | #define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804) |
|
- | 5517 | #define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT) |
|
- | 5518 | #define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008) |
|
- | 5519 | #define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808) |
|
- | 5520 | #define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN) |
|
- | 5521 | #define TEARING_EFFECT (1 << 31) |
|
- | 5522 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) |
|
- | 5523 | #define GEN_READ_DATA_AVAIL (1 << 29) |
|
- | 5524 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) |
|
- | 5525 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) |
|
- | 5526 | #define RX_PROT_VIOLATION (1 << 26) |
|
- | 5527 | #define RX_INVALID_TX_LENGTH (1 << 25) |
|
- | 5528 | #define ACK_WITH_NO_ERROR (1 << 24) |
|
- | 5529 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) |
|
- | 5530 | #define LP_RX_TIMEOUT (1 << 22) |
|
- | 5531 | #define HS_TX_TIMEOUT (1 << 21) |
|
- | 5532 | #define DPI_FIFO_UNDERRUN (1 << 20) |
|
- | 5533 | #define LOW_CONTENTION (1 << 19) |
|
- | 5534 | #define HIGH_CONTENTION (1 << 18) |
|
- | 5535 | #define TXDSI_VC_ID_INVALID (1 << 17) |
|
- | 5536 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) |
|
- | 5537 | #define TXCHECKSUM_ERROR (1 << 15) |
|
- | 5538 | #define TXECC_MULTIBIT_ERROR (1 << 14) |
|
- | 5539 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) |
|
- | 5540 | #define TXFALSE_CONTROL_ERROR (1 << 12) |
|
- | 5541 | #define RXDSI_VC_ID_INVALID (1 << 11) |
|
- | 5542 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) |
|
- | 5543 | #define RXCHECKSUM_ERROR (1 << 9) |
|
- | 5544 | #define RXECC_MULTIBIT_ERROR (1 << 8) |
|
- | 5545 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) |
|
- | 5546 | #define RXFALSE_CONTROL_ERROR (1 << 6) |
|
- | 5547 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) |
|
- | 5548 | #define RX_LP_TX_SYNC_ERROR (1 << 4) |
|
- | 5549 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) |
|
- | 5550 | #define RXEOT_SYNC_ERROR (1 << 2) |
|
- | 5551 | #define RXSOT_SYNC_ERROR (1 << 1) |
|
- | 5552 | #define RXSOT_ERROR (1 << 0) |
|
- | 5553 | ||
- | 5554 | #define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c) |
|
- | 5555 | #define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c) |
|
- | 5556 | #define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG) |
|
- | 5557 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
|
- | 5558 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) |
|
- | 5559 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) |
|
- | 5560 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) |
|
- | 5561 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) |
|
- | 5562 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) |
|
- | 5563 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) |
|
- | 5564 | #define VID_MODE_FORMAT_MASK (0xf << 7) |
|
- | 5565 | #define VID_MODE_NOT_SUPPORTED (0 << 7) |
|
- | 5566 | #define VID_MODE_FORMAT_RGB565 (1 << 7) |
|
- | 5567 | #define VID_MODE_FORMAT_RGB666 (2 << 7) |
|
- | 5568 | #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) |
|
- | 5569 | #define VID_MODE_FORMAT_RGB888 (4 << 7) |
|
- | 5570 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 |
|
- | 5571 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) |
|
- | 5572 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 |
|
- | 5573 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) |
|
- | 5574 | #define DATA_LANES_PRG_REG_SHIFT 0 |
|
- | 5575 | #define DATA_LANES_PRG_REG_MASK (7 << 0) |
|
- | 5576 | ||
- | 5577 | #define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010) |
|
- | 5578 | #define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810) |
|
- | 5579 | #define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT) |
|
- | 5580 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
|
- | 5581 | ||
- | 5582 | #define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014) |
|
- | 5583 | #define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814) |
|
- | 5584 | #define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT) |
|
- | 5585 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
|
- | 5586 | ||
- | 5587 | #define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018) |
|
- | 5588 | #define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818) |
|
- | 5589 | #define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) |
|
- | 5590 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
|
- | 5591 | ||
- | 5592 | #define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c) |
|
- | 5593 | #define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c) |
|
- | 5594 | #define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) |
|
- | 5595 | #define DEVICE_RESET_TIMER_MASK 0xffff |
|
- | 5596 | ||
- | 5597 | #define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020) |
|
- | 5598 | #define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820) |
|
- | 5599 | #define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION) |
|
- | 5600 | #define VERTICAL_ADDRESS_SHIFT 16 |
|
- | 5601 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) |
|
- | 5602 | #define HORIZONTAL_ADDRESS_SHIFT 0 |
|
- | 5603 | #define HORIZONTAL_ADDRESS_MASK 0xffff |
|
- | 5604 | ||
- | 5605 | #define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024) |
|
- | 5606 | #define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824) |
|
- | 5607 | #define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) |
|
- | 5608 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
|
- | 5609 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) |
|
- | 5610 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) |
|
- | 5611 | ||
- | 5612 | /* regs below are bits 15:0 */ |
|
- | 5613 | #define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028) |
|
- | 5614 | #define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828) |
|
- | 5615 | #define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) |
|
- | 5616 | ||
- | 5617 | #define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c) |
|
- | 5618 | #define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c) |
|
- | 5619 | #define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT) |
|
- | 5620 | ||
- | 5621 | #define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030) |
|
- | 5622 | #define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830) |
|
- | 5623 | #define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT) |
|
- | 5624 | ||
- | 5625 | #define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034) |
|
- | 5626 | #define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834) |
|
- | 5627 | #define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) |
|
- | 5628 | ||
- | 5629 | #define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038) |
|
- | 5630 | #define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838) |
|
- | 5631 | #define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) |
|
- | 5632 | ||
- | 5633 | #define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c) |
|
- | 5634 | #define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c) |
|
- | 5635 | #define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT) |
|
- | 5636 | ||
- | 5637 | #define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040) |
|
- | 5638 | #define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840) |
|
- | 5639 | #define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT) |
|
- | 5640 | ||
- | 5641 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044) |
|
- | 5642 | #define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844) |
|
- | 5643 | #define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) |
|
- | 5644 | /* regs above are bits 15:0 */ |
|
- | 5645 | ||
- | 5646 | #define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048) |
|
- | 5647 | #define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848) |
|
- | 5648 | #define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL) |
|
- | 5649 | #define DPI_LP_MODE (1 << 6) |
|
- | 5650 | #define BACKLIGHT_OFF (1 << 5) |
|
- | 5651 | #define BACKLIGHT_ON (1 << 4) |
|
- | 5652 | #define COLOR_MODE_OFF (1 << 3) |
|
- | 5653 | #define COLOR_MODE_ON (1 << 2) |
|
- | 5654 | #define TURN_ON (1 << 1) |
|
- | 5655 | #define SHUTDOWN (1 << 0) |
|
- | 5656 | ||
- | 5657 | #define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c) |
|
- | 5658 | #define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c) |
|
- | 5659 | #define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA) |
|
- | 5660 | #define COMMAND_BYTE_SHIFT 0 |
|
- | 5661 | #define COMMAND_BYTE_MASK (0x3f << 0) |
|
- | 5662 | ||
- | 5663 | #define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050) |
|
- | 5664 | #define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850) |
|
- | 5665 | #define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT) |
|
- | 5666 | #define MASTER_INIT_TIMER_SHIFT 0 |
|
- | 5667 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) |
|
- | 5668 | ||
- | 5669 | #define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054) |
|
- | 5670 | #define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854) |
|
- | 5671 | #define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) |
|
- | 5672 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
|
- | 5673 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) |
|
- | 5674 | ||
- | 5675 | #define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058) |
|
- | 5676 | #define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858) |
|
- | 5677 | #define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) |
|
- | 5678 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
|
- | 5679 | #define DISABLE_VIDEO_BTA (1 << 3) |
|
- | 5680 | #define IP_TG_CONFIG (1 << 2) |
|
- | 5681 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) |
|
- | 5682 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) |
|
- | 5683 | #define VIDEO_MODE_BURST (3 << 0) |
|
- | 5684 | ||
- | 5685 | #define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c) |
|
- | 5686 | #define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c) |
|
- | 5687 | #define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE) |
|
- | 5688 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
|
- | 5689 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) |
|
- | 5690 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) |
|
- | 5691 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) |
|
- | 5692 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) |
|
- | 5693 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) |
|
- | 5694 | #define CLOCKSTOP (1 << 1) |
|
- | 5695 | #define EOT_DISABLE (1 << 0) |
|
- | 5696 | ||
- | 5697 | #define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060) |
|
- | 5698 | #define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860) |
|
- | 5699 | #define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK) |
|
- | 5700 | #define LP_BYTECLK_SHIFT 0 |
|
- | 5701 | #define LP_BYTECLK_MASK (0xffff << 0) |
|
- | 5702 | ||
- | 5703 | /* bits 31:0 */ |
|
- | 5704 | #define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064) |
|
- | 5705 | #define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864) |
|
- | 5706 | #define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA) |
|
- | 5707 | ||
- | 5708 | /* bits 31:0 */ |
|
- | 5709 | #define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068) |
|
- | 5710 | #define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868) |
|
- | 5711 | #define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA) |
|
- | 5712 | ||
- | 5713 | #define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c) |
|
- | 5714 | #define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c) |
|
- | 5715 | #define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL) |
|
- | 5716 | #define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070) |
|
- | 5717 | #define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870) |
|
- | 5718 | #define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL) |
|
- | 5719 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 |
|
- | 5720 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) |
|
- | 5721 | #define SHORT_PACKET_PARAM_SHIFT 8 |
|
- | 5722 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) |
|
- | 5723 | #define VIRTUAL_CHANNEL_SHIFT 6 |
|
- | 5724 | #define VIRTUAL_CHANNEL_MASK (3 << 6) |
|
- | 5725 | #define DATA_TYPE_SHIFT 0 |
|
- | 5726 | #define DATA_TYPE_MASK (3f << 0) |
|
- | 5727 | /* data type values, see include/video/mipi_display.h */ |
|
- | 5728 | ||
- | 5729 | #define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074) |
|
- | 5730 | #define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874) |
|
- | 5731 | #define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT) |
|
- | 5732 | #define DPI_FIFO_EMPTY (1 << 28) |
|
- | 5733 | #define DBI_FIFO_EMPTY (1 << 27) |
|
- | 5734 | #define LP_CTRL_FIFO_EMPTY (1 << 26) |
|
- | 5735 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) |
|
- | 5736 | #define LP_CTRL_FIFO_FULL (1 << 24) |
|
- | 5737 | #define HS_CTRL_FIFO_EMPTY (1 << 18) |
|
- | 5738 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) |
|
- | 5739 | #define HS_CTRL_FIFO_FULL (1 << 16) |
|
- | 5740 | #define LP_DATA_FIFO_EMPTY (1 << 10) |
|
- | 5741 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) |
|
- | 5742 | #define LP_DATA_FIFO_FULL (1 << 8) |
|
- | 5743 | #define HS_DATA_FIFO_EMPTY (1 << 2) |
|
- | 5744 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) |
|
- | 5745 | #define HS_DATA_FIFO_FULL (1 << 0) |
|
- | 5746 | ||
- | 5747 | #define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078) |
|
- | 5748 | #define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878) |
|
- | 5749 | #define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) |
|
- | 5750 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
|
- | 5751 | #define DBI_LP_MODE (1 << 0) |
|
- | 5752 | #define DBI_HS_MODE (0 << 0) |
|
- | 5753 | ||
- | 5754 | #define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080) |
|
- | 5755 | #define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880) |
|
- | 5756 | #define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM) |
|
- | 5757 | #define EXIT_ZERO_COUNT_SHIFT 24 |
|
- | 5758 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) |
|
- | 5759 | #define TRAIL_COUNT_SHIFT 16 |
|
- | 5760 | #define TRAIL_COUNT_MASK (0x1f << 16) |
|
- | 5761 | #define CLK_ZERO_COUNT_SHIFT 8 |
|
- | 5762 | #define CLK_ZERO_COUNT_MASK (0xff << 8) |
|
- | 5763 | #define PREPARE_COUNT_SHIFT 0 |
|
- | 5764 | #define PREPARE_COUNT_MASK (0x3f << 0) |
|
- | 5765 | ||
- | 5766 | /* bits 31:0 */ |
|
- | 5767 | #define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084) |
|
- | 5768 | #define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884) |
|
- | 5769 | #define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL) |
|
- | 5770 | ||
- | 5771 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088) |
|
- | 5772 | #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888) |
|
- | 5773 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) |
|
- | 5774 | #define LP_HS_SSW_CNT_SHIFT 16 |
|
- | 5775 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) |
|
- | 5776 | #define HS_LP_PWR_SW_CNT_SHIFT 0 |
|
- | 5777 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) |
|
- | 5778 | ||
- | 5779 | #define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c) |
|
- | 5780 | #define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c) |
|
- | 5781 | #define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) |
|
- | 5782 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
|
- | 5783 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) |
|
- | 5784 | ||
- | 5785 | #define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090) |
|
- | 5786 | #define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890) |
|
- | 5787 | #define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) |
|
- | 5788 | #define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094) |
|
- | 5789 | #define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894) |
|
- | 5790 | #define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1) |
|
- | 5791 | #define RX_CONTENTION_DETECTED (1 << 0) |
|
- | 5792 | ||
- | 5793 | /* XXX: only pipe A ?!? */ |
|
- | 5794 | #define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100) |
|
- | 5795 | #define DBI_TYPEC_ENABLE (1 << 31) |
|
- | 5796 | #define DBI_TYPEC_WIP (1 << 30) |
|
- | 5797 | #define DBI_TYPEC_OPTION_SHIFT 28 |
|
- | 5798 | #define DBI_TYPEC_OPTION_MASK (3 << 28) |
|
- | 5799 | #define DBI_TYPEC_FREQ_SHIFT 24 |
|
- | 5800 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) |
|
- | 5801 | #define DBI_TYPEC_OVERRIDE (1 << 8) |
|
- | 5802 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 |
|
- | 5803 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) |
|
- | 5804 | ||
- | 5805 | ||
- | 5806 | /* MIPI adapter registers */ |
|
- | 5807 | ||
- | 5808 | #define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104) |
|
- | 5809 | #define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904) |
|
- | 5810 | #define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL) |
|
- | 5811 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
|
- | 5812 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) |
|
- | 5813 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) |
|
- | 5814 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) |
|
- | 5815 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) |
|
- | 5816 | #define READ_REQUEST_PRIORITY_SHIFT 3 |
|
- | 5817 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) |
|
- | 5818 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) |
|
- | 5819 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) |
|
- | 5820 | #define RGB_FLIP_TO_BGR (1 << 2) |
|
- | 5821 | ||
- | 5822 | #define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108) |
|
- | 5823 | #define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908) |
|
- | 5824 | #define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS) |
|
- | 5825 | #define DATA_MEM_ADDRESS_SHIFT 5 |
|
- | 5826 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) |
|
- | 5827 | #define DATA_VALID (1 << 0) |
|
- | 5828 | ||
- | 5829 | #define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c) |
|
- | 5830 | #define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c) |
|
- | 5831 | #define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH) |
|
- | 5832 | #define DATA_LENGTH_SHIFT 0 |
|
- | 5833 | #define DATA_LENGTH_MASK (0xfffff << 0) |
|
- | 5834 | ||
- | 5835 | #define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110) |
|
- | 5836 | #define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910) |
|
- | 5837 | #define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) |
|
- | 5838 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
|
- | 5839 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) |
|
- | 5840 | #define AUTO_PWG_ENABLE (1 << 2) |
|
- | 5841 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) |
|
- | 5842 | #define COMMAND_VALID (1 << 0) |
|
- | 5843 | ||
- | 5844 | #define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114) |
|
- | 5845 | #define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914) |
|
- | 5846 | #define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH) |
|
- | 5847 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
|
- | 5848 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) |
|
- | 5849 | ||
- | 5850 | #define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118) |
|
- | 5851 | #define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918) |
|
- | 5852 | #define MIPI_READ_DATA_RETURN(pipe, n) \ |
|
- | 5853 | (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ |
|
- | 5854 | ||
- | 5855 | #define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138) |
|
- | 5856 | #define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938) |
|
- | 5857 | #define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) |
|
- | 5858 | #define READ_DATA_VALID(n) (1 << (n)) |
|
5130 | 5859 |