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| Rev 4104 | Rev 4280 | ||
|---|---|---|---|
| Line 602... | Line 602... | ||
| 602 | #define ARB_MODE 0x04030 |
602 | #define ARB_MODE 0x04030 |
| 603 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
603 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
| 604 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
604 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
| 605 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
605 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
| 606 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
606 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
| - | 607 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
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| - | 608 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) |
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| - | 609 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) |
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| - | 610 | #define RING_FAULT_VALID (1<<0) |
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| 607 | #define DONE_REG 0x40b0 |
611 | #define DONE_REG 0x40b0 |
| 608 | #define BSD_HWS_PGA_GEN7 (0x04180) |
612 | #define BSD_HWS_PGA_GEN7 (0x04180) |
| 609 | #define BLT_HWS_PGA_GEN7 (0x04280) |
613 | #define BLT_HWS_PGA_GEN7 (0x04280) |
| 610 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
614 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
| 611 | #define RING_ACTHD(base) ((base)+0x74) |
615 | #define RING_ACTHD(base) ((base)+0x74) |
| Line 4277... | Line 4281... | ||
| 4277 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
4281 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
| 4278 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) |
4282 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) |
| 4279 | #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
4283 | #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
| Line 4280... | Line 4284... | ||
| 4280 | 4284 | ||
| - | 4285 | #define SOUTH_DSPCLK_GATE_D 0xc2020 |
|
| 4281 | #define SOUTH_DSPCLK_GATE_D 0xc2020 |
4286 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) |
| - | 4287 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
|
| 4282 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
4288 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) |
| Line 4283... | Line 4289... | ||
| 4283 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
4289 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
| 4284 | 4290 | ||
| 4285 | /* CPU: FDI_TX */ |
4291 | /* CPU: FDI_TX */ |