WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_irq.c

 	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 				~dev_priv->pm_rps_events);
+	spin_unlock_irq(&dev_priv->irq_lock);
 	spin_unlock_irq(&dev_priv->irq_lock);
 	synchronize_irq(dev->irq);
+}
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pipe_stats[I915_MAX_PIPES] = { };
 	int pipe;
+	spin_lock(&dev_priv->irq_lock);
+	if (!dev_priv->display_irqs_enabled) {
+		spin_unlock(&dev_priv->irq_lock);
+		return;
+	}
 	spin_lock(&dev_priv->irq_lock);
 	for_each_pipe(dev_priv, pipe) {
 		i915_reg_t reg;
 		u32 mask, iir_bit = 0;
 		return IRQ_NONE;
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-	disable_rpm_wakeref_asserts(dev_priv);
-	/* We get interrupts on unclaimed registers, so check for this before we
-	 * do any I915_{READ,WRITE}. */
-	intel_uncore_check_errors(dev);
+	disable_rpm_wakeref_asserts(dev_priv);
 	/* disable master interrupt before clearing iir  */
 	de_ier = I915_READ(DEIER);
 			   bxt_port_hotplug_long_detect);
 	intel_hpd_irq_handler(dev, pin_mask, long_mask);
+}
-}
 static irqreturn_t
-static irqreturn_t gen8_irq_handler(int irq, void *arg)
+gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
-{
-	struct drm_device *dev = arg;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 master_ctl;
+	struct drm_device *dev = dev_priv->dev;
 	irqreturn_t ret = IRQ_NONE;
-	uint32_t tmp = 0;
-	enum pipe pipe;
-	u32 aux_mask = GEN8_AUX_CHANNEL_A;
-	if (!intel_irqs_enabled(dev_priv))
-		return IRQ_NONE;
-	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-	disable_rpm_wakeref_asserts(dev_priv);
-	if (INTEL_INFO(dev_priv)->gen >= 9)
-		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
-			GEN9_AUX_CHANNEL_D;
-	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
-	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
-	if (!master_ctl)
-		goto out;
-	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
-	/* Find, clear, then process each source of interrupt */
 	u32 iir;
-	ret = gen8_gt_irq_handler(dev_priv, master_ctl);
+	enum pipe pipe;
 	if (master_ctl & GEN8_DE_MISC_IRQ) {
-		tmp = I915_READ(GEN8_DE_MISC_IIR);
+		iir = I915_READ(GEN8_DE_MISC_IIR);
-		if (tmp) {
+		if (iir) {
-			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
+			I915_WRITE(GEN8_DE_MISC_IIR, iir);
 			ret = IRQ_HANDLED;
-			if (tmp & GEN8_DE_MISC_GSE)
+			if (iir & GEN8_DE_MISC_GSE)
 				intel_opregion_asle_intr(dev);
 			else
 				DRM_ERROR("Unexpected DE Misc interrupt\n");
+		}
 		else
 			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
 	}
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
-	if (master_ctl & GEN8_DE_PORT_IRQ) {
-		tmp = I915_READ(GEN8_DE_PORT_IIR);
-		if (tmp) {
-			bool found = false;
-			u32 hotplug_trigger = 0;
-			if (IS_BROXTON(dev_priv))
+		iir = I915_READ(GEN8_DE_PORT_IIR);
-				hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
+		if (iir) {
+			u32 tmp_mask;
+			bool found = false;
+			I915_WRITE(GEN8_DE_PORT_IIR, iir);
+			ret = IRQ_HANDLED;
-			else if (IS_BROADWELL(dev_priv))
+			tmp_mask = GEN8_AUX_CHANNEL_A;
-				hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
+			if (INTEL_INFO(dev_priv)->gen >= 9)
 				tmp_mask |= GEN9_AUX_CHANNEL_B |
-			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
+					    GEN9_AUX_CHANNEL_C |
-			ret = IRQ_HANDLED;
+					    GEN9_AUX_CHANNEL_D;
+			if (iir & tmp_mask) {
-			if (tmp & aux_mask) {
+				dp_aux_irq_handler(dev);
+				found = true;
-				dp_aux_irq_handler(dev);
+			}
+			if (IS_BROXTON(dev_priv)) {
+				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
-				found = true;
+				if (tmp_mask) {
 					bxt_hpd_irq_handler(dev, tmp_mask, hpd_bxt);
 					found = true;
+				}
-			if (hotplug_trigger) {
+			} else if (IS_BROADWELL(dev_priv)) {
-				if (IS_BROXTON(dev))
+				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
-					bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
+				if (tmp_mask) {
-				else
+					ilk_hpd_irq_handler(dev, tmp_mask, hpd_bdw);
-					ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
+					found = true;
 		else
 			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
+	}
 	for_each_pipe(dev_priv, pipe) {
-		uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
+		u32 flip_done, fault_errors;
 		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
 			continue;
+		iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+		if (!iir) {
+			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
 			continue;
-		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+		}
-		if (pipe_iir) {
-			ret = IRQ_HANDLED;
+		ret = IRQ_HANDLED;
-			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
+		I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
 		if (iir & GEN8_PIPE_VBLANK &&
-			if (pipe_iir & GEN8_PIPE_VBLANK &&
+		    intel_pipe_handle_vblank(dev, pipe))
-			    intel_pipe_handle_vblank(dev, pipe))
+			intel_check_page_flip(dev, pipe);
-				intel_check_page_flip(dev, pipe);
 		flip_done = iir;
-			if (INTEL_INFO(dev_priv)->gen >= 9)
+		if (INTEL_INFO(dev_priv)->gen >= 9)
-				flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
+			flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
-			else
+		else
-				flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
+			flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
-			if (flip_done) {
+		if (flip_done) {
-				intel_prepare_page_flip(dev, pipe);
+			intel_prepare_page_flip(dev, pipe);
-				intel_finish_page_flip_plane(dev, pipe);
-			}
+			intel_finish_page_flip_plane(dev, pipe);
+		}
-			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
-				hsw_pipe_crc_irq_handler(dev, pipe);
+		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
+			hsw_pipe_crc_irq_handler(dev, pipe);
 			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
-				intel_cpu_fifo_underrun_irq_handler(dev_priv,
+		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
-								    pipe);
+			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
-			if (INTEL_INFO(dev_priv)->gen >= 9)
-				fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
+		fault_errors = iir;
-			else
+		if (INTEL_INFO(dev_priv)->gen >= 9)
-				fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
 		else
-			if (fault_errors)
+			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
 				DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
-					  pipe_name(pipe),
+		if (fault_errors)
-					  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
+			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
-		} else
+				  pipe_name(pipe),
-			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
+				  fault_errors);
 	}
 	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
 	    master_ctl & GEN8_DE_PCH_IRQ) {
 		/*
 		 * FIXME(BDW): Assume for now that the new interrupt handling
 		 * scheme also closed the SDE interrupt handling race we've seen
 		 * on older pch-split platforms. But this needs testing.
 		 */
-		u32 pch_iir = I915_READ(SDEIIR);
+		iir = I915_READ(SDEIIR);
-		if (pch_iir) {
+		if (iir) {
-			I915_WRITE(SDEIIR, pch_iir);
+			I915_WRITE(SDEIIR, iir);
 			ret = IRQ_HANDLED;
+			if (HAS_PCH_SPT(dev_priv))
+				spt_irq_handler(dev, iir);
+			else
+				cpt_irq_handler(dev, iir);
+		} else {
+			/*
+			 * Like on previous PCH there seems to be something
+			 * fishy going on with forwarding PCH interrupts.
+			 */
+			DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
+		}
+	}
+	return ret;
+}
+static irqreturn_t gen8_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = arg;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 master_ctl;
+	irqreturn_t ret;
+	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
-			if (HAS_PCH_SPT(dev_priv))
+	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
-				spt_irq_handler(dev, pch_iir);
+	if (!master_ctl)
-			else
-				cpt_irq_handler(dev, pch_iir);
+		return IRQ_NONE;
 		} else {
-			/*
+	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
 		 * isn't the case at least when we get here by doing a
 		 * simulated reset via debugs, so get an RPM reference.
 		 */
 		intel_runtime_pm_get(dev_priv);
+		intel_prepare_reset(dev);
 		/*
 		 * All state reset _must_ be completed before we update the
 		 * reset counter, for otherwise waiters might miss the reset
 		 * pending state and not properly drop locks, resulting in
 		 * deadlocks with the reset work.
 		 */
-//		ret = i915_reset(dev);
+		ret = i915_reset(dev);
-//		intel_finish_reset(dev);
+		intel_finish_reset(dev);
 	va_start(args, fmt);
 	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
 	va_end(args);
-//	i915_capture_error_state(dev);
+	i915_capture_error_state(dev, wedged, error_msg);
 	i915_report_and_clear_eir(dev);
 	for_each_ring(ring, dev_priv, i)
 		ring->hangcheck.deadlock = 0;
-}
+}
 static enum intel_ring_hangcheck_action
+static bool subunits_stuck(struct intel_engine_cs *ring)
+{
+	u32 instdone[I915_NUM_INSTDONE_REG];
+	bool stuck;
+	int i;
+	if (ring->id != RCS)
-ring_stuck(struct intel_engine_cs *ring, u64 acthd)
+		return true;
-{
+	i915_get_extra_instdone(ring->dev, instdone);
+	/* There might be unstable subunit states even when
+	 * actual head is not moving. Filter out the unstable ones by
+	 * accumulating the undone -> done transitions and only
-	struct drm_device *dev = ring->dev;
+	 * consider those as progress.
+	 */
+	stuck = true;
+	for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
+		const u32 tmp = instdone[i] | ring->hangcheck.instdone[i];
+		if (tmp != ring->hangcheck.instdone[i])
+			stuck = false;
+		ring->hangcheck.instdone[i] |= tmp;
+	}
+	return stuck;
+}
-	struct drm_i915_private *dev_priv = dev->dev_private;
+static enum intel_ring_hangcheck_action
+head_stuck(struct intel_engine_cs *ring, u64 acthd)
+{
+	if (acthd != ring->hangcheck.acthd) {
+		/* Clear subunit states on head movement */
-	u32 tmp;
+		memset(ring->hangcheck.instdone, 0,
 		       sizeof(ring->hangcheck.instdone));
 	if (acthd != ring->hangcheck.acthd) {
 		if (acthd > ring->hangcheck.max_acthd) {
 			ring->hangcheck.max_acthd = acthd;
 			return HANGCHECK_ACTIVE;
+		}
+		return HANGCHECK_ACTIVE_LOOP;
+	}
+	if (!subunits_stuck(ring))
+		return HANGCHECK_ACTIVE;
+	return HANGCHECK_HUNG;
+}
+static enum intel_ring_hangcheck_action
+ring_stuck(struct intel_engine_cs *ring, u64 acthd)
+{
+	struct drm_device *dev = ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum intel_ring_hangcheck_action ha;
+	u32 tmp;
 	ha = head_stuck(ring, acthd);
-		return HANGCHECK_ACTIVE_LOOP;
+	if (ha != HANGCHECK_HUNG)
 		return ha;
 	 * require a wakeref. TODO: instead of disabling the asserts make
 	 * sure that we hold a reference when this work is running.
 	 */
 	DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
+	/* As enabling the GPU requires fairly extensive mmio access,
+	 * periodically arm the mmio checker to see if we are triggering
+	 * any invalid access.
+	 */
+	intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
 	for_each_ring(ring, dev_priv, i) {
 		u64 acthd;
 		u32 seqno;
 			 * attempts across multiple batches.
 			 */
 			if (ring->hangcheck.score > 0)
 				ring->hangcheck.score--;
 			/* Clear head and subunit states on seqno movement */
+			ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
+			memset(ring->hangcheck.instdone, 0,
-			ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
+			       sizeof(ring->hangcheck.instdone));
+		}
 		ring->hangcheck.seqno = seqno;
 				 ring->name);
 			rings_hung++;
+		}
+	}
-//   if (rings_hung)
+	if (rings_hung) {
+		i915_handle_error(dev, true, "Ring hung");
+		goto out;
+	}
+	if (busy_count)
+		/* Reset timer case chip hangs without another request
+		 * being added */
+		i915_queue_hangcheck(dev);
+out:
+	ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
+}
+void i915_queue_hangcheck(struct drm_device *dev)
+{
+	struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
+	if (!i915.enable_hangcheck)
+		return;
+	/* Don't continually defer the hangcheck so that it is always run at
+	 * least once after work has been scheduled on any ring. Otherwise,
+	 * we will ignore a hung ring if a second ring is kept busy.
+	 */
-//       return i915_handle_error(dev, true);
+	queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
 			   round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
+}
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     unsigned int pipe_mask)
+{
+	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
+	enum pipe pipe;
+	spin_lock_irq(&dev_priv->irq_lock);
+	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
+		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
+				  dev_priv->de_irq_mask[pipe],
+				  ~dev_priv->de_irq_mask[pipe] | extra_ier);
+	spin_unlock_irq(&dev_priv->irq_lock);
+}
+void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
+				     unsigned int pipe_mask)
+{
-	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
+	enum pipe pipe;
-	spin_lock_irq(&dev_priv->irq_lock);
-	if (pipe_mask & 1 << PIPE_A)
-		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
-				  dev_priv->de_irq_mask[PIPE_A],
-				  ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
-	if (pipe_mask & 1 << PIPE_B)
-		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
-				  dev_priv->de_irq_mask[PIPE_B],
-				  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
+	spin_lock_irq(&dev_priv->irq_lock);
-	if (pipe_mask & 1 << PIPE_C)
-		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
-				  dev_priv->de_irq_mask[PIPE_C],
+	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
+		GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+	spin_unlock_irq(&dev_priv->irq_lock);
-				  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
+	/* make sure we're done processing display irqs */
-	spin_unlock_irq(&dev_priv->irq_lock);
+	synchronize_irq(dev_priv->dev->irq);
+}
  */
 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
+{
 	dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
 	dev_priv->pm.irqs_enabled = false;
+	synchronize_irq(dev_priv->dev->irq);
+}
 /**
  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_irq.c – Rev 6937 → 7144