WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_irq.c

 	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
 	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
 	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
 };
-static const u32 hpd_status_gen4[] = {
+static const u32 hpd_status_g4x[] = {
 	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
 	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
 	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 				      pipe_name(pipe));
+		}
+	}
+}
+static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
+						  enum pipe pipe, bool enable)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	assert_spin_locked(&dev_priv->irq_lock);
+	if (enable)
+		dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
+	else
+		dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
+	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+}
 /**
  * ibx_display_interrupt_update - update SDEIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
 	if (IS_GEN5(dev) || IS_GEN6(dev))
 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN7(dev))
+		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
+	else if (IS_GEN8(dev))
-		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
+		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 done:
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 	return ret;
+}
 void
-i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
+i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
+{
 		u32 reg = PIPESTAT(pipe);
 	I915_WRITE(reg, pipestat);
 		POSTING_READ(reg);
+}
 void
-i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
+i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
+{
 		u32 reg = PIPESTAT(pipe);
 	u32 pipestat = I915_READ(reg) & 0x7fff0000;
 	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 		return;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
+	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
+		if (INTEL_INFO(dev)->gen >= 4)
-		if (INTEL_INFO(dev)->gen >= 4)
+		i915_enable_pipestat(dev_priv, PIPE_A,
-		i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
+				     PIPE_LEGACY_BLC_EVENT_ENABLE);
 	} else {
 		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
+	}
+}
+static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
+{
+	/* Gen2 doesn't have a hardware frame counter */
+	return 0;
+}
 /* Called from drm generic code, passed a 'crtc', which
  * we use as a pipe index
  */
 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long high_frame;
 	unsigned long low_frame;
-	u32 high1, high2, low;
+	u32 high1, high2, low, pixel, vbl_start;
 	if (!i915_pipe_enabled(dev, pipe)) {
 		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 				"pipe %c\n", pipe_name(pipe));
+		return 0;
+	}
+	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+		struct intel_crtc *intel_crtc =
+			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+		const struct drm_display_mode *mode =
+			&intel_crtc->config.adjusted_mode;
+		vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
+	} else {
+		enum transcoder cpu_transcoder =
+			intel_pipe_to_cpu_transcoder(dev_priv, pipe);
+		u32 htotal;
+		htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
+		vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
-		return 0;
+		vbl_start *= htotal;
+	}
 	high_frame = PIPEFRAME(pipe);
 	low_frame = PIPEFRAMEPIXEL(pipe);
 	/*
 	 * High & low register fields aren't synchronized, so make sure
 	 * we get a low value that's stable across two reads of the high
 	 * register.
 	 */
 	do {
 		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
+		low   = I915_READ(low_frame);
-		low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
+		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
+	} while (high1 != high2);
+	high1 >>= PIPE_FRAME_HIGH_SHIFT;
+	pixel = low & PIPE_PIXEL_MASK;
+	low >>= PIPE_FRAME_LOW_SHIFT;
-		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
+	/*
-	} while (high1 != high2);
+	 * The frame counter increments at beginning of active.
 	 * Cook up a vblank counter by also checking the pixel
-	high1 >>= PIPE_FRAME_HIGH_SHIFT;
+	 * counter against vblank start.
-	low >>= PIPE_FRAME_LOW_SHIFT;
+	 */
+	}
 	return I915_READ(reg);
+}
+/* raw reads, only for fast reads of display block, no need for forcewake etc. */
+#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
+#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
+static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t status;
+	if (INTEL_INFO(dev)->gen < 7) {
+		status = pipe == PIPE_A ?
+			DE_PIPEA_VBLANK :
+			DE_PIPEB_VBLANK;
+	} else {
+		switch (pipe) {
+		default:
+		case PIPE_A:
+			status = DE_PIPEA_VBLANK_IVB;
+			break;
+		case PIPE_B:
+			status = DE_PIPEB_VBLANK_IVB;
+			break;
+		case PIPE_C:
+			status = DE_PIPEC_VBLANK_IVB;
+			break;
+		}
+	}
+	return __raw_i915_read32(dev_priv, DEISR) & status;
+}
+static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
-static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
+				    unsigned int flags, int *vpos, int *hpos,
-			     int *vpos, int *hpos)
+                    void *stime, void *etime)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
-{
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
-	u32 vbl = 0, position = 0;
+	int position;
 	int vbl_start, vbl_end, htotal, vtotal;
-	bool in_vbl = true;
-	int ret = 0;
+	bool in_vbl = true;
-	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+	int ret = 0;
-								      pipe);
+	unsigned long irqflags;
-	if (!i915_pipe_enabled(dev, pipe)) {
+	if (!intel_crtc->active) {
 		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
+				 "pipe %c\n", pipe_name(pipe));
-				 "pipe %c\n", pipe_name(pipe));
+		return 0;
+	}
+	htotal = mode->crtc_htotal;
+	vtotal = mode->crtc_vtotal;
-		return 0;
+	vbl_start = mode->crtc_vblank_start;
+	vbl_end = mode->crtc_vblank_end;
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+		vbl_start = DIV_ROUND_UP(vbl_start, 2);
+		vbl_end /= 2;
+		vtotal /= 2;
+	}
+	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
+	/*
+	 * Lock uncore.lock, as we will do multiple timing critical raw
+	 * register reads, potentially with preemption disabled, so the
+	 * following code must not block on uncore.lock.
+	 */
-	}
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-	/* Get vtotal. */
+	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 	vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
+	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
+		/* No obvious pixelcount register. Only query vertical
+		 * scanout position from Display scan line register.
+		 */
+		if (IS_GEN2(dev))
+			position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
+		else
+			position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+		if (HAS_PCH_SPLIT(dev)) {
+			/*
+			 * The scanline counter increments at the leading edge
+			 * of hsync, ie. it completely misses the active portion
+			 * of the line. Fix up the counter at both edges of vblank
+			 * to get a more accurate picture whether we're in vblank
+			 * or not.
+			 */
-	if (INTEL_INFO(dev)->gen >= 4) {
+			in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
-		/* No obvious pixelcount register. Only query vertical
+			if ((in_vbl && position == vbl_start - 1) ||
+			    (!in_vbl && position == vbl_end - 1))
+				position = (position + 1) % vtotal;
+		} else {
+			/*
+			 * ISR vblank status bits don't work the way we'd want
+			 * them to work on non-PCH platforms (for
+			 * ilk_pipe_in_vblank_locked()), and there doesn't
+			 * appear any other way to determine if we're currently
+			 * in vblank.
+			 *
+			 * Instead let's assume that we're already in vblank if
-		 * scanout position from Display scan line register.
+			 * we got called from the vblank interrupt and the
+			 * scanline counter value indicates that we're on the
+			 * line just prior to vblank start. This should result
-		 */
+			 * in the correct answer, unless the vblank interrupt
+			 * delivery really got delayed for almost exactly one
+			 * full frame/field.
-		position = I915_READ(PIPEDSL(pipe));
+			 */
+			if (flags & DRM_CALLED_FROM_VBLIRQ &&
+			    position == vbl_start - 1) {
 				position = (position + 1) % vtotal;
 		/* Decode into vertical scanout position. Don't have
-		 * horizontal scanout position.
+				/* Signal this correction as "applied". */
-		 */
+				ret |= 0x8;
 		*vpos = position & 0x1fff;
-		*hpos = 0;
+		}
 	} else {
 		/* Have access to pixelcount since start of frame.
+		 * We can split this into vertical and horizontal
-		 * We can split this into vertical and horizontal
+		 * scanout position.
-		 * scanout position.
+		 */
-		 */
-		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
-		htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
-		*vpos = position / htotal;
-		*hpos = position - (*vpos * htotal);
-	}
-	/* Query vblank area. */
-	vbl = I915_READ(VBLANK(cpu_transcoder));
+		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
-	/* Test position against vblank region. */
+		/* convert to pixel counts */
+		vbl_start *= htotal;
+		vbl_end *= htotal;
+		vtotal *= htotal;
+	}
-	vbl_start = vbl & 0x1fff;
+	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+	in_vbl = position >= vbl_start && position < vbl_end;
+	/*
+	 * While in vblank, position will be negative
+	 * counting up towards 0 at vbl_end. And outside
-	vbl_end = (vbl >> 16) & 0x1fff;
+	 * vblank, position will be positive counting
+	 * up since vbl_end.
+	 */
+	if (position >= vbl_start)
+		position -= vbl_end;
-	if ((*vpos < vbl_start) || (*vpos > vbl_end))
+	else
-		in_vbl = false;
+		position += vtotal - vbl_end;
+	}
 	/* Helper routine in DRM core does all the work: */
 	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 						     vblank_time, flags,
+						     crtc,
-						     crtc);
+						     &to_intel_crtc(crtc)->config.adjusted_mode);
 }
 static bool intel_hpd_irq_event(struct drm_device *dev,
-static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
+				struct drm_connector *connector)
+{
 	enum drm_connector_status old_status;
+	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
+	old_status = connector->status;
-	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
+	connector->status = connector->funcs->detect(connector, false);
-	old_status = connector->status;
+	if (old_status == connector->status)
 		return false;
-	connector->status = connector->funcs->detect(connector, false);
-	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
+	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
+		      connector->base.id,
+		      drm_get_connector_name(connector),
-		      connector->base.id,
+		      drm_get_connector_status_name(old_status),
-		      drm_get_connector_name(connector),
+		      drm_get_connector_status_name(connector->status));
 		      old_status, connector->status);
-	return (old_status != connector->status);
+	return true;
 			struct intel_ring_buffer *ring)
+{
 	if (ring->obj == NULL)
 		return;
-	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
+	trace_i915_gem_request_complete(ring);
 	wake_up_all(&ring->irq_queue);
+}
 static void gen6_pm_rps_work(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 						    rps.work);
 	u32 pm_iir;
-	u8 new_delay;
+	int new_delay, adj;
 	if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
 		return;
+	mutex_lock(&dev_priv->rps.hw_lock);
 	mutex_lock(&dev_priv->rps.hw_lock);
+	adj = dev_priv->rps.last_adj;
+	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
+		if (adj > 0)
+			adj *= 2;
+		else
-	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
+			adj = 1;
-		new_delay = dev_priv->rps.cur_delay + 1;
+		new_delay = dev_priv->rps.cur_delay + adj;
 		/*
-		 * For better performance, jump directly
-		 * to RPe if we're below it.
+		 * For better performance, jump directly
-		 */
+		 * to RPe if we're below it.
+		 */
+		if (new_delay < dev_priv->rps.rpe_delay)
+			new_delay = dev_priv->rps.rpe_delay;
-		if (IS_VALLEYVIEW(dev_priv->dev) &&
+	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
+		if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
+			new_delay = dev_priv->rps.rpe_delay;
+		else
+			new_delay = dev_priv->rps.min_delay;
+		adj = 0;
+	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
+		if (adj < 0)
-		    dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
+			adj *= 2;
+		else
+			adj = -1;
+		new_delay = dev_priv->rps.cur_delay + adj;
-			new_delay = dev_priv->rps.rpe_delay;
+	} else { /* unknown event */
-	} else
+		new_delay = dev_priv->rps.cur_delay;
 		new_delay = dev_priv->rps.cur_delay - 1;
 	/* sysfs frequency interfaces may have snuck in while servicing the
+	 * interrupt
+	 */
-	 * interrupt
+	new_delay = clamp_t(int, new_delay,
-	 */
+			    dev_priv->rps.min_delay, dev_priv->rps.max_delay);
-	if (new_delay >= dev_priv->rps.min_delay &&
+	dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
 	    new_delay <= dev_priv->rps.max_delay) {
-		if (IS_VALLEYVIEW(dev_priv->dev))
-			valleyview_set_rps(dev_priv->dev, new_delay);
-		else
-		gen6_set_rps(dev_priv->dev, new_delay);
-	}
-	if (IS_VALLEYVIEW(dev_priv->dev)) {
-		/*
-		 * On VLV, when we enter RC6 we may not be at the minimum
-		 * voltage level, so arm a timer to check.  It should only
-		 * fire when there's activity or once after we've entered
-		 * RC6, and then won't be re-armed until the next RPS interrupt.
-		 */
+		if (IS_VALLEYVIEW(dev_priv->dev))
-//		mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
+			valleyview_set_rps(dev_priv->dev, new_delay);
 static void ivybridge_parity_work(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 						    l3_parity.error_work);
 	u32 error_status, row, bank, subbank;
-	char *parity_event[5];
+	char *parity_event[6];
 	uint32_t misccpctl;
 	unsigned long flags;
+	uint8_t slice = 0;
 	/* We must turn off DOP level clock gating to access the L3 registers.
 	 * In order to prevent a get/put style interface, acquire struct mutex
 	 * any time we access those registers.
 	 */
+	mutex_lock(&dev_priv->dev->struct_mutex);
+	/* If we've screwed up tracking, just let the interrupt fire again */
+	if (WARN_ON(!dev_priv->l3_parity.which_slice))
-	mutex_lock(&dev_priv->dev->struct_mutex);
+		goto out;
 	misccpctl = I915_READ(GEN7_MISCCPCTL);
+	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	POSTING_READ(GEN7_MISCCPCTL);
+	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
+		u32 reg;
+		slice--;
+		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
+			break;
+		dev_priv->l3_parity.which_slice &= ~(1<
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-	POSTING_READ(GEN7_MISCCPCTL);
+		reg = GEN7_L3CDERRST1 + (slice * 0x200);
-	error_status = I915_READ(GEN7_L3CDERRST1);
+		error_status = I915_READ(reg);
 	row = GEN7_PARITY_ERROR_ROW(error_status);
 	bank = GEN7_PARITY_ERROR_BANK(error_status);
+	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
-	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
+		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
+		POSTING_READ(reg);
 		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
+			  slice, row, bank, subbank);
 	I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
-				    GEN7_L3CDERRST1_ENABLE);
-	POSTING_READ(GEN7_L3CDERRST1);
+	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
-	spin_lock_irqsave(&dev_priv->irq_lock, flags);
-	ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
-	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+out:
+	WARN_ON(dev_priv->l3_parity.which_slice);
-	mutex_unlock(&dev_priv->dev->struct_mutex);
+	spin_lock_irqsave(&dev_priv->irq_lock, flags);
 	ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
-	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
+	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 		  row, bank, subbank);
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 }
+static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	if (!HAS_L3_DPF(dev))
+		return;
-static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
+	spin_lock(&dev_priv->irq_lock);
 	ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
-	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	spin_unlock(&dev_priv->irq_lock);
 		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
 		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 		i915_handle_error(dev, false);
+	}
-	if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
+	if (gt_iir & GT_PARITY_ERROR(dev))
+		ivybridge_parity_error_irq_handler(dev, gt_iir);
+}
+static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
+				       struct drm_i915_private *dev_priv,
+				       u32 master_ctl)
+{
+	u32 rcs, bcs, vcs;
+	uint32_t tmp = 0;
+	irqreturn_t ret = IRQ_NONE;
+	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
+		tmp = I915_READ(GEN8_GT_IIR(0));
+		if (tmp) {
+			ret = IRQ_HANDLED;
+			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
+			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
+			if (rcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[RCS]);
+			if (bcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[BCS]);
+			I915_WRITE(GEN8_GT_IIR(0), tmp);
+		} else
+			DRM_ERROR("The master control interrupt lied (GT0)!\n");
+	}
+	if (master_ctl & GEN8_GT_VCS1_IRQ) {
+		tmp = I915_READ(GEN8_GT_IIR(1));
+		if (tmp) {
+			ret = IRQ_HANDLED;
+			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
+			if (vcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[VCS]);
+			I915_WRITE(GEN8_GT_IIR(1), tmp);
+		} else
+			DRM_ERROR("The master control interrupt lied (GT1)!\n");
+	}
+	if (master_ctl & GEN8_GT_VECS_IRQ) {
+		tmp = I915_READ(GEN8_GT_IIR(3));
+		if (tmp) {
+			ret = IRQ_HANDLED;
+			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
+			if (vcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[VECS]);
+			I915_WRITE(GEN8_GT_IIR(3), tmp);
+		} else
+			DRM_ERROR("The master control interrupt lied (GT3)!\n");
+	}
-		ivybridge_parity_error_irq_handler(dev);
+	return ret;
+}
 		return;
 	spin_lock(&dev_priv->irq_lock);
 	for (i = 1; i < HPD_NUM_PINS; i++) {
-		WARN(((hpd[i] & hotplug_trigger) &&
+		WARN_ONCE(hpd[i] & hotplug_trigger &&
+			  dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
-		      dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
+			  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
-		     "Received HPD interrupt although disabled\n");
+			  hotplug_trigger, i, hpd[i]);
 	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	wake_up_all(&dev_priv->gmbus_wait_queue);
+}
+#if defined(CONFIG_DEBUG_FS)
+static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
+					 uint32_t crc0, uint32_t crc1,
+					 uint32_t crc2, uint32_t crc3,
+					 uint32_t crc4)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
+	struct intel_pipe_crc_entry *entry;
+	int head, tail;
+	spin_lock(&pipe_crc->lock);
+	if (!pipe_crc->entries) {
+		spin_unlock(&pipe_crc->lock);
+		DRM_ERROR("spurious interrupt\n");
+		return;
+	}
+	head = pipe_crc->head;
+	tail = pipe_crc->tail;
+	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
+		spin_unlock(&pipe_crc->lock);
+		DRM_ERROR("CRC buffer overflowing\n");
+		return;
+	}
+	entry = &pipe_crc->entries[head];
+	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
+	entry->crc[0] = crc0;
+	entry->crc[1] = crc1;
+	entry->crc[2] = crc2;
+	entry->crc[3] = crc3;
+	entry->crc[4] = crc4;
+	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
+	pipe_crc->head = head;
+	spin_unlock(&pipe_crc->lock);
+	wake_up_interruptible(&pipe_crc->wq);
+}
+#else
+static inline void
+display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
+			     uint32_t crc0, uint32_t crc1,
+			     uint32_t crc2, uint32_t crc3,
+			     uint32_t crc4) {}
+#endif
+static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	display_pipe_crc_irq_handler(dev, pipe,
+				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
+, 0, 0, 0);
+}
+static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	display_pipe_crc_irq_handler(dev, pipe,
+				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
+				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
+				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
+				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
+				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
+}
+static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t res1, res2;
+	if (INTEL_INFO(dev)->gen >= 3)
+		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
+	else
+		res1 = 0;
+	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
+	else
+		res2 = 0;
+	display_pipe_crc_irq_handler(dev, pipe,
+				     I915_READ(PIPE_CRC_RES_RED(pipe)),
+				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
+				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
+				     res1, res2);
+}
 /* The RPS events need forcewake, so we add them to a work queue and mask their
  * IMR bits until the work is done. Other interrupts can be processed without
  * the work queue. */
 				I915_WRITE(reg, pipe_stats[pipe]);
+			}
+		}
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 #if 0
 		for_each_pipe(pipe) {
-			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+//			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
-				drm_handle_vblank(dev, pipe);
+//				drm_handle_vblank(dev, pipe);
 			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
-				intel_prepare_page_flip(dev, pipe);
+//				intel_prepare_page_flip(dev, pipe);
+//				intel_finish_page_flip(dev, pipe);
+			}
-				intel_finish_page_flip(dev, pipe);
+			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-			}
 				i9xx_pipe_crc_irq_handler(dev, pipe);
 #endif
 		/* Consume port.  Then clear IIR or we'll miss events */
 			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 					 hotplug_status);
+			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
+			if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
-			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
+				dp_aux_irq_handler(dev);
 			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 			I915_READ(PORT_HOTPLUG_STAT);
 static void ivb_err_int_handler(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 err_int = I915_READ(GEN7_ERR_INT);
-	u32 err_int = I915_READ(GEN7_ERR_INT);
+	enum pipe pipe;
+	if (err_int & ERR_INT_POISON)
-	if (err_int & ERR_INT_POISON)
+		DRM_ERROR("Poison interrupt\n");
-		DRM_ERROR("Poison interrupt\n");
+	for_each_pipe(pipe) {
+		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
+			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
+								  false))
-	if (err_int & ERR_INT_FIFO_UNDERRUN_A)
+				DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
-		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
+						 pipe_name(pipe));
+		}
-			DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
+		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
+			if (IS_IVYBRIDGE(dev))
+				ivb_pipe_crc_irq_handler(dev, pipe);
-	if (err_int & ERR_INT_FIFO_UNDERRUN_B)
+			else
-		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
-			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
-	if (err_int & ERR_INT_FIFO_UNDERRUN_C)
+				hsw_pipe_crc_irq_handler(dev, pipe);
 		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
 			DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
+}
 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum pipe pipe;
 	if (de_iir & DE_AUX_CHANNEL_A)
 		dp_aux_irq_handler(dev);
-	if (de_iir & DE_GSE)
-		intel_opregion_asle_intr(dev);
-#if 0
-	if (de_iir & DE_PIPEA_VBLANK)
-		drm_handle_vblank(dev, 0);
 	if (de_iir & DE_PIPEB_VBLANK)
-		drm_handle_vblank(dev, 1);
+	if (de_iir & DE_GSE)
-#endif
+		intel_opregion_asle_intr(dev);
 	if (de_iir & DE_POISON)
 		DRM_ERROR("Poison interrupt\n");
-	if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
+	for_each_pipe(pipe) {
-		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
+//		if (de_iir & DE_PIPE_VBLANK(pipe))
-			DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
-	if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
+//			drm_handle_vblank(dev, pipe);
-		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
-			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
+		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
+			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+				DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
-#if 0
+						 pipe_name(pipe));
-	if (de_iir & DE_PLANEA_FLIP_DONE) {
-		intel_prepare_page_flip(dev, 0);
+		if (de_iir & DE_PIPE_CRC_DONE(pipe))
+			i9xx_pipe_crc_irq_handler(dev, pipe);
 		intel_finish_page_flip_plane(dev, 0);
-	}
 		/* plane/pipes map 1:1 on ilk+ */
-	if (de_iir & DE_PLANEB_FLIP_DONE) {
+		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
-		intel_prepare_page_flip(dev, 1);
+//			intel_prepare_page_flip(dev, pipe);
+}
 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int i;
+	enum pipe i;
 	if (de_iir & DE_ERR_INT_IVB)
 		ivb_err_int_handler(dev);
 	if (de_iir & DE_AUX_CHANNEL_A_IVB)
 		dp_aux_irq_handler(dev);
 	if (de_iir & DE_GSE_IVB)
 		intel_opregion_asle_intr(dev);
+	for_each_pipe(i) {
-#if 0
+//		if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
-	for (i = 0; i < 3; i++) {
+//			drm_handle_vblank(dev, i);
-		if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
-			drm_handle_vblank(dev, i);
+		/* plane/pipes map 1:1 on ilk+ */
-		if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
+		if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
-			intel_prepare_page_flip(dev, i);
-			intel_finish_page_flip_plane(dev, i);
+//			intel_prepare_page_flip(dev, i);
 //			intel_finish_page_flip_plane(dev, i);
+		}
+{
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
 	irqreturn_t ret = IRQ_NONE;
-	bool err_int_reenable = false;
 	atomic_inc(&dev_priv->irq_received);
 		sde_ier = I915_READ(SDEIER);
 		I915_WRITE(SDEIER, 0);
 		POSTING_READ(SDEIER);
+	}
-	/* On Haswell, also mask ERR_INT because we don't want to risk
-	 * generating "unclaimed register" interrupts from inside the interrupt
-	 * handler. */
-	if (IS_HASWELL(dev)) {
-		spin_lock(&dev_priv->irq_lock);
-		err_int_reenable = ~dev_priv->irq_mask & DE_ERR_INT_IVB;
-		if (err_int_reenable)
-			ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
-		spin_unlock(&dev_priv->irq_lock);
-	}
 	gt_iir = I915_READ(GTIIR);
 	if (gt_iir) {
 		if (INTEL_INFO(dev)->gen >= 6)
 			snb_gt_irq_handler(dev, dev_priv, gt_iir);
 			I915_WRITE(GEN6_PMIIR, pm_iir);
 			ret = IRQ_HANDLED;
+		}
+	}
-	if (err_int_reenable) {
-		spin_lock(&dev_priv->irq_lock);
-		if (ivb_can_enable_err_int(dev))
-			ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
-		spin_unlock(&dev_priv->irq_lock);
-	}
 	I915_WRITE(DEIER, de_ier);
 	POSTING_READ(DEIER);
 	if (!HAS_PCH_NOP(dev)) {
 		I915_WRITE(SDEIER, sde_ier);
 		POSTING_READ(SDEIER);
+	}
+	return ret;
+}
+static irqreturn_t gen8_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = arg;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 master_ctl;
+	irqreturn_t ret = IRQ_NONE;
+	uint32_t tmp = 0;
+	enum pipe pipe;
+	atomic_inc(&dev_priv->irq_received);
+	master_ctl = I915_READ(GEN8_MASTER_IRQ);
+	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
+	if (!master_ctl)
+		return IRQ_NONE;
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+	POSTING_READ(GEN8_MASTER_IRQ);
+	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
+	if (master_ctl & GEN8_DE_MISC_IRQ) {
+		tmp = I915_READ(GEN8_DE_MISC_IIR);
+		if (tmp & GEN8_DE_MISC_GSE)
+			intel_opregion_asle_intr(dev);
+		else if (tmp)
+			DRM_ERROR("Unexpected DE Misc interrupt\n");
+		else
+			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
+		if (tmp) {
+			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
+			ret = IRQ_HANDLED;
+		}
+	}
+	if (master_ctl & GEN8_DE_PORT_IRQ) {
+		tmp = I915_READ(GEN8_DE_PORT_IIR);
+		if (tmp & GEN8_AUX_CHANNEL_A)
+			dp_aux_irq_handler(dev);
+		else if (tmp)
+			DRM_ERROR("Unexpected DE Port interrupt\n");
+		else
+			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
+		if (tmp) {
+			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
+			ret = IRQ_HANDLED;
+		}
+	}
+	for_each_pipe(pipe) {
+		uint32_t pipe_iir;
+		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
+			continue;
+		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+//		if (pipe_iir & GEN8_PIPE_VBLANK)
+//			drm_handle_vblank(dev, pipe);
+		if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
+//			intel_prepare_page_flip(dev, pipe);
+//			intel_finish_page_flip_plane(dev, pipe);
+		}
+		if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
+			hsw_pipe_crc_irq_handler(dev, pipe);
+		if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
+			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
+								  false))
+				DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
+						 pipe_name(pipe));
+		}
+		if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
+			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
+				  pipe_name(pipe),
+				  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
+		}
+		if (pipe_iir) {
+			ret = IRQ_HANDLED;
+			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
+		} else
+			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
+	}
+	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
+		/*
+		 * FIXME(BDW): Assume for now that the new interrupt handling
+		 * scheme also closed the SDE interrupt handling race we've seen
+		 * on older pch-split platforms. But this needs testing.
+		 */
+		u32 pch_iir = I915_READ(SDEIIR);
+		cpt_irq_handler(dev, pch_iir);
+		if (pch_iir) {
+			I915_WRITE(SDEIIR, pch_iir);
+			ret = IRQ_HANDLED;
+		}
+	}
+	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+	POSTING_READ(GEN8_MASTER_IRQ);
 	return ret;
+}
 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
 			       bool reset_completed)
 			 * the counter increment.
 			 */
 			atomic_inc(&dev_priv->gpu_error.reset_counter);
 		} else {
-			atomic_set(&error->reset_counter, I915_WEDGED);
+			atomic_set_mask(I915_WEDGED, &error->reset_counter);
+	}
 		/*
 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
-						     DE_PIPE_VBLANK_ILK(pipe);
+						     DE_PIPE_VBLANK(pipe);
 	if (!i915_pipe_enabled(dev, pipe))
 		return -EINVAL;
 	if (!i915_pipe_enabled(dev, pipe))
 		return -EINVAL;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	imr = I915_READ(VLV_IMR);
-	if (pipe == 0)
+	if (pipe == PIPE_A)
 		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
 	else
 		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 	I915_WRITE(VLV_IMR, imr);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
+static int gen8_enable_vblank(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long irqflags;
+	if (!i915_pipe_enabled(dev, pipe))
+		return -EINVAL;
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
+	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+	return 0;
+}
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
 	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
-						     DE_PIPE_VBLANK_ILK(pipe);
+						     DE_PIPE_VBLANK(pipe);
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	ironlake_disable_display_irq(dev_priv, bit);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	i915_disable_pipestat(dev_priv, pipe,
 			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	imr = I915_READ(VLV_IMR);
-	if (pipe == 0)
+	if (pipe == PIPE_A)
 		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
 	else
 		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 	I915_WRITE(VLV_IMR, imr);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+static void gen8_disable_vblank(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long irqflags;
+	if (!i915_pipe_enabled(dev, pipe))
+		return;
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
+	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 static u32
 ring_last_seqno(struct intel_ring_buffer *ring)
+{
 				 */
 				ring->hangcheck.action = ring_stuck(ring,
 								    acthd);
+				switch (ring->hangcheck.action) {
-				switch (ring->hangcheck.action) {
+				case HANGCHECK_IDLE:
 				case HANGCHECK_WAIT:
 					break;
 				case HANGCHECK_ACTIVE:
 					ring->hangcheck.score += BUSY;
 					stuck[i] = true;
 					break;
+				}
+			}
 		} else {
+			ring->hangcheck.action = HANGCHECK_ACTIVE;
 			/* Gradually reduce the count so that we catch DoS
 			 * attempts across multiple batches.
 			 */
 			if (ring->hangcheck.score > 0)
 				ring->hangcheck.score--;
 	I915_WRITE(VLV_IMR, 0xffffffff);
 	I915_WRITE(VLV_IER, 0x0);
 	POSTING_READ(VLV_IER);
+}
+static void gen8_irq_preinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+	atomic_set(&dev_priv->irq_received, 0);
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+	POSTING_READ(GEN8_MASTER_IRQ);
+	/* IIR can theoretically queue up two events. Be paranoid */
+#define GEN8_IRQ_INIT_NDX(type, which) do { \
+		I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
+		POSTING_READ(GEN8_##type##_IMR(which)); \
+		I915_WRITE(GEN8_##type##_IER(which), 0); \
+		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
+		POSTING_READ(GEN8_##type##_IIR(which)); \
+		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
+	} while (0)
+#define GEN8_IRQ_INIT(type) do { \
+		I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
+		POSTING_READ(GEN8_##type##_IMR); \
+		I915_WRITE(GEN8_##type##_IER, 0); \
+		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
+		POSTING_READ(GEN8_##type##_IIR); \
+		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
+	} while (0)
+	GEN8_IRQ_INIT_NDX(GT, 0);
+	GEN8_IRQ_INIT_NDX(GT, 1);
+	GEN8_IRQ_INIT_NDX(GT, 2);
+	GEN8_IRQ_INIT_NDX(GT, 3);
+	for_each_pipe(pipe) {
+		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
+	}
+	GEN8_IRQ_INIT(DE_PORT);
+	GEN8_IRQ_INIT(DE_MISC);
+	GEN8_IRQ_INIT(PCU);
+#undef GEN8_IRQ_INIT
+#undef GEN8_IRQ_INIT_NDX
+	POSTING_READ(GEN8_PCU_IIR);
+	ibx_irq_preinstall(dev);
+}
 static void ibx_hpd_irq_setup(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	u32 pm_irqs, gt_irqs;
 	pm_irqs = gt_irqs = 0;
 	dev_priv->gt_irq_mask = ~0;
-	if (HAS_L3_GPU_CACHE(dev)) {
+	if (HAS_L3_DPF(dev)) {
 		/* L3 parity interrupt is always unmasked. */
-		dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
-		gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+		gt_irqs |= GT_PARITY_ERROR(dev);
+	}
 		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
 	} else {
 		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
+				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
-				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
+				DE_AUX_CHANNEL_A |
-				DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
+				DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
+				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
-				DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
+				DE_POISON);
 		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
+	}
 static int valleyview_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u32 enable_mask;
+	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
-	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
+		PIPE_CRC_DONE_ENABLE;
 	unsigned long irqflags;
 	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
 	POSTING_READ(VLV_IER);
 	/* Interrupt setup is already guaranteed to be single-threaded, this is
 	 * just to make the assert_spin_locked check happy. */
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	i915_enable_pipestat(dev_priv, 0, pipestat_enable);
+	i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
-	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
-	i915_enable_pipestat(dev_priv, 1, pipestat_enable);
+	i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 	return 0;
+}
+static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	int i;
+	/* These are interrupts we'll toggle with the ring mask register */
+	uint32_t gt_interrupts[] = {
+		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
+			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
+			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
+		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
+			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
+,
+		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
+		};
+	for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
+		u32 tmp = I915_READ(GEN8_GT_IIR(i));
+		if (tmp)
+			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
+				  i, tmp);
+		I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
+		I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
+	}
+	POSTING_READ(GEN8_GT_IER(0));
+}
+static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+	uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
+		GEN8_PIPE_CDCLK_CRC_DONE |
+		GEN8_PIPE_FIFO_UNDERRUN |
+		GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+	uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
+	int pipe;
+	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
+	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
+	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
+	for_each_pipe(pipe) {
+		u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+		if (tmp)
+			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
+				  pipe, tmp);
+		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+		I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
+	}
+	POSTING_READ(GEN8_DE_PIPE_ISR(0));
+	I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
+	I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
+	POSTING_READ(GEN8_DE_PORT_IER);
+}
+static int gen8_irq_postinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	gen8_gt_irq_postinstall(dev_priv);
+	gen8_de_irq_postinstall(dev_priv);
+	ibx_irq_postinstall(dev);
+	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
+	POSTING_READ(GEN8_MASTER_IRQ);
+	return 0;
+}
+static void gen8_irq_uninstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+	if (!dev_priv)
+		return;
+	atomic_set(&dev_priv->irq_received, 0);
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+#define GEN8_IRQ_FINI_NDX(type, which) do { \
+		I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
+		I915_WRITE(GEN8_##type##_IER(which), 0); \
+		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
+	} while (0)
+#define GEN8_IRQ_FINI(type) do { \
+		I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
+		I915_WRITE(GEN8_##type##_IER, 0); \
+		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
+	} while (0)
+	GEN8_IRQ_FINI_NDX(GT, 0);
+	GEN8_IRQ_FINI_NDX(GT, 1);
+	GEN8_IRQ_FINI_NDX(GT, 2);
+	GEN8_IRQ_FINI_NDX(GT, 3);
+	for_each_pipe(pipe) {
+		GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
+	}
+	GEN8_IRQ_FINI(DE_PORT);
+	GEN8_IRQ_FINI(DE_MISC);
+	GEN8_IRQ_FINI(PCU);
+#undef GEN8_IRQ_FINI
+#undef GEN8_IRQ_FINI_NDX
+	POSTING_READ(GEN8_PCU_IIR);
+}
 static void valleyview_irq_uninstall(struct drm_device *dev)
+{
+}
 static int i8xx_irq_postinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
 	I915_WRITE16(EMR,
 		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
 		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
 		     I915_USER_INTERRUPT);
 	POSTING_READ16(IER);
+	/* Interrupt setup is already guaranteed to be single-threaded, this is
+	 * just to make the assert_spin_locked check happy. */
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
+	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
 /*
  * Returns true when a page flip has completed.
  */
 static bool i8xx_handle_vblank(struct drm_device *dev,
-			       int pipe, u16 iir)
+			       int plane, int pipe, u32 iir)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
+	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
 		i915_update_dri1_breadcrumb(dev);
 		if (iir & I915_USER_INTERRUPT)
+			notify_ring(dev, &dev_priv->ring[RCS]);
+		for_each_pipe(pipe) {
+			int plane = pipe;
+			if (HAS_FBC(dev))
-			notify_ring(dev, &dev_priv->ring[RCS]);
+				plane = !plane;
-		if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
+			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
-		    i8xx_handle_vblank(dev, 0, iir))
+			    i8xx_handle_vblank(dev, plane, pipe, iir))
-			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
+				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
-		if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
+			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-		    i8xx_handle_vblank(dev, 1, iir))
+				i9xx_pipe_crc_irq_handler(dev, pipe);
 			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
 static int i915_irq_postinstall(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	u32 enable_mask;
-	u32 enable_mask;
+	unsigned long irqflags;
 	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
 	I915_WRITE(IER, enable_mask);
 	POSTING_READ(IER);
+	i915_enable_asle_pipestat(dev);
+	/* Interrupt setup is already guaranteed to be single-threaded, this is
+	 * just to make the assert_spin_locked check happy. */
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
+	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
-	i915_enable_asle_pipestat(dev);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
 		if (iir & I915_USER_INTERRUPT)
 			notify_ring(dev, &dev_priv->ring[RCS]);
 		for_each_pipe(pipe) {
 			int plane = pipe;
-			if (IS_MOBILE(dev))
+			if (HAS_FBC(dev))
 				plane = !plane;
 			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
 			    i915_handle_vblank(dev, plane, pipe, iir))
 				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
+			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+				blc_event = true;
-			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-				blc_event = true;
+				i9xx_pipe_crc_irq_handler(dev, pipe);
 		enable_mask |= I915_BSD_USER_INTERRUPT;
 	/* Interrupt setup is already guaranteed to be single-threaded, this is
 	 * just to make the assert_spin_locked check happy. */
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
-	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
+	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	/*
 			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 				  hotplug_status);
+			intel_hpd_irq_handler(dev, hotplug_trigger,
+					      IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
+			if (IS_G4X(dev) &&
-			intel_hpd_irq_handler(dev, hotplug_trigger,
+			    (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
-					      IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
+				dp_aux_irq_handler(dev);
 			    i915_handle_vblank(dev, pipe, pipe, iir))
 				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
 			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+				blc_event = true;
+			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-				blc_event = true;
+				i9xx_pipe_crc_irq_handler(dev, pipe);
+		}
 	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 	setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
+		    (unsigned long) dev_priv);
-		    (unsigned long) dev_priv);
+	if (IS_GEN2(dev)) {
-	dev->driver->get_vblank_counter = i915_get_vblank_counter;
+		dev->max_vblank_count = 0;
-	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
+		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
-	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
+	} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
+		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
+		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
+	} else {
-		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
+	dev->driver->get_vblank_counter = i915_get_vblank_counter;
-		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
+	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
+	}
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
 		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
+	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-	else
+		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
-		dev->driver->get_vblank_timestamp = NULL;
+	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 	if (IS_VALLEYVIEW(dev)) {
 		dev->driver->irq_handler = valleyview_irq_handler;
 		dev->driver->irq_preinstall = valleyview_irq_preinstall;
 		dev->driver->irq_postinstall = valleyview_irq_postinstall;
+		dev->driver->irq_uninstall = valleyview_irq_uninstall;
+		dev->driver->enable_vblank = valleyview_enable_vblank;
+		dev->driver->disable_vblank = valleyview_disable_vblank;
+		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+	} else if (IS_GEN8(dev)) {
+		dev->driver->irq_handler = gen8_irq_handler;
+		dev->driver->irq_preinstall = gen8_irq_preinstall;
+		dev->driver->irq_postinstall = gen8_irq_postinstall;
-		dev->driver->irq_uninstall = valleyview_irq_uninstall;
+		dev->driver->irq_uninstall = gen8_irq_uninstall;
-		dev->driver->enable_vblank = valleyview_enable_vblank;
+		dev->driver->enable_vblank = gen8_enable_vblank;
-		dev->driver->disable_vblank = valleyview_disable_vblank;
+		dev->driver->disable_vblank = gen8_disable_vblank;
-		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
 	} else if (HAS_PCH_SPLIT(dev)) {
 	dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
 	dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
 	dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
 	dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
-	ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
+	ironlake_disable_display_irq(dev_priv, 0xffffffff);
-	ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
+	ibx_disable_display_interrupt(dev_priv, 0xffffffff);
 	ilk_disable_gt_irq(dev_priv, 0xffffffff);
 	snb_disable_pm_irq(dev_priv, 0xffffffff);
 /* Restore interrupts so we can recover from Package C8+. */
 void hsw_pc8_restore_interrupts(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long irqflags;
-	uint32_t val, expected;
+	uint32_t val;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	val = I915_READ(DEIMR);
-	expected = ~DE_PCH_EVENT_IVB;
+	val = I915_READ(DEIMR);
-	WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
+	WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
-	val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
 	expected = ~SDE_HOTPLUG_MASK_CPT;
-	WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
-	     val, expected);
+	val = I915_READ(SDEIMR);
 	WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
-	val = I915_READ(GTIMR);
-	expected = 0xffffffff;
-	WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
 	val = I915_READ(GTIMR);
-	val = I915_READ(GEN6_PMIMR);
+	WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
-	expected = 0xffffffff;
-	WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
-	     expected);
 	val = I915_READ(GEN6_PMIMR);
-	dev_priv->pc8.irqs_disabled = false;
+	WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
-	ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
+	dev_priv->pc8.irqs_disabled = false;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_irq.c – Rev 4539 → 4560