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Rev 3051 Rev 3243
Line 26... Line 26...
26
 *
26
 *
27
 */
27
 */
Line 28... Line 28...
28
 
28
 
Line 29... Line -...
29
#define pr_fmt(fmt) ": " fmt
-
 
30
 
29
#define pr_fmt(fmt) ": " fmt
31
#include 
30
 
32
#include 
31
#include 
33
#include 
32
#include 
34
#include 
33
#include 
Line 38... Line 37...
38
 
37
 
39
 
38
 
Line 40... Line -...
40
#define pr_err(fmt, ...) \
-
 
41
        printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
-
 
42
 
-
 
43
#define DRM_IRQ_ARGS            void *arg
-
 
44
 
-
 
45
static struct drm_driver {
-
 
46
    irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
-
 
47
    void (*irq_preinstall) (struct drm_device *dev);
-
 
48
    int (*irq_postinstall) (struct drm_device *dev);
-
 
Line 49... Line 39...
49
}drm_driver;
39
#define pr_err(fmt, ...) \
50
 
40
        printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
Line 51... Line 41...
51
static struct drm_driver *driver = &drm_driver;
41
 
Line 168... Line 158...
168
 */
158
 */
169
static int
159
static int
170
i915_pipe_enabled(struct drm_device *dev, int pipe)
160
i915_pipe_enabled(struct drm_device *dev, int pipe)
171
{
161
{
172
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
162
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-
 
163
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
-
 
164
								      pipe);
-
 
165
 
173
	return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
166
	return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
174
}
167
}
Line 175... Line 168...
175
 
168
 
176
/* Called from drm generic code, passed a 'crtc', which
169
/* Called from drm generic code, passed a 'crtc', which
177
 * we use as a pipe index
170
 * we use as a pipe index
Line 258... Line 251...
258
	spin_unlock_irq(&dev_priv->rps.lock);
251
	spin_unlock_irq(&dev_priv->rps.lock);
Line 259... Line 252...
259
 
252
 
260
	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
253
	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
Line 261... Line 254...
261
		return;
254
		return;
Line 262... Line 255...
262
 
255
 
263
	mutex_lock(&dev_priv->dev->struct_mutex);
256
	mutex_lock(&dev_priv->rps.hw_lock);
264
 
257
 
265
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
258
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
Line 273... Line 266...
273
	if (!(new_delay > dev_priv->rps.max_delay ||
266
	if (!(new_delay > dev_priv->rps.max_delay ||
274
	      new_delay < dev_priv->rps.min_delay)) {
267
	      new_delay < dev_priv->rps.min_delay)) {
275
		gen6_set_rps(dev_priv->dev, new_delay);
268
		gen6_set_rps(dev_priv->dev, new_delay);
276
	}
269
	}
Line 277... Line 270...
277
 
270
 
278
	mutex_unlock(&dev_priv->dev->struct_mutex);
271
	mutex_unlock(&dev_priv->rps.hw_lock);
Line 279... Line 272...
279
}
272
}
280
 
273
 
Line 289... Line 282...
289
 * it is likely the same row is more likely to go bad again.
282
 * it is likely the same row is more likely to go bad again.
290
 */
283
 */
291
static void ivybridge_parity_work(struct work_struct *work)
284
static void ivybridge_parity_work(struct work_struct *work)
292
{
285
{
293
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
286
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
294
						    parity_error_work);
287
						    l3_parity.error_work);
295
	u32 error_status, row, bank, subbank;
288
	u32 error_status, row, bank, subbank;
296
	char *parity_event[5];
289
	char *parity_event[5];
297
	uint32_t misccpctl;
290
	uint32_t misccpctl;
298
	unsigned long flags;
291
	unsigned long flags;
Line 353... Line 346...
353
	spin_lock_irqsave(&dev_priv->irq_lock, flags);
346
	spin_lock_irqsave(&dev_priv->irq_lock, flags);
354
	dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
347
	dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
355
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
348
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
356
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
349
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Line 357... Line 350...
357
 
350
 
358
	queue_work(dev_priv->wq, &dev_priv->parity_error_work);
351
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Line 359... Line 352...
359
}
352
}
Line 360... Line 353...
360
 
353
 
361
#endif
354
#endif
362
 
355
 
363
static void snb_gt_irq_handler(struct drm_device *dev,
356
static void snb_gt_irq_handler(struct drm_device *dev,
-
 
357
			       struct drm_i915_private *dev_priv,
Line 364... Line 358...
364
			       struct drm_i915_private *dev_priv,
358
			       u32 gt_iir)
365
			       u32 gt_iir)
359
{
366
{
360
    printf("%s\n", __FUNCTION__);
367
 
361
 
Line 403... Line 397...
403
	dev_priv->rps.pm_iir |= pm_iir;
397
	dev_priv->rps.pm_iir |= pm_iir;
404
	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
398
	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
405
	POSTING_READ(GEN6_PMIMR);
399
	POSTING_READ(GEN6_PMIMR);
406
	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
400
	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
Line 407... Line 401...
407
 
401
 
408
	queue_work(dev_priv->wq, &dev_priv->rps.work);
402
//   queue_work(dev_priv->wq, &dev_priv->rps.work);
Line 409... Line 403...
409
}
403
}
410
 
404
 
411
static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
405
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
412
{
406
{
413
	struct drm_device *dev = (struct drm_device *) arg;
407
	struct drm_device *dev = (struct drm_device *) arg;
414
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
408
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
415
	u32 iir, gt_iir, pm_iir;
409
	u32 iir, gt_iir, pm_iir;
416
	irqreturn_t ret = IRQ_NONE;
410
	irqreturn_t ret = IRQ_NONE;
417
	unsigned long irqflags;
411
	unsigned long irqflags;
418
	int pipe;
412
	int pipe;
Line -... Line 413...
-
 
413
	u32 pipe_stats[I915_MAX_PIPES];
-
 
414
	bool blc_event;
419
	u32 pipe_stats[I915_MAX_PIPES];
415
 
Line 420... Line 416...
420
	bool blc_event;
416
    printf("%s\n", __FUNCTION__);
421
 
417
 
422
	atomic_inc(&dev_priv->irq_received);
418
	atomic_inc(&dev_priv->irq_received);
Line 477... Line 473...
477
		}
473
		}
Line 478... Line 474...
478
 
474
 
479
		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
475
		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
Line 480... Line 476...
480
			blc_event = true;
476
			blc_event = true;
481
 
477
 
Line 482... Line 478...
482
//		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
478
        if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
483
//			gen6_queue_rps_work(dev_priv, pm_iir);
479
            gen6_queue_rps_work(dev_priv, pm_iir);
484
 
480
 
485
		I915_WRITE(GTIIR, gt_iir);
481
		I915_WRITE(GTIIR, gt_iir);
Line 494... Line 490...
494
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
490
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
495
{
491
{
496
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
492
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
497
	int pipe;
493
	int pipe;
Line -... Line 494...
-
 
494
 
-
 
495
    printf("%s\n", __FUNCTION__);
498
 
496
 
499
	if (pch_iir & SDE_AUDIO_POWER_MASK)
497
	if (pch_iir & SDE_AUDIO_POWER_MASK)
500
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
498
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
501
				 (pch_iir & SDE_AUDIO_POWER_MASK) >>
499
				 (pch_iir & SDE_AUDIO_POWER_MASK) >>
Line 558... Line 556...
558
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
556
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
559
					 pipe_name(pipe),
557
					 pipe_name(pipe),
560
					 I915_READ(FDI_RX_IIR(pipe)));
558
					 I915_READ(FDI_RX_IIR(pipe)));
561
}
559
}
Line 562... Line 560...
562
 
560
 
563
static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
561
static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
564
{
562
{
565
	struct drm_device *dev = (struct drm_device *) arg;
563
	struct drm_device *dev = (struct drm_device *) arg;
566
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
564
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
567
	u32 de_iir, gt_iir, de_ier, pm_iir;
565
	u32 de_iir, gt_iir, de_ier, pm_iir;
568
	irqreturn_t ret = IRQ_NONE;
566
	irqreturn_t ret = IRQ_NONE;
Line -... Line 567...
-
 
567
	int i;
-
 
568
 
569
	int i;
569
    printf("%s\n", __FUNCTION__);
Line 570... Line 570...
570
 
570
 
571
	atomic_inc(&dev_priv->irq_received);
571
	atomic_inc(&dev_priv->irq_received);
572
 
572
 
Line 634... Line 634...
634
		notify_ring(dev, &dev_priv->ring[RCS]);
634
		notify_ring(dev, &dev_priv->ring[RCS]);
635
	if (gt_iir & GT_BSD_USER_INTERRUPT)
635
	if (gt_iir & GT_BSD_USER_INTERRUPT)
636
		notify_ring(dev, &dev_priv->ring[VCS]);
636
		notify_ring(dev, &dev_priv->ring[VCS]);
637
}
637
}
Line 638... Line 638...
638
 
638
 
639
static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
639
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
640
{
640
{
641
	struct drm_device *dev = (struct drm_device *) arg;
641
	struct drm_device *dev = (struct drm_device *) arg;
642
    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
642
    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
643
    int ret = IRQ_NONE;
643
    int ret = IRQ_NONE;
-
 
644
    u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
644
    u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
645
 
Line 645... Line 646...
645
    u32 hotplug_mask;
646
    printf("%s\n", __FUNCTION__);
Line 646... Line 647...
646
 
647
 
647
    atomic_inc(&dev_priv->irq_received);
648
    atomic_inc(&dev_priv->irq_received);
Line 658... Line 659...
658
 
659
 
659
    if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
660
    if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
660
        (!IS_GEN6(dev) || pm_iir == 0))
661
        (!IS_GEN6(dev) || pm_iir == 0))
Line 661... Line -...
661
        goto done;
-
 
662
 
-
 
663
    if (HAS_PCH_CPT(dev))
-
 
664
        hotplug_mask = SDE_HOTPLUG_MASK_CPT;
-
 
665
    else
-
 
666
        hotplug_mask = SDE_HOTPLUG_MASK;
662
        goto done;
Line 667... Line 663...
667
 
663
 
668
    ret = IRQ_HANDLED;
664
    ret = IRQ_HANDLED;
669
 
665
 
Line 984... Line 980...
984
		error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
980
		error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
985
		error->semaphore_mboxes[ring->id][0]
981
		error->semaphore_mboxes[ring->id][0]
986
			= I915_READ(RING_SYNC_0(ring->mmio_base));
982
			= I915_READ(RING_SYNC_0(ring->mmio_base));
987
		error->semaphore_mboxes[ring->id][1]
983
		error->semaphore_mboxes[ring->id][1]
988
			= I915_READ(RING_SYNC_1(ring->mmio_base));
984
			= I915_READ(RING_SYNC_1(ring->mmio_base));
-
 
985
		error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
-
 
986
		error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
989
	}
987
	}
Line 990... Line 988...
990
 
988
 
991
	if (INTEL_INFO(dev)->gen >= 4) {
989
	if (INTEL_INFO(dev)->gen >= 4) {
992
		error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
990
		error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
Line 1007... Line 1005...
1007
	error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1005
	error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1008
	error->seqno[ring->id] = ring->get_seqno(ring, false);
1006
	error->seqno[ring->id] = ring->get_seqno(ring, false);
1009
	error->acthd[ring->id] = intel_ring_get_active_head(ring);
1007
	error->acthd[ring->id] = intel_ring_get_active_head(ring);
1010
	error->head[ring->id] = I915_READ_HEAD(ring);
1008
	error->head[ring->id] = I915_READ_HEAD(ring);
1011
	error->tail[ring->id] = I915_READ_TAIL(ring);
1009
	error->tail[ring->id] = I915_READ_TAIL(ring);
-
 
1010
	error->ctl[ring->id] = I915_READ_CTL(ring);
Line 1012... Line 1011...
1012
 
1011
 
1013
	error->cpu_ring_head[ring->id] = ring->head;
1012
	error->cpu_ring_head[ring->id] = ring->head;
1014
	error->cpu_ring_tail[ring->id] = ring->tail;
1013
	error->cpu_ring_tail[ring->id] = ring->tail;
Line 1101... Line 1100...
1101
	else if (IS_GEN2(dev))
1100
	else if (IS_GEN2(dev))
1102
		error->ier = I915_READ16(IER);
1101
		error->ier = I915_READ16(IER);
1103
	else
1102
	else
1104
		error->ier = I915_READ(IER);
1103
		error->ier = I915_READ(IER);
Line -... Line 1104...
-
 
1104
 
-
 
1105
	if (INTEL_INFO(dev)->gen >= 6)
-
 
1106
		error->derrmr = I915_READ(DERRMR);
-
 
1107
 
-
 
1108
	if (IS_VALLEYVIEW(dev))
-
 
1109
		error->forcewake = I915_READ(FORCEWAKE_VLV);
-
 
1110
	else if (INTEL_INFO(dev)->gen >= 7)
-
 
1111
		error->forcewake = I915_READ(FORCEWAKE_MT);
-
 
1112
	else if (INTEL_INFO(dev)->gen == 6)
-
 
1113
		error->forcewake = I915_READ(FORCEWAKE);
1105
 
1114
 
1106
	for_each_pipe(pipe)
1115
	for_each_pipe(pipe)
Line 1107... Line 1116...
1107
		error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1116
		error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1108
 
1117
 
Line 1331... Line 1340...
1331
		return;
1340
		return;
Line 1332... Line 1341...
1332
 
1341
 
1333
	spin_lock_irqsave(&dev->event_lock, flags);
1342
	spin_lock_irqsave(&dev->event_lock, flags);
Line -... Line 1343...
-
 
1343
	work = intel_crtc->unpin_work;
-
 
1344
 
1334
	work = intel_crtc->unpin_work;
1345
	if (work == NULL ||
1335
 
1346
	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1336
	if (work == NULL || work->pending || !work->enable_stall_check) {
1347
	    !work->enable_stall_check) {
1337
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
1348
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
1338
		spin_unlock_irqrestore(&dev->event_lock, flags);
1349
		spin_unlock_irqrestore(&dev->event_lock, flags);
Line 1646... Line 1657...
1646
 
1657
 
1647
    if (IS_IRONLAKE_M(dev)) {
1658
    if (IS_IRONLAKE_M(dev)) {
1648
        /* Clear & enable PCU event interrupts */
1659
        /* Clear & enable PCU event interrupts */
1649
        I915_WRITE(DEIIR, DE_PCU_EVENT);
1660
        I915_WRITE(DEIIR, DE_PCU_EVENT);
1650
        I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1661
        I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1651
        ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1662
//        ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
Line 1652... Line 1663...
1652
    }
1663
    }
1653
 
1664
 
Line 1708... Line 1719...
1708
{
1719
{
1709
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1720
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1710
	u32 enable_mask;
1721
	u32 enable_mask;
1711
	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1722
	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1712
	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
1723
	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
-
 
1724
	u32 render_irqs;
1713
	u16 msid;
1725
	u16 msid;
Line 1714... Line 1726...
1714
 
1726
 
1715
	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1727
	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1716
	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1728
	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
Line 1728... Line 1740...
1728
 
1740
 
1729
	dev_priv->pipestat[0] = 0;
1741
	dev_priv->pipestat[0] = 0;
Line 1730... Line 1742...
1730
	dev_priv->pipestat[1] = 0;
1742
	dev_priv->pipestat[1] = 0;
1731
 
1743
 
1732
	/* Hack for broken MSIs on VLV */
1744
	/* Hack for broken MSIs on VLV */
1733
	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1745
//   pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1734
	pci_read_config_word(dev->pdev, 0x98, &msid);
1746
//   pci_read_config_word(dev->pdev, 0x98, &msid);
1735
	msid &= 0xff; /* mask out delivery bits */
1747
//   msid &= 0xff; /* mask out delivery bits */
Line 1736... Line 1748...
1736
	msid |= (1<<14);
1748
//   msid |= (1<<14);
1737
	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1749
//   pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1738
 
1750
 
1739
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1751
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
Line 1747... Line 1759...
1747
	i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1759
	i915_enable_pipestat(dev_priv, 1, pipestat_enable);
Line 1748... Line 1760...
1748
 
1760
 
1749
	I915_WRITE(VLV_IIR, 0xffffffff);
1761
	I915_WRITE(VLV_IIR, 0xffffffff);
Line 1750... Line -...
1750
	I915_WRITE(VLV_IIR, 0xffffffff);
-
 
1751
 
-
 
1752
	dev_priv->gt_irq_mask = ~0;
-
 
1753
 
1762
	I915_WRITE(VLV_IIR, 0xffffffff);
1754
	I915_WRITE(GTIIR, I915_READ(GTIIR));
1763
 
-
 
1764
	I915_WRITE(GTIIR, I915_READ(GTIIR));
1755
	I915_WRITE(GTIIR, I915_READ(GTIIR));
1765
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1756
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
-
 
1757
	I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1766
 
1758
		   GT_GEN6_BLT_CS_ERROR_INTERRUPT |
-
 
1759
		   GT_GEN6_BLT_USER_INTERRUPT |
-
 
1760
		   GT_GEN6_BSD_USER_INTERRUPT |
-
 
1761
		   GT_GEN6_BSD_CS_ERROR_INTERRUPT |
-
 
1762
		   GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1767
	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1763
		   GT_PIPE_NOTIFY |
-
 
1764
		   GT_RENDER_CS_ERROR_INTERRUPT |
-
 
1765
		   GT_SYNC_STATUS |
1768
		GEN6_BLITTER_USER_INTERRUPT;
Line 1766... Line 1769...
1766
		   GT_USER_INTERRUPT);
1769
	I915_WRITE(GTIER, render_irqs);
1767
	POSTING_READ(GTIER);
1770
	POSTING_READ(GTIER);
1768
 
1771
 
Line 1779... Line 1782...
1779
		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1782
		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1780
	if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1783
	if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1781
		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1784
		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1782
	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1785
	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1783
		hotplug_en |= HDMID_HOTPLUG_INT_EN;
1786
		hotplug_en |= HDMID_HOTPLUG_INT_EN;
1784
	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1787
	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
1785
		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1788
		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1786
	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1789
	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
1787
		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1790
		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1788
	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1791
	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1789
		hotplug_en |= CRT_HOTPLUG_INT_EN;
1792
		hotplug_en |= CRT_HOTPLUG_INT_EN;
1790
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1793
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1791
	}
1794
	}
Line 1794... Line 1797...
1794
	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1797
	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
Line 1795... Line 1798...
1795
 
1798
 
1796
	return 0;
1799
	return 0;
Line 1797... Line -...
1797
}
-
 
1798
 
1800
}
1799
 
1801
 
1800
static void valleyview_irq_uninstall(struct drm_device *dev)
1802
static void valleyview_irq_uninstall(struct drm_device *dev)
1801
{
1803
{
Line 1884... Line 1886...
1884
	POSTING_READ16(IER);
1886
	POSTING_READ16(IER);
Line 1885... Line 1887...
1885
 
1887
 
1886
	return 0;
1888
	return 0;
Line 1887... Line -...
1887
}
-
 
1888
 
1889
}
1889
 
1890
 
1890
static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
1891
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
1891
{
1892
{
1892
	struct drm_device *dev = (struct drm_device *) arg;
1893
	struct drm_device *dev = (struct drm_device *) arg;
1893
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1894
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Line 2066... Line 2067...
2066
//	intel_opregion_enable_asle(dev);
2067
//	intel_opregion_enable_asle(dev);
Line 2067... Line 2068...
2067
 
2068
 
2068
	return 0;
2069
	return 0;
Line 2069... Line 2070...
2069
}
2070
}
2070
 
2071
 
2071
static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2072
static irqreturn_t i915_irq_handler(int irq, void *arg)
2072
{
2073
{
2073
	struct drm_device *dev = (struct drm_device *) arg;
2074
	struct drm_device *dev = (struct drm_device *) arg;
2074
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2075
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Line 2305... Line 2306...
2305
//	intel_opregion_enable_asle(dev);
2306
//	intel_opregion_enable_asle(dev);
Line 2306... Line 2307...
2306
 
2307
 
2307
	return 0;
2308
	return 0;
Line 2308... Line 2309...
2308
}
2309
}
2309
 
2310
 
2310
static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2311
static irqreturn_t i965_irq_handler(int irq, void *arg)
2311
{
2312
{
2312
	struct drm_device *dev = (struct drm_device *) arg;
2313
	struct drm_device *dev = (struct drm_device *) arg;
2313
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2314
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Line 2449... Line 2450...
2449
void intel_irq_init(struct drm_device *dev)
2450
void intel_irq_init(struct drm_device *dev)
2450
{
2451
{
2451
	struct drm_i915_private *dev_priv = dev->dev_private;
2452
	struct drm_i915_private *dev_priv = dev->dev_private;
Line 2452... Line 2453...
2452
 
2453
 
2453
	if (IS_VALLEYVIEW(dev)) {
2454
	if (IS_VALLEYVIEW(dev)) {
2454
        driver->irq_handler = valleyview_irq_handler;
2455
		dev->driver->irq_handler = valleyview_irq_handler;
2455
        driver->irq_preinstall = valleyview_irq_preinstall;
2456
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
2456
        driver->irq_postinstall = valleyview_irq_postinstall;
2457
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
2457
	} else if (IS_IVYBRIDGE(dev)) {
2458
	} else if (IS_IVYBRIDGE(dev)) {
2458
		/* Share pre & uninstall handlers with ILK/SNB */
2459
		/* Share pre & uninstall handlers with ILK/SNB */
2459
        driver->irq_handler = ivybridge_irq_handler;
2460
		dev->driver->irq_handler = ivybridge_irq_handler;
2460
        driver->irq_preinstall = ironlake_irq_preinstall;
2461
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
2461
        driver->irq_postinstall = ivybridge_irq_postinstall;
2462
		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2462
	} else if (IS_HASWELL(dev)) {
2463
	} else if (IS_HASWELL(dev)) {
2463
		/* Share interrupts handling with IVB */
2464
		/* Share interrupts handling with IVB */
2464
        driver->irq_handler = ivybridge_irq_handler;
2465
		dev->driver->irq_handler = ivybridge_irq_handler;
2465
        driver->irq_preinstall = ironlake_irq_preinstall;
2466
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
2466
        driver->irq_postinstall = ivybridge_irq_postinstall;
2467
		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2467
	} else if (HAS_PCH_SPLIT(dev)) {
2468
	} else if (HAS_PCH_SPLIT(dev)) {
2468
        driver->irq_handler = ironlake_irq_handler;
2469
		dev->driver->irq_handler = ironlake_irq_handler;
2469
        driver->irq_preinstall = ironlake_irq_preinstall;
2470
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
2470
        driver->irq_postinstall = ironlake_irq_postinstall;
2471
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
2471
	} else {
2472
	} else {
2472
		if (INTEL_INFO(dev)->gen == 2) {
2473
		if (INTEL_INFO(dev)->gen == 2) {
2473
		} else if (INTEL_INFO(dev)->gen == 3) {
2474
		} else if (INTEL_INFO(dev)->gen == 3) {
2474
            driver->irq_handler = i915_irq_handler;
2475
			dev->driver->irq_preinstall = i915_irq_preinstall;
2475
            driver->irq_preinstall = i915_irq_preinstall;
2476
			dev->driver->irq_postinstall = i915_irq_postinstall;
2476
            driver->irq_postinstall = i915_irq_postinstall;
2477
			dev->driver->irq_handler = i915_irq_handler;
2477
		} else {
2478
		} else {
2478
            driver->irq_handler = i965_irq_handler;
2479
			dev->driver->irq_preinstall = i965_irq_preinstall;
2479
            driver->irq_preinstall = i965_irq_preinstall;
2480
			dev->driver->irq_postinstall = i965_irq_postinstall;
2480
            driver->irq_postinstall = i965_irq_postinstall;
2481
			dev->driver->irq_handler = i965_irq_handler;
2481
		}
2482
		}
-
 
2483
	}
-
 
2484
 
2482
	}
2485
    printf("device %p driver %p handler %p\n", dev, dev->driver, dev->driver->irq_handler) ;
Line -... Line 2486...
-
 
2486
}
-
 
2487
 
-
 
2488
irqreturn_t intel_irq_handler(struct drm_device *dev)
-
 
2489
{
-
 
2490
 
-
 
2491
    printf("i915 irq\n");
-
 
2492
 
-
 
2493
//    printf("device %p driver %p handler %p\n", dev, dev->driver, dev->driver->irq_handler) ;
-
 
2494
 
Line 2483... Line 2495...
2483
}
2495
    return dev->driver->irq_handler(0, dev);
2484
 
2496
}
2485
 
2497
 
2486
int drm_irq_install(struct drm_device *dev)
2498
int drm_irq_install(struct drm_device *dev)
Line 2509... Line 2521...
2509
    irq_line   = drm_dev_to_irq(dev);
2521
    irq_line   = drm_dev_to_irq(dev);
Line 2510... Line 2522...
2510
 
2522
 
Line 2511... Line 2523...
2511
    DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
2523
    DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
2512
 
2524
 
2513
    /* Before installing handler */
2525
    /* Before installing handler */
Line 2514... Line 2526...
2514
    if (driver->irq_preinstall)
2526
    if (dev->driver->irq_preinstall)
Line 2515... Line 2527...
2515
            driver->irq_preinstall(dev);
2527
            dev->driver->irq_preinstall(dev);
2516
 
2528
 
2517
    ret = AttachIntHandler(irq_line, driver->irq_handler, (u32)dev);
2529
    ret = AttachIntHandler(irq_line, intel_irq_handler, (u32)dev);
Line 2518... Line 2530...
2518
 
2530
 
2519
    /* After installing handler */
2531
    /* After installing handler */
2520
    if (driver->irq_postinstall)
2532
    if (dev->driver->irq_postinstall)